1 /* 2 * OMAP2 McSPI controller driver 3 * 4 * Copyright (C) 2005, 2006 Nokia Corporation 5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and 6 * Juha Yrj�l� <juha.yrjola@nokia.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 * 22 */ 23 24 #include <linux/kernel.h> 25 #include <linux/interrupt.h> 26 #include <linux/module.h> 27 #include <linux/device.h> 28 #include <linux/delay.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/dmaengine.h> 31 #include <linux/omap-dma.h> 32 #include <linux/platform_device.h> 33 #include <linux/err.h> 34 #include <linux/clk.h> 35 #include <linux/io.h> 36 #include <linux/slab.h> 37 #include <linux/pm_runtime.h> 38 #include <linux/of.h> 39 #include <linux/of_device.h> 40 #include <linux/gcd.h> 41 42 #include <linux/spi/spi.h> 43 44 #include <linux/platform_data/spi-omap2-mcspi.h> 45 46 #define OMAP2_MCSPI_MAX_FREQ 48000000 47 #define OMAP2_MCSPI_MAX_DIVIDER 4096 48 #define OMAP2_MCSPI_MAX_FIFODEPTH 64 49 #define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF 50 #define SPI_AUTOSUSPEND_TIMEOUT 2000 51 52 #define OMAP2_MCSPI_REVISION 0x00 53 #define OMAP2_MCSPI_SYSSTATUS 0x14 54 #define OMAP2_MCSPI_IRQSTATUS 0x18 55 #define OMAP2_MCSPI_IRQENABLE 0x1c 56 #define OMAP2_MCSPI_WAKEUPENABLE 0x20 57 #define OMAP2_MCSPI_SYST 0x24 58 #define OMAP2_MCSPI_MODULCTRL 0x28 59 #define OMAP2_MCSPI_XFERLEVEL 0x7c 60 61 /* per-channel banks, 0x14 bytes each, first is: */ 62 #define OMAP2_MCSPI_CHCONF0 0x2c 63 #define OMAP2_MCSPI_CHSTAT0 0x30 64 #define OMAP2_MCSPI_CHCTRL0 0x34 65 #define OMAP2_MCSPI_TX0 0x38 66 #define OMAP2_MCSPI_RX0 0x3c 67 68 /* per-register bitmasks: */ 69 #define OMAP2_MCSPI_IRQSTATUS_EOW BIT(17) 70 71 #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0) 72 #define OMAP2_MCSPI_MODULCTRL_MS BIT(2) 73 #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3) 74 75 #define OMAP2_MCSPI_CHCONF_PHA BIT(0) 76 #define OMAP2_MCSPI_CHCONF_POL BIT(1) 77 #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2) 78 #define OMAP2_MCSPI_CHCONF_EPOL BIT(6) 79 #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7) 80 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12) 81 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13) 82 #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12) 83 #define OMAP2_MCSPI_CHCONF_DMAW BIT(14) 84 #define OMAP2_MCSPI_CHCONF_DMAR BIT(15) 85 #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16) 86 #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17) 87 #define OMAP2_MCSPI_CHCONF_IS BIT(18) 88 #define OMAP2_MCSPI_CHCONF_TURBO BIT(19) 89 #define OMAP2_MCSPI_CHCONF_FORCE BIT(20) 90 #define OMAP2_MCSPI_CHCONF_FFET BIT(27) 91 #define OMAP2_MCSPI_CHCONF_FFER BIT(28) 92 #define OMAP2_MCSPI_CHCONF_CLKG BIT(29) 93 94 #define OMAP2_MCSPI_CHSTAT_RXS BIT(0) 95 #define OMAP2_MCSPI_CHSTAT_TXS BIT(1) 96 #define OMAP2_MCSPI_CHSTAT_EOT BIT(2) 97 #define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3) 98 99 #define OMAP2_MCSPI_CHCTRL_EN BIT(0) 100 #define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK (0xff << 8) 101 102 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0) 103 104 /* We have 2 DMA channels per CS, one for RX and one for TX */ 105 struct omap2_mcspi_dma { 106 struct dma_chan *dma_tx; 107 struct dma_chan *dma_rx; 108 109 int dma_tx_sync_dev; 110 int dma_rx_sync_dev; 111 112 struct completion dma_tx_completion; 113 struct completion dma_rx_completion; 114 115 char dma_rx_ch_name[14]; 116 char dma_tx_ch_name[14]; 117 }; 118 119 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and 120 * cache operations; better heuristics consider wordsize and bitrate. 121 */ 122 #define DMA_MIN_BYTES 160 123 124 125 /* 126 * Used for context save and restore, structure members to be updated whenever 127 * corresponding registers are modified. 128 */ 129 struct omap2_mcspi_regs { 130 u32 modulctrl; 131 u32 wakeupenable; 132 struct list_head cs; 133 }; 134 135 struct omap2_mcspi { 136 struct spi_master *master; 137 /* Virtual base address of the controller */ 138 void __iomem *base; 139 unsigned long phys; 140 /* SPI1 has 4 channels, while SPI2 has 2 */ 141 struct omap2_mcspi_dma *dma_channels; 142 struct device *dev; 143 struct omap2_mcspi_regs ctx; 144 int fifo_depth; 145 unsigned int pin_dir:1; 146 }; 147 148 struct omap2_mcspi_cs { 149 void __iomem *base; 150 unsigned long phys; 151 int word_len; 152 struct list_head node; 153 /* Context save and restore shadow register */ 154 u32 chconf0, chctrl0; 155 }; 156 157 static inline void mcspi_write_reg(struct spi_master *master, 158 int idx, u32 val) 159 { 160 struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 161 162 writel_relaxed(val, mcspi->base + idx); 163 } 164 165 static inline u32 mcspi_read_reg(struct spi_master *master, int idx) 166 { 167 struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 168 169 return readl_relaxed(mcspi->base + idx); 170 } 171 172 static inline void mcspi_write_cs_reg(const struct spi_device *spi, 173 int idx, u32 val) 174 { 175 struct omap2_mcspi_cs *cs = spi->controller_state; 176 177 writel_relaxed(val, cs->base + idx); 178 } 179 180 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx) 181 { 182 struct omap2_mcspi_cs *cs = spi->controller_state; 183 184 return readl_relaxed(cs->base + idx); 185 } 186 187 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi) 188 { 189 struct omap2_mcspi_cs *cs = spi->controller_state; 190 191 return cs->chconf0; 192 } 193 194 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val) 195 { 196 struct omap2_mcspi_cs *cs = spi->controller_state; 197 198 cs->chconf0 = val; 199 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val); 200 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0); 201 } 202 203 static inline int mcspi_bytes_per_word(int word_len) 204 { 205 if (word_len <= 8) 206 return 1; 207 else if (word_len <= 16) 208 return 2; 209 else /* word_len <= 32 */ 210 return 4; 211 } 212 213 static void omap2_mcspi_set_dma_req(const struct spi_device *spi, 214 int is_read, int enable) 215 { 216 u32 l, rw; 217 218 l = mcspi_cached_chconf0(spi); 219 220 if (is_read) /* 1 is read, 0 write */ 221 rw = OMAP2_MCSPI_CHCONF_DMAR; 222 else 223 rw = OMAP2_MCSPI_CHCONF_DMAW; 224 225 if (enable) 226 l |= rw; 227 else 228 l &= ~rw; 229 230 mcspi_write_chconf0(spi, l); 231 } 232 233 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) 234 { 235 struct omap2_mcspi_cs *cs = spi->controller_state; 236 u32 l; 237 238 l = cs->chctrl0; 239 if (enable) 240 l |= OMAP2_MCSPI_CHCTRL_EN; 241 else 242 l &= ~OMAP2_MCSPI_CHCTRL_EN; 243 cs->chctrl0 = l; 244 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); 245 /* Flash post-writes */ 246 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0); 247 } 248 249 static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active) 250 { 251 u32 l; 252 253 l = mcspi_cached_chconf0(spi); 254 if (cs_active) 255 l |= OMAP2_MCSPI_CHCONF_FORCE; 256 else 257 l &= ~OMAP2_MCSPI_CHCONF_FORCE; 258 259 mcspi_write_chconf0(spi, l); 260 } 261 262 static void omap2_mcspi_set_master_mode(struct spi_master *master) 263 { 264 struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 265 struct omap2_mcspi_regs *ctx = &mcspi->ctx; 266 u32 l; 267 268 /* 269 * Setup when switching from (reset default) slave mode 270 * to single-channel master mode 271 */ 272 l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL); 273 l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS); 274 l |= OMAP2_MCSPI_MODULCTRL_SINGLE; 275 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l); 276 277 ctx->modulctrl = l; 278 } 279 280 static void omap2_mcspi_set_fifo(const struct spi_device *spi, 281 struct spi_transfer *t, int enable) 282 { 283 struct spi_master *master = spi->master; 284 struct omap2_mcspi_cs *cs = spi->controller_state; 285 struct omap2_mcspi *mcspi; 286 unsigned int wcnt; 287 int max_fifo_depth, fifo_depth, bytes_per_word; 288 u32 chconf, xferlevel; 289 290 mcspi = spi_master_get_devdata(master); 291 292 chconf = mcspi_cached_chconf0(spi); 293 if (enable) { 294 bytes_per_word = mcspi_bytes_per_word(cs->word_len); 295 if (t->len % bytes_per_word != 0) 296 goto disable_fifo; 297 298 if (t->rx_buf != NULL && t->tx_buf != NULL) 299 max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2; 300 else 301 max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH; 302 303 fifo_depth = gcd(t->len, max_fifo_depth); 304 if (fifo_depth < 2 || fifo_depth % bytes_per_word != 0) 305 goto disable_fifo; 306 307 wcnt = t->len / bytes_per_word; 308 if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT) 309 goto disable_fifo; 310 311 xferlevel = wcnt << 16; 312 if (t->rx_buf != NULL) { 313 chconf |= OMAP2_MCSPI_CHCONF_FFER; 314 xferlevel |= (fifo_depth - 1) << 8; 315 } 316 if (t->tx_buf != NULL) { 317 chconf |= OMAP2_MCSPI_CHCONF_FFET; 318 xferlevel |= fifo_depth - 1; 319 } 320 321 mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel); 322 mcspi_write_chconf0(spi, chconf); 323 mcspi->fifo_depth = fifo_depth; 324 325 return; 326 } 327 328 disable_fifo: 329 if (t->rx_buf != NULL) 330 chconf &= ~OMAP2_MCSPI_CHCONF_FFER; 331 else 332 chconf &= ~OMAP2_MCSPI_CHCONF_FFET; 333 334 mcspi_write_chconf0(spi, chconf); 335 mcspi->fifo_depth = 0; 336 } 337 338 static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi) 339 { 340 struct spi_master *spi_cntrl = mcspi->master; 341 struct omap2_mcspi_regs *ctx = &mcspi->ctx; 342 struct omap2_mcspi_cs *cs; 343 344 /* McSPI: context restore */ 345 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl); 346 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable); 347 348 list_for_each_entry(cs, &ctx->cs, node) 349 writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); 350 } 351 352 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) 353 { 354 unsigned long timeout; 355 356 timeout = jiffies + msecs_to_jiffies(1000); 357 while (!(readl_relaxed(reg) & bit)) { 358 if (time_after(jiffies, timeout)) { 359 if (!(readl_relaxed(reg) & bit)) 360 return -ETIMEDOUT; 361 else 362 return 0; 363 } 364 cpu_relax(); 365 } 366 return 0; 367 } 368 369 static void omap2_mcspi_rx_callback(void *data) 370 { 371 struct spi_device *spi = data; 372 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); 373 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 374 375 /* We must disable the DMA RX request */ 376 omap2_mcspi_set_dma_req(spi, 1, 0); 377 378 complete(&mcspi_dma->dma_rx_completion); 379 } 380 381 static void omap2_mcspi_tx_callback(void *data) 382 { 383 struct spi_device *spi = data; 384 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); 385 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 386 387 /* We must disable the DMA TX request */ 388 omap2_mcspi_set_dma_req(spi, 0, 0); 389 390 complete(&mcspi_dma->dma_tx_completion); 391 } 392 393 static void omap2_mcspi_tx_dma(struct spi_device *spi, 394 struct spi_transfer *xfer, 395 struct dma_slave_config cfg) 396 { 397 struct omap2_mcspi *mcspi; 398 struct omap2_mcspi_dma *mcspi_dma; 399 unsigned int count; 400 401 mcspi = spi_master_get_devdata(spi->master); 402 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 403 count = xfer->len; 404 405 if (mcspi_dma->dma_tx) { 406 struct dma_async_tx_descriptor *tx; 407 struct scatterlist sg; 408 409 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg); 410 411 sg_init_table(&sg, 1); 412 sg_dma_address(&sg) = xfer->tx_dma; 413 sg_dma_len(&sg) = xfer->len; 414 415 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1, 416 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 417 if (tx) { 418 tx->callback = omap2_mcspi_tx_callback; 419 tx->callback_param = spi; 420 dmaengine_submit(tx); 421 } else { 422 /* FIXME: fall back to PIO? */ 423 } 424 } 425 dma_async_issue_pending(mcspi_dma->dma_tx); 426 omap2_mcspi_set_dma_req(spi, 0, 1); 427 428 } 429 430 static unsigned 431 omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer, 432 struct dma_slave_config cfg, 433 unsigned es) 434 { 435 struct omap2_mcspi *mcspi; 436 struct omap2_mcspi_dma *mcspi_dma; 437 unsigned int count, dma_count; 438 u32 l; 439 int elements = 0; 440 int word_len, element_count; 441 struct omap2_mcspi_cs *cs = spi->controller_state; 442 mcspi = spi_master_get_devdata(spi->master); 443 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 444 count = xfer->len; 445 dma_count = xfer->len; 446 447 if (mcspi->fifo_depth == 0) 448 dma_count -= es; 449 450 word_len = cs->word_len; 451 l = mcspi_cached_chconf0(spi); 452 453 if (word_len <= 8) 454 element_count = count; 455 else if (word_len <= 16) 456 element_count = count >> 1; 457 else /* word_len <= 32 */ 458 element_count = count >> 2; 459 460 if (mcspi_dma->dma_rx) { 461 struct dma_async_tx_descriptor *tx; 462 struct scatterlist sg; 463 464 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg); 465 466 if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0) 467 dma_count -= es; 468 469 sg_init_table(&sg, 1); 470 sg_dma_address(&sg) = xfer->rx_dma; 471 sg_dma_len(&sg) = dma_count; 472 473 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1, 474 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | 475 DMA_CTRL_ACK); 476 if (tx) { 477 tx->callback = omap2_mcspi_rx_callback; 478 tx->callback_param = spi; 479 dmaengine_submit(tx); 480 } else { 481 /* FIXME: fall back to PIO? */ 482 } 483 } 484 485 dma_async_issue_pending(mcspi_dma->dma_rx); 486 omap2_mcspi_set_dma_req(spi, 1, 1); 487 488 wait_for_completion(&mcspi_dma->dma_rx_completion); 489 dma_unmap_single(mcspi->dev, xfer->rx_dma, count, 490 DMA_FROM_DEVICE); 491 492 if (mcspi->fifo_depth > 0) 493 return count; 494 495 omap2_mcspi_set_enable(spi, 0); 496 497 elements = element_count - 1; 498 499 if (l & OMAP2_MCSPI_CHCONF_TURBO) { 500 elements--; 501 502 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) 503 & OMAP2_MCSPI_CHSTAT_RXS)) { 504 u32 w; 505 506 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); 507 if (word_len <= 8) 508 ((u8 *)xfer->rx_buf)[elements++] = w; 509 else if (word_len <= 16) 510 ((u16 *)xfer->rx_buf)[elements++] = w; 511 else /* word_len <= 32 */ 512 ((u32 *)xfer->rx_buf)[elements++] = w; 513 } else { 514 int bytes_per_word = mcspi_bytes_per_word(word_len); 515 dev_err(&spi->dev, "DMA RX penultimate word empty\n"); 516 count -= (bytes_per_word << 1); 517 omap2_mcspi_set_enable(spi, 1); 518 return count; 519 } 520 } 521 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) 522 & OMAP2_MCSPI_CHSTAT_RXS)) { 523 u32 w; 524 525 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); 526 if (word_len <= 8) 527 ((u8 *)xfer->rx_buf)[elements] = w; 528 else if (word_len <= 16) 529 ((u16 *)xfer->rx_buf)[elements] = w; 530 else /* word_len <= 32 */ 531 ((u32 *)xfer->rx_buf)[elements] = w; 532 } else { 533 dev_err(&spi->dev, "DMA RX last word empty\n"); 534 count -= mcspi_bytes_per_word(word_len); 535 } 536 omap2_mcspi_set_enable(spi, 1); 537 return count; 538 } 539 540 static unsigned 541 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) 542 { 543 struct omap2_mcspi *mcspi; 544 struct omap2_mcspi_cs *cs = spi->controller_state; 545 struct omap2_mcspi_dma *mcspi_dma; 546 unsigned int count; 547 u32 l; 548 u8 *rx; 549 const u8 *tx; 550 struct dma_slave_config cfg; 551 enum dma_slave_buswidth width; 552 unsigned es; 553 u32 burst; 554 void __iomem *chstat_reg; 555 void __iomem *irqstat_reg; 556 int wait_res; 557 558 mcspi = spi_master_get_devdata(spi->master); 559 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 560 l = mcspi_cached_chconf0(spi); 561 562 563 if (cs->word_len <= 8) { 564 width = DMA_SLAVE_BUSWIDTH_1_BYTE; 565 es = 1; 566 } else if (cs->word_len <= 16) { 567 width = DMA_SLAVE_BUSWIDTH_2_BYTES; 568 es = 2; 569 } else { 570 width = DMA_SLAVE_BUSWIDTH_4_BYTES; 571 es = 4; 572 } 573 574 count = xfer->len; 575 burst = 1; 576 577 if (mcspi->fifo_depth > 0) { 578 if (count > mcspi->fifo_depth) 579 burst = mcspi->fifo_depth / es; 580 else 581 burst = count / es; 582 } 583 584 memset(&cfg, 0, sizeof(cfg)); 585 cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0; 586 cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0; 587 cfg.src_addr_width = width; 588 cfg.dst_addr_width = width; 589 cfg.src_maxburst = burst; 590 cfg.dst_maxburst = burst; 591 592 rx = xfer->rx_buf; 593 tx = xfer->tx_buf; 594 595 if (tx != NULL) 596 omap2_mcspi_tx_dma(spi, xfer, cfg); 597 598 if (rx != NULL) 599 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es); 600 601 if (tx != NULL) { 602 wait_for_completion(&mcspi_dma->dma_tx_completion); 603 dma_unmap_single(mcspi->dev, xfer->tx_dma, xfer->len, 604 DMA_TO_DEVICE); 605 606 if (mcspi->fifo_depth > 0) { 607 irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS; 608 609 if (mcspi_wait_for_reg_bit(irqstat_reg, 610 OMAP2_MCSPI_IRQSTATUS_EOW) < 0) 611 dev_err(&spi->dev, "EOW timed out\n"); 612 613 mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS, 614 OMAP2_MCSPI_IRQSTATUS_EOW); 615 } 616 617 /* for TX_ONLY mode, be sure all words have shifted out */ 618 if (rx == NULL) { 619 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; 620 if (mcspi->fifo_depth > 0) { 621 wait_res = mcspi_wait_for_reg_bit(chstat_reg, 622 OMAP2_MCSPI_CHSTAT_TXFFE); 623 if (wait_res < 0) 624 dev_err(&spi->dev, "TXFFE timed out\n"); 625 } else { 626 wait_res = mcspi_wait_for_reg_bit(chstat_reg, 627 OMAP2_MCSPI_CHSTAT_TXS); 628 if (wait_res < 0) 629 dev_err(&spi->dev, "TXS timed out\n"); 630 } 631 if (wait_res >= 0 && 632 (mcspi_wait_for_reg_bit(chstat_reg, 633 OMAP2_MCSPI_CHSTAT_EOT) < 0)) 634 dev_err(&spi->dev, "EOT timed out\n"); 635 } 636 } 637 return count; 638 } 639 640 static unsigned 641 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) 642 { 643 struct omap2_mcspi *mcspi; 644 struct omap2_mcspi_cs *cs = spi->controller_state; 645 unsigned int count, c; 646 u32 l; 647 void __iomem *base = cs->base; 648 void __iomem *tx_reg; 649 void __iomem *rx_reg; 650 void __iomem *chstat_reg; 651 int word_len; 652 653 mcspi = spi_master_get_devdata(spi->master); 654 count = xfer->len; 655 c = count; 656 word_len = cs->word_len; 657 658 l = mcspi_cached_chconf0(spi); 659 660 /* We store the pre-calculated register addresses on stack to speed 661 * up the transfer loop. */ 662 tx_reg = base + OMAP2_MCSPI_TX0; 663 rx_reg = base + OMAP2_MCSPI_RX0; 664 chstat_reg = base + OMAP2_MCSPI_CHSTAT0; 665 666 if (c < (word_len>>3)) 667 return 0; 668 669 if (word_len <= 8) { 670 u8 *rx; 671 const u8 *tx; 672 673 rx = xfer->rx_buf; 674 tx = xfer->tx_buf; 675 676 do { 677 c -= 1; 678 if (tx != NULL) { 679 if (mcspi_wait_for_reg_bit(chstat_reg, 680 OMAP2_MCSPI_CHSTAT_TXS) < 0) { 681 dev_err(&spi->dev, "TXS timed out\n"); 682 goto out; 683 } 684 dev_vdbg(&spi->dev, "write-%d %02x\n", 685 word_len, *tx); 686 writel_relaxed(*tx++, tx_reg); 687 } 688 if (rx != NULL) { 689 if (mcspi_wait_for_reg_bit(chstat_reg, 690 OMAP2_MCSPI_CHSTAT_RXS) < 0) { 691 dev_err(&spi->dev, "RXS timed out\n"); 692 goto out; 693 } 694 695 if (c == 1 && tx == NULL && 696 (l & OMAP2_MCSPI_CHCONF_TURBO)) { 697 omap2_mcspi_set_enable(spi, 0); 698 *rx++ = readl_relaxed(rx_reg); 699 dev_vdbg(&spi->dev, "read-%d %02x\n", 700 word_len, *(rx - 1)); 701 if (mcspi_wait_for_reg_bit(chstat_reg, 702 OMAP2_MCSPI_CHSTAT_RXS) < 0) { 703 dev_err(&spi->dev, 704 "RXS timed out\n"); 705 goto out; 706 } 707 c = 0; 708 } else if (c == 0 && tx == NULL) { 709 omap2_mcspi_set_enable(spi, 0); 710 } 711 712 *rx++ = readl_relaxed(rx_reg); 713 dev_vdbg(&spi->dev, "read-%d %02x\n", 714 word_len, *(rx - 1)); 715 } 716 } while (c); 717 } else if (word_len <= 16) { 718 u16 *rx; 719 const u16 *tx; 720 721 rx = xfer->rx_buf; 722 tx = xfer->tx_buf; 723 do { 724 c -= 2; 725 if (tx != NULL) { 726 if (mcspi_wait_for_reg_bit(chstat_reg, 727 OMAP2_MCSPI_CHSTAT_TXS) < 0) { 728 dev_err(&spi->dev, "TXS timed out\n"); 729 goto out; 730 } 731 dev_vdbg(&spi->dev, "write-%d %04x\n", 732 word_len, *tx); 733 writel_relaxed(*tx++, tx_reg); 734 } 735 if (rx != NULL) { 736 if (mcspi_wait_for_reg_bit(chstat_reg, 737 OMAP2_MCSPI_CHSTAT_RXS) < 0) { 738 dev_err(&spi->dev, "RXS timed out\n"); 739 goto out; 740 } 741 742 if (c == 2 && tx == NULL && 743 (l & OMAP2_MCSPI_CHCONF_TURBO)) { 744 omap2_mcspi_set_enable(spi, 0); 745 *rx++ = readl_relaxed(rx_reg); 746 dev_vdbg(&spi->dev, "read-%d %04x\n", 747 word_len, *(rx - 1)); 748 if (mcspi_wait_for_reg_bit(chstat_reg, 749 OMAP2_MCSPI_CHSTAT_RXS) < 0) { 750 dev_err(&spi->dev, 751 "RXS timed out\n"); 752 goto out; 753 } 754 c = 0; 755 } else if (c == 0 && tx == NULL) { 756 omap2_mcspi_set_enable(spi, 0); 757 } 758 759 *rx++ = readl_relaxed(rx_reg); 760 dev_vdbg(&spi->dev, "read-%d %04x\n", 761 word_len, *(rx - 1)); 762 } 763 } while (c >= 2); 764 } else if (word_len <= 32) { 765 u32 *rx; 766 const u32 *tx; 767 768 rx = xfer->rx_buf; 769 tx = xfer->tx_buf; 770 do { 771 c -= 4; 772 if (tx != NULL) { 773 if (mcspi_wait_for_reg_bit(chstat_reg, 774 OMAP2_MCSPI_CHSTAT_TXS) < 0) { 775 dev_err(&spi->dev, "TXS timed out\n"); 776 goto out; 777 } 778 dev_vdbg(&spi->dev, "write-%d %08x\n", 779 word_len, *tx); 780 writel_relaxed(*tx++, tx_reg); 781 } 782 if (rx != NULL) { 783 if (mcspi_wait_for_reg_bit(chstat_reg, 784 OMAP2_MCSPI_CHSTAT_RXS) < 0) { 785 dev_err(&spi->dev, "RXS timed out\n"); 786 goto out; 787 } 788 789 if (c == 4 && tx == NULL && 790 (l & OMAP2_MCSPI_CHCONF_TURBO)) { 791 omap2_mcspi_set_enable(spi, 0); 792 *rx++ = readl_relaxed(rx_reg); 793 dev_vdbg(&spi->dev, "read-%d %08x\n", 794 word_len, *(rx - 1)); 795 if (mcspi_wait_for_reg_bit(chstat_reg, 796 OMAP2_MCSPI_CHSTAT_RXS) < 0) { 797 dev_err(&spi->dev, 798 "RXS timed out\n"); 799 goto out; 800 } 801 c = 0; 802 } else if (c == 0 && tx == NULL) { 803 omap2_mcspi_set_enable(spi, 0); 804 } 805 806 *rx++ = readl_relaxed(rx_reg); 807 dev_vdbg(&spi->dev, "read-%d %08x\n", 808 word_len, *(rx - 1)); 809 } 810 } while (c >= 4); 811 } 812 813 /* for TX_ONLY mode, be sure all words have shifted out */ 814 if (xfer->rx_buf == NULL) { 815 if (mcspi_wait_for_reg_bit(chstat_reg, 816 OMAP2_MCSPI_CHSTAT_TXS) < 0) { 817 dev_err(&spi->dev, "TXS timed out\n"); 818 } else if (mcspi_wait_for_reg_bit(chstat_reg, 819 OMAP2_MCSPI_CHSTAT_EOT) < 0) 820 dev_err(&spi->dev, "EOT timed out\n"); 821 822 /* disable chan to purge rx datas received in TX_ONLY transfer, 823 * otherwise these rx datas will affect the direct following 824 * RX_ONLY transfer. 825 */ 826 omap2_mcspi_set_enable(spi, 0); 827 } 828 out: 829 omap2_mcspi_set_enable(spi, 1); 830 return count - c; 831 } 832 833 static u32 omap2_mcspi_calc_divisor(u32 speed_hz) 834 { 835 u32 div; 836 837 for (div = 0; div < 15; div++) 838 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div)) 839 return div; 840 841 return 15; 842 } 843 844 /* called only when no transfer is active to this device */ 845 static int omap2_mcspi_setup_transfer(struct spi_device *spi, 846 struct spi_transfer *t) 847 { 848 struct omap2_mcspi_cs *cs = spi->controller_state; 849 struct omap2_mcspi *mcspi; 850 struct spi_master *spi_cntrl; 851 u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0; 852 u8 word_len = spi->bits_per_word; 853 u32 speed_hz = spi->max_speed_hz; 854 855 mcspi = spi_master_get_devdata(spi->master); 856 spi_cntrl = mcspi->master; 857 858 if (t != NULL && t->bits_per_word) 859 word_len = t->bits_per_word; 860 861 cs->word_len = word_len; 862 863 if (t && t->speed_hz) 864 speed_hz = t->speed_hz; 865 866 speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ); 867 if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) { 868 clkd = omap2_mcspi_calc_divisor(speed_hz); 869 speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd; 870 clkg = 0; 871 } else { 872 div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz; 873 speed_hz = OMAP2_MCSPI_MAX_FREQ / div; 874 clkd = (div - 1) & 0xf; 875 extclk = (div - 1) >> 4; 876 clkg = OMAP2_MCSPI_CHCONF_CLKG; 877 } 878 879 l = mcspi_cached_chconf0(spi); 880 881 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS 882 * REVISIT: this controller could support SPI_3WIRE mode. 883 */ 884 if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) { 885 l &= ~OMAP2_MCSPI_CHCONF_IS; 886 l &= ~OMAP2_MCSPI_CHCONF_DPE1; 887 l |= OMAP2_MCSPI_CHCONF_DPE0; 888 } else { 889 l |= OMAP2_MCSPI_CHCONF_IS; 890 l |= OMAP2_MCSPI_CHCONF_DPE1; 891 l &= ~OMAP2_MCSPI_CHCONF_DPE0; 892 } 893 894 /* wordlength */ 895 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK; 896 l |= (word_len - 1) << 7; 897 898 /* set chipselect polarity; manage with FORCE */ 899 if (!(spi->mode & SPI_CS_HIGH)) 900 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */ 901 else 902 l &= ~OMAP2_MCSPI_CHCONF_EPOL; 903 904 /* set clock divisor */ 905 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK; 906 l |= clkd << 2; 907 908 /* set clock granularity */ 909 l &= ~OMAP2_MCSPI_CHCONF_CLKG; 910 l |= clkg; 911 if (clkg) { 912 cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK; 913 cs->chctrl0 |= extclk << 8; 914 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); 915 } 916 917 /* set SPI mode 0..3 */ 918 if (spi->mode & SPI_CPOL) 919 l |= OMAP2_MCSPI_CHCONF_POL; 920 else 921 l &= ~OMAP2_MCSPI_CHCONF_POL; 922 if (spi->mode & SPI_CPHA) 923 l |= OMAP2_MCSPI_CHCONF_PHA; 924 else 925 l &= ~OMAP2_MCSPI_CHCONF_PHA; 926 927 mcspi_write_chconf0(spi, l); 928 929 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", 930 speed_hz, 931 (spi->mode & SPI_CPHA) ? "trailing" : "leading", 932 (spi->mode & SPI_CPOL) ? "inverted" : "normal"); 933 934 return 0; 935 } 936 937 /* 938 * Note that we currently allow DMA only if we get a channel 939 * for both rx and tx. Otherwise we'll do PIO for both rx and tx. 940 */ 941 static int omap2_mcspi_request_dma(struct spi_device *spi) 942 { 943 struct spi_master *master = spi->master; 944 struct omap2_mcspi *mcspi; 945 struct omap2_mcspi_dma *mcspi_dma; 946 dma_cap_mask_t mask; 947 unsigned sig; 948 949 mcspi = spi_master_get_devdata(master); 950 mcspi_dma = mcspi->dma_channels + spi->chip_select; 951 952 init_completion(&mcspi_dma->dma_rx_completion); 953 init_completion(&mcspi_dma->dma_tx_completion); 954 955 dma_cap_zero(mask); 956 dma_cap_set(DMA_SLAVE, mask); 957 sig = mcspi_dma->dma_rx_sync_dev; 958 959 mcspi_dma->dma_rx = 960 dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 961 &sig, &master->dev, 962 mcspi_dma->dma_rx_ch_name); 963 if (!mcspi_dma->dma_rx) 964 goto no_dma; 965 966 sig = mcspi_dma->dma_tx_sync_dev; 967 mcspi_dma->dma_tx = 968 dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 969 &sig, &master->dev, 970 mcspi_dma->dma_tx_ch_name); 971 972 if (!mcspi_dma->dma_tx) { 973 dma_release_channel(mcspi_dma->dma_rx); 974 mcspi_dma->dma_rx = NULL; 975 goto no_dma; 976 } 977 978 return 0; 979 980 no_dma: 981 dev_warn(&spi->dev, "not using DMA for McSPI\n"); 982 return -EAGAIN; 983 } 984 985 static int omap2_mcspi_setup(struct spi_device *spi) 986 { 987 int ret; 988 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); 989 struct omap2_mcspi_regs *ctx = &mcspi->ctx; 990 struct omap2_mcspi_dma *mcspi_dma; 991 struct omap2_mcspi_cs *cs = spi->controller_state; 992 993 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 994 995 if (!cs) { 996 cs = kzalloc(sizeof *cs, GFP_KERNEL); 997 if (!cs) 998 return -ENOMEM; 999 cs->base = mcspi->base + spi->chip_select * 0x14; 1000 cs->phys = mcspi->phys + spi->chip_select * 0x14; 1001 cs->chconf0 = 0; 1002 cs->chctrl0 = 0; 1003 spi->controller_state = cs; 1004 /* Link this to context save list */ 1005 list_add_tail(&cs->node, &ctx->cs); 1006 } 1007 1008 if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) { 1009 ret = omap2_mcspi_request_dma(spi); 1010 if (ret < 0 && ret != -EAGAIN) 1011 return ret; 1012 } 1013 1014 ret = pm_runtime_get_sync(mcspi->dev); 1015 if (ret < 0) 1016 return ret; 1017 1018 ret = omap2_mcspi_setup_transfer(spi, NULL); 1019 pm_runtime_mark_last_busy(mcspi->dev); 1020 pm_runtime_put_autosuspend(mcspi->dev); 1021 1022 return ret; 1023 } 1024 1025 static void omap2_mcspi_cleanup(struct spi_device *spi) 1026 { 1027 struct omap2_mcspi *mcspi; 1028 struct omap2_mcspi_dma *mcspi_dma; 1029 struct omap2_mcspi_cs *cs; 1030 1031 mcspi = spi_master_get_devdata(spi->master); 1032 1033 if (spi->controller_state) { 1034 /* Unlink controller state from context save list */ 1035 cs = spi->controller_state; 1036 list_del(&cs->node); 1037 1038 kfree(cs); 1039 } 1040 1041 if (spi->chip_select < spi->master->num_chipselect) { 1042 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 1043 1044 if (mcspi_dma->dma_rx) { 1045 dma_release_channel(mcspi_dma->dma_rx); 1046 mcspi_dma->dma_rx = NULL; 1047 } 1048 if (mcspi_dma->dma_tx) { 1049 dma_release_channel(mcspi_dma->dma_tx); 1050 mcspi_dma->dma_tx = NULL; 1051 } 1052 } 1053 } 1054 1055 static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m) 1056 { 1057 1058 /* We only enable one channel at a time -- the one whose message is 1059 * -- although this controller would gladly 1060 * arbitrate among multiple channels. This corresponds to "single 1061 * channel" master mode. As a side effect, we need to manage the 1062 * chipselect with the FORCE bit ... CS != channel enable. 1063 */ 1064 1065 struct spi_device *spi; 1066 struct spi_transfer *t = NULL; 1067 struct spi_master *master; 1068 struct omap2_mcspi_dma *mcspi_dma; 1069 int cs_active = 0; 1070 struct omap2_mcspi_cs *cs; 1071 struct omap2_mcspi_device_config *cd; 1072 int par_override = 0; 1073 int status = 0; 1074 u32 chconf; 1075 1076 spi = m->spi; 1077 master = spi->master; 1078 mcspi_dma = mcspi->dma_channels + spi->chip_select; 1079 cs = spi->controller_state; 1080 cd = spi->controller_data; 1081 1082 omap2_mcspi_set_enable(spi, 0); 1083 list_for_each_entry(t, &m->transfers, transfer_list) { 1084 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) { 1085 status = -EINVAL; 1086 break; 1087 } 1088 if (par_override || 1089 (t->speed_hz != spi->max_speed_hz) || 1090 (t->bits_per_word != spi->bits_per_word)) { 1091 par_override = 1; 1092 status = omap2_mcspi_setup_transfer(spi, t); 1093 if (status < 0) 1094 break; 1095 if (t->speed_hz == spi->max_speed_hz && 1096 t->bits_per_word == spi->bits_per_word) 1097 par_override = 0; 1098 } 1099 if (cd && cd->cs_per_word) { 1100 chconf = mcspi->ctx.modulctrl; 1101 chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE; 1102 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf); 1103 mcspi->ctx.modulctrl = 1104 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); 1105 } 1106 1107 1108 if (!cs_active) { 1109 omap2_mcspi_force_cs(spi, 1); 1110 cs_active = 1; 1111 } 1112 1113 chconf = mcspi_cached_chconf0(spi); 1114 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; 1115 chconf &= ~OMAP2_MCSPI_CHCONF_TURBO; 1116 1117 if (t->tx_buf == NULL) 1118 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY; 1119 else if (t->rx_buf == NULL) 1120 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY; 1121 1122 if (cd && cd->turbo_mode && t->tx_buf == NULL) { 1123 /* Turbo mode is for more than one word */ 1124 if (t->len > ((cs->word_len + 7) >> 3)) 1125 chconf |= OMAP2_MCSPI_CHCONF_TURBO; 1126 } 1127 1128 mcspi_write_chconf0(spi, chconf); 1129 1130 if (t->len) { 1131 unsigned count; 1132 1133 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && 1134 (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)) 1135 omap2_mcspi_set_fifo(spi, t, 1); 1136 1137 omap2_mcspi_set_enable(spi, 1); 1138 1139 /* RX_ONLY mode needs dummy data in TX reg */ 1140 if (t->tx_buf == NULL) 1141 writel_relaxed(0, cs->base 1142 + OMAP2_MCSPI_TX0); 1143 1144 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && 1145 (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)) 1146 count = omap2_mcspi_txrx_dma(spi, t); 1147 else 1148 count = omap2_mcspi_txrx_pio(spi, t); 1149 m->actual_length += count; 1150 1151 if (count != t->len) { 1152 status = -EIO; 1153 break; 1154 } 1155 } 1156 1157 if (t->delay_usecs) 1158 udelay(t->delay_usecs); 1159 1160 /* ignore the "leave it on after last xfer" hint */ 1161 if (t->cs_change) { 1162 omap2_mcspi_force_cs(spi, 0); 1163 cs_active = 0; 1164 } 1165 1166 omap2_mcspi_set_enable(spi, 0); 1167 1168 if (mcspi->fifo_depth > 0) 1169 omap2_mcspi_set_fifo(spi, t, 0); 1170 } 1171 /* Restore defaults if they were overriden */ 1172 if (par_override) { 1173 par_override = 0; 1174 status = omap2_mcspi_setup_transfer(spi, NULL); 1175 } 1176 1177 if (cs_active) 1178 omap2_mcspi_force_cs(spi, 0); 1179 1180 if (cd && cd->cs_per_word) { 1181 chconf = mcspi->ctx.modulctrl; 1182 chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE; 1183 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf); 1184 mcspi->ctx.modulctrl = 1185 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); 1186 } 1187 1188 omap2_mcspi_set_enable(spi, 0); 1189 1190 if (mcspi->fifo_depth > 0 && t) 1191 omap2_mcspi_set_fifo(spi, t, 0); 1192 1193 m->status = status; 1194 } 1195 1196 static int omap2_mcspi_transfer_one_message(struct spi_master *master, 1197 struct spi_message *m) 1198 { 1199 struct spi_device *spi; 1200 struct omap2_mcspi *mcspi; 1201 struct omap2_mcspi_dma *mcspi_dma; 1202 struct spi_transfer *t; 1203 1204 spi = m->spi; 1205 mcspi = spi_master_get_devdata(master); 1206 mcspi_dma = mcspi->dma_channels + spi->chip_select; 1207 m->actual_length = 0; 1208 m->status = 0; 1209 1210 list_for_each_entry(t, &m->transfers, transfer_list) { 1211 const void *tx_buf = t->tx_buf; 1212 void *rx_buf = t->rx_buf; 1213 unsigned len = t->len; 1214 1215 if ((len && !(rx_buf || tx_buf))) { 1216 dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n", 1217 t->speed_hz, 1218 len, 1219 tx_buf ? "tx" : "", 1220 rx_buf ? "rx" : "", 1221 t->bits_per_word); 1222 return -EINVAL; 1223 } 1224 1225 if (m->is_dma_mapped || len < DMA_MIN_BYTES) 1226 continue; 1227 1228 if (mcspi_dma->dma_tx && tx_buf != NULL) { 1229 t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf, 1230 len, DMA_TO_DEVICE); 1231 if (dma_mapping_error(mcspi->dev, t->tx_dma)) { 1232 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", 1233 'T', len); 1234 return -EINVAL; 1235 } 1236 } 1237 if (mcspi_dma->dma_rx && rx_buf != NULL) { 1238 t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len, 1239 DMA_FROM_DEVICE); 1240 if (dma_mapping_error(mcspi->dev, t->rx_dma)) { 1241 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", 1242 'R', len); 1243 if (tx_buf != NULL) 1244 dma_unmap_single(mcspi->dev, t->tx_dma, 1245 len, DMA_TO_DEVICE); 1246 return -EINVAL; 1247 } 1248 } 1249 } 1250 1251 omap2_mcspi_work(mcspi, m); 1252 spi_finalize_current_message(master); 1253 return 0; 1254 } 1255 1256 static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi) 1257 { 1258 struct spi_master *master = mcspi->master; 1259 struct omap2_mcspi_regs *ctx = &mcspi->ctx; 1260 int ret = 0; 1261 1262 ret = pm_runtime_get_sync(mcspi->dev); 1263 if (ret < 0) 1264 return ret; 1265 1266 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, 1267 OMAP2_MCSPI_WAKEUPENABLE_WKEN); 1268 ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN; 1269 1270 omap2_mcspi_set_master_mode(master); 1271 pm_runtime_mark_last_busy(mcspi->dev); 1272 pm_runtime_put_autosuspend(mcspi->dev); 1273 return 0; 1274 } 1275 1276 static int omap_mcspi_runtime_resume(struct device *dev) 1277 { 1278 struct omap2_mcspi *mcspi; 1279 struct spi_master *master; 1280 1281 master = dev_get_drvdata(dev); 1282 mcspi = spi_master_get_devdata(master); 1283 omap2_mcspi_restore_ctx(mcspi); 1284 1285 return 0; 1286 } 1287 1288 static struct omap2_mcspi_platform_config omap2_pdata = { 1289 .regs_offset = 0, 1290 }; 1291 1292 static struct omap2_mcspi_platform_config omap4_pdata = { 1293 .regs_offset = OMAP4_MCSPI_REG_OFFSET, 1294 }; 1295 1296 static const struct of_device_id omap_mcspi_of_match[] = { 1297 { 1298 .compatible = "ti,omap2-mcspi", 1299 .data = &omap2_pdata, 1300 }, 1301 { 1302 .compatible = "ti,omap4-mcspi", 1303 .data = &omap4_pdata, 1304 }, 1305 { }, 1306 }; 1307 MODULE_DEVICE_TABLE(of, omap_mcspi_of_match); 1308 1309 static int omap2_mcspi_probe(struct platform_device *pdev) 1310 { 1311 struct spi_master *master; 1312 const struct omap2_mcspi_platform_config *pdata; 1313 struct omap2_mcspi *mcspi; 1314 struct resource *r; 1315 int status = 0, i; 1316 u32 regs_offset = 0; 1317 static int bus_num = 1; 1318 struct device_node *node = pdev->dev.of_node; 1319 const struct of_device_id *match; 1320 1321 master = spi_alloc_master(&pdev->dev, sizeof *mcspi); 1322 if (master == NULL) { 1323 dev_dbg(&pdev->dev, "master allocation failed\n"); 1324 return -ENOMEM; 1325 } 1326 1327 /* the spi->mode bits understood by this driver: */ 1328 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1329 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1330 master->setup = omap2_mcspi_setup; 1331 master->auto_runtime_pm = true; 1332 master->transfer_one_message = omap2_mcspi_transfer_one_message; 1333 master->cleanup = omap2_mcspi_cleanup; 1334 master->dev.of_node = node; 1335 master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ; 1336 master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15; 1337 1338 platform_set_drvdata(pdev, master); 1339 1340 mcspi = spi_master_get_devdata(master); 1341 mcspi->master = master; 1342 1343 match = of_match_device(omap_mcspi_of_match, &pdev->dev); 1344 if (match) { 1345 u32 num_cs = 1; /* default number of chipselect */ 1346 pdata = match->data; 1347 1348 of_property_read_u32(node, "ti,spi-num-cs", &num_cs); 1349 master->num_chipselect = num_cs; 1350 master->bus_num = bus_num++; 1351 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL)) 1352 mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN; 1353 } else { 1354 pdata = dev_get_platdata(&pdev->dev); 1355 master->num_chipselect = pdata->num_cs; 1356 if (pdev->id != -1) 1357 master->bus_num = pdev->id; 1358 mcspi->pin_dir = pdata->pin_dir; 1359 } 1360 regs_offset = pdata->regs_offset; 1361 1362 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1363 if (r == NULL) { 1364 status = -ENODEV; 1365 goto free_master; 1366 } 1367 1368 r->start += regs_offset; 1369 r->end += regs_offset; 1370 mcspi->phys = r->start; 1371 1372 mcspi->base = devm_ioremap_resource(&pdev->dev, r); 1373 if (IS_ERR(mcspi->base)) { 1374 status = PTR_ERR(mcspi->base); 1375 goto free_master; 1376 } 1377 1378 mcspi->dev = &pdev->dev; 1379 1380 INIT_LIST_HEAD(&mcspi->ctx.cs); 1381 1382 mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect, 1383 sizeof(struct omap2_mcspi_dma), 1384 GFP_KERNEL); 1385 if (mcspi->dma_channels == NULL) { 1386 status = -ENOMEM; 1387 goto free_master; 1388 } 1389 1390 for (i = 0; i < master->num_chipselect; i++) { 1391 char *dma_rx_ch_name = mcspi->dma_channels[i].dma_rx_ch_name; 1392 char *dma_tx_ch_name = mcspi->dma_channels[i].dma_tx_ch_name; 1393 struct resource *dma_res; 1394 1395 sprintf(dma_rx_ch_name, "rx%d", i); 1396 if (!pdev->dev.of_node) { 1397 dma_res = 1398 platform_get_resource_byname(pdev, 1399 IORESOURCE_DMA, 1400 dma_rx_ch_name); 1401 if (!dma_res) { 1402 dev_dbg(&pdev->dev, 1403 "cannot get DMA RX channel\n"); 1404 status = -ENODEV; 1405 break; 1406 } 1407 1408 mcspi->dma_channels[i].dma_rx_sync_dev = 1409 dma_res->start; 1410 } 1411 sprintf(dma_tx_ch_name, "tx%d", i); 1412 if (!pdev->dev.of_node) { 1413 dma_res = 1414 platform_get_resource_byname(pdev, 1415 IORESOURCE_DMA, 1416 dma_tx_ch_name); 1417 if (!dma_res) { 1418 dev_dbg(&pdev->dev, 1419 "cannot get DMA TX channel\n"); 1420 status = -ENODEV; 1421 break; 1422 } 1423 1424 mcspi->dma_channels[i].dma_tx_sync_dev = 1425 dma_res->start; 1426 } 1427 } 1428 1429 if (status < 0) 1430 goto free_master; 1431 1432 pm_runtime_use_autosuspend(&pdev->dev); 1433 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); 1434 pm_runtime_enable(&pdev->dev); 1435 1436 status = omap2_mcspi_master_setup(mcspi); 1437 if (status < 0) 1438 goto disable_pm; 1439 1440 status = devm_spi_register_master(&pdev->dev, master); 1441 if (status < 0) 1442 goto disable_pm; 1443 1444 return status; 1445 1446 disable_pm: 1447 pm_runtime_disable(&pdev->dev); 1448 free_master: 1449 spi_master_put(master); 1450 return status; 1451 } 1452 1453 static int omap2_mcspi_remove(struct platform_device *pdev) 1454 { 1455 struct spi_master *master = platform_get_drvdata(pdev); 1456 struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 1457 1458 pm_runtime_put_sync(mcspi->dev); 1459 pm_runtime_disable(&pdev->dev); 1460 1461 return 0; 1462 } 1463 1464 /* work with hotplug and coldplug */ 1465 MODULE_ALIAS("platform:omap2_mcspi"); 1466 1467 #ifdef CONFIG_SUSPEND 1468 /* 1469 * When SPI wake up from off-mode, CS is in activate state. If it was in 1470 * unactive state when driver was suspend, then force it to unactive state at 1471 * wake up. 1472 */ 1473 static int omap2_mcspi_resume(struct device *dev) 1474 { 1475 struct spi_master *master = dev_get_drvdata(dev); 1476 struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 1477 struct omap2_mcspi_regs *ctx = &mcspi->ctx; 1478 struct omap2_mcspi_cs *cs; 1479 1480 pm_runtime_get_sync(mcspi->dev); 1481 list_for_each_entry(cs, &ctx->cs, node) { 1482 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) { 1483 /* 1484 * We need to toggle CS state for OMAP take this 1485 * change in account. 1486 */ 1487 cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE; 1488 writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); 1489 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; 1490 writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); 1491 } 1492 } 1493 pm_runtime_mark_last_busy(mcspi->dev); 1494 pm_runtime_put_autosuspend(mcspi->dev); 1495 return 0; 1496 } 1497 #else 1498 #define omap2_mcspi_resume NULL 1499 #endif 1500 1501 static const struct dev_pm_ops omap2_mcspi_pm_ops = { 1502 .resume = omap2_mcspi_resume, 1503 .runtime_resume = omap_mcspi_runtime_resume, 1504 }; 1505 1506 static struct platform_driver omap2_mcspi_driver = { 1507 .driver = { 1508 .name = "omap2_mcspi", 1509 .owner = THIS_MODULE, 1510 .pm = &omap2_mcspi_pm_ops, 1511 .of_match_table = omap_mcspi_of_match, 1512 }, 1513 .probe = omap2_mcspi_probe, 1514 .remove = omap2_mcspi_remove, 1515 }; 1516 1517 module_platform_driver(omap2_mcspi_driver); 1518 MODULE_LICENSE("GPL"); 1519