1 /* 2 * OMAP2 McSPI controller driver 3 * 4 * Copyright (C) 2005, 2006 Nokia Corporation 5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and 6 * Juha Yrj�l� <juha.yrjola@nokia.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/interrupt.h> 21 #include <linux/module.h> 22 #include <linux/device.h> 23 #include <linux/delay.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/dmaengine.h> 26 #include <linux/pinctrl/consumer.h> 27 #include <linux/platform_device.h> 28 #include <linux/err.h> 29 #include <linux/clk.h> 30 #include <linux/io.h> 31 #include <linux/slab.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/of.h> 34 #include <linux/of_device.h> 35 #include <linux/gcd.h> 36 37 #include <linux/spi/spi.h> 38 #include <linux/gpio.h> 39 40 #include <linux/platform_data/spi-omap2-mcspi.h> 41 42 #define OMAP2_MCSPI_MAX_FREQ 48000000 43 #define OMAP2_MCSPI_MAX_DIVIDER 4096 44 #define OMAP2_MCSPI_MAX_FIFODEPTH 64 45 #define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF 46 #define SPI_AUTOSUSPEND_TIMEOUT 2000 47 48 #define OMAP2_MCSPI_REVISION 0x00 49 #define OMAP2_MCSPI_SYSSTATUS 0x14 50 #define OMAP2_MCSPI_IRQSTATUS 0x18 51 #define OMAP2_MCSPI_IRQENABLE 0x1c 52 #define OMAP2_MCSPI_WAKEUPENABLE 0x20 53 #define OMAP2_MCSPI_SYST 0x24 54 #define OMAP2_MCSPI_MODULCTRL 0x28 55 #define OMAP2_MCSPI_XFERLEVEL 0x7c 56 57 /* per-channel banks, 0x14 bytes each, first is: */ 58 #define OMAP2_MCSPI_CHCONF0 0x2c 59 #define OMAP2_MCSPI_CHSTAT0 0x30 60 #define OMAP2_MCSPI_CHCTRL0 0x34 61 #define OMAP2_MCSPI_TX0 0x38 62 #define OMAP2_MCSPI_RX0 0x3c 63 64 /* per-register bitmasks: */ 65 #define OMAP2_MCSPI_IRQSTATUS_EOW BIT(17) 66 67 #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0) 68 #define OMAP2_MCSPI_MODULCTRL_MS BIT(2) 69 #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3) 70 71 #define OMAP2_MCSPI_CHCONF_PHA BIT(0) 72 #define OMAP2_MCSPI_CHCONF_POL BIT(1) 73 #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2) 74 #define OMAP2_MCSPI_CHCONF_EPOL BIT(6) 75 #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7) 76 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12) 77 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13) 78 #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12) 79 #define OMAP2_MCSPI_CHCONF_DMAW BIT(14) 80 #define OMAP2_MCSPI_CHCONF_DMAR BIT(15) 81 #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16) 82 #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17) 83 #define OMAP2_MCSPI_CHCONF_IS BIT(18) 84 #define OMAP2_MCSPI_CHCONF_TURBO BIT(19) 85 #define OMAP2_MCSPI_CHCONF_FORCE BIT(20) 86 #define OMAP2_MCSPI_CHCONF_FFET BIT(27) 87 #define OMAP2_MCSPI_CHCONF_FFER BIT(28) 88 #define OMAP2_MCSPI_CHCONF_CLKG BIT(29) 89 90 #define OMAP2_MCSPI_CHSTAT_RXS BIT(0) 91 #define OMAP2_MCSPI_CHSTAT_TXS BIT(1) 92 #define OMAP2_MCSPI_CHSTAT_EOT BIT(2) 93 #define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3) 94 95 #define OMAP2_MCSPI_CHCTRL_EN BIT(0) 96 #define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK (0xff << 8) 97 98 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0) 99 100 /* We have 2 DMA channels per CS, one for RX and one for TX */ 101 struct omap2_mcspi_dma { 102 struct dma_chan *dma_tx; 103 struct dma_chan *dma_rx; 104 105 struct completion dma_tx_completion; 106 struct completion dma_rx_completion; 107 108 char dma_rx_ch_name[14]; 109 char dma_tx_ch_name[14]; 110 }; 111 112 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and 113 * cache operations; better heuristics consider wordsize and bitrate. 114 */ 115 #define DMA_MIN_BYTES 160 116 117 118 /* 119 * Used for context save and restore, structure members to be updated whenever 120 * corresponding registers are modified. 121 */ 122 struct omap2_mcspi_regs { 123 u32 modulctrl; 124 u32 wakeupenable; 125 struct list_head cs; 126 }; 127 128 struct omap2_mcspi { 129 struct spi_master *master; 130 /* Virtual base address of the controller */ 131 void __iomem *base; 132 unsigned long phys; 133 /* SPI1 has 4 channels, while SPI2 has 2 */ 134 struct omap2_mcspi_dma *dma_channels; 135 struct device *dev; 136 struct omap2_mcspi_regs ctx; 137 int fifo_depth; 138 unsigned int pin_dir:1; 139 }; 140 141 struct omap2_mcspi_cs { 142 void __iomem *base; 143 unsigned long phys; 144 int word_len; 145 u16 mode; 146 struct list_head node; 147 /* Context save and restore shadow register */ 148 u32 chconf0, chctrl0; 149 }; 150 151 static inline void mcspi_write_reg(struct spi_master *master, 152 int idx, u32 val) 153 { 154 struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 155 156 writel_relaxed(val, mcspi->base + idx); 157 } 158 159 static inline u32 mcspi_read_reg(struct spi_master *master, int idx) 160 { 161 struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 162 163 return readl_relaxed(mcspi->base + idx); 164 } 165 166 static inline void mcspi_write_cs_reg(const struct spi_device *spi, 167 int idx, u32 val) 168 { 169 struct omap2_mcspi_cs *cs = spi->controller_state; 170 171 writel_relaxed(val, cs->base + idx); 172 } 173 174 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx) 175 { 176 struct omap2_mcspi_cs *cs = spi->controller_state; 177 178 return readl_relaxed(cs->base + idx); 179 } 180 181 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi) 182 { 183 struct omap2_mcspi_cs *cs = spi->controller_state; 184 185 return cs->chconf0; 186 } 187 188 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val) 189 { 190 struct omap2_mcspi_cs *cs = spi->controller_state; 191 192 cs->chconf0 = val; 193 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val); 194 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0); 195 } 196 197 static inline int mcspi_bytes_per_word(int word_len) 198 { 199 if (word_len <= 8) 200 return 1; 201 else if (word_len <= 16) 202 return 2; 203 else /* word_len <= 32 */ 204 return 4; 205 } 206 207 static void omap2_mcspi_set_dma_req(const struct spi_device *spi, 208 int is_read, int enable) 209 { 210 u32 l, rw; 211 212 l = mcspi_cached_chconf0(spi); 213 214 if (is_read) /* 1 is read, 0 write */ 215 rw = OMAP2_MCSPI_CHCONF_DMAR; 216 else 217 rw = OMAP2_MCSPI_CHCONF_DMAW; 218 219 if (enable) 220 l |= rw; 221 else 222 l &= ~rw; 223 224 mcspi_write_chconf0(spi, l); 225 } 226 227 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) 228 { 229 struct omap2_mcspi_cs *cs = spi->controller_state; 230 u32 l; 231 232 l = cs->chctrl0; 233 if (enable) 234 l |= OMAP2_MCSPI_CHCTRL_EN; 235 else 236 l &= ~OMAP2_MCSPI_CHCTRL_EN; 237 cs->chctrl0 = l; 238 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); 239 /* Flash post-writes */ 240 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0); 241 } 242 243 static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable) 244 { 245 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); 246 u32 l; 247 248 /* The controller handles the inverted chip selects 249 * using the OMAP2_MCSPI_CHCONF_EPOL bit so revert 250 * the inversion from the core spi_set_cs function. 251 */ 252 if (spi->mode & SPI_CS_HIGH) 253 enable = !enable; 254 255 if (spi->controller_state) { 256 int err = pm_runtime_get_sync(mcspi->dev); 257 if (err < 0) { 258 pm_runtime_put_noidle(mcspi->dev); 259 dev_err(mcspi->dev, "failed to get sync: %d\n", err); 260 return; 261 } 262 263 l = mcspi_cached_chconf0(spi); 264 265 if (enable) 266 l &= ~OMAP2_MCSPI_CHCONF_FORCE; 267 else 268 l |= OMAP2_MCSPI_CHCONF_FORCE; 269 270 mcspi_write_chconf0(spi, l); 271 272 pm_runtime_mark_last_busy(mcspi->dev); 273 pm_runtime_put_autosuspend(mcspi->dev); 274 } 275 } 276 277 static void omap2_mcspi_set_master_mode(struct spi_master *master) 278 { 279 struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 280 struct omap2_mcspi_regs *ctx = &mcspi->ctx; 281 u32 l; 282 283 /* 284 * Setup when switching from (reset default) slave mode 285 * to single-channel master mode 286 */ 287 l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL); 288 l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS); 289 l |= OMAP2_MCSPI_MODULCTRL_SINGLE; 290 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l); 291 292 ctx->modulctrl = l; 293 } 294 295 static void omap2_mcspi_set_fifo(const struct spi_device *spi, 296 struct spi_transfer *t, int enable) 297 { 298 struct spi_master *master = spi->master; 299 struct omap2_mcspi_cs *cs = spi->controller_state; 300 struct omap2_mcspi *mcspi; 301 unsigned int wcnt; 302 int max_fifo_depth, fifo_depth, bytes_per_word; 303 u32 chconf, xferlevel; 304 305 mcspi = spi_master_get_devdata(master); 306 307 chconf = mcspi_cached_chconf0(spi); 308 if (enable) { 309 bytes_per_word = mcspi_bytes_per_word(cs->word_len); 310 if (t->len % bytes_per_word != 0) 311 goto disable_fifo; 312 313 if (t->rx_buf != NULL && t->tx_buf != NULL) 314 max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2; 315 else 316 max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH; 317 318 fifo_depth = gcd(t->len, max_fifo_depth); 319 if (fifo_depth < 2 || fifo_depth % bytes_per_word != 0) 320 goto disable_fifo; 321 322 wcnt = t->len / bytes_per_word; 323 if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT) 324 goto disable_fifo; 325 326 xferlevel = wcnt << 16; 327 if (t->rx_buf != NULL) { 328 chconf |= OMAP2_MCSPI_CHCONF_FFER; 329 xferlevel |= (fifo_depth - 1) << 8; 330 } 331 if (t->tx_buf != NULL) { 332 chconf |= OMAP2_MCSPI_CHCONF_FFET; 333 xferlevel |= fifo_depth - 1; 334 } 335 336 mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel); 337 mcspi_write_chconf0(spi, chconf); 338 mcspi->fifo_depth = fifo_depth; 339 340 return; 341 } 342 343 disable_fifo: 344 if (t->rx_buf != NULL) 345 chconf &= ~OMAP2_MCSPI_CHCONF_FFER; 346 347 if (t->tx_buf != NULL) 348 chconf &= ~OMAP2_MCSPI_CHCONF_FFET; 349 350 mcspi_write_chconf0(spi, chconf); 351 mcspi->fifo_depth = 0; 352 } 353 354 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) 355 { 356 unsigned long timeout; 357 358 timeout = jiffies + msecs_to_jiffies(1000); 359 while (!(readl_relaxed(reg) & bit)) { 360 if (time_after(jiffies, timeout)) { 361 if (!(readl_relaxed(reg) & bit)) 362 return -ETIMEDOUT; 363 else 364 return 0; 365 } 366 cpu_relax(); 367 } 368 return 0; 369 } 370 371 static void omap2_mcspi_rx_callback(void *data) 372 { 373 struct spi_device *spi = data; 374 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); 375 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 376 377 /* We must disable the DMA RX request */ 378 omap2_mcspi_set_dma_req(spi, 1, 0); 379 380 complete(&mcspi_dma->dma_rx_completion); 381 } 382 383 static void omap2_mcspi_tx_callback(void *data) 384 { 385 struct spi_device *spi = data; 386 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); 387 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 388 389 /* We must disable the DMA TX request */ 390 omap2_mcspi_set_dma_req(spi, 0, 0); 391 392 complete(&mcspi_dma->dma_tx_completion); 393 } 394 395 static void omap2_mcspi_tx_dma(struct spi_device *spi, 396 struct spi_transfer *xfer, 397 struct dma_slave_config cfg) 398 { 399 struct omap2_mcspi *mcspi; 400 struct omap2_mcspi_dma *mcspi_dma; 401 unsigned int count; 402 403 mcspi = spi_master_get_devdata(spi->master); 404 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 405 count = xfer->len; 406 407 if (mcspi_dma->dma_tx) { 408 struct dma_async_tx_descriptor *tx; 409 410 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg); 411 412 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, xfer->tx_sg.sgl, 413 xfer->tx_sg.nents, 414 DMA_MEM_TO_DEV, 415 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 416 if (tx) { 417 tx->callback = omap2_mcspi_tx_callback; 418 tx->callback_param = spi; 419 dmaengine_submit(tx); 420 } else { 421 /* FIXME: fall back to PIO? */ 422 } 423 } 424 dma_async_issue_pending(mcspi_dma->dma_tx); 425 omap2_mcspi_set_dma_req(spi, 0, 1); 426 427 } 428 429 static unsigned 430 omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer, 431 struct dma_slave_config cfg, 432 unsigned es) 433 { 434 struct omap2_mcspi *mcspi; 435 struct omap2_mcspi_dma *mcspi_dma; 436 unsigned int count, transfer_reduction = 0; 437 struct scatterlist *sg_out[2]; 438 int nb_sizes = 0, out_mapped_nents[2], ret, x; 439 size_t sizes[2]; 440 u32 l; 441 int elements = 0; 442 int word_len, element_count; 443 struct omap2_mcspi_cs *cs = spi->controller_state; 444 void __iomem *chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; 445 446 mcspi = spi_master_get_devdata(spi->master); 447 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 448 count = xfer->len; 449 450 /* 451 * In the "End-of-Transfer Procedure" section for DMA RX in OMAP35x TRM 452 * it mentions reducing DMA transfer length by one element in master 453 * normal mode. 454 */ 455 if (mcspi->fifo_depth == 0) 456 transfer_reduction = es; 457 458 word_len = cs->word_len; 459 l = mcspi_cached_chconf0(spi); 460 461 if (word_len <= 8) 462 element_count = count; 463 else if (word_len <= 16) 464 element_count = count >> 1; 465 else /* word_len <= 32 */ 466 element_count = count >> 2; 467 468 if (mcspi_dma->dma_rx) { 469 struct dma_async_tx_descriptor *tx; 470 471 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg); 472 473 /* 474 * Reduce DMA transfer length by one more if McSPI is 475 * configured in turbo mode. 476 */ 477 if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0) 478 transfer_reduction += es; 479 480 if (transfer_reduction) { 481 /* Split sgl into two. The second sgl won't be used. */ 482 sizes[0] = count - transfer_reduction; 483 sizes[1] = transfer_reduction; 484 nb_sizes = 2; 485 } else { 486 /* 487 * Don't bother splitting the sgl. This essentially 488 * clones the original sgl. 489 */ 490 sizes[0] = count; 491 nb_sizes = 1; 492 } 493 494 ret = sg_split(xfer->rx_sg.sgl, xfer->rx_sg.nents, 495 0, nb_sizes, 496 sizes, 497 sg_out, out_mapped_nents, 498 GFP_KERNEL); 499 500 if (ret < 0) { 501 dev_err(&spi->dev, "sg_split failed\n"); 502 return 0; 503 } 504 505 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, 506 sg_out[0], 507 out_mapped_nents[0], 508 DMA_DEV_TO_MEM, 509 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 510 if (tx) { 511 tx->callback = omap2_mcspi_rx_callback; 512 tx->callback_param = spi; 513 dmaengine_submit(tx); 514 } else { 515 /* FIXME: fall back to PIO? */ 516 } 517 } 518 519 dma_async_issue_pending(mcspi_dma->dma_rx); 520 omap2_mcspi_set_dma_req(spi, 1, 1); 521 522 wait_for_completion(&mcspi_dma->dma_rx_completion); 523 524 for (x = 0; x < nb_sizes; x++) 525 kfree(sg_out[x]); 526 527 if (mcspi->fifo_depth > 0) 528 return count; 529 530 /* 531 * Due to the DMA transfer length reduction the missing bytes must 532 * be read manually to receive all of the expected data. 533 */ 534 omap2_mcspi_set_enable(spi, 0); 535 536 elements = element_count - 1; 537 538 if (l & OMAP2_MCSPI_CHCONF_TURBO) { 539 elements--; 540 541 if (!mcspi_wait_for_reg_bit(chstat_reg, 542 OMAP2_MCSPI_CHSTAT_RXS)) { 543 u32 w; 544 545 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); 546 if (word_len <= 8) 547 ((u8 *)xfer->rx_buf)[elements++] = w; 548 else if (word_len <= 16) 549 ((u16 *)xfer->rx_buf)[elements++] = w; 550 else /* word_len <= 32 */ 551 ((u32 *)xfer->rx_buf)[elements++] = w; 552 } else { 553 int bytes_per_word = mcspi_bytes_per_word(word_len); 554 dev_err(&spi->dev, "DMA RX penultimate word empty\n"); 555 count -= (bytes_per_word << 1); 556 omap2_mcspi_set_enable(spi, 1); 557 return count; 558 } 559 } 560 if (!mcspi_wait_for_reg_bit(chstat_reg, OMAP2_MCSPI_CHSTAT_RXS)) { 561 u32 w; 562 563 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); 564 if (word_len <= 8) 565 ((u8 *)xfer->rx_buf)[elements] = w; 566 else if (word_len <= 16) 567 ((u16 *)xfer->rx_buf)[elements] = w; 568 else /* word_len <= 32 */ 569 ((u32 *)xfer->rx_buf)[elements] = w; 570 } else { 571 dev_err(&spi->dev, "DMA RX last word empty\n"); 572 count -= mcspi_bytes_per_word(word_len); 573 } 574 omap2_mcspi_set_enable(spi, 1); 575 return count; 576 } 577 578 static unsigned 579 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) 580 { 581 struct omap2_mcspi *mcspi; 582 struct omap2_mcspi_cs *cs = spi->controller_state; 583 struct omap2_mcspi_dma *mcspi_dma; 584 unsigned int count; 585 u32 l; 586 u8 *rx; 587 const u8 *tx; 588 struct dma_slave_config cfg; 589 enum dma_slave_buswidth width; 590 unsigned es; 591 u32 burst; 592 void __iomem *chstat_reg; 593 void __iomem *irqstat_reg; 594 int wait_res; 595 596 mcspi = spi_master_get_devdata(spi->master); 597 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 598 l = mcspi_cached_chconf0(spi); 599 600 601 if (cs->word_len <= 8) { 602 width = DMA_SLAVE_BUSWIDTH_1_BYTE; 603 es = 1; 604 } else if (cs->word_len <= 16) { 605 width = DMA_SLAVE_BUSWIDTH_2_BYTES; 606 es = 2; 607 } else { 608 width = DMA_SLAVE_BUSWIDTH_4_BYTES; 609 es = 4; 610 } 611 612 count = xfer->len; 613 burst = 1; 614 615 if (mcspi->fifo_depth > 0) { 616 if (count > mcspi->fifo_depth) 617 burst = mcspi->fifo_depth / es; 618 else 619 burst = count / es; 620 } 621 622 memset(&cfg, 0, sizeof(cfg)); 623 cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0; 624 cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0; 625 cfg.src_addr_width = width; 626 cfg.dst_addr_width = width; 627 cfg.src_maxburst = burst; 628 cfg.dst_maxburst = burst; 629 630 rx = xfer->rx_buf; 631 tx = xfer->tx_buf; 632 633 if (tx != NULL) 634 omap2_mcspi_tx_dma(spi, xfer, cfg); 635 636 if (rx != NULL) 637 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es); 638 639 if (tx != NULL) { 640 wait_for_completion(&mcspi_dma->dma_tx_completion); 641 642 if (mcspi->fifo_depth > 0) { 643 irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS; 644 645 if (mcspi_wait_for_reg_bit(irqstat_reg, 646 OMAP2_MCSPI_IRQSTATUS_EOW) < 0) 647 dev_err(&spi->dev, "EOW timed out\n"); 648 649 mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS, 650 OMAP2_MCSPI_IRQSTATUS_EOW); 651 } 652 653 /* for TX_ONLY mode, be sure all words have shifted out */ 654 if (rx == NULL) { 655 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; 656 if (mcspi->fifo_depth > 0) { 657 wait_res = mcspi_wait_for_reg_bit(chstat_reg, 658 OMAP2_MCSPI_CHSTAT_TXFFE); 659 if (wait_res < 0) 660 dev_err(&spi->dev, "TXFFE timed out\n"); 661 } else { 662 wait_res = mcspi_wait_for_reg_bit(chstat_reg, 663 OMAP2_MCSPI_CHSTAT_TXS); 664 if (wait_res < 0) 665 dev_err(&spi->dev, "TXS timed out\n"); 666 } 667 if (wait_res >= 0 && 668 (mcspi_wait_for_reg_bit(chstat_reg, 669 OMAP2_MCSPI_CHSTAT_EOT) < 0)) 670 dev_err(&spi->dev, "EOT timed out\n"); 671 } 672 } 673 return count; 674 } 675 676 static unsigned 677 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) 678 { 679 struct omap2_mcspi *mcspi; 680 struct omap2_mcspi_cs *cs = spi->controller_state; 681 unsigned int count, c; 682 u32 l; 683 void __iomem *base = cs->base; 684 void __iomem *tx_reg; 685 void __iomem *rx_reg; 686 void __iomem *chstat_reg; 687 int word_len; 688 689 mcspi = spi_master_get_devdata(spi->master); 690 count = xfer->len; 691 c = count; 692 word_len = cs->word_len; 693 694 l = mcspi_cached_chconf0(spi); 695 696 /* We store the pre-calculated register addresses on stack to speed 697 * up the transfer loop. */ 698 tx_reg = base + OMAP2_MCSPI_TX0; 699 rx_reg = base + OMAP2_MCSPI_RX0; 700 chstat_reg = base + OMAP2_MCSPI_CHSTAT0; 701 702 if (c < (word_len>>3)) 703 return 0; 704 705 if (word_len <= 8) { 706 u8 *rx; 707 const u8 *tx; 708 709 rx = xfer->rx_buf; 710 tx = xfer->tx_buf; 711 712 do { 713 c -= 1; 714 if (tx != NULL) { 715 if (mcspi_wait_for_reg_bit(chstat_reg, 716 OMAP2_MCSPI_CHSTAT_TXS) < 0) { 717 dev_err(&spi->dev, "TXS timed out\n"); 718 goto out; 719 } 720 dev_vdbg(&spi->dev, "write-%d %02x\n", 721 word_len, *tx); 722 writel_relaxed(*tx++, tx_reg); 723 } 724 if (rx != NULL) { 725 if (mcspi_wait_for_reg_bit(chstat_reg, 726 OMAP2_MCSPI_CHSTAT_RXS) < 0) { 727 dev_err(&spi->dev, "RXS timed out\n"); 728 goto out; 729 } 730 731 if (c == 1 && tx == NULL && 732 (l & OMAP2_MCSPI_CHCONF_TURBO)) { 733 omap2_mcspi_set_enable(spi, 0); 734 *rx++ = readl_relaxed(rx_reg); 735 dev_vdbg(&spi->dev, "read-%d %02x\n", 736 word_len, *(rx - 1)); 737 if (mcspi_wait_for_reg_bit(chstat_reg, 738 OMAP2_MCSPI_CHSTAT_RXS) < 0) { 739 dev_err(&spi->dev, 740 "RXS timed out\n"); 741 goto out; 742 } 743 c = 0; 744 } else if (c == 0 && tx == NULL) { 745 omap2_mcspi_set_enable(spi, 0); 746 } 747 748 *rx++ = readl_relaxed(rx_reg); 749 dev_vdbg(&spi->dev, "read-%d %02x\n", 750 word_len, *(rx - 1)); 751 } 752 } while (c); 753 } else if (word_len <= 16) { 754 u16 *rx; 755 const u16 *tx; 756 757 rx = xfer->rx_buf; 758 tx = xfer->tx_buf; 759 do { 760 c -= 2; 761 if (tx != NULL) { 762 if (mcspi_wait_for_reg_bit(chstat_reg, 763 OMAP2_MCSPI_CHSTAT_TXS) < 0) { 764 dev_err(&spi->dev, "TXS timed out\n"); 765 goto out; 766 } 767 dev_vdbg(&spi->dev, "write-%d %04x\n", 768 word_len, *tx); 769 writel_relaxed(*tx++, tx_reg); 770 } 771 if (rx != NULL) { 772 if (mcspi_wait_for_reg_bit(chstat_reg, 773 OMAP2_MCSPI_CHSTAT_RXS) < 0) { 774 dev_err(&spi->dev, "RXS timed out\n"); 775 goto out; 776 } 777 778 if (c == 2 && tx == NULL && 779 (l & OMAP2_MCSPI_CHCONF_TURBO)) { 780 omap2_mcspi_set_enable(spi, 0); 781 *rx++ = readl_relaxed(rx_reg); 782 dev_vdbg(&spi->dev, "read-%d %04x\n", 783 word_len, *(rx - 1)); 784 if (mcspi_wait_for_reg_bit(chstat_reg, 785 OMAP2_MCSPI_CHSTAT_RXS) < 0) { 786 dev_err(&spi->dev, 787 "RXS timed out\n"); 788 goto out; 789 } 790 c = 0; 791 } else if (c == 0 && tx == NULL) { 792 omap2_mcspi_set_enable(spi, 0); 793 } 794 795 *rx++ = readl_relaxed(rx_reg); 796 dev_vdbg(&spi->dev, "read-%d %04x\n", 797 word_len, *(rx - 1)); 798 } 799 } while (c >= 2); 800 } else if (word_len <= 32) { 801 u32 *rx; 802 const u32 *tx; 803 804 rx = xfer->rx_buf; 805 tx = xfer->tx_buf; 806 do { 807 c -= 4; 808 if (tx != NULL) { 809 if (mcspi_wait_for_reg_bit(chstat_reg, 810 OMAP2_MCSPI_CHSTAT_TXS) < 0) { 811 dev_err(&spi->dev, "TXS timed out\n"); 812 goto out; 813 } 814 dev_vdbg(&spi->dev, "write-%d %08x\n", 815 word_len, *tx); 816 writel_relaxed(*tx++, tx_reg); 817 } 818 if (rx != NULL) { 819 if (mcspi_wait_for_reg_bit(chstat_reg, 820 OMAP2_MCSPI_CHSTAT_RXS) < 0) { 821 dev_err(&spi->dev, "RXS timed out\n"); 822 goto out; 823 } 824 825 if (c == 4 && tx == NULL && 826 (l & OMAP2_MCSPI_CHCONF_TURBO)) { 827 omap2_mcspi_set_enable(spi, 0); 828 *rx++ = readl_relaxed(rx_reg); 829 dev_vdbg(&spi->dev, "read-%d %08x\n", 830 word_len, *(rx - 1)); 831 if (mcspi_wait_for_reg_bit(chstat_reg, 832 OMAP2_MCSPI_CHSTAT_RXS) < 0) { 833 dev_err(&spi->dev, 834 "RXS timed out\n"); 835 goto out; 836 } 837 c = 0; 838 } else if (c == 0 && tx == NULL) { 839 omap2_mcspi_set_enable(spi, 0); 840 } 841 842 *rx++ = readl_relaxed(rx_reg); 843 dev_vdbg(&spi->dev, "read-%d %08x\n", 844 word_len, *(rx - 1)); 845 } 846 } while (c >= 4); 847 } 848 849 /* for TX_ONLY mode, be sure all words have shifted out */ 850 if (xfer->rx_buf == NULL) { 851 if (mcspi_wait_for_reg_bit(chstat_reg, 852 OMAP2_MCSPI_CHSTAT_TXS) < 0) { 853 dev_err(&spi->dev, "TXS timed out\n"); 854 } else if (mcspi_wait_for_reg_bit(chstat_reg, 855 OMAP2_MCSPI_CHSTAT_EOT) < 0) 856 dev_err(&spi->dev, "EOT timed out\n"); 857 858 /* disable chan to purge rx datas received in TX_ONLY transfer, 859 * otherwise these rx datas will affect the direct following 860 * RX_ONLY transfer. 861 */ 862 omap2_mcspi_set_enable(spi, 0); 863 } 864 out: 865 omap2_mcspi_set_enable(spi, 1); 866 return count - c; 867 } 868 869 static u32 omap2_mcspi_calc_divisor(u32 speed_hz) 870 { 871 u32 div; 872 873 for (div = 0; div < 15; div++) 874 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div)) 875 return div; 876 877 return 15; 878 } 879 880 /* called only when no transfer is active to this device */ 881 static int omap2_mcspi_setup_transfer(struct spi_device *spi, 882 struct spi_transfer *t) 883 { 884 struct omap2_mcspi_cs *cs = spi->controller_state; 885 struct omap2_mcspi *mcspi; 886 struct spi_master *spi_cntrl; 887 u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0; 888 u8 word_len = spi->bits_per_word; 889 u32 speed_hz = spi->max_speed_hz; 890 891 mcspi = spi_master_get_devdata(spi->master); 892 spi_cntrl = mcspi->master; 893 894 if (t != NULL && t->bits_per_word) 895 word_len = t->bits_per_word; 896 897 cs->word_len = word_len; 898 899 if (t && t->speed_hz) 900 speed_hz = t->speed_hz; 901 902 speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ); 903 if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) { 904 clkd = omap2_mcspi_calc_divisor(speed_hz); 905 speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd; 906 clkg = 0; 907 } else { 908 div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz; 909 speed_hz = OMAP2_MCSPI_MAX_FREQ / div; 910 clkd = (div - 1) & 0xf; 911 extclk = (div - 1) >> 4; 912 clkg = OMAP2_MCSPI_CHCONF_CLKG; 913 } 914 915 l = mcspi_cached_chconf0(spi); 916 917 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS 918 * REVISIT: this controller could support SPI_3WIRE mode. 919 */ 920 if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) { 921 l &= ~OMAP2_MCSPI_CHCONF_IS; 922 l &= ~OMAP2_MCSPI_CHCONF_DPE1; 923 l |= OMAP2_MCSPI_CHCONF_DPE0; 924 } else { 925 l |= OMAP2_MCSPI_CHCONF_IS; 926 l |= OMAP2_MCSPI_CHCONF_DPE1; 927 l &= ~OMAP2_MCSPI_CHCONF_DPE0; 928 } 929 930 /* wordlength */ 931 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK; 932 l |= (word_len - 1) << 7; 933 934 /* set chipselect polarity; manage with FORCE */ 935 if (!(spi->mode & SPI_CS_HIGH)) 936 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */ 937 else 938 l &= ~OMAP2_MCSPI_CHCONF_EPOL; 939 940 /* set clock divisor */ 941 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK; 942 l |= clkd << 2; 943 944 /* set clock granularity */ 945 l &= ~OMAP2_MCSPI_CHCONF_CLKG; 946 l |= clkg; 947 if (clkg) { 948 cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK; 949 cs->chctrl0 |= extclk << 8; 950 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); 951 } 952 953 /* set SPI mode 0..3 */ 954 if (spi->mode & SPI_CPOL) 955 l |= OMAP2_MCSPI_CHCONF_POL; 956 else 957 l &= ~OMAP2_MCSPI_CHCONF_POL; 958 if (spi->mode & SPI_CPHA) 959 l |= OMAP2_MCSPI_CHCONF_PHA; 960 else 961 l &= ~OMAP2_MCSPI_CHCONF_PHA; 962 963 mcspi_write_chconf0(spi, l); 964 965 cs->mode = spi->mode; 966 967 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", 968 speed_hz, 969 (spi->mode & SPI_CPHA) ? "trailing" : "leading", 970 (spi->mode & SPI_CPOL) ? "inverted" : "normal"); 971 972 return 0; 973 } 974 975 /* 976 * Note that we currently allow DMA only if we get a channel 977 * for both rx and tx. Otherwise we'll do PIO for both rx and tx. 978 */ 979 static int omap2_mcspi_request_dma(struct spi_device *spi) 980 { 981 struct spi_master *master = spi->master; 982 struct omap2_mcspi *mcspi; 983 struct omap2_mcspi_dma *mcspi_dma; 984 int ret = 0; 985 986 mcspi = spi_master_get_devdata(master); 987 mcspi_dma = mcspi->dma_channels + spi->chip_select; 988 989 init_completion(&mcspi_dma->dma_rx_completion); 990 init_completion(&mcspi_dma->dma_tx_completion); 991 992 mcspi_dma->dma_rx = dma_request_chan(&master->dev, 993 mcspi_dma->dma_rx_ch_name); 994 if (IS_ERR(mcspi_dma->dma_rx)) { 995 ret = PTR_ERR(mcspi_dma->dma_rx); 996 mcspi_dma->dma_rx = NULL; 997 goto no_dma; 998 } 999 1000 mcspi_dma->dma_tx = dma_request_chan(&master->dev, 1001 mcspi_dma->dma_tx_ch_name); 1002 if (IS_ERR(mcspi_dma->dma_tx)) { 1003 ret = PTR_ERR(mcspi_dma->dma_tx); 1004 mcspi_dma->dma_tx = NULL; 1005 dma_release_channel(mcspi_dma->dma_rx); 1006 mcspi_dma->dma_rx = NULL; 1007 } 1008 1009 no_dma: 1010 return ret; 1011 } 1012 1013 static int omap2_mcspi_setup(struct spi_device *spi) 1014 { 1015 int ret; 1016 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); 1017 struct omap2_mcspi_regs *ctx = &mcspi->ctx; 1018 struct omap2_mcspi_dma *mcspi_dma; 1019 struct omap2_mcspi_cs *cs = spi->controller_state; 1020 1021 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 1022 1023 if (!cs) { 1024 cs = kzalloc(sizeof *cs, GFP_KERNEL); 1025 if (!cs) 1026 return -ENOMEM; 1027 cs->base = mcspi->base + spi->chip_select * 0x14; 1028 cs->phys = mcspi->phys + spi->chip_select * 0x14; 1029 cs->mode = 0; 1030 cs->chconf0 = 0; 1031 cs->chctrl0 = 0; 1032 spi->controller_state = cs; 1033 /* Link this to context save list */ 1034 list_add_tail(&cs->node, &ctx->cs); 1035 1036 if (gpio_is_valid(spi->cs_gpio)) { 1037 ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev)); 1038 if (ret) { 1039 dev_err(&spi->dev, "failed to request gpio\n"); 1040 return ret; 1041 } 1042 gpio_direction_output(spi->cs_gpio, 1043 !(spi->mode & SPI_CS_HIGH)); 1044 } 1045 } 1046 1047 if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) { 1048 ret = omap2_mcspi_request_dma(spi); 1049 if (ret) 1050 dev_warn(&spi->dev, "not using DMA for McSPI (%d)\n", 1051 ret); 1052 } 1053 1054 ret = pm_runtime_get_sync(mcspi->dev); 1055 if (ret < 0) { 1056 pm_runtime_put_noidle(mcspi->dev); 1057 1058 return ret; 1059 } 1060 1061 ret = omap2_mcspi_setup_transfer(spi, NULL); 1062 pm_runtime_mark_last_busy(mcspi->dev); 1063 pm_runtime_put_autosuspend(mcspi->dev); 1064 1065 return ret; 1066 } 1067 1068 static void omap2_mcspi_cleanup(struct spi_device *spi) 1069 { 1070 struct omap2_mcspi *mcspi; 1071 struct omap2_mcspi_dma *mcspi_dma; 1072 struct omap2_mcspi_cs *cs; 1073 1074 mcspi = spi_master_get_devdata(spi->master); 1075 1076 if (spi->controller_state) { 1077 /* Unlink controller state from context save list */ 1078 cs = spi->controller_state; 1079 list_del(&cs->node); 1080 1081 kfree(cs); 1082 } 1083 1084 if (spi->chip_select < spi->master->num_chipselect) { 1085 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 1086 1087 if (mcspi_dma->dma_rx) { 1088 dma_release_channel(mcspi_dma->dma_rx); 1089 mcspi_dma->dma_rx = NULL; 1090 } 1091 if (mcspi_dma->dma_tx) { 1092 dma_release_channel(mcspi_dma->dma_tx); 1093 mcspi_dma->dma_tx = NULL; 1094 } 1095 } 1096 1097 if (gpio_is_valid(spi->cs_gpio)) 1098 gpio_free(spi->cs_gpio); 1099 } 1100 1101 static int omap2_mcspi_transfer_one(struct spi_master *master, 1102 struct spi_device *spi, 1103 struct spi_transfer *t) 1104 { 1105 1106 /* We only enable one channel at a time -- the one whose message is 1107 * -- although this controller would gladly 1108 * arbitrate among multiple channels. This corresponds to "single 1109 * channel" master mode. As a side effect, we need to manage the 1110 * chipselect with the FORCE bit ... CS != channel enable. 1111 */ 1112 1113 struct omap2_mcspi *mcspi; 1114 struct omap2_mcspi_dma *mcspi_dma; 1115 struct omap2_mcspi_cs *cs; 1116 struct omap2_mcspi_device_config *cd; 1117 int par_override = 0; 1118 int status = 0; 1119 u32 chconf; 1120 1121 mcspi = spi_master_get_devdata(master); 1122 mcspi_dma = mcspi->dma_channels + spi->chip_select; 1123 cs = spi->controller_state; 1124 cd = spi->controller_data; 1125 1126 /* 1127 * The slave driver could have changed spi->mode in which case 1128 * it will be different from cs->mode (the current hardware setup). 1129 * If so, set par_override (even though its not a parity issue) so 1130 * omap2_mcspi_setup_transfer will be called to configure the hardware 1131 * with the correct mode on the first iteration of the loop below. 1132 */ 1133 if (spi->mode != cs->mode) 1134 par_override = 1; 1135 1136 omap2_mcspi_set_enable(spi, 0); 1137 1138 if (gpio_is_valid(spi->cs_gpio)) 1139 omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH); 1140 1141 if (par_override || 1142 (t->speed_hz != spi->max_speed_hz) || 1143 (t->bits_per_word != spi->bits_per_word)) { 1144 par_override = 1; 1145 status = omap2_mcspi_setup_transfer(spi, t); 1146 if (status < 0) 1147 goto out; 1148 if (t->speed_hz == spi->max_speed_hz && 1149 t->bits_per_word == spi->bits_per_word) 1150 par_override = 0; 1151 } 1152 if (cd && cd->cs_per_word) { 1153 chconf = mcspi->ctx.modulctrl; 1154 chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE; 1155 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf); 1156 mcspi->ctx.modulctrl = 1157 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); 1158 } 1159 1160 chconf = mcspi_cached_chconf0(spi); 1161 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; 1162 chconf &= ~OMAP2_MCSPI_CHCONF_TURBO; 1163 1164 if (t->tx_buf == NULL) 1165 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY; 1166 else if (t->rx_buf == NULL) 1167 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY; 1168 1169 if (cd && cd->turbo_mode && t->tx_buf == NULL) { 1170 /* Turbo mode is for more than one word */ 1171 if (t->len > ((cs->word_len + 7) >> 3)) 1172 chconf |= OMAP2_MCSPI_CHCONF_TURBO; 1173 } 1174 1175 mcspi_write_chconf0(spi, chconf); 1176 1177 if (t->len) { 1178 unsigned count; 1179 1180 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && 1181 master->cur_msg_mapped && 1182 master->can_dma(master, spi, t)) 1183 omap2_mcspi_set_fifo(spi, t, 1); 1184 1185 omap2_mcspi_set_enable(spi, 1); 1186 1187 /* RX_ONLY mode needs dummy data in TX reg */ 1188 if (t->tx_buf == NULL) 1189 writel_relaxed(0, cs->base 1190 + OMAP2_MCSPI_TX0); 1191 1192 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && 1193 master->cur_msg_mapped && 1194 master->can_dma(master, spi, t)) 1195 count = omap2_mcspi_txrx_dma(spi, t); 1196 else 1197 count = omap2_mcspi_txrx_pio(spi, t); 1198 1199 if (count != t->len) { 1200 status = -EIO; 1201 goto out; 1202 } 1203 } 1204 1205 omap2_mcspi_set_enable(spi, 0); 1206 1207 if (mcspi->fifo_depth > 0) 1208 omap2_mcspi_set_fifo(spi, t, 0); 1209 1210 out: 1211 /* Restore defaults if they were overriden */ 1212 if (par_override) { 1213 par_override = 0; 1214 status = omap2_mcspi_setup_transfer(spi, NULL); 1215 } 1216 1217 if (cd && cd->cs_per_word) { 1218 chconf = mcspi->ctx.modulctrl; 1219 chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE; 1220 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf); 1221 mcspi->ctx.modulctrl = 1222 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); 1223 } 1224 1225 omap2_mcspi_set_enable(spi, 0); 1226 1227 if (gpio_is_valid(spi->cs_gpio)) 1228 omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH)); 1229 1230 if (mcspi->fifo_depth > 0 && t) 1231 omap2_mcspi_set_fifo(spi, t, 0); 1232 1233 return status; 1234 } 1235 1236 static int omap2_mcspi_prepare_message(struct spi_master *master, 1237 struct spi_message *msg) 1238 { 1239 struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 1240 struct omap2_mcspi_regs *ctx = &mcspi->ctx; 1241 struct omap2_mcspi_cs *cs; 1242 1243 /* Only a single channel can have the FORCE bit enabled 1244 * in its chconf0 register. 1245 * Scan all channels and disable them except the current one. 1246 * A FORCE can remain from a last transfer having cs_change enabled 1247 */ 1248 list_for_each_entry(cs, &ctx->cs, node) { 1249 if (msg->spi->controller_state == cs) 1250 continue; 1251 1252 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE)) { 1253 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; 1254 writel_relaxed(cs->chconf0, 1255 cs->base + OMAP2_MCSPI_CHCONF0); 1256 readl_relaxed(cs->base + OMAP2_MCSPI_CHCONF0); 1257 } 1258 } 1259 1260 return 0; 1261 } 1262 1263 static bool omap2_mcspi_can_dma(struct spi_master *master, 1264 struct spi_device *spi, 1265 struct spi_transfer *xfer) 1266 { 1267 return (xfer->len >= DMA_MIN_BYTES); 1268 } 1269 1270 static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi) 1271 { 1272 struct spi_master *master = mcspi->master; 1273 struct omap2_mcspi_regs *ctx = &mcspi->ctx; 1274 int ret = 0; 1275 1276 ret = pm_runtime_get_sync(mcspi->dev); 1277 if (ret < 0) { 1278 pm_runtime_put_noidle(mcspi->dev); 1279 1280 return ret; 1281 } 1282 1283 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, 1284 OMAP2_MCSPI_WAKEUPENABLE_WKEN); 1285 ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN; 1286 1287 omap2_mcspi_set_master_mode(master); 1288 pm_runtime_mark_last_busy(mcspi->dev); 1289 pm_runtime_put_autosuspend(mcspi->dev); 1290 return 0; 1291 } 1292 1293 /* 1294 * When SPI wake up from off-mode, CS is in activate state. If it was in 1295 * inactive state when driver was suspend, then force it to inactive state at 1296 * wake up. 1297 */ 1298 static int omap_mcspi_runtime_resume(struct device *dev) 1299 { 1300 struct spi_master *master = dev_get_drvdata(dev); 1301 struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 1302 struct omap2_mcspi_regs *ctx = &mcspi->ctx; 1303 struct omap2_mcspi_cs *cs; 1304 1305 /* McSPI: context restore */ 1306 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl); 1307 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable); 1308 1309 list_for_each_entry(cs, &ctx->cs, node) { 1310 /* 1311 * We need to toggle CS state for OMAP take this 1312 * change in account. 1313 */ 1314 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) { 1315 cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE; 1316 writel_relaxed(cs->chconf0, 1317 cs->base + OMAP2_MCSPI_CHCONF0); 1318 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; 1319 writel_relaxed(cs->chconf0, 1320 cs->base + OMAP2_MCSPI_CHCONF0); 1321 } else { 1322 writel_relaxed(cs->chconf0, 1323 cs->base + OMAP2_MCSPI_CHCONF0); 1324 } 1325 } 1326 1327 return 0; 1328 } 1329 1330 static struct omap2_mcspi_platform_config omap2_pdata = { 1331 .regs_offset = 0, 1332 }; 1333 1334 static struct omap2_mcspi_platform_config omap4_pdata = { 1335 .regs_offset = OMAP4_MCSPI_REG_OFFSET, 1336 }; 1337 1338 static const struct of_device_id omap_mcspi_of_match[] = { 1339 { 1340 .compatible = "ti,omap2-mcspi", 1341 .data = &omap2_pdata, 1342 }, 1343 { 1344 .compatible = "ti,omap4-mcspi", 1345 .data = &omap4_pdata, 1346 }, 1347 { }, 1348 }; 1349 MODULE_DEVICE_TABLE(of, omap_mcspi_of_match); 1350 1351 static int omap2_mcspi_probe(struct platform_device *pdev) 1352 { 1353 struct spi_master *master; 1354 const struct omap2_mcspi_platform_config *pdata; 1355 struct omap2_mcspi *mcspi; 1356 struct resource *r; 1357 int status = 0, i; 1358 u32 regs_offset = 0; 1359 struct device_node *node = pdev->dev.of_node; 1360 const struct of_device_id *match; 1361 1362 master = spi_alloc_master(&pdev->dev, sizeof *mcspi); 1363 if (master == NULL) { 1364 dev_dbg(&pdev->dev, "master allocation failed\n"); 1365 return -ENOMEM; 1366 } 1367 1368 /* the spi->mode bits understood by this driver: */ 1369 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1370 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1371 master->setup = omap2_mcspi_setup; 1372 master->auto_runtime_pm = true; 1373 master->prepare_message = omap2_mcspi_prepare_message; 1374 master->can_dma = omap2_mcspi_can_dma; 1375 master->transfer_one = omap2_mcspi_transfer_one; 1376 master->set_cs = omap2_mcspi_set_cs; 1377 master->cleanup = omap2_mcspi_cleanup; 1378 master->dev.of_node = node; 1379 master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ; 1380 master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15; 1381 1382 platform_set_drvdata(pdev, master); 1383 1384 mcspi = spi_master_get_devdata(master); 1385 mcspi->master = master; 1386 1387 match = of_match_device(omap_mcspi_of_match, &pdev->dev); 1388 if (match) { 1389 u32 num_cs = 1; /* default number of chipselect */ 1390 pdata = match->data; 1391 1392 of_property_read_u32(node, "ti,spi-num-cs", &num_cs); 1393 master->num_chipselect = num_cs; 1394 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL)) 1395 mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN; 1396 } else { 1397 pdata = dev_get_platdata(&pdev->dev); 1398 master->num_chipselect = pdata->num_cs; 1399 mcspi->pin_dir = pdata->pin_dir; 1400 } 1401 regs_offset = pdata->regs_offset; 1402 1403 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1404 mcspi->base = devm_ioremap_resource(&pdev->dev, r); 1405 if (IS_ERR(mcspi->base)) { 1406 status = PTR_ERR(mcspi->base); 1407 goto free_master; 1408 } 1409 mcspi->phys = r->start + regs_offset; 1410 mcspi->base += regs_offset; 1411 1412 mcspi->dev = &pdev->dev; 1413 1414 INIT_LIST_HEAD(&mcspi->ctx.cs); 1415 1416 mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect, 1417 sizeof(struct omap2_mcspi_dma), 1418 GFP_KERNEL); 1419 if (mcspi->dma_channels == NULL) { 1420 status = -ENOMEM; 1421 goto free_master; 1422 } 1423 1424 for (i = 0; i < master->num_chipselect; i++) { 1425 sprintf(mcspi->dma_channels[i].dma_rx_ch_name, "rx%d", i); 1426 sprintf(mcspi->dma_channels[i].dma_tx_ch_name, "tx%d", i); 1427 } 1428 1429 pm_runtime_use_autosuspend(&pdev->dev); 1430 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); 1431 pm_runtime_enable(&pdev->dev); 1432 1433 status = omap2_mcspi_master_setup(mcspi); 1434 if (status < 0) 1435 goto disable_pm; 1436 1437 status = devm_spi_register_master(&pdev->dev, master); 1438 if (status < 0) 1439 goto disable_pm; 1440 1441 return status; 1442 1443 disable_pm: 1444 pm_runtime_dont_use_autosuspend(&pdev->dev); 1445 pm_runtime_put_sync(&pdev->dev); 1446 pm_runtime_disable(&pdev->dev); 1447 free_master: 1448 spi_master_put(master); 1449 return status; 1450 } 1451 1452 static int omap2_mcspi_remove(struct platform_device *pdev) 1453 { 1454 struct spi_master *master = platform_get_drvdata(pdev); 1455 struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 1456 1457 pm_runtime_dont_use_autosuspend(mcspi->dev); 1458 pm_runtime_put_sync(mcspi->dev); 1459 pm_runtime_disable(&pdev->dev); 1460 1461 return 0; 1462 } 1463 1464 /* work with hotplug and coldplug */ 1465 MODULE_ALIAS("platform:omap2_mcspi"); 1466 1467 #ifdef CONFIG_SUSPEND 1468 static int omap2_mcspi_suspend_noirq(struct device *dev) 1469 { 1470 return pinctrl_pm_select_sleep_state(dev); 1471 } 1472 1473 static int omap2_mcspi_resume_noirq(struct device *dev) 1474 { 1475 struct spi_master *master = dev_get_drvdata(dev); 1476 struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 1477 int error; 1478 1479 error = pinctrl_pm_select_default_state(dev); 1480 if (error) 1481 dev_warn(mcspi->dev, "%s: failed to set pins: %i\n", 1482 __func__, error); 1483 1484 return 0; 1485 } 1486 1487 #else 1488 #define omap2_mcspi_suspend_noirq NULL 1489 #define omap2_mcspi_resume_noirq NULL 1490 #endif 1491 1492 static const struct dev_pm_ops omap2_mcspi_pm_ops = { 1493 .suspend_noirq = omap2_mcspi_suspend_noirq, 1494 .resume_noirq = omap2_mcspi_resume_noirq, 1495 .runtime_resume = omap_mcspi_runtime_resume, 1496 }; 1497 1498 static struct platform_driver omap2_mcspi_driver = { 1499 .driver = { 1500 .name = "omap2_mcspi", 1501 .pm = &omap2_mcspi_pm_ops, 1502 .of_match_table = omap_mcspi_of_match, 1503 }, 1504 .probe = omap2_mcspi_probe, 1505 .remove = omap2_mcspi_remove, 1506 }; 1507 1508 module_platform_driver(omap2_mcspi_driver); 1509 MODULE_LICENSE("GPL"); 1510