1 /* 2 * OMAP2 McSPI controller driver 3 * 4 * Copyright (C) 2005, 2006 Nokia Corporation 5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and 6 * Juha Yrj�l� <juha.yrjola@nokia.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 * 22 */ 23 24 #include <linux/kernel.h> 25 #include <linux/init.h> 26 #include <linux/interrupt.h> 27 #include <linux/module.h> 28 #include <linux/device.h> 29 #include <linux/delay.h> 30 #include <linux/dma-mapping.h> 31 #include <linux/dmaengine.h> 32 #include <linux/omap-dma.h> 33 #include <linux/platform_device.h> 34 #include <linux/err.h> 35 #include <linux/clk.h> 36 #include <linux/io.h> 37 #include <linux/slab.h> 38 #include <linux/pm_runtime.h> 39 #include <linux/of.h> 40 #include <linux/of_device.h> 41 #include <linux/gcd.h> 42 43 #include <linux/spi/spi.h> 44 45 #include <linux/platform_data/spi-omap2-mcspi.h> 46 47 #define OMAP2_MCSPI_MAX_FREQ 48000000 48 #define OMAP2_MCSPI_MAX_FIFODEPTH 64 49 #define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF 50 #define SPI_AUTOSUSPEND_TIMEOUT 2000 51 52 #define OMAP2_MCSPI_REVISION 0x00 53 #define OMAP2_MCSPI_SYSSTATUS 0x14 54 #define OMAP2_MCSPI_IRQSTATUS 0x18 55 #define OMAP2_MCSPI_IRQENABLE 0x1c 56 #define OMAP2_MCSPI_WAKEUPENABLE 0x20 57 #define OMAP2_MCSPI_SYST 0x24 58 #define OMAP2_MCSPI_MODULCTRL 0x28 59 #define OMAP2_MCSPI_XFERLEVEL 0x7c 60 61 /* per-channel banks, 0x14 bytes each, first is: */ 62 #define OMAP2_MCSPI_CHCONF0 0x2c 63 #define OMAP2_MCSPI_CHSTAT0 0x30 64 #define OMAP2_MCSPI_CHCTRL0 0x34 65 #define OMAP2_MCSPI_TX0 0x38 66 #define OMAP2_MCSPI_RX0 0x3c 67 68 /* per-register bitmasks: */ 69 #define OMAP2_MCSPI_IRQSTATUS_EOW BIT(17) 70 71 #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0) 72 #define OMAP2_MCSPI_MODULCTRL_MS BIT(2) 73 #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3) 74 75 #define OMAP2_MCSPI_CHCONF_PHA BIT(0) 76 #define OMAP2_MCSPI_CHCONF_POL BIT(1) 77 #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2) 78 #define OMAP2_MCSPI_CHCONF_EPOL BIT(6) 79 #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7) 80 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12) 81 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13) 82 #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12) 83 #define OMAP2_MCSPI_CHCONF_DMAW BIT(14) 84 #define OMAP2_MCSPI_CHCONF_DMAR BIT(15) 85 #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16) 86 #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17) 87 #define OMAP2_MCSPI_CHCONF_IS BIT(18) 88 #define OMAP2_MCSPI_CHCONF_TURBO BIT(19) 89 #define OMAP2_MCSPI_CHCONF_FORCE BIT(20) 90 #define OMAP2_MCSPI_CHCONF_FFET BIT(27) 91 #define OMAP2_MCSPI_CHCONF_FFER BIT(28) 92 93 #define OMAP2_MCSPI_CHSTAT_RXS BIT(0) 94 #define OMAP2_MCSPI_CHSTAT_TXS BIT(1) 95 #define OMAP2_MCSPI_CHSTAT_EOT BIT(2) 96 #define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3) 97 98 #define OMAP2_MCSPI_CHCTRL_EN BIT(0) 99 100 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0) 101 102 /* We have 2 DMA channels per CS, one for RX and one for TX */ 103 struct omap2_mcspi_dma { 104 struct dma_chan *dma_tx; 105 struct dma_chan *dma_rx; 106 107 int dma_tx_sync_dev; 108 int dma_rx_sync_dev; 109 110 struct completion dma_tx_completion; 111 struct completion dma_rx_completion; 112 113 char dma_rx_ch_name[14]; 114 char dma_tx_ch_name[14]; 115 }; 116 117 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and 118 * cache operations; better heuristics consider wordsize and bitrate. 119 */ 120 #define DMA_MIN_BYTES 160 121 122 123 /* 124 * Used for context save and restore, structure members to be updated whenever 125 * corresponding registers are modified. 126 */ 127 struct omap2_mcspi_regs { 128 u32 modulctrl; 129 u32 wakeupenable; 130 struct list_head cs; 131 }; 132 133 struct omap2_mcspi { 134 struct spi_master *master; 135 /* Virtual base address of the controller */ 136 void __iomem *base; 137 unsigned long phys; 138 /* SPI1 has 4 channels, while SPI2 has 2 */ 139 struct omap2_mcspi_dma *dma_channels; 140 struct device *dev; 141 struct omap2_mcspi_regs ctx; 142 int fifo_depth; 143 unsigned int pin_dir:1; 144 }; 145 146 struct omap2_mcspi_cs { 147 void __iomem *base; 148 unsigned long phys; 149 int word_len; 150 struct list_head node; 151 /* Context save and restore shadow register */ 152 u32 chconf0; 153 }; 154 155 static inline void mcspi_write_reg(struct spi_master *master, 156 int idx, u32 val) 157 { 158 struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 159 160 __raw_writel(val, mcspi->base + idx); 161 } 162 163 static inline u32 mcspi_read_reg(struct spi_master *master, int idx) 164 { 165 struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 166 167 return __raw_readl(mcspi->base + idx); 168 } 169 170 static inline void mcspi_write_cs_reg(const struct spi_device *spi, 171 int idx, u32 val) 172 { 173 struct omap2_mcspi_cs *cs = spi->controller_state; 174 175 __raw_writel(val, cs->base + idx); 176 } 177 178 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx) 179 { 180 struct omap2_mcspi_cs *cs = spi->controller_state; 181 182 return __raw_readl(cs->base + idx); 183 } 184 185 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi) 186 { 187 struct omap2_mcspi_cs *cs = spi->controller_state; 188 189 return cs->chconf0; 190 } 191 192 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val) 193 { 194 struct omap2_mcspi_cs *cs = spi->controller_state; 195 196 cs->chconf0 = val; 197 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val); 198 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0); 199 } 200 201 static inline int mcspi_bytes_per_word(int word_len) 202 { 203 if (word_len <= 8) 204 return 1; 205 else if (word_len <= 16) 206 return 2; 207 else /* word_len <= 32 */ 208 return 4; 209 } 210 211 static void omap2_mcspi_set_dma_req(const struct spi_device *spi, 212 int is_read, int enable) 213 { 214 u32 l, rw; 215 216 l = mcspi_cached_chconf0(spi); 217 218 if (is_read) /* 1 is read, 0 write */ 219 rw = OMAP2_MCSPI_CHCONF_DMAR; 220 else 221 rw = OMAP2_MCSPI_CHCONF_DMAW; 222 223 if (enable) 224 l |= rw; 225 else 226 l &= ~rw; 227 228 mcspi_write_chconf0(spi, l); 229 } 230 231 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) 232 { 233 u32 l; 234 235 l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0; 236 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l); 237 /* Flash post-writes */ 238 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0); 239 } 240 241 static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active) 242 { 243 u32 l; 244 245 l = mcspi_cached_chconf0(spi); 246 if (cs_active) 247 l |= OMAP2_MCSPI_CHCONF_FORCE; 248 else 249 l &= ~OMAP2_MCSPI_CHCONF_FORCE; 250 251 mcspi_write_chconf0(spi, l); 252 } 253 254 static void omap2_mcspi_set_master_mode(struct spi_master *master) 255 { 256 struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 257 struct omap2_mcspi_regs *ctx = &mcspi->ctx; 258 u32 l; 259 260 /* 261 * Setup when switching from (reset default) slave mode 262 * to single-channel master mode 263 */ 264 l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL); 265 l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS); 266 l |= OMAP2_MCSPI_MODULCTRL_SINGLE; 267 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l); 268 269 ctx->modulctrl = l; 270 } 271 272 static void omap2_mcspi_set_fifo(const struct spi_device *spi, 273 struct spi_transfer *t, int enable) 274 { 275 struct spi_master *master = spi->master; 276 struct omap2_mcspi_cs *cs = spi->controller_state; 277 struct omap2_mcspi *mcspi; 278 unsigned int wcnt; 279 int max_fifo_depth, fifo_depth, bytes_per_word; 280 u32 chconf, xferlevel; 281 282 mcspi = spi_master_get_devdata(master); 283 284 chconf = mcspi_cached_chconf0(spi); 285 if (enable) { 286 bytes_per_word = mcspi_bytes_per_word(cs->word_len); 287 if (t->len % bytes_per_word != 0) 288 goto disable_fifo; 289 290 if (t->rx_buf != NULL && t->tx_buf != NULL) 291 max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2; 292 else 293 max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH; 294 295 fifo_depth = gcd(t->len, max_fifo_depth); 296 if (fifo_depth < 2 || fifo_depth % bytes_per_word != 0) 297 goto disable_fifo; 298 299 wcnt = t->len / bytes_per_word; 300 if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT) 301 goto disable_fifo; 302 303 xferlevel = wcnt << 16; 304 if (t->rx_buf != NULL) { 305 chconf |= OMAP2_MCSPI_CHCONF_FFER; 306 xferlevel |= (fifo_depth - 1) << 8; 307 } 308 if (t->tx_buf != NULL) { 309 chconf |= OMAP2_MCSPI_CHCONF_FFET; 310 xferlevel |= fifo_depth - 1; 311 } 312 313 mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel); 314 mcspi_write_chconf0(spi, chconf); 315 mcspi->fifo_depth = fifo_depth; 316 317 return; 318 } 319 320 disable_fifo: 321 if (t->rx_buf != NULL) 322 chconf &= ~OMAP2_MCSPI_CHCONF_FFER; 323 else 324 chconf &= ~OMAP2_MCSPI_CHCONF_FFET; 325 326 mcspi_write_chconf0(spi, chconf); 327 mcspi->fifo_depth = 0; 328 } 329 330 static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi) 331 { 332 struct spi_master *spi_cntrl = mcspi->master; 333 struct omap2_mcspi_regs *ctx = &mcspi->ctx; 334 struct omap2_mcspi_cs *cs; 335 336 /* McSPI: context restore */ 337 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl); 338 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable); 339 340 list_for_each_entry(cs, &ctx->cs, node) 341 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); 342 } 343 344 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) 345 { 346 unsigned long timeout; 347 348 timeout = jiffies + msecs_to_jiffies(1000); 349 while (!(__raw_readl(reg) & bit)) { 350 if (time_after(jiffies, timeout)) { 351 if (!(__raw_readl(reg) & bit)) 352 return -ETIMEDOUT; 353 else 354 return 0; 355 } 356 cpu_relax(); 357 } 358 return 0; 359 } 360 361 static void omap2_mcspi_rx_callback(void *data) 362 { 363 struct spi_device *spi = data; 364 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); 365 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 366 367 /* We must disable the DMA RX request */ 368 omap2_mcspi_set_dma_req(spi, 1, 0); 369 370 complete(&mcspi_dma->dma_rx_completion); 371 } 372 373 static void omap2_mcspi_tx_callback(void *data) 374 { 375 struct spi_device *spi = data; 376 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); 377 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 378 379 /* We must disable the DMA TX request */ 380 omap2_mcspi_set_dma_req(spi, 0, 0); 381 382 complete(&mcspi_dma->dma_tx_completion); 383 } 384 385 static void omap2_mcspi_tx_dma(struct spi_device *spi, 386 struct spi_transfer *xfer, 387 struct dma_slave_config cfg) 388 { 389 struct omap2_mcspi *mcspi; 390 struct omap2_mcspi_dma *mcspi_dma; 391 unsigned int count; 392 393 mcspi = spi_master_get_devdata(spi->master); 394 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 395 count = xfer->len; 396 397 if (mcspi_dma->dma_tx) { 398 struct dma_async_tx_descriptor *tx; 399 struct scatterlist sg; 400 401 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg); 402 403 sg_init_table(&sg, 1); 404 sg_dma_address(&sg) = xfer->tx_dma; 405 sg_dma_len(&sg) = xfer->len; 406 407 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1, 408 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 409 if (tx) { 410 tx->callback = omap2_mcspi_tx_callback; 411 tx->callback_param = spi; 412 dmaengine_submit(tx); 413 } else { 414 /* FIXME: fall back to PIO? */ 415 } 416 } 417 dma_async_issue_pending(mcspi_dma->dma_tx); 418 omap2_mcspi_set_dma_req(spi, 0, 1); 419 420 } 421 422 static unsigned 423 omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer, 424 struct dma_slave_config cfg, 425 unsigned es) 426 { 427 struct omap2_mcspi *mcspi; 428 struct omap2_mcspi_dma *mcspi_dma; 429 unsigned int count, dma_count; 430 u32 l; 431 int elements = 0; 432 int word_len, element_count; 433 struct omap2_mcspi_cs *cs = spi->controller_state; 434 mcspi = spi_master_get_devdata(spi->master); 435 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 436 count = xfer->len; 437 dma_count = xfer->len; 438 439 if (mcspi->fifo_depth == 0) 440 dma_count -= es; 441 442 word_len = cs->word_len; 443 l = mcspi_cached_chconf0(spi); 444 445 if (word_len <= 8) 446 element_count = count; 447 else if (word_len <= 16) 448 element_count = count >> 1; 449 else /* word_len <= 32 */ 450 element_count = count >> 2; 451 452 if (mcspi_dma->dma_rx) { 453 struct dma_async_tx_descriptor *tx; 454 struct scatterlist sg; 455 456 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg); 457 458 if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0) 459 dma_count -= es; 460 461 sg_init_table(&sg, 1); 462 sg_dma_address(&sg) = xfer->rx_dma; 463 sg_dma_len(&sg) = dma_count; 464 465 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1, 466 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | 467 DMA_CTRL_ACK); 468 if (tx) { 469 tx->callback = omap2_mcspi_rx_callback; 470 tx->callback_param = spi; 471 dmaengine_submit(tx); 472 } else { 473 /* FIXME: fall back to PIO? */ 474 } 475 } 476 477 dma_async_issue_pending(mcspi_dma->dma_rx); 478 omap2_mcspi_set_dma_req(spi, 1, 1); 479 480 wait_for_completion(&mcspi_dma->dma_rx_completion); 481 dma_unmap_single(mcspi->dev, xfer->rx_dma, count, 482 DMA_FROM_DEVICE); 483 484 if (mcspi->fifo_depth > 0) 485 return count; 486 487 omap2_mcspi_set_enable(spi, 0); 488 489 elements = element_count - 1; 490 491 if (l & OMAP2_MCSPI_CHCONF_TURBO) { 492 elements--; 493 494 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) 495 & OMAP2_MCSPI_CHSTAT_RXS)) { 496 u32 w; 497 498 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); 499 if (word_len <= 8) 500 ((u8 *)xfer->rx_buf)[elements++] = w; 501 else if (word_len <= 16) 502 ((u16 *)xfer->rx_buf)[elements++] = w; 503 else /* word_len <= 32 */ 504 ((u32 *)xfer->rx_buf)[elements++] = w; 505 } else { 506 int bytes_per_word = mcspi_bytes_per_word(word_len); 507 dev_err(&spi->dev, "DMA RX penultimate word empty\n"); 508 count -= (bytes_per_word << 1); 509 omap2_mcspi_set_enable(spi, 1); 510 return count; 511 } 512 } 513 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) 514 & OMAP2_MCSPI_CHSTAT_RXS)) { 515 u32 w; 516 517 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); 518 if (word_len <= 8) 519 ((u8 *)xfer->rx_buf)[elements] = w; 520 else if (word_len <= 16) 521 ((u16 *)xfer->rx_buf)[elements] = w; 522 else /* word_len <= 32 */ 523 ((u32 *)xfer->rx_buf)[elements] = w; 524 } else { 525 dev_err(&spi->dev, "DMA RX last word empty\n"); 526 count -= mcspi_bytes_per_word(word_len); 527 } 528 omap2_mcspi_set_enable(spi, 1); 529 return count; 530 } 531 532 static unsigned 533 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) 534 { 535 struct omap2_mcspi *mcspi; 536 struct omap2_mcspi_cs *cs = spi->controller_state; 537 struct omap2_mcspi_dma *mcspi_dma; 538 unsigned int count; 539 u32 l; 540 u8 *rx; 541 const u8 *tx; 542 struct dma_slave_config cfg; 543 enum dma_slave_buswidth width; 544 unsigned es; 545 u32 burst; 546 void __iomem *chstat_reg; 547 void __iomem *irqstat_reg; 548 int wait_res; 549 550 mcspi = spi_master_get_devdata(spi->master); 551 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 552 l = mcspi_cached_chconf0(spi); 553 554 555 if (cs->word_len <= 8) { 556 width = DMA_SLAVE_BUSWIDTH_1_BYTE; 557 es = 1; 558 } else if (cs->word_len <= 16) { 559 width = DMA_SLAVE_BUSWIDTH_2_BYTES; 560 es = 2; 561 } else { 562 width = DMA_SLAVE_BUSWIDTH_4_BYTES; 563 es = 4; 564 } 565 566 count = xfer->len; 567 burst = 1; 568 569 if (mcspi->fifo_depth > 0) { 570 if (count > mcspi->fifo_depth) 571 burst = mcspi->fifo_depth / es; 572 else 573 burst = count / es; 574 } 575 576 memset(&cfg, 0, sizeof(cfg)); 577 cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0; 578 cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0; 579 cfg.src_addr_width = width; 580 cfg.dst_addr_width = width; 581 cfg.src_maxburst = burst; 582 cfg.dst_maxburst = burst; 583 584 rx = xfer->rx_buf; 585 tx = xfer->tx_buf; 586 587 if (tx != NULL) 588 omap2_mcspi_tx_dma(spi, xfer, cfg); 589 590 if (rx != NULL) 591 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es); 592 593 if (tx != NULL) { 594 wait_for_completion(&mcspi_dma->dma_tx_completion); 595 dma_unmap_single(mcspi->dev, xfer->tx_dma, xfer->len, 596 DMA_TO_DEVICE); 597 598 if (mcspi->fifo_depth > 0) { 599 irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS; 600 601 if (mcspi_wait_for_reg_bit(irqstat_reg, 602 OMAP2_MCSPI_IRQSTATUS_EOW) < 0) 603 dev_err(&spi->dev, "EOW timed out\n"); 604 605 mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS, 606 OMAP2_MCSPI_IRQSTATUS_EOW); 607 } 608 609 /* for TX_ONLY mode, be sure all words have shifted out */ 610 if (rx == NULL) { 611 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; 612 if (mcspi->fifo_depth > 0) { 613 wait_res = mcspi_wait_for_reg_bit(chstat_reg, 614 OMAP2_MCSPI_CHSTAT_TXFFE); 615 if (wait_res < 0) 616 dev_err(&spi->dev, "TXFFE timed out\n"); 617 } else { 618 wait_res = mcspi_wait_for_reg_bit(chstat_reg, 619 OMAP2_MCSPI_CHSTAT_TXS); 620 if (wait_res < 0) 621 dev_err(&spi->dev, "TXS timed out\n"); 622 } 623 if (wait_res >= 0 && 624 (mcspi_wait_for_reg_bit(chstat_reg, 625 OMAP2_MCSPI_CHSTAT_EOT) < 0)) 626 dev_err(&spi->dev, "EOT timed out\n"); 627 } 628 } 629 return count; 630 } 631 632 static unsigned 633 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) 634 { 635 struct omap2_mcspi *mcspi; 636 struct omap2_mcspi_cs *cs = spi->controller_state; 637 unsigned int count, c; 638 u32 l; 639 void __iomem *base = cs->base; 640 void __iomem *tx_reg; 641 void __iomem *rx_reg; 642 void __iomem *chstat_reg; 643 int word_len; 644 645 mcspi = spi_master_get_devdata(spi->master); 646 count = xfer->len; 647 c = count; 648 word_len = cs->word_len; 649 650 l = mcspi_cached_chconf0(spi); 651 652 /* We store the pre-calculated register addresses on stack to speed 653 * up the transfer loop. */ 654 tx_reg = base + OMAP2_MCSPI_TX0; 655 rx_reg = base + OMAP2_MCSPI_RX0; 656 chstat_reg = base + OMAP2_MCSPI_CHSTAT0; 657 658 if (c < (word_len>>3)) 659 return 0; 660 661 if (word_len <= 8) { 662 u8 *rx; 663 const u8 *tx; 664 665 rx = xfer->rx_buf; 666 tx = xfer->tx_buf; 667 668 do { 669 c -= 1; 670 if (tx != NULL) { 671 if (mcspi_wait_for_reg_bit(chstat_reg, 672 OMAP2_MCSPI_CHSTAT_TXS) < 0) { 673 dev_err(&spi->dev, "TXS timed out\n"); 674 goto out; 675 } 676 dev_vdbg(&spi->dev, "write-%d %02x\n", 677 word_len, *tx); 678 __raw_writel(*tx++, tx_reg); 679 } 680 if (rx != NULL) { 681 if (mcspi_wait_for_reg_bit(chstat_reg, 682 OMAP2_MCSPI_CHSTAT_RXS) < 0) { 683 dev_err(&spi->dev, "RXS timed out\n"); 684 goto out; 685 } 686 687 if (c == 1 && tx == NULL && 688 (l & OMAP2_MCSPI_CHCONF_TURBO)) { 689 omap2_mcspi_set_enable(spi, 0); 690 *rx++ = __raw_readl(rx_reg); 691 dev_vdbg(&spi->dev, "read-%d %02x\n", 692 word_len, *(rx - 1)); 693 if (mcspi_wait_for_reg_bit(chstat_reg, 694 OMAP2_MCSPI_CHSTAT_RXS) < 0) { 695 dev_err(&spi->dev, 696 "RXS timed out\n"); 697 goto out; 698 } 699 c = 0; 700 } else if (c == 0 && tx == NULL) { 701 omap2_mcspi_set_enable(spi, 0); 702 } 703 704 *rx++ = __raw_readl(rx_reg); 705 dev_vdbg(&spi->dev, "read-%d %02x\n", 706 word_len, *(rx - 1)); 707 } 708 } while (c); 709 } else if (word_len <= 16) { 710 u16 *rx; 711 const u16 *tx; 712 713 rx = xfer->rx_buf; 714 tx = xfer->tx_buf; 715 do { 716 c -= 2; 717 if (tx != NULL) { 718 if (mcspi_wait_for_reg_bit(chstat_reg, 719 OMAP2_MCSPI_CHSTAT_TXS) < 0) { 720 dev_err(&spi->dev, "TXS timed out\n"); 721 goto out; 722 } 723 dev_vdbg(&spi->dev, "write-%d %04x\n", 724 word_len, *tx); 725 __raw_writel(*tx++, tx_reg); 726 } 727 if (rx != NULL) { 728 if (mcspi_wait_for_reg_bit(chstat_reg, 729 OMAP2_MCSPI_CHSTAT_RXS) < 0) { 730 dev_err(&spi->dev, "RXS timed out\n"); 731 goto out; 732 } 733 734 if (c == 2 && tx == NULL && 735 (l & OMAP2_MCSPI_CHCONF_TURBO)) { 736 omap2_mcspi_set_enable(spi, 0); 737 *rx++ = __raw_readl(rx_reg); 738 dev_vdbg(&spi->dev, "read-%d %04x\n", 739 word_len, *(rx - 1)); 740 if (mcspi_wait_for_reg_bit(chstat_reg, 741 OMAP2_MCSPI_CHSTAT_RXS) < 0) { 742 dev_err(&spi->dev, 743 "RXS timed out\n"); 744 goto out; 745 } 746 c = 0; 747 } else if (c == 0 && tx == NULL) { 748 omap2_mcspi_set_enable(spi, 0); 749 } 750 751 *rx++ = __raw_readl(rx_reg); 752 dev_vdbg(&spi->dev, "read-%d %04x\n", 753 word_len, *(rx - 1)); 754 } 755 } while (c >= 2); 756 } else if (word_len <= 32) { 757 u32 *rx; 758 const u32 *tx; 759 760 rx = xfer->rx_buf; 761 tx = xfer->tx_buf; 762 do { 763 c -= 4; 764 if (tx != NULL) { 765 if (mcspi_wait_for_reg_bit(chstat_reg, 766 OMAP2_MCSPI_CHSTAT_TXS) < 0) { 767 dev_err(&spi->dev, "TXS timed out\n"); 768 goto out; 769 } 770 dev_vdbg(&spi->dev, "write-%d %08x\n", 771 word_len, *tx); 772 __raw_writel(*tx++, tx_reg); 773 } 774 if (rx != NULL) { 775 if (mcspi_wait_for_reg_bit(chstat_reg, 776 OMAP2_MCSPI_CHSTAT_RXS) < 0) { 777 dev_err(&spi->dev, "RXS timed out\n"); 778 goto out; 779 } 780 781 if (c == 4 && tx == NULL && 782 (l & OMAP2_MCSPI_CHCONF_TURBO)) { 783 omap2_mcspi_set_enable(spi, 0); 784 *rx++ = __raw_readl(rx_reg); 785 dev_vdbg(&spi->dev, "read-%d %08x\n", 786 word_len, *(rx - 1)); 787 if (mcspi_wait_for_reg_bit(chstat_reg, 788 OMAP2_MCSPI_CHSTAT_RXS) < 0) { 789 dev_err(&spi->dev, 790 "RXS timed out\n"); 791 goto out; 792 } 793 c = 0; 794 } else if (c == 0 && tx == NULL) { 795 omap2_mcspi_set_enable(spi, 0); 796 } 797 798 *rx++ = __raw_readl(rx_reg); 799 dev_vdbg(&spi->dev, "read-%d %08x\n", 800 word_len, *(rx - 1)); 801 } 802 } while (c >= 4); 803 } 804 805 /* for TX_ONLY mode, be sure all words have shifted out */ 806 if (xfer->rx_buf == NULL) { 807 if (mcspi_wait_for_reg_bit(chstat_reg, 808 OMAP2_MCSPI_CHSTAT_TXS) < 0) { 809 dev_err(&spi->dev, "TXS timed out\n"); 810 } else if (mcspi_wait_for_reg_bit(chstat_reg, 811 OMAP2_MCSPI_CHSTAT_EOT) < 0) 812 dev_err(&spi->dev, "EOT timed out\n"); 813 814 /* disable chan to purge rx datas received in TX_ONLY transfer, 815 * otherwise these rx datas will affect the direct following 816 * RX_ONLY transfer. 817 */ 818 omap2_mcspi_set_enable(spi, 0); 819 } 820 out: 821 omap2_mcspi_set_enable(spi, 1); 822 return count - c; 823 } 824 825 static u32 omap2_mcspi_calc_divisor(u32 speed_hz) 826 { 827 u32 div; 828 829 for (div = 0; div < 15; div++) 830 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div)) 831 return div; 832 833 return 15; 834 } 835 836 /* called only when no transfer is active to this device */ 837 static int omap2_mcspi_setup_transfer(struct spi_device *spi, 838 struct spi_transfer *t) 839 { 840 struct omap2_mcspi_cs *cs = spi->controller_state; 841 struct omap2_mcspi *mcspi; 842 struct spi_master *spi_cntrl; 843 u32 l = 0, div = 0; 844 u8 word_len = spi->bits_per_word; 845 u32 speed_hz = spi->max_speed_hz; 846 847 mcspi = spi_master_get_devdata(spi->master); 848 spi_cntrl = mcspi->master; 849 850 if (t != NULL && t->bits_per_word) 851 word_len = t->bits_per_word; 852 853 cs->word_len = word_len; 854 855 if (t && t->speed_hz) 856 speed_hz = t->speed_hz; 857 858 speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ); 859 div = omap2_mcspi_calc_divisor(speed_hz); 860 861 l = mcspi_cached_chconf0(spi); 862 863 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS 864 * REVISIT: this controller could support SPI_3WIRE mode. 865 */ 866 if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) { 867 l &= ~OMAP2_MCSPI_CHCONF_IS; 868 l &= ~OMAP2_MCSPI_CHCONF_DPE1; 869 l |= OMAP2_MCSPI_CHCONF_DPE0; 870 } else { 871 l |= OMAP2_MCSPI_CHCONF_IS; 872 l |= OMAP2_MCSPI_CHCONF_DPE1; 873 l &= ~OMAP2_MCSPI_CHCONF_DPE0; 874 } 875 876 /* wordlength */ 877 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK; 878 l |= (word_len - 1) << 7; 879 880 /* set chipselect polarity; manage with FORCE */ 881 if (!(spi->mode & SPI_CS_HIGH)) 882 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */ 883 else 884 l &= ~OMAP2_MCSPI_CHCONF_EPOL; 885 886 /* set clock divisor */ 887 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK; 888 l |= div << 2; 889 890 /* set SPI mode 0..3 */ 891 if (spi->mode & SPI_CPOL) 892 l |= OMAP2_MCSPI_CHCONF_POL; 893 else 894 l &= ~OMAP2_MCSPI_CHCONF_POL; 895 if (spi->mode & SPI_CPHA) 896 l |= OMAP2_MCSPI_CHCONF_PHA; 897 else 898 l &= ~OMAP2_MCSPI_CHCONF_PHA; 899 900 mcspi_write_chconf0(spi, l); 901 902 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", 903 OMAP2_MCSPI_MAX_FREQ >> div, 904 (spi->mode & SPI_CPHA) ? "trailing" : "leading", 905 (spi->mode & SPI_CPOL) ? "inverted" : "normal"); 906 907 return 0; 908 } 909 910 /* 911 * Note that we currently allow DMA only if we get a channel 912 * for both rx and tx. Otherwise we'll do PIO for both rx and tx. 913 */ 914 static int omap2_mcspi_request_dma(struct spi_device *spi) 915 { 916 struct spi_master *master = spi->master; 917 struct omap2_mcspi *mcspi; 918 struct omap2_mcspi_dma *mcspi_dma; 919 dma_cap_mask_t mask; 920 unsigned sig; 921 922 mcspi = spi_master_get_devdata(master); 923 mcspi_dma = mcspi->dma_channels + spi->chip_select; 924 925 init_completion(&mcspi_dma->dma_rx_completion); 926 init_completion(&mcspi_dma->dma_tx_completion); 927 928 dma_cap_zero(mask); 929 dma_cap_set(DMA_SLAVE, mask); 930 sig = mcspi_dma->dma_rx_sync_dev; 931 932 mcspi_dma->dma_rx = 933 dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 934 &sig, &master->dev, 935 mcspi_dma->dma_rx_ch_name); 936 if (!mcspi_dma->dma_rx) 937 goto no_dma; 938 939 sig = mcspi_dma->dma_tx_sync_dev; 940 mcspi_dma->dma_tx = 941 dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 942 &sig, &master->dev, 943 mcspi_dma->dma_tx_ch_name); 944 945 if (!mcspi_dma->dma_tx) { 946 dma_release_channel(mcspi_dma->dma_rx); 947 mcspi_dma->dma_rx = NULL; 948 goto no_dma; 949 } 950 951 return 0; 952 953 no_dma: 954 dev_warn(&spi->dev, "not using DMA for McSPI\n"); 955 return -EAGAIN; 956 } 957 958 static int omap2_mcspi_setup(struct spi_device *spi) 959 { 960 int ret; 961 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); 962 struct omap2_mcspi_regs *ctx = &mcspi->ctx; 963 struct omap2_mcspi_dma *mcspi_dma; 964 struct omap2_mcspi_cs *cs = spi->controller_state; 965 966 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 967 968 if (!cs) { 969 cs = kzalloc(sizeof *cs, GFP_KERNEL); 970 if (!cs) 971 return -ENOMEM; 972 cs->base = mcspi->base + spi->chip_select * 0x14; 973 cs->phys = mcspi->phys + spi->chip_select * 0x14; 974 cs->chconf0 = 0; 975 spi->controller_state = cs; 976 /* Link this to context save list */ 977 list_add_tail(&cs->node, &ctx->cs); 978 } 979 980 if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) { 981 ret = omap2_mcspi_request_dma(spi); 982 if (ret < 0 && ret != -EAGAIN) 983 return ret; 984 } 985 986 ret = pm_runtime_get_sync(mcspi->dev); 987 if (ret < 0) 988 return ret; 989 990 ret = omap2_mcspi_setup_transfer(spi, NULL); 991 pm_runtime_mark_last_busy(mcspi->dev); 992 pm_runtime_put_autosuspend(mcspi->dev); 993 994 return ret; 995 } 996 997 static void omap2_mcspi_cleanup(struct spi_device *spi) 998 { 999 struct omap2_mcspi *mcspi; 1000 struct omap2_mcspi_dma *mcspi_dma; 1001 struct omap2_mcspi_cs *cs; 1002 1003 mcspi = spi_master_get_devdata(spi->master); 1004 1005 if (spi->controller_state) { 1006 /* Unlink controller state from context save list */ 1007 cs = spi->controller_state; 1008 list_del(&cs->node); 1009 1010 kfree(cs); 1011 } 1012 1013 if (spi->chip_select < spi->master->num_chipselect) { 1014 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 1015 1016 if (mcspi_dma->dma_rx) { 1017 dma_release_channel(mcspi_dma->dma_rx); 1018 mcspi_dma->dma_rx = NULL; 1019 } 1020 if (mcspi_dma->dma_tx) { 1021 dma_release_channel(mcspi_dma->dma_tx); 1022 mcspi_dma->dma_tx = NULL; 1023 } 1024 } 1025 } 1026 1027 static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m) 1028 { 1029 1030 /* We only enable one channel at a time -- the one whose message is 1031 * -- although this controller would gladly 1032 * arbitrate among multiple channels. This corresponds to "single 1033 * channel" master mode. As a side effect, we need to manage the 1034 * chipselect with the FORCE bit ... CS != channel enable. 1035 */ 1036 1037 struct spi_device *spi; 1038 struct spi_transfer *t = NULL; 1039 struct spi_master *master; 1040 struct omap2_mcspi_dma *mcspi_dma; 1041 int cs_active = 0; 1042 struct omap2_mcspi_cs *cs; 1043 struct omap2_mcspi_device_config *cd; 1044 int par_override = 0; 1045 int status = 0; 1046 u32 chconf; 1047 1048 spi = m->spi; 1049 master = spi->master; 1050 mcspi_dma = mcspi->dma_channels + spi->chip_select; 1051 cs = spi->controller_state; 1052 cd = spi->controller_data; 1053 1054 omap2_mcspi_set_enable(spi, 0); 1055 list_for_each_entry(t, &m->transfers, transfer_list) { 1056 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) { 1057 status = -EINVAL; 1058 break; 1059 } 1060 if (par_override || t->speed_hz || t->bits_per_word) { 1061 par_override = 1; 1062 status = omap2_mcspi_setup_transfer(spi, t); 1063 if (status < 0) 1064 break; 1065 if (!t->speed_hz && !t->bits_per_word) 1066 par_override = 0; 1067 } 1068 if (cd && cd->cs_per_word) { 1069 chconf = mcspi->ctx.modulctrl; 1070 chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE; 1071 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf); 1072 mcspi->ctx.modulctrl = 1073 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); 1074 } 1075 1076 1077 if (!cs_active) { 1078 omap2_mcspi_force_cs(spi, 1); 1079 cs_active = 1; 1080 } 1081 1082 chconf = mcspi_cached_chconf0(spi); 1083 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; 1084 chconf &= ~OMAP2_MCSPI_CHCONF_TURBO; 1085 1086 if (t->tx_buf == NULL) 1087 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY; 1088 else if (t->rx_buf == NULL) 1089 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY; 1090 1091 if (cd && cd->turbo_mode && t->tx_buf == NULL) { 1092 /* Turbo mode is for more than one word */ 1093 if (t->len > ((cs->word_len + 7) >> 3)) 1094 chconf |= OMAP2_MCSPI_CHCONF_TURBO; 1095 } 1096 1097 mcspi_write_chconf0(spi, chconf); 1098 1099 if (t->len) { 1100 unsigned count; 1101 1102 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && 1103 (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)) 1104 omap2_mcspi_set_fifo(spi, t, 1); 1105 1106 omap2_mcspi_set_enable(spi, 1); 1107 1108 /* RX_ONLY mode needs dummy data in TX reg */ 1109 if (t->tx_buf == NULL) 1110 __raw_writel(0, cs->base 1111 + OMAP2_MCSPI_TX0); 1112 1113 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && 1114 (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)) 1115 count = omap2_mcspi_txrx_dma(spi, t); 1116 else 1117 count = omap2_mcspi_txrx_pio(spi, t); 1118 m->actual_length += count; 1119 1120 if (count != t->len) { 1121 status = -EIO; 1122 break; 1123 } 1124 } 1125 1126 if (t->delay_usecs) 1127 udelay(t->delay_usecs); 1128 1129 /* ignore the "leave it on after last xfer" hint */ 1130 if (t->cs_change) { 1131 omap2_mcspi_force_cs(spi, 0); 1132 cs_active = 0; 1133 } 1134 1135 omap2_mcspi_set_enable(spi, 0); 1136 1137 if (mcspi->fifo_depth > 0) 1138 omap2_mcspi_set_fifo(spi, t, 0); 1139 } 1140 /* Restore defaults if they were overriden */ 1141 if (par_override) { 1142 par_override = 0; 1143 status = omap2_mcspi_setup_transfer(spi, NULL); 1144 } 1145 1146 if (cs_active) 1147 omap2_mcspi_force_cs(spi, 0); 1148 1149 if (cd && cd->cs_per_word) { 1150 chconf = mcspi->ctx.modulctrl; 1151 chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE; 1152 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf); 1153 mcspi->ctx.modulctrl = 1154 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); 1155 } 1156 1157 omap2_mcspi_set_enable(spi, 0); 1158 1159 if (mcspi->fifo_depth > 0 && t) 1160 omap2_mcspi_set_fifo(spi, t, 0); 1161 1162 m->status = status; 1163 } 1164 1165 static int omap2_mcspi_transfer_one_message(struct spi_master *master, 1166 struct spi_message *m) 1167 { 1168 struct spi_device *spi; 1169 struct omap2_mcspi *mcspi; 1170 struct omap2_mcspi_dma *mcspi_dma; 1171 struct spi_transfer *t; 1172 1173 spi = m->spi; 1174 mcspi = spi_master_get_devdata(master); 1175 mcspi_dma = mcspi->dma_channels + spi->chip_select; 1176 m->actual_length = 0; 1177 m->status = 0; 1178 1179 /* reject invalid messages and transfers */ 1180 if (list_empty(&m->transfers)) 1181 return -EINVAL; 1182 list_for_each_entry(t, &m->transfers, transfer_list) { 1183 const void *tx_buf = t->tx_buf; 1184 void *rx_buf = t->rx_buf; 1185 unsigned len = t->len; 1186 1187 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ 1188 || (len && !(rx_buf || tx_buf))) { 1189 dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n", 1190 t->speed_hz, 1191 len, 1192 tx_buf ? "tx" : "", 1193 rx_buf ? "rx" : "", 1194 t->bits_per_word); 1195 return -EINVAL; 1196 } 1197 if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) { 1198 dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n", 1199 t->speed_hz, 1200 OMAP2_MCSPI_MAX_FREQ >> 15); 1201 return -EINVAL; 1202 } 1203 1204 if (m->is_dma_mapped || len < DMA_MIN_BYTES) 1205 continue; 1206 1207 if (mcspi_dma->dma_tx && tx_buf != NULL) { 1208 t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf, 1209 len, DMA_TO_DEVICE); 1210 if (dma_mapping_error(mcspi->dev, t->tx_dma)) { 1211 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", 1212 'T', len); 1213 return -EINVAL; 1214 } 1215 } 1216 if (mcspi_dma->dma_rx && rx_buf != NULL) { 1217 t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len, 1218 DMA_FROM_DEVICE); 1219 if (dma_mapping_error(mcspi->dev, t->rx_dma)) { 1220 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", 1221 'R', len); 1222 if (tx_buf != NULL) 1223 dma_unmap_single(mcspi->dev, t->tx_dma, 1224 len, DMA_TO_DEVICE); 1225 return -EINVAL; 1226 } 1227 } 1228 } 1229 1230 omap2_mcspi_work(mcspi, m); 1231 spi_finalize_current_message(master); 1232 return 0; 1233 } 1234 1235 static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi) 1236 { 1237 struct spi_master *master = mcspi->master; 1238 struct omap2_mcspi_regs *ctx = &mcspi->ctx; 1239 int ret = 0; 1240 1241 ret = pm_runtime_get_sync(mcspi->dev); 1242 if (ret < 0) 1243 return ret; 1244 1245 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, 1246 OMAP2_MCSPI_WAKEUPENABLE_WKEN); 1247 ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN; 1248 1249 omap2_mcspi_set_master_mode(master); 1250 pm_runtime_mark_last_busy(mcspi->dev); 1251 pm_runtime_put_autosuspend(mcspi->dev); 1252 return 0; 1253 } 1254 1255 static int omap_mcspi_runtime_resume(struct device *dev) 1256 { 1257 struct omap2_mcspi *mcspi; 1258 struct spi_master *master; 1259 1260 master = dev_get_drvdata(dev); 1261 mcspi = spi_master_get_devdata(master); 1262 omap2_mcspi_restore_ctx(mcspi); 1263 1264 return 0; 1265 } 1266 1267 static struct omap2_mcspi_platform_config omap2_pdata = { 1268 .regs_offset = 0, 1269 }; 1270 1271 static struct omap2_mcspi_platform_config omap4_pdata = { 1272 .regs_offset = OMAP4_MCSPI_REG_OFFSET, 1273 }; 1274 1275 static const struct of_device_id omap_mcspi_of_match[] = { 1276 { 1277 .compatible = "ti,omap2-mcspi", 1278 .data = &omap2_pdata, 1279 }, 1280 { 1281 .compatible = "ti,omap4-mcspi", 1282 .data = &omap4_pdata, 1283 }, 1284 { }, 1285 }; 1286 MODULE_DEVICE_TABLE(of, omap_mcspi_of_match); 1287 1288 static int omap2_mcspi_probe(struct platform_device *pdev) 1289 { 1290 struct spi_master *master; 1291 const struct omap2_mcspi_platform_config *pdata; 1292 struct omap2_mcspi *mcspi; 1293 struct resource *r; 1294 int status = 0, i; 1295 u32 regs_offset = 0; 1296 static int bus_num = 1; 1297 struct device_node *node = pdev->dev.of_node; 1298 const struct of_device_id *match; 1299 1300 master = spi_alloc_master(&pdev->dev, sizeof *mcspi); 1301 if (master == NULL) { 1302 dev_dbg(&pdev->dev, "master allocation failed\n"); 1303 return -ENOMEM; 1304 } 1305 1306 /* the spi->mode bits understood by this driver: */ 1307 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1308 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1309 master->setup = omap2_mcspi_setup; 1310 master->auto_runtime_pm = true; 1311 master->transfer_one_message = omap2_mcspi_transfer_one_message; 1312 master->cleanup = omap2_mcspi_cleanup; 1313 master->dev.of_node = node; 1314 1315 platform_set_drvdata(pdev, master); 1316 1317 mcspi = spi_master_get_devdata(master); 1318 mcspi->master = master; 1319 1320 match = of_match_device(omap_mcspi_of_match, &pdev->dev); 1321 if (match) { 1322 u32 num_cs = 1; /* default number of chipselect */ 1323 pdata = match->data; 1324 1325 of_property_read_u32(node, "ti,spi-num-cs", &num_cs); 1326 master->num_chipselect = num_cs; 1327 master->bus_num = bus_num++; 1328 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL)) 1329 mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN; 1330 } else { 1331 pdata = dev_get_platdata(&pdev->dev); 1332 master->num_chipselect = pdata->num_cs; 1333 if (pdev->id != -1) 1334 master->bus_num = pdev->id; 1335 mcspi->pin_dir = pdata->pin_dir; 1336 } 1337 regs_offset = pdata->regs_offset; 1338 1339 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1340 if (r == NULL) { 1341 status = -ENODEV; 1342 goto free_master; 1343 } 1344 1345 r->start += regs_offset; 1346 r->end += regs_offset; 1347 mcspi->phys = r->start; 1348 1349 mcspi->base = devm_ioremap_resource(&pdev->dev, r); 1350 if (IS_ERR(mcspi->base)) { 1351 status = PTR_ERR(mcspi->base); 1352 goto free_master; 1353 } 1354 1355 mcspi->dev = &pdev->dev; 1356 1357 INIT_LIST_HEAD(&mcspi->ctx.cs); 1358 1359 mcspi->dma_channels = kcalloc(master->num_chipselect, 1360 sizeof(struct omap2_mcspi_dma), 1361 GFP_KERNEL); 1362 1363 if (mcspi->dma_channels == NULL) 1364 goto free_master; 1365 1366 for (i = 0; i < master->num_chipselect; i++) { 1367 char *dma_rx_ch_name = mcspi->dma_channels[i].dma_rx_ch_name; 1368 char *dma_tx_ch_name = mcspi->dma_channels[i].dma_tx_ch_name; 1369 struct resource *dma_res; 1370 1371 sprintf(dma_rx_ch_name, "rx%d", i); 1372 if (!pdev->dev.of_node) { 1373 dma_res = 1374 platform_get_resource_byname(pdev, 1375 IORESOURCE_DMA, 1376 dma_rx_ch_name); 1377 if (!dma_res) { 1378 dev_dbg(&pdev->dev, 1379 "cannot get DMA RX channel\n"); 1380 status = -ENODEV; 1381 break; 1382 } 1383 1384 mcspi->dma_channels[i].dma_rx_sync_dev = 1385 dma_res->start; 1386 } 1387 sprintf(dma_tx_ch_name, "tx%d", i); 1388 if (!pdev->dev.of_node) { 1389 dma_res = 1390 platform_get_resource_byname(pdev, 1391 IORESOURCE_DMA, 1392 dma_tx_ch_name); 1393 if (!dma_res) { 1394 dev_dbg(&pdev->dev, 1395 "cannot get DMA TX channel\n"); 1396 status = -ENODEV; 1397 break; 1398 } 1399 1400 mcspi->dma_channels[i].dma_tx_sync_dev = 1401 dma_res->start; 1402 } 1403 } 1404 1405 if (status < 0) 1406 goto dma_chnl_free; 1407 1408 pm_runtime_use_autosuspend(&pdev->dev); 1409 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); 1410 pm_runtime_enable(&pdev->dev); 1411 1412 status = omap2_mcspi_master_setup(mcspi); 1413 if (status < 0) 1414 goto disable_pm; 1415 1416 status = devm_spi_register_master(&pdev->dev, master); 1417 if (status < 0) 1418 goto disable_pm; 1419 1420 return status; 1421 1422 disable_pm: 1423 pm_runtime_disable(&pdev->dev); 1424 dma_chnl_free: 1425 kfree(mcspi->dma_channels); 1426 free_master: 1427 spi_master_put(master); 1428 return status; 1429 } 1430 1431 static int omap2_mcspi_remove(struct platform_device *pdev) 1432 { 1433 struct spi_master *master; 1434 struct omap2_mcspi *mcspi; 1435 struct omap2_mcspi_dma *dma_channels; 1436 1437 master = platform_get_drvdata(pdev); 1438 mcspi = spi_master_get_devdata(master); 1439 dma_channels = mcspi->dma_channels; 1440 1441 pm_runtime_put_sync(mcspi->dev); 1442 pm_runtime_disable(&pdev->dev); 1443 1444 kfree(dma_channels); 1445 1446 return 0; 1447 } 1448 1449 /* work with hotplug and coldplug */ 1450 MODULE_ALIAS("platform:omap2_mcspi"); 1451 1452 #ifdef CONFIG_SUSPEND 1453 /* 1454 * When SPI wake up from off-mode, CS is in activate state. If it was in 1455 * unactive state when driver was suspend, then force it to unactive state at 1456 * wake up. 1457 */ 1458 static int omap2_mcspi_resume(struct device *dev) 1459 { 1460 struct spi_master *master = dev_get_drvdata(dev); 1461 struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 1462 struct omap2_mcspi_regs *ctx = &mcspi->ctx; 1463 struct omap2_mcspi_cs *cs; 1464 1465 pm_runtime_get_sync(mcspi->dev); 1466 list_for_each_entry(cs, &ctx->cs, node) { 1467 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) { 1468 /* 1469 * We need to toggle CS state for OMAP take this 1470 * change in account. 1471 */ 1472 cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE; 1473 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); 1474 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; 1475 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); 1476 } 1477 } 1478 pm_runtime_mark_last_busy(mcspi->dev); 1479 pm_runtime_put_autosuspend(mcspi->dev); 1480 return 0; 1481 } 1482 #else 1483 #define omap2_mcspi_resume NULL 1484 #endif 1485 1486 static const struct dev_pm_ops omap2_mcspi_pm_ops = { 1487 .resume = omap2_mcspi_resume, 1488 .runtime_resume = omap_mcspi_runtime_resume, 1489 }; 1490 1491 static struct platform_driver omap2_mcspi_driver = { 1492 .driver = { 1493 .name = "omap2_mcspi", 1494 .owner = THIS_MODULE, 1495 .pm = &omap2_mcspi_pm_ops, 1496 .of_match_table = omap_mcspi_of_match, 1497 }, 1498 .probe = omap2_mcspi_probe, 1499 .remove = omap2_mcspi_remove, 1500 }; 1501 1502 module_platform_driver(omap2_mcspi_driver); 1503 MODULE_LICENSE("GPL"); 1504