1 /* 2 * OMAP2 McSPI controller driver 3 * 4 * Copyright (C) 2005, 2006 Nokia Corporation 5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and 6 * Juha Yrj�l� <juha.yrjola@nokia.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 * 22 */ 23 24 #include <linux/kernel.h> 25 #include <linux/interrupt.h> 26 #include <linux/module.h> 27 #include <linux/device.h> 28 #include <linux/delay.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/dmaengine.h> 31 #include <linux/omap-dma.h> 32 #include <linux/platform_device.h> 33 #include <linux/err.h> 34 #include <linux/clk.h> 35 #include <linux/io.h> 36 #include <linux/slab.h> 37 #include <linux/pm_runtime.h> 38 #include <linux/of.h> 39 #include <linux/of_device.h> 40 #include <linux/gcd.h> 41 42 #include <linux/spi/spi.h> 43 44 #include <linux/platform_data/spi-omap2-mcspi.h> 45 46 #define OMAP2_MCSPI_MAX_FREQ 48000000 47 #define OMAP2_MCSPI_MAX_DIVIDER 4096 48 #define OMAP2_MCSPI_MAX_FIFODEPTH 64 49 #define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF 50 #define SPI_AUTOSUSPEND_TIMEOUT 2000 51 52 #define OMAP2_MCSPI_REVISION 0x00 53 #define OMAP2_MCSPI_SYSSTATUS 0x14 54 #define OMAP2_MCSPI_IRQSTATUS 0x18 55 #define OMAP2_MCSPI_IRQENABLE 0x1c 56 #define OMAP2_MCSPI_WAKEUPENABLE 0x20 57 #define OMAP2_MCSPI_SYST 0x24 58 #define OMAP2_MCSPI_MODULCTRL 0x28 59 #define OMAP2_MCSPI_XFERLEVEL 0x7c 60 61 /* per-channel banks, 0x14 bytes each, first is: */ 62 #define OMAP2_MCSPI_CHCONF0 0x2c 63 #define OMAP2_MCSPI_CHSTAT0 0x30 64 #define OMAP2_MCSPI_CHCTRL0 0x34 65 #define OMAP2_MCSPI_TX0 0x38 66 #define OMAP2_MCSPI_RX0 0x3c 67 68 /* per-register bitmasks: */ 69 #define OMAP2_MCSPI_IRQSTATUS_EOW BIT(17) 70 71 #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0) 72 #define OMAP2_MCSPI_MODULCTRL_MS BIT(2) 73 #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3) 74 75 #define OMAP2_MCSPI_CHCONF_PHA BIT(0) 76 #define OMAP2_MCSPI_CHCONF_POL BIT(1) 77 #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2) 78 #define OMAP2_MCSPI_CHCONF_EPOL BIT(6) 79 #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7) 80 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12) 81 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13) 82 #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12) 83 #define OMAP2_MCSPI_CHCONF_DMAW BIT(14) 84 #define OMAP2_MCSPI_CHCONF_DMAR BIT(15) 85 #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16) 86 #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17) 87 #define OMAP2_MCSPI_CHCONF_IS BIT(18) 88 #define OMAP2_MCSPI_CHCONF_TURBO BIT(19) 89 #define OMAP2_MCSPI_CHCONF_FORCE BIT(20) 90 #define OMAP2_MCSPI_CHCONF_FFET BIT(27) 91 #define OMAP2_MCSPI_CHCONF_FFER BIT(28) 92 #define OMAP2_MCSPI_CHCONF_CLKG BIT(29) 93 94 #define OMAP2_MCSPI_CHSTAT_RXS BIT(0) 95 #define OMAP2_MCSPI_CHSTAT_TXS BIT(1) 96 #define OMAP2_MCSPI_CHSTAT_EOT BIT(2) 97 #define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3) 98 99 #define OMAP2_MCSPI_CHCTRL_EN BIT(0) 100 #define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK (0xff << 8) 101 102 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0) 103 104 /* We have 2 DMA channels per CS, one for RX and one for TX */ 105 struct omap2_mcspi_dma { 106 struct dma_chan *dma_tx; 107 struct dma_chan *dma_rx; 108 109 int dma_tx_sync_dev; 110 int dma_rx_sync_dev; 111 112 struct completion dma_tx_completion; 113 struct completion dma_rx_completion; 114 115 char dma_rx_ch_name[14]; 116 char dma_tx_ch_name[14]; 117 }; 118 119 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and 120 * cache operations; better heuristics consider wordsize and bitrate. 121 */ 122 #define DMA_MIN_BYTES 160 123 124 125 /* 126 * Used for context save and restore, structure members to be updated whenever 127 * corresponding registers are modified. 128 */ 129 struct omap2_mcspi_regs { 130 u32 modulctrl; 131 u32 wakeupenable; 132 struct list_head cs; 133 }; 134 135 struct omap2_mcspi { 136 struct spi_master *master; 137 /* Virtual base address of the controller */ 138 void __iomem *base; 139 unsigned long phys; 140 /* SPI1 has 4 channels, while SPI2 has 2 */ 141 struct omap2_mcspi_dma *dma_channels; 142 struct device *dev; 143 struct omap2_mcspi_regs ctx; 144 int fifo_depth; 145 unsigned int pin_dir:1; 146 }; 147 148 struct omap2_mcspi_cs { 149 void __iomem *base; 150 unsigned long phys; 151 int word_len; 152 u16 mode; 153 struct list_head node; 154 /* Context save and restore shadow register */ 155 u32 chconf0, chctrl0; 156 }; 157 158 static inline void mcspi_write_reg(struct spi_master *master, 159 int idx, u32 val) 160 { 161 struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 162 163 writel_relaxed(val, mcspi->base + idx); 164 } 165 166 static inline u32 mcspi_read_reg(struct spi_master *master, int idx) 167 { 168 struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 169 170 return readl_relaxed(mcspi->base + idx); 171 } 172 173 static inline void mcspi_write_cs_reg(const struct spi_device *spi, 174 int idx, u32 val) 175 { 176 struct omap2_mcspi_cs *cs = spi->controller_state; 177 178 writel_relaxed(val, cs->base + idx); 179 } 180 181 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx) 182 { 183 struct omap2_mcspi_cs *cs = spi->controller_state; 184 185 return readl_relaxed(cs->base + idx); 186 } 187 188 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi) 189 { 190 struct omap2_mcspi_cs *cs = spi->controller_state; 191 192 return cs->chconf0; 193 } 194 195 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val) 196 { 197 struct omap2_mcspi_cs *cs = spi->controller_state; 198 199 cs->chconf0 = val; 200 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val); 201 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0); 202 } 203 204 static inline int mcspi_bytes_per_word(int word_len) 205 { 206 if (word_len <= 8) 207 return 1; 208 else if (word_len <= 16) 209 return 2; 210 else /* word_len <= 32 */ 211 return 4; 212 } 213 214 static void omap2_mcspi_set_dma_req(const struct spi_device *spi, 215 int is_read, int enable) 216 { 217 u32 l, rw; 218 219 l = mcspi_cached_chconf0(spi); 220 221 if (is_read) /* 1 is read, 0 write */ 222 rw = OMAP2_MCSPI_CHCONF_DMAR; 223 else 224 rw = OMAP2_MCSPI_CHCONF_DMAW; 225 226 if (enable) 227 l |= rw; 228 else 229 l &= ~rw; 230 231 mcspi_write_chconf0(spi, l); 232 } 233 234 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) 235 { 236 struct omap2_mcspi_cs *cs = spi->controller_state; 237 u32 l; 238 239 l = cs->chctrl0; 240 if (enable) 241 l |= OMAP2_MCSPI_CHCTRL_EN; 242 else 243 l &= ~OMAP2_MCSPI_CHCTRL_EN; 244 cs->chctrl0 = l; 245 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); 246 /* Flash post-writes */ 247 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0); 248 } 249 250 static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active) 251 { 252 u32 l; 253 254 l = mcspi_cached_chconf0(spi); 255 if (cs_active) 256 l |= OMAP2_MCSPI_CHCONF_FORCE; 257 else 258 l &= ~OMAP2_MCSPI_CHCONF_FORCE; 259 260 mcspi_write_chconf0(spi, l); 261 } 262 263 static void omap2_mcspi_set_master_mode(struct spi_master *master) 264 { 265 struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 266 struct omap2_mcspi_regs *ctx = &mcspi->ctx; 267 u32 l; 268 269 /* 270 * Setup when switching from (reset default) slave mode 271 * to single-channel master mode 272 */ 273 l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL); 274 l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS); 275 l |= OMAP2_MCSPI_MODULCTRL_SINGLE; 276 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l); 277 278 ctx->modulctrl = l; 279 } 280 281 static void omap2_mcspi_set_fifo(const struct spi_device *spi, 282 struct spi_transfer *t, int enable) 283 { 284 struct spi_master *master = spi->master; 285 struct omap2_mcspi_cs *cs = spi->controller_state; 286 struct omap2_mcspi *mcspi; 287 unsigned int wcnt; 288 int max_fifo_depth, fifo_depth, bytes_per_word; 289 u32 chconf, xferlevel; 290 291 mcspi = spi_master_get_devdata(master); 292 293 chconf = mcspi_cached_chconf0(spi); 294 if (enable) { 295 bytes_per_word = mcspi_bytes_per_word(cs->word_len); 296 if (t->len % bytes_per_word != 0) 297 goto disable_fifo; 298 299 if (t->rx_buf != NULL && t->tx_buf != NULL) 300 max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2; 301 else 302 max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH; 303 304 fifo_depth = gcd(t->len, max_fifo_depth); 305 if (fifo_depth < 2 || fifo_depth % bytes_per_word != 0) 306 goto disable_fifo; 307 308 wcnt = t->len / bytes_per_word; 309 if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT) 310 goto disable_fifo; 311 312 xferlevel = wcnt << 16; 313 if (t->rx_buf != NULL) { 314 chconf |= OMAP2_MCSPI_CHCONF_FFER; 315 xferlevel |= (fifo_depth - 1) << 8; 316 } 317 if (t->tx_buf != NULL) { 318 chconf |= OMAP2_MCSPI_CHCONF_FFET; 319 xferlevel |= fifo_depth - 1; 320 } 321 322 mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel); 323 mcspi_write_chconf0(spi, chconf); 324 mcspi->fifo_depth = fifo_depth; 325 326 return; 327 } 328 329 disable_fifo: 330 if (t->rx_buf != NULL) 331 chconf &= ~OMAP2_MCSPI_CHCONF_FFER; 332 else 333 chconf &= ~OMAP2_MCSPI_CHCONF_FFET; 334 335 mcspi_write_chconf0(spi, chconf); 336 mcspi->fifo_depth = 0; 337 } 338 339 static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi) 340 { 341 struct spi_master *spi_cntrl = mcspi->master; 342 struct omap2_mcspi_regs *ctx = &mcspi->ctx; 343 struct omap2_mcspi_cs *cs; 344 345 /* McSPI: context restore */ 346 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl); 347 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable); 348 349 list_for_each_entry(cs, &ctx->cs, node) 350 writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); 351 } 352 353 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) 354 { 355 unsigned long timeout; 356 357 timeout = jiffies + msecs_to_jiffies(1000); 358 while (!(readl_relaxed(reg) & bit)) { 359 if (time_after(jiffies, timeout)) { 360 if (!(readl_relaxed(reg) & bit)) 361 return -ETIMEDOUT; 362 else 363 return 0; 364 } 365 cpu_relax(); 366 } 367 return 0; 368 } 369 370 static void omap2_mcspi_rx_callback(void *data) 371 { 372 struct spi_device *spi = data; 373 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); 374 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 375 376 /* We must disable the DMA RX request */ 377 omap2_mcspi_set_dma_req(spi, 1, 0); 378 379 complete(&mcspi_dma->dma_rx_completion); 380 } 381 382 static void omap2_mcspi_tx_callback(void *data) 383 { 384 struct spi_device *spi = data; 385 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); 386 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 387 388 /* We must disable the DMA TX request */ 389 omap2_mcspi_set_dma_req(spi, 0, 0); 390 391 complete(&mcspi_dma->dma_tx_completion); 392 } 393 394 static void omap2_mcspi_tx_dma(struct spi_device *spi, 395 struct spi_transfer *xfer, 396 struct dma_slave_config cfg) 397 { 398 struct omap2_mcspi *mcspi; 399 struct omap2_mcspi_dma *mcspi_dma; 400 unsigned int count; 401 402 mcspi = spi_master_get_devdata(spi->master); 403 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 404 count = xfer->len; 405 406 if (mcspi_dma->dma_tx) { 407 struct dma_async_tx_descriptor *tx; 408 struct scatterlist sg; 409 410 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg); 411 412 sg_init_table(&sg, 1); 413 sg_dma_address(&sg) = xfer->tx_dma; 414 sg_dma_len(&sg) = xfer->len; 415 416 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1, 417 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 418 if (tx) { 419 tx->callback = omap2_mcspi_tx_callback; 420 tx->callback_param = spi; 421 dmaengine_submit(tx); 422 } else { 423 /* FIXME: fall back to PIO? */ 424 } 425 } 426 dma_async_issue_pending(mcspi_dma->dma_tx); 427 omap2_mcspi_set_dma_req(spi, 0, 1); 428 429 } 430 431 static unsigned 432 omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer, 433 struct dma_slave_config cfg, 434 unsigned es) 435 { 436 struct omap2_mcspi *mcspi; 437 struct omap2_mcspi_dma *mcspi_dma; 438 unsigned int count, dma_count; 439 u32 l; 440 int elements = 0; 441 int word_len, element_count; 442 struct omap2_mcspi_cs *cs = spi->controller_state; 443 mcspi = spi_master_get_devdata(spi->master); 444 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 445 count = xfer->len; 446 dma_count = xfer->len; 447 448 if (mcspi->fifo_depth == 0) 449 dma_count -= es; 450 451 word_len = cs->word_len; 452 l = mcspi_cached_chconf0(spi); 453 454 if (word_len <= 8) 455 element_count = count; 456 else if (word_len <= 16) 457 element_count = count >> 1; 458 else /* word_len <= 32 */ 459 element_count = count >> 2; 460 461 if (mcspi_dma->dma_rx) { 462 struct dma_async_tx_descriptor *tx; 463 struct scatterlist sg; 464 465 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg); 466 467 if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0) 468 dma_count -= es; 469 470 sg_init_table(&sg, 1); 471 sg_dma_address(&sg) = xfer->rx_dma; 472 sg_dma_len(&sg) = dma_count; 473 474 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1, 475 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | 476 DMA_CTRL_ACK); 477 if (tx) { 478 tx->callback = omap2_mcspi_rx_callback; 479 tx->callback_param = spi; 480 dmaengine_submit(tx); 481 } else { 482 /* FIXME: fall back to PIO? */ 483 } 484 } 485 486 dma_async_issue_pending(mcspi_dma->dma_rx); 487 omap2_mcspi_set_dma_req(spi, 1, 1); 488 489 wait_for_completion(&mcspi_dma->dma_rx_completion); 490 dma_unmap_single(mcspi->dev, xfer->rx_dma, count, 491 DMA_FROM_DEVICE); 492 493 if (mcspi->fifo_depth > 0) 494 return count; 495 496 omap2_mcspi_set_enable(spi, 0); 497 498 elements = element_count - 1; 499 500 if (l & OMAP2_MCSPI_CHCONF_TURBO) { 501 elements--; 502 503 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) 504 & OMAP2_MCSPI_CHSTAT_RXS)) { 505 u32 w; 506 507 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); 508 if (word_len <= 8) 509 ((u8 *)xfer->rx_buf)[elements++] = w; 510 else if (word_len <= 16) 511 ((u16 *)xfer->rx_buf)[elements++] = w; 512 else /* word_len <= 32 */ 513 ((u32 *)xfer->rx_buf)[elements++] = w; 514 } else { 515 int bytes_per_word = mcspi_bytes_per_word(word_len); 516 dev_err(&spi->dev, "DMA RX penultimate word empty\n"); 517 count -= (bytes_per_word << 1); 518 omap2_mcspi_set_enable(spi, 1); 519 return count; 520 } 521 } 522 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) 523 & OMAP2_MCSPI_CHSTAT_RXS)) { 524 u32 w; 525 526 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); 527 if (word_len <= 8) 528 ((u8 *)xfer->rx_buf)[elements] = w; 529 else if (word_len <= 16) 530 ((u16 *)xfer->rx_buf)[elements] = w; 531 else /* word_len <= 32 */ 532 ((u32 *)xfer->rx_buf)[elements] = w; 533 } else { 534 dev_err(&spi->dev, "DMA RX last word empty\n"); 535 count -= mcspi_bytes_per_word(word_len); 536 } 537 omap2_mcspi_set_enable(spi, 1); 538 return count; 539 } 540 541 static unsigned 542 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) 543 { 544 struct omap2_mcspi *mcspi; 545 struct omap2_mcspi_cs *cs = spi->controller_state; 546 struct omap2_mcspi_dma *mcspi_dma; 547 unsigned int count; 548 u32 l; 549 u8 *rx; 550 const u8 *tx; 551 struct dma_slave_config cfg; 552 enum dma_slave_buswidth width; 553 unsigned es; 554 u32 burst; 555 void __iomem *chstat_reg; 556 void __iomem *irqstat_reg; 557 int wait_res; 558 559 mcspi = spi_master_get_devdata(spi->master); 560 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 561 l = mcspi_cached_chconf0(spi); 562 563 564 if (cs->word_len <= 8) { 565 width = DMA_SLAVE_BUSWIDTH_1_BYTE; 566 es = 1; 567 } else if (cs->word_len <= 16) { 568 width = DMA_SLAVE_BUSWIDTH_2_BYTES; 569 es = 2; 570 } else { 571 width = DMA_SLAVE_BUSWIDTH_4_BYTES; 572 es = 4; 573 } 574 575 count = xfer->len; 576 burst = 1; 577 578 if (mcspi->fifo_depth > 0) { 579 if (count > mcspi->fifo_depth) 580 burst = mcspi->fifo_depth / es; 581 else 582 burst = count / es; 583 } 584 585 memset(&cfg, 0, sizeof(cfg)); 586 cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0; 587 cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0; 588 cfg.src_addr_width = width; 589 cfg.dst_addr_width = width; 590 cfg.src_maxburst = burst; 591 cfg.dst_maxburst = burst; 592 593 rx = xfer->rx_buf; 594 tx = xfer->tx_buf; 595 596 if (tx != NULL) 597 omap2_mcspi_tx_dma(spi, xfer, cfg); 598 599 if (rx != NULL) 600 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es); 601 602 if (tx != NULL) { 603 wait_for_completion(&mcspi_dma->dma_tx_completion); 604 dma_unmap_single(mcspi->dev, xfer->tx_dma, xfer->len, 605 DMA_TO_DEVICE); 606 607 if (mcspi->fifo_depth > 0) { 608 irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS; 609 610 if (mcspi_wait_for_reg_bit(irqstat_reg, 611 OMAP2_MCSPI_IRQSTATUS_EOW) < 0) 612 dev_err(&spi->dev, "EOW timed out\n"); 613 614 mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS, 615 OMAP2_MCSPI_IRQSTATUS_EOW); 616 } 617 618 /* for TX_ONLY mode, be sure all words have shifted out */ 619 if (rx == NULL) { 620 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; 621 if (mcspi->fifo_depth > 0) { 622 wait_res = mcspi_wait_for_reg_bit(chstat_reg, 623 OMAP2_MCSPI_CHSTAT_TXFFE); 624 if (wait_res < 0) 625 dev_err(&spi->dev, "TXFFE timed out\n"); 626 } else { 627 wait_res = mcspi_wait_for_reg_bit(chstat_reg, 628 OMAP2_MCSPI_CHSTAT_TXS); 629 if (wait_res < 0) 630 dev_err(&spi->dev, "TXS timed out\n"); 631 } 632 if (wait_res >= 0 && 633 (mcspi_wait_for_reg_bit(chstat_reg, 634 OMAP2_MCSPI_CHSTAT_EOT) < 0)) 635 dev_err(&spi->dev, "EOT timed out\n"); 636 } 637 } 638 return count; 639 } 640 641 static unsigned 642 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) 643 { 644 struct omap2_mcspi *mcspi; 645 struct omap2_mcspi_cs *cs = spi->controller_state; 646 unsigned int count, c; 647 u32 l; 648 void __iomem *base = cs->base; 649 void __iomem *tx_reg; 650 void __iomem *rx_reg; 651 void __iomem *chstat_reg; 652 int word_len; 653 654 mcspi = spi_master_get_devdata(spi->master); 655 count = xfer->len; 656 c = count; 657 word_len = cs->word_len; 658 659 l = mcspi_cached_chconf0(spi); 660 661 /* We store the pre-calculated register addresses on stack to speed 662 * up the transfer loop. */ 663 tx_reg = base + OMAP2_MCSPI_TX0; 664 rx_reg = base + OMAP2_MCSPI_RX0; 665 chstat_reg = base + OMAP2_MCSPI_CHSTAT0; 666 667 if (c < (word_len>>3)) 668 return 0; 669 670 if (word_len <= 8) { 671 u8 *rx; 672 const u8 *tx; 673 674 rx = xfer->rx_buf; 675 tx = xfer->tx_buf; 676 677 do { 678 c -= 1; 679 if (tx != NULL) { 680 if (mcspi_wait_for_reg_bit(chstat_reg, 681 OMAP2_MCSPI_CHSTAT_TXS) < 0) { 682 dev_err(&spi->dev, "TXS timed out\n"); 683 goto out; 684 } 685 dev_vdbg(&spi->dev, "write-%d %02x\n", 686 word_len, *tx); 687 writel_relaxed(*tx++, tx_reg); 688 } 689 if (rx != NULL) { 690 if (mcspi_wait_for_reg_bit(chstat_reg, 691 OMAP2_MCSPI_CHSTAT_RXS) < 0) { 692 dev_err(&spi->dev, "RXS timed out\n"); 693 goto out; 694 } 695 696 if (c == 1 && tx == NULL && 697 (l & OMAP2_MCSPI_CHCONF_TURBO)) { 698 omap2_mcspi_set_enable(spi, 0); 699 *rx++ = readl_relaxed(rx_reg); 700 dev_vdbg(&spi->dev, "read-%d %02x\n", 701 word_len, *(rx - 1)); 702 if (mcspi_wait_for_reg_bit(chstat_reg, 703 OMAP2_MCSPI_CHSTAT_RXS) < 0) { 704 dev_err(&spi->dev, 705 "RXS timed out\n"); 706 goto out; 707 } 708 c = 0; 709 } else if (c == 0 && tx == NULL) { 710 omap2_mcspi_set_enable(spi, 0); 711 } 712 713 *rx++ = readl_relaxed(rx_reg); 714 dev_vdbg(&spi->dev, "read-%d %02x\n", 715 word_len, *(rx - 1)); 716 } 717 } while (c); 718 } else if (word_len <= 16) { 719 u16 *rx; 720 const u16 *tx; 721 722 rx = xfer->rx_buf; 723 tx = xfer->tx_buf; 724 do { 725 c -= 2; 726 if (tx != NULL) { 727 if (mcspi_wait_for_reg_bit(chstat_reg, 728 OMAP2_MCSPI_CHSTAT_TXS) < 0) { 729 dev_err(&spi->dev, "TXS timed out\n"); 730 goto out; 731 } 732 dev_vdbg(&spi->dev, "write-%d %04x\n", 733 word_len, *tx); 734 writel_relaxed(*tx++, tx_reg); 735 } 736 if (rx != NULL) { 737 if (mcspi_wait_for_reg_bit(chstat_reg, 738 OMAP2_MCSPI_CHSTAT_RXS) < 0) { 739 dev_err(&spi->dev, "RXS timed out\n"); 740 goto out; 741 } 742 743 if (c == 2 && tx == NULL && 744 (l & OMAP2_MCSPI_CHCONF_TURBO)) { 745 omap2_mcspi_set_enable(spi, 0); 746 *rx++ = readl_relaxed(rx_reg); 747 dev_vdbg(&spi->dev, "read-%d %04x\n", 748 word_len, *(rx - 1)); 749 if (mcspi_wait_for_reg_bit(chstat_reg, 750 OMAP2_MCSPI_CHSTAT_RXS) < 0) { 751 dev_err(&spi->dev, 752 "RXS timed out\n"); 753 goto out; 754 } 755 c = 0; 756 } else if (c == 0 && tx == NULL) { 757 omap2_mcspi_set_enable(spi, 0); 758 } 759 760 *rx++ = readl_relaxed(rx_reg); 761 dev_vdbg(&spi->dev, "read-%d %04x\n", 762 word_len, *(rx - 1)); 763 } 764 } while (c >= 2); 765 } else if (word_len <= 32) { 766 u32 *rx; 767 const u32 *tx; 768 769 rx = xfer->rx_buf; 770 tx = xfer->tx_buf; 771 do { 772 c -= 4; 773 if (tx != NULL) { 774 if (mcspi_wait_for_reg_bit(chstat_reg, 775 OMAP2_MCSPI_CHSTAT_TXS) < 0) { 776 dev_err(&spi->dev, "TXS timed out\n"); 777 goto out; 778 } 779 dev_vdbg(&spi->dev, "write-%d %08x\n", 780 word_len, *tx); 781 writel_relaxed(*tx++, tx_reg); 782 } 783 if (rx != NULL) { 784 if (mcspi_wait_for_reg_bit(chstat_reg, 785 OMAP2_MCSPI_CHSTAT_RXS) < 0) { 786 dev_err(&spi->dev, "RXS timed out\n"); 787 goto out; 788 } 789 790 if (c == 4 && tx == NULL && 791 (l & OMAP2_MCSPI_CHCONF_TURBO)) { 792 omap2_mcspi_set_enable(spi, 0); 793 *rx++ = readl_relaxed(rx_reg); 794 dev_vdbg(&spi->dev, "read-%d %08x\n", 795 word_len, *(rx - 1)); 796 if (mcspi_wait_for_reg_bit(chstat_reg, 797 OMAP2_MCSPI_CHSTAT_RXS) < 0) { 798 dev_err(&spi->dev, 799 "RXS timed out\n"); 800 goto out; 801 } 802 c = 0; 803 } else if (c == 0 && tx == NULL) { 804 omap2_mcspi_set_enable(spi, 0); 805 } 806 807 *rx++ = readl_relaxed(rx_reg); 808 dev_vdbg(&spi->dev, "read-%d %08x\n", 809 word_len, *(rx - 1)); 810 } 811 } while (c >= 4); 812 } 813 814 /* for TX_ONLY mode, be sure all words have shifted out */ 815 if (xfer->rx_buf == NULL) { 816 if (mcspi_wait_for_reg_bit(chstat_reg, 817 OMAP2_MCSPI_CHSTAT_TXS) < 0) { 818 dev_err(&spi->dev, "TXS timed out\n"); 819 } else if (mcspi_wait_for_reg_bit(chstat_reg, 820 OMAP2_MCSPI_CHSTAT_EOT) < 0) 821 dev_err(&spi->dev, "EOT timed out\n"); 822 823 /* disable chan to purge rx datas received in TX_ONLY transfer, 824 * otherwise these rx datas will affect the direct following 825 * RX_ONLY transfer. 826 */ 827 omap2_mcspi_set_enable(spi, 0); 828 } 829 out: 830 omap2_mcspi_set_enable(spi, 1); 831 return count - c; 832 } 833 834 static u32 omap2_mcspi_calc_divisor(u32 speed_hz) 835 { 836 u32 div; 837 838 for (div = 0; div < 15; div++) 839 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div)) 840 return div; 841 842 return 15; 843 } 844 845 /* called only when no transfer is active to this device */ 846 static int omap2_mcspi_setup_transfer(struct spi_device *spi, 847 struct spi_transfer *t) 848 { 849 struct omap2_mcspi_cs *cs = spi->controller_state; 850 struct omap2_mcspi *mcspi; 851 struct spi_master *spi_cntrl; 852 u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0; 853 u8 word_len = spi->bits_per_word; 854 u32 speed_hz = spi->max_speed_hz; 855 856 mcspi = spi_master_get_devdata(spi->master); 857 spi_cntrl = mcspi->master; 858 859 if (t != NULL && t->bits_per_word) 860 word_len = t->bits_per_word; 861 862 cs->word_len = word_len; 863 864 if (t && t->speed_hz) 865 speed_hz = t->speed_hz; 866 867 speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ); 868 if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) { 869 clkd = omap2_mcspi_calc_divisor(speed_hz); 870 speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd; 871 clkg = 0; 872 } else { 873 div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz; 874 speed_hz = OMAP2_MCSPI_MAX_FREQ / div; 875 clkd = (div - 1) & 0xf; 876 extclk = (div - 1) >> 4; 877 clkg = OMAP2_MCSPI_CHCONF_CLKG; 878 } 879 880 l = mcspi_cached_chconf0(spi); 881 882 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS 883 * REVISIT: this controller could support SPI_3WIRE mode. 884 */ 885 if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) { 886 l &= ~OMAP2_MCSPI_CHCONF_IS; 887 l &= ~OMAP2_MCSPI_CHCONF_DPE1; 888 l |= OMAP2_MCSPI_CHCONF_DPE0; 889 } else { 890 l |= OMAP2_MCSPI_CHCONF_IS; 891 l |= OMAP2_MCSPI_CHCONF_DPE1; 892 l &= ~OMAP2_MCSPI_CHCONF_DPE0; 893 } 894 895 /* wordlength */ 896 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK; 897 l |= (word_len - 1) << 7; 898 899 /* set chipselect polarity; manage with FORCE */ 900 if (!(spi->mode & SPI_CS_HIGH)) 901 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */ 902 else 903 l &= ~OMAP2_MCSPI_CHCONF_EPOL; 904 905 /* set clock divisor */ 906 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK; 907 l |= clkd << 2; 908 909 /* set clock granularity */ 910 l &= ~OMAP2_MCSPI_CHCONF_CLKG; 911 l |= clkg; 912 if (clkg) { 913 cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK; 914 cs->chctrl0 |= extclk << 8; 915 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); 916 } 917 918 /* set SPI mode 0..3 */ 919 if (spi->mode & SPI_CPOL) 920 l |= OMAP2_MCSPI_CHCONF_POL; 921 else 922 l &= ~OMAP2_MCSPI_CHCONF_POL; 923 if (spi->mode & SPI_CPHA) 924 l |= OMAP2_MCSPI_CHCONF_PHA; 925 else 926 l &= ~OMAP2_MCSPI_CHCONF_PHA; 927 928 mcspi_write_chconf0(spi, l); 929 930 cs->mode = spi->mode; 931 932 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", 933 speed_hz, 934 (spi->mode & SPI_CPHA) ? "trailing" : "leading", 935 (spi->mode & SPI_CPOL) ? "inverted" : "normal"); 936 937 return 0; 938 } 939 940 /* 941 * Note that we currently allow DMA only if we get a channel 942 * for both rx and tx. Otherwise we'll do PIO for both rx and tx. 943 */ 944 static int omap2_mcspi_request_dma(struct spi_device *spi) 945 { 946 struct spi_master *master = spi->master; 947 struct omap2_mcspi *mcspi; 948 struct omap2_mcspi_dma *mcspi_dma; 949 dma_cap_mask_t mask; 950 unsigned sig; 951 952 mcspi = spi_master_get_devdata(master); 953 mcspi_dma = mcspi->dma_channels + spi->chip_select; 954 955 init_completion(&mcspi_dma->dma_rx_completion); 956 init_completion(&mcspi_dma->dma_tx_completion); 957 958 dma_cap_zero(mask); 959 dma_cap_set(DMA_SLAVE, mask); 960 sig = mcspi_dma->dma_rx_sync_dev; 961 962 mcspi_dma->dma_rx = 963 dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 964 &sig, &master->dev, 965 mcspi_dma->dma_rx_ch_name); 966 if (!mcspi_dma->dma_rx) 967 goto no_dma; 968 969 sig = mcspi_dma->dma_tx_sync_dev; 970 mcspi_dma->dma_tx = 971 dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 972 &sig, &master->dev, 973 mcspi_dma->dma_tx_ch_name); 974 975 if (!mcspi_dma->dma_tx) { 976 dma_release_channel(mcspi_dma->dma_rx); 977 mcspi_dma->dma_rx = NULL; 978 goto no_dma; 979 } 980 981 return 0; 982 983 no_dma: 984 dev_warn(&spi->dev, "not using DMA for McSPI\n"); 985 return -EAGAIN; 986 } 987 988 static int omap2_mcspi_setup(struct spi_device *spi) 989 { 990 int ret; 991 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); 992 struct omap2_mcspi_regs *ctx = &mcspi->ctx; 993 struct omap2_mcspi_dma *mcspi_dma; 994 struct omap2_mcspi_cs *cs = spi->controller_state; 995 996 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 997 998 if (!cs) { 999 cs = kzalloc(sizeof *cs, GFP_KERNEL); 1000 if (!cs) 1001 return -ENOMEM; 1002 cs->base = mcspi->base + spi->chip_select * 0x14; 1003 cs->phys = mcspi->phys + spi->chip_select * 0x14; 1004 cs->mode = 0; 1005 cs->chconf0 = 0; 1006 cs->chctrl0 = 0; 1007 spi->controller_state = cs; 1008 /* Link this to context save list */ 1009 list_add_tail(&cs->node, &ctx->cs); 1010 } 1011 1012 if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) { 1013 ret = omap2_mcspi_request_dma(spi); 1014 if (ret < 0 && ret != -EAGAIN) 1015 return ret; 1016 } 1017 1018 ret = pm_runtime_get_sync(mcspi->dev); 1019 if (ret < 0) 1020 return ret; 1021 1022 ret = omap2_mcspi_setup_transfer(spi, NULL); 1023 pm_runtime_mark_last_busy(mcspi->dev); 1024 pm_runtime_put_autosuspend(mcspi->dev); 1025 1026 return ret; 1027 } 1028 1029 static void omap2_mcspi_cleanup(struct spi_device *spi) 1030 { 1031 struct omap2_mcspi *mcspi; 1032 struct omap2_mcspi_dma *mcspi_dma; 1033 struct omap2_mcspi_cs *cs; 1034 1035 mcspi = spi_master_get_devdata(spi->master); 1036 1037 if (spi->controller_state) { 1038 /* Unlink controller state from context save list */ 1039 cs = spi->controller_state; 1040 list_del(&cs->node); 1041 1042 kfree(cs); 1043 } 1044 1045 if (spi->chip_select < spi->master->num_chipselect) { 1046 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 1047 1048 if (mcspi_dma->dma_rx) { 1049 dma_release_channel(mcspi_dma->dma_rx); 1050 mcspi_dma->dma_rx = NULL; 1051 } 1052 if (mcspi_dma->dma_tx) { 1053 dma_release_channel(mcspi_dma->dma_tx); 1054 mcspi_dma->dma_tx = NULL; 1055 } 1056 } 1057 } 1058 1059 static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m) 1060 { 1061 1062 /* We only enable one channel at a time -- the one whose message is 1063 * -- although this controller would gladly 1064 * arbitrate among multiple channels. This corresponds to "single 1065 * channel" master mode. As a side effect, we need to manage the 1066 * chipselect with the FORCE bit ... CS != channel enable. 1067 */ 1068 1069 struct spi_device *spi; 1070 struct spi_transfer *t = NULL; 1071 struct spi_master *master; 1072 struct omap2_mcspi_dma *mcspi_dma; 1073 int cs_active = 0; 1074 struct omap2_mcspi_cs *cs; 1075 struct omap2_mcspi_device_config *cd; 1076 int par_override = 0; 1077 int status = 0; 1078 u32 chconf; 1079 1080 spi = m->spi; 1081 master = spi->master; 1082 mcspi_dma = mcspi->dma_channels + spi->chip_select; 1083 cs = spi->controller_state; 1084 cd = spi->controller_data; 1085 1086 /* 1087 * The slave driver could have changed spi->mode in which case 1088 * it will be different from cs->mode (the current hardware setup). 1089 * If so, set par_override (even though its not a parity issue) so 1090 * omap2_mcspi_setup_transfer will be called to configure the hardware 1091 * with the correct mode on the first iteration of the loop below. 1092 */ 1093 if (spi->mode != cs->mode) 1094 par_override = 1; 1095 1096 omap2_mcspi_set_enable(spi, 0); 1097 list_for_each_entry(t, &m->transfers, transfer_list) { 1098 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) { 1099 status = -EINVAL; 1100 break; 1101 } 1102 if (par_override || 1103 (t->speed_hz != spi->max_speed_hz) || 1104 (t->bits_per_word != spi->bits_per_word)) { 1105 par_override = 1; 1106 status = omap2_mcspi_setup_transfer(spi, t); 1107 if (status < 0) 1108 break; 1109 if (t->speed_hz == spi->max_speed_hz && 1110 t->bits_per_word == spi->bits_per_word) 1111 par_override = 0; 1112 } 1113 if (cd && cd->cs_per_word) { 1114 chconf = mcspi->ctx.modulctrl; 1115 chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE; 1116 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf); 1117 mcspi->ctx.modulctrl = 1118 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); 1119 } 1120 1121 1122 if (!cs_active) { 1123 omap2_mcspi_force_cs(spi, 1); 1124 cs_active = 1; 1125 } 1126 1127 chconf = mcspi_cached_chconf0(spi); 1128 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; 1129 chconf &= ~OMAP2_MCSPI_CHCONF_TURBO; 1130 1131 if (t->tx_buf == NULL) 1132 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY; 1133 else if (t->rx_buf == NULL) 1134 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY; 1135 1136 if (cd && cd->turbo_mode && t->tx_buf == NULL) { 1137 /* Turbo mode is for more than one word */ 1138 if (t->len > ((cs->word_len + 7) >> 3)) 1139 chconf |= OMAP2_MCSPI_CHCONF_TURBO; 1140 } 1141 1142 mcspi_write_chconf0(spi, chconf); 1143 1144 if (t->len) { 1145 unsigned count; 1146 1147 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && 1148 (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)) 1149 omap2_mcspi_set_fifo(spi, t, 1); 1150 1151 omap2_mcspi_set_enable(spi, 1); 1152 1153 /* RX_ONLY mode needs dummy data in TX reg */ 1154 if (t->tx_buf == NULL) 1155 writel_relaxed(0, cs->base 1156 + OMAP2_MCSPI_TX0); 1157 1158 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && 1159 (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)) 1160 count = omap2_mcspi_txrx_dma(spi, t); 1161 else 1162 count = omap2_mcspi_txrx_pio(spi, t); 1163 m->actual_length += count; 1164 1165 if (count != t->len) { 1166 status = -EIO; 1167 break; 1168 } 1169 } 1170 1171 if (t->delay_usecs) 1172 udelay(t->delay_usecs); 1173 1174 /* ignore the "leave it on after last xfer" hint */ 1175 if (t->cs_change) { 1176 omap2_mcspi_force_cs(spi, 0); 1177 cs_active = 0; 1178 } 1179 1180 omap2_mcspi_set_enable(spi, 0); 1181 1182 if (mcspi->fifo_depth > 0) 1183 omap2_mcspi_set_fifo(spi, t, 0); 1184 } 1185 /* Restore defaults if they were overriden */ 1186 if (par_override) { 1187 par_override = 0; 1188 status = omap2_mcspi_setup_transfer(spi, NULL); 1189 } 1190 1191 if (cs_active) 1192 omap2_mcspi_force_cs(spi, 0); 1193 1194 if (cd && cd->cs_per_word) { 1195 chconf = mcspi->ctx.modulctrl; 1196 chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE; 1197 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf); 1198 mcspi->ctx.modulctrl = 1199 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); 1200 } 1201 1202 omap2_mcspi_set_enable(spi, 0); 1203 1204 if (mcspi->fifo_depth > 0 && t) 1205 omap2_mcspi_set_fifo(spi, t, 0); 1206 1207 m->status = status; 1208 } 1209 1210 static int omap2_mcspi_transfer_one_message(struct spi_master *master, 1211 struct spi_message *m) 1212 { 1213 struct spi_device *spi; 1214 struct omap2_mcspi *mcspi; 1215 struct omap2_mcspi_dma *mcspi_dma; 1216 struct spi_transfer *t; 1217 1218 spi = m->spi; 1219 mcspi = spi_master_get_devdata(master); 1220 mcspi_dma = mcspi->dma_channels + spi->chip_select; 1221 m->actual_length = 0; 1222 m->status = 0; 1223 1224 list_for_each_entry(t, &m->transfers, transfer_list) { 1225 const void *tx_buf = t->tx_buf; 1226 void *rx_buf = t->rx_buf; 1227 unsigned len = t->len; 1228 1229 if ((len && !(rx_buf || tx_buf))) { 1230 dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n", 1231 t->speed_hz, 1232 len, 1233 tx_buf ? "tx" : "", 1234 rx_buf ? "rx" : "", 1235 t->bits_per_word); 1236 return -EINVAL; 1237 } 1238 1239 if (m->is_dma_mapped || len < DMA_MIN_BYTES) 1240 continue; 1241 1242 if (mcspi_dma->dma_tx && tx_buf != NULL) { 1243 t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf, 1244 len, DMA_TO_DEVICE); 1245 if (dma_mapping_error(mcspi->dev, t->tx_dma)) { 1246 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", 1247 'T', len); 1248 return -EINVAL; 1249 } 1250 } 1251 if (mcspi_dma->dma_rx && rx_buf != NULL) { 1252 t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len, 1253 DMA_FROM_DEVICE); 1254 if (dma_mapping_error(mcspi->dev, t->rx_dma)) { 1255 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", 1256 'R', len); 1257 if (tx_buf != NULL) 1258 dma_unmap_single(mcspi->dev, t->tx_dma, 1259 len, DMA_TO_DEVICE); 1260 return -EINVAL; 1261 } 1262 } 1263 } 1264 1265 omap2_mcspi_work(mcspi, m); 1266 spi_finalize_current_message(master); 1267 return 0; 1268 } 1269 1270 static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi) 1271 { 1272 struct spi_master *master = mcspi->master; 1273 struct omap2_mcspi_regs *ctx = &mcspi->ctx; 1274 int ret = 0; 1275 1276 ret = pm_runtime_get_sync(mcspi->dev); 1277 if (ret < 0) 1278 return ret; 1279 1280 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, 1281 OMAP2_MCSPI_WAKEUPENABLE_WKEN); 1282 ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN; 1283 1284 omap2_mcspi_set_master_mode(master); 1285 pm_runtime_mark_last_busy(mcspi->dev); 1286 pm_runtime_put_autosuspend(mcspi->dev); 1287 return 0; 1288 } 1289 1290 static int omap_mcspi_runtime_resume(struct device *dev) 1291 { 1292 struct omap2_mcspi *mcspi; 1293 struct spi_master *master; 1294 1295 master = dev_get_drvdata(dev); 1296 mcspi = spi_master_get_devdata(master); 1297 omap2_mcspi_restore_ctx(mcspi); 1298 1299 return 0; 1300 } 1301 1302 static struct omap2_mcspi_platform_config omap2_pdata = { 1303 .regs_offset = 0, 1304 }; 1305 1306 static struct omap2_mcspi_platform_config omap4_pdata = { 1307 .regs_offset = OMAP4_MCSPI_REG_OFFSET, 1308 }; 1309 1310 static const struct of_device_id omap_mcspi_of_match[] = { 1311 { 1312 .compatible = "ti,omap2-mcspi", 1313 .data = &omap2_pdata, 1314 }, 1315 { 1316 .compatible = "ti,omap4-mcspi", 1317 .data = &omap4_pdata, 1318 }, 1319 { }, 1320 }; 1321 MODULE_DEVICE_TABLE(of, omap_mcspi_of_match); 1322 1323 static int omap2_mcspi_probe(struct platform_device *pdev) 1324 { 1325 struct spi_master *master; 1326 const struct omap2_mcspi_platform_config *pdata; 1327 struct omap2_mcspi *mcspi; 1328 struct resource *r; 1329 int status = 0, i; 1330 u32 regs_offset = 0; 1331 static int bus_num = 1; 1332 struct device_node *node = pdev->dev.of_node; 1333 const struct of_device_id *match; 1334 1335 master = spi_alloc_master(&pdev->dev, sizeof *mcspi); 1336 if (master == NULL) { 1337 dev_dbg(&pdev->dev, "master allocation failed\n"); 1338 return -ENOMEM; 1339 } 1340 1341 /* the spi->mode bits understood by this driver: */ 1342 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1343 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1344 master->setup = omap2_mcspi_setup; 1345 master->auto_runtime_pm = true; 1346 master->transfer_one_message = omap2_mcspi_transfer_one_message; 1347 master->cleanup = omap2_mcspi_cleanup; 1348 master->dev.of_node = node; 1349 master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ; 1350 master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15; 1351 1352 platform_set_drvdata(pdev, master); 1353 1354 mcspi = spi_master_get_devdata(master); 1355 mcspi->master = master; 1356 1357 match = of_match_device(omap_mcspi_of_match, &pdev->dev); 1358 if (match) { 1359 u32 num_cs = 1; /* default number of chipselect */ 1360 pdata = match->data; 1361 1362 of_property_read_u32(node, "ti,spi-num-cs", &num_cs); 1363 master->num_chipselect = num_cs; 1364 master->bus_num = bus_num++; 1365 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL)) 1366 mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN; 1367 } else { 1368 pdata = dev_get_platdata(&pdev->dev); 1369 master->num_chipselect = pdata->num_cs; 1370 if (pdev->id != -1) 1371 master->bus_num = pdev->id; 1372 mcspi->pin_dir = pdata->pin_dir; 1373 } 1374 regs_offset = pdata->regs_offset; 1375 1376 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1377 if (r == NULL) { 1378 status = -ENODEV; 1379 goto free_master; 1380 } 1381 1382 r->start += regs_offset; 1383 r->end += regs_offset; 1384 mcspi->phys = r->start; 1385 1386 mcspi->base = devm_ioremap_resource(&pdev->dev, r); 1387 if (IS_ERR(mcspi->base)) { 1388 status = PTR_ERR(mcspi->base); 1389 goto free_master; 1390 } 1391 1392 mcspi->dev = &pdev->dev; 1393 1394 INIT_LIST_HEAD(&mcspi->ctx.cs); 1395 1396 mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect, 1397 sizeof(struct omap2_mcspi_dma), 1398 GFP_KERNEL); 1399 if (mcspi->dma_channels == NULL) { 1400 status = -ENOMEM; 1401 goto free_master; 1402 } 1403 1404 for (i = 0; i < master->num_chipselect; i++) { 1405 char *dma_rx_ch_name = mcspi->dma_channels[i].dma_rx_ch_name; 1406 char *dma_tx_ch_name = mcspi->dma_channels[i].dma_tx_ch_name; 1407 struct resource *dma_res; 1408 1409 sprintf(dma_rx_ch_name, "rx%d", i); 1410 if (!pdev->dev.of_node) { 1411 dma_res = 1412 platform_get_resource_byname(pdev, 1413 IORESOURCE_DMA, 1414 dma_rx_ch_name); 1415 if (!dma_res) { 1416 dev_dbg(&pdev->dev, 1417 "cannot get DMA RX channel\n"); 1418 status = -ENODEV; 1419 break; 1420 } 1421 1422 mcspi->dma_channels[i].dma_rx_sync_dev = 1423 dma_res->start; 1424 } 1425 sprintf(dma_tx_ch_name, "tx%d", i); 1426 if (!pdev->dev.of_node) { 1427 dma_res = 1428 platform_get_resource_byname(pdev, 1429 IORESOURCE_DMA, 1430 dma_tx_ch_name); 1431 if (!dma_res) { 1432 dev_dbg(&pdev->dev, 1433 "cannot get DMA TX channel\n"); 1434 status = -ENODEV; 1435 break; 1436 } 1437 1438 mcspi->dma_channels[i].dma_tx_sync_dev = 1439 dma_res->start; 1440 } 1441 } 1442 1443 if (status < 0) 1444 goto free_master; 1445 1446 pm_runtime_use_autosuspend(&pdev->dev); 1447 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); 1448 pm_runtime_enable(&pdev->dev); 1449 1450 status = omap2_mcspi_master_setup(mcspi); 1451 if (status < 0) 1452 goto disable_pm; 1453 1454 status = devm_spi_register_master(&pdev->dev, master); 1455 if (status < 0) 1456 goto disable_pm; 1457 1458 return status; 1459 1460 disable_pm: 1461 pm_runtime_disable(&pdev->dev); 1462 free_master: 1463 spi_master_put(master); 1464 return status; 1465 } 1466 1467 static int omap2_mcspi_remove(struct platform_device *pdev) 1468 { 1469 struct spi_master *master = platform_get_drvdata(pdev); 1470 struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 1471 1472 pm_runtime_put_sync(mcspi->dev); 1473 pm_runtime_disable(&pdev->dev); 1474 1475 return 0; 1476 } 1477 1478 /* work with hotplug and coldplug */ 1479 MODULE_ALIAS("platform:omap2_mcspi"); 1480 1481 #ifdef CONFIG_SUSPEND 1482 /* 1483 * When SPI wake up from off-mode, CS is in activate state. If it was in 1484 * unactive state when driver was suspend, then force it to unactive state at 1485 * wake up. 1486 */ 1487 static int omap2_mcspi_resume(struct device *dev) 1488 { 1489 struct spi_master *master = dev_get_drvdata(dev); 1490 struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 1491 struct omap2_mcspi_regs *ctx = &mcspi->ctx; 1492 struct omap2_mcspi_cs *cs; 1493 1494 pm_runtime_get_sync(mcspi->dev); 1495 list_for_each_entry(cs, &ctx->cs, node) { 1496 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) { 1497 /* 1498 * We need to toggle CS state for OMAP take this 1499 * change in account. 1500 */ 1501 cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE; 1502 writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); 1503 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; 1504 writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); 1505 } 1506 } 1507 pm_runtime_mark_last_busy(mcspi->dev); 1508 pm_runtime_put_autosuspend(mcspi->dev); 1509 return 0; 1510 } 1511 #else 1512 #define omap2_mcspi_resume NULL 1513 #endif 1514 1515 static const struct dev_pm_ops omap2_mcspi_pm_ops = { 1516 .resume = omap2_mcspi_resume, 1517 .runtime_resume = omap_mcspi_runtime_resume, 1518 }; 1519 1520 static struct platform_driver omap2_mcspi_driver = { 1521 .driver = { 1522 .name = "omap2_mcspi", 1523 .owner = THIS_MODULE, 1524 .pm = &omap2_mcspi_pm_ops, 1525 .of_match_table = omap_mcspi_of_match, 1526 }, 1527 .probe = omap2_mcspi_probe, 1528 .remove = omap2_mcspi_remove, 1529 }; 1530 1531 module_platform_driver(omap2_mcspi_driver); 1532 MODULE_LICENSE("GPL"); 1533