1 // SPDX-License-Identifier: GPL-2.0+ 2 3 /* 4 * NXP FlexSPI(FSPI) controller driver. 5 * 6 * Copyright 2019-2020 NXP 7 * Copyright 2020 Puresoftware Ltd. 8 * 9 * FlexSPI is a flexsible SPI host controller which supports two SPI 10 * channels and up to 4 external devices. Each channel supports 11 * Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional 12 * data lines). 13 * 14 * FlexSPI controller is driven by the LUT(Look-up Table) registers 15 * LUT registers are a look-up-table for sequences of instructions. 16 * A valid sequence consists of four LUT registers. 17 * Maximum 32 LUT sequences can be programmed simultaneously. 18 * 19 * LUTs are being created at run-time based on the commands passed 20 * from the spi-mem framework, thus using single LUT index. 21 * 22 * Software triggered Flash read/write access by IP Bus. 23 * 24 * Memory mapped read access by AHB Bus. 25 * 26 * Based on SPI MEM interface and spi-fsl-qspi.c driver. 27 * 28 * Author: 29 * Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com> 30 * Boris Brezillon <bbrezillon@kernel.org> 31 * Frieder Schrempf <frieder.schrempf@kontron.de> 32 */ 33 34 #include <linux/acpi.h> 35 #include <linux/bitops.h> 36 #include <linux/bitfield.h> 37 #include <linux/clk.h> 38 #include <linux/completion.h> 39 #include <linux/delay.h> 40 #include <linux/err.h> 41 #include <linux/errno.h> 42 #include <linux/interrupt.h> 43 #include <linux/io.h> 44 #include <linux/iopoll.h> 45 #include <linux/jiffies.h> 46 #include <linux/kernel.h> 47 #include <linux/module.h> 48 #include <linux/mutex.h> 49 #include <linux/of.h> 50 #include <linux/of_device.h> 51 #include <linux/platform_device.h> 52 #include <linux/pm_qos.h> 53 #include <linux/regmap.h> 54 #include <linux/sizes.h> 55 #include <linux/sys_soc.h> 56 57 #include <linux/mfd/syscon.h> 58 #include <linux/spi/spi.h> 59 #include <linux/spi/spi-mem.h> 60 61 /* 62 * The driver only uses one single LUT entry, that is updated on 63 * each call of exec_op(). Index 0 is preset at boot with a basic 64 * read operation, so let's use the last entry (31). 65 */ 66 #define SEQID_LUT 31 67 68 /* Registers used by the driver */ 69 #define FSPI_MCR0 0x00 70 #define FSPI_MCR0_AHB_TIMEOUT(x) ((x) << 24) 71 #define FSPI_MCR0_IP_TIMEOUT(x) ((x) << 16) 72 #define FSPI_MCR0_LEARN_EN BIT(15) 73 #define FSPI_MCR0_SCRFRUN_EN BIT(14) 74 #define FSPI_MCR0_OCTCOMB_EN BIT(13) 75 #define FSPI_MCR0_DOZE_EN BIT(12) 76 #define FSPI_MCR0_HSEN BIT(11) 77 #define FSPI_MCR0_SERCLKDIV BIT(8) 78 #define FSPI_MCR0_ATDF_EN BIT(7) 79 #define FSPI_MCR0_ARDF_EN BIT(6) 80 #define FSPI_MCR0_RXCLKSRC(x) ((x) << 4) 81 #define FSPI_MCR0_END_CFG(x) ((x) << 2) 82 #define FSPI_MCR0_MDIS BIT(1) 83 #define FSPI_MCR0_SWRST BIT(0) 84 85 #define FSPI_MCR1 0x04 86 #define FSPI_MCR1_SEQ_TIMEOUT(x) ((x) << 16) 87 #define FSPI_MCR1_AHB_TIMEOUT(x) (x) 88 89 #define FSPI_MCR2 0x08 90 #define FSPI_MCR2_IDLE_WAIT(x) ((x) << 24) 91 #define FSPI_MCR2_SAMEDEVICEEN BIT(15) 92 #define FSPI_MCR2_CLRLRPHS BIT(14) 93 #define FSPI_MCR2_ABRDATSZ BIT(8) 94 #define FSPI_MCR2_ABRLEARN BIT(7) 95 #define FSPI_MCR2_ABR_READ BIT(6) 96 #define FSPI_MCR2_ABRWRITE BIT(5) 97 #define FSPI_MCR2_ABRDUMMY BIT(4) 98 #define FSPI_MCR2_ABR_MODE BIT(3) 99 #define FSPI_MCR2_ABRCADDR BIT(2) 100 #define FSPI_MCR2_ABRRADDR BIT(1) 101 #define FSPI_MCR2_ABR_CMD BIT(0) 102 103 #define FSPI_AHBCR 0x0c 104 #define FSPI_AHBCR_RDADDROPT BIT(6) 105 #define FSPI_AHBCR_PREF_EN BIT(5) 106 #define FSPI_AHBCR_BUFF_EN BIT(4) 107 #define FSPI_AHBCR_CACH_EN BIT(3) 108 #define FSPI_AHBCR_CLRTXBUF BIT(2) 109 #define FSPI_AHBCR_CLRRXBUF BIT(1) 110 #define FSPI_AHBCR_PAR_EN BIT(0) 111 112 #define FSPI_INTEN 0x10 113 #define FSPI_INTEN_SCLKSBWR BIT(9) 114 #define FSPI_INTEN_SCLKSBRD BIT(8) 115 #define FSPI_INTEN_DATALRNFL BIT(7) 116 #define FSPI_INTEN_IPTXWE BIT(6) 117 #define FSPI_INTEN_IPRXWA BIT(5) 118 #define FSPI_INTEN_AHBCMDERR BIT(4) 119 #define FSPI_INTEN_IPCMDERR BIT(3) 120 #define FSPI_INTEN_AHBCMDGE BIT(2) 121 #define FSPI_INTEN_IPCMDGE BIT(1) 122 #define FSPI_INTEN_IPCMDDONE BIT(0) 123 124 #define FSPI_INTR 0x14 125 #define FSPI_INTR_SCLKSBWR BIT(9) 126 #define FSPI_INTR_SCLKSBRD BIT(8) 127 #define FSPI_INTR_DATALRNFL BIT(7) 128 #define FSPI_INTR_IPTXWE BIT(6) 129 #define FSPI_INTR_IPRXWA BIT(5) 130 #define FSPI_INTR_AHBCMDERR BIT(4) 131 #define FSPI_INTR_IPCMDERR BIT(3) 132 #define FSPI_INTR_AHBCMDGE BIT(2) 133 #define FSPI_INTR_IPCMDGE BIT(1) 134 #define FSPI_INTR_IPCMDDONE BIT(0) 135 136 #define FSPI_LUTKEY 0x18 137 #define FSPI_LUTKEY_VALUE 0x5AF05AF0 138 139 #define FSPI_LCKCR 0x1C 140 141 #define FSPI_LCKER_LOCK 0x1 142 #define FSPI_LCKER_UNLOCK 0x2 143 144 #define FSPI_BUFXCR_INVALID_MSTRID 0xE 145 #define FSPI_AHBRX_BUF0CR0 0x20 146 #define FSPI_AHBRX_BUF1CR0 0x24 147 #define FSPI_AHBRX_BUF2CR0 0x28 148 #define FSPI_AHBRX_BUF3CR0 0x2C 149 #define FSPI_AHBRX_BUF4CR0 0x30 150 #define FSPI_AHBRX_BUF5CR0 0x34 151 #define FSPI_AHBRX_BUF6CR0 0x38 152 #define FSPI_AHBRX_BUF7CR0 0x3C 153 #define FSPI_AHBRXBUF0CR7_PREF BIT(31) 154 155 #define FSPI_AHBRX_BUF0CR1 0x40 156 #define FSPI_AHBRX_BUF1CR1 0x44 157 #define FSPI_AHBRX_BUF2CR1 0x48 158 #define FSPI_AHBRX_BUF3CR1 0x4C 159 #define FSPI_AHBRX_BUF4CR1 0x50 160 #define FSPI_AHBRX_BUF5CR1 0x54 161 #define FSPI_AHBRX_BUF6CR1 0x58 162 #define FSPI_AHBRX_BUF7CR1 0x5C 163 164 #define FSPI_FLSHA1CR0 0x60 165 #define FSPI_FLSHA2CR0 0x64 166 #define FSPI_FLSHB1CR0 0x68 167 #define FSPI_FLSHB2CR0 0x6C 168 #define FSPI_FLSHXCR0_SZ_KB 10 169 #define FSPI_FLSHXCR0_SZ(x) ((x) >> FSPI_FLSHXCR0_SZ_KB) 170 171 #define FSPI_FLSHA1CR1 0x70 172 #define FSPI_FLSHA2CR1 0x74 173 #define FSPI_FLSHB1CR1 0x78 174 #define FSPI_FLSHB2CR1 0x7C 175 #define FSPI_FLSHXCR1_CSINTR(x) ((x) << 16) 176 #define FSPI_FLSHXCR1_CAS(x) ((x) << 11) 177 #define FSPI_FLSHXCR1_WA BIT(10) 178 #define FSPI_FLSHXCR1_TCSH(x) ((x) << 5) 179 #define FSPI_FLSHXCR1_TCSS(x) (x) 180 181 #define FSPI_FLSHA1CR2 0x80 182 #define FSPI_FLSHA2CR2 0x84 183 #define FSPI_FLSHB1CR2 0x88 184 #define FSPI_FLSHB2CR2 0x8C 185 #define FSPI_FLSHXCR2_CLRINSP BIT(24) 186 #define FSPI_FLSHXCR2_AWRWAIT BIT(16) 187 #define FSPI_FLSHXCR2_AWRSEQN_SHIFT 13 188 #define FSPI_FLSHXCR2_AWRSEQI_SHIFT 8 189 #define FSPI_FLSHXCR2_ARDSEQN_SHIFT 5 190 #define FSPI_FLSHXCR2_ARDSEQI_SHIFT 0 191 192 #define FSPI_IPCR0 0xA0 193 194 #define FSPI_IPCR1 0xA4 195 #define FSPI_IPCR1_IPAREN BIT(31) 196 #define FSPI_IPCR1_SEQNUM_SHIFT 24 197 #define FSPI_IPCR1_SEQID_SHIFT 16 198 #define FSPI_IPCR1_IDATSZ(x) (x) 199 200 #define FSPI_IPCMD 0xB0 201 #define FSPI_IPCMD_TRG BIT(0) 202 203 #define FSPI_DLPR 0xB4 204 205 #define FSPI_IPRXFCR 0xB8 206 #define FSPI_IPRXFCR_CLR BIT(0) 207 #define FSPI_IPRXFCR_DMA_EN BIT(1) 208 #define FSPI_IPRXFCR_WMRK(x) ((x) << 2) 209 210 #define FSPI_IPTXFCR 0xBC 211 #define FSPI_IPTXFCR_CLR BIT(0) 212 #define FSPI_IPTXFCR_DMA_EN BIT(1) 213 #define FSPI_IPTXFCR_WMRK(x) ((x) << 2) 214 215 #define FSPI_DLLACR 0xC0 216 #define FSPI_DLLACR_OVRDEN BIT(8) 217 #define FSPI_DLLACR_SLVDLY(x) ((x) << 3) 218 #define FSPI_DLLACR_DLLRESET BIT(1) 219 #define FSPI_DLLACR_DLLEN BIT(0) 220 221 #define FSPI_DLLBCR 0xC4 222 #define FSPI_DLLBCR_OVRDEN BIT(8) 223 #define FSPI_DLLBCR_SLVDLY(x) ((x) << 3) 224 #define FSPI_DLLBCR_DLLRESET BIT(1) 225 #define FSPI_DLLBCR_DLLEN BIT(0) 226 227 #define FSPI_STS0 0xE0 228 #define FSPI_STS0_DLPHB(x) ((x) << 8) 229 #define FSPI_STS0_DLPHA(x) ((x) << 4) 230 #define FSPI_STS0_CMD_SRC(x) ((x) << 2) 231 #define FSPI_STS0_ARB_IDLE BIT(1) 232 #define FSPI_STS0_SEQ_IDLE BIT(0) 233 234 #define FSPI_STS1 0xE4 235 #define FSPI_STS1_IP_ERRCD(x) ((x) << 24) 236 #define FSPI_STS1_IP_ERRID(x) ((x) << 16) 237 #define FSPI_STS1_AHB_ERRCD(x) ((x) << 8) 238 #define FSPI_STS1_AHB_ERRID(x) (x) 239 240 #define FSPI_STS2 0xE8 241 #define FSPI_STS2_BREFLOCK BIT(17) 242 #define FSPI_STS2_BSLVLOCK BIT(16) 243 #define FSPI_STS2_AREFLOCK BIT(1) 244 #define FSPI_STS2_ASLVLOCK BIT(0) 245 #define FSPI_STS2_AB_LOCK (FSPI_STS2_BREFLOCK | \ 246 FSPI_STS2_BSLVLOCK | \ 247 FSPI_STS2_AREFLOCK | \ 248 FSPI_STS2_ASLVLOCK) 249 250 #define FSPI_AHBSPNST 0xEC 251 #define FSPI_AHBSPNST_DATLFT(x) ((x) << 16) 252 #define FSPI_AHBSPNST_BUFID(x) ((x) << 1) 253 #define FSPI_AHBSPNST_ACTIVE BIT(0) 254 255 #define FSPI_IPRXFSTS 0xF0 256 #define FSPI_IPRXFSTS_RDCNTR(x) ((x) << 16) 257 #define FSPI_IPRXFSTS_FILL(x) (x) 258 259 #define FSPI_IPTXFSTS 0xF4 260 #define FSPI_IPTXFSTS_WRCNTR(x) ((x) << 16) 261 #define FSPI_IPTXFSTS_FILL(x) (x) 262 263 #define FSPI_RFDR 0x100 264 #define FSPI_TFDR 0x180 265 266 #define FSPI_LUT_BASE 0x200 267 #define FSPI_LUT_OFFSET (SEQID_LUT * 4 * 4) 268 #define FSPI_LUT_REG(idx) \ 269 (FSPI_LUT_BASE + FSPI_LUT_OFFSET + (idx) * 4) 270 271 /* register map end */ 272 273 /* Instruction set for the LUT register. */ 274 #define LUT_STOP 0x00 275 #define LUT_CMD 0x01 276 #define LUT_ADDR 0x02 277 #define LUT_CADDR_SDR 0x03 278 #define LUT_MODE 0x04 279 #define LUT_MODE2 0x05 280 #define LUT_MODE4 0x06 281 #define LUT_MODE8 0x07 282 #define LUT_NXP_WRITE 0x08 283 #define LUT_NXP_READ 0x09 284 #define LUT_LEARN_SDR 0x0A 285 #define LUT_DATSZ_SDR 0x0B 286 #define LUT_DUMMY 0x0C 287 #define LUT_DUMMY_RWDS_SDR 0x0D 288 #define LUT_JMP_ON_CS 0x1F 289 #define LUT_CMD_DDR 0x21 290 #define LUT_ADDR_DDR 0x22 291 #define LUT_CADDR_DDR 0x23 292 #define LUT_MODE_DDR 0x24 293 #define LUT_MODE2_DDR 0x25 294 #define LUT_MODE4_DDR 0x26 295 #define LUT_MODE8_DDR 0x27 296 #define LUT_WRITE_DDR 0x28 297 #define LUT_READ_DDR 0x29 298 #define LUT_LEARN_DDR 0x2A 299 #define LUT_DATSZ_DDR 0x2B 300 #define LUT_DUMMY_DDR 0x2C 301 #define LUT_DUMMY_RWDS_DDR 0x2D 302 303 /* 304 * Calculate number of required PAD bits for LUT register. 305 * 306 * The pad stands for the number of IO lines [0:7]. 307 * For example, the octal read needs eight IO lines, 308 * so you should use LUT_PAD(8). This macro 309 * returns 3 i.e. use eight (2^3) IP lines for read. 310 */ 311 #define LUT_PAD(x) (fls(x) - 1) 312 313 /* 314 * Macro for constructing the LUT entries with the following 315 * register layout: 316 * 317 * --------------------------------------------------- 318 * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 | 319 * --------------------------------------------------- 320 */ 321 #define PAD_SHIFT 8 322 #define INSTR_SHIFT 10 323 #define OPRND_SHIFT 16 324 325 /* Macros for constructing the LUT register. */ 326 #define LUT_DEF(idx, ins, pad, opr) \ 327 ((((ins) << INSTR_SHIFT) | ((pad) << PAD_SHIFT) | \ 328 (opr)) << (((idx) % 2) * OPRND_SHIFT)) 329 330 #define POLL_TOUT 5000 331 #define NXP_FSPI_MAX_CHIPSELECT 4 332 #define NXP_FSPI_MIN_IOMAP SZ_4M 333 334 #define DCFG_RCWSR1 0x100 335 #define SYS_PLL_RAT GENMASK(6, 2) 336 337 /* Access flash memory using IP bus only */ 338 #define FSPI_QUIRK_USE_IP_ONLY BIT(0) 339 340 struct nxp_fspi_devtype_data { 341 unsigned int rxfifo; 342 unsigned int txfifo; 343 unsigned int ahb_buf_size; 344 unsigned int quirks; 345 bool little_endian; 346 }; 347 348 static struct nxp_fspi_devtype_data lx2160a_data = { 349 .rxfifo = SZ_512, /* (64 * 64 bits) */ 350 .txfifo = SZ_1K, /* (128 * 64 bits) */ 351 .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ 352 .quirks = 0, 353 .little_endian = true, /* little-endian */ 354 }; 355 356 static struct nxp_fspi_devtype_data imx8mm_data = { 357 .rxfifo = SZ_512, /* (64 * 64 bits) */ 358 .txfifo = SZ_1K, /* (128 * 64 bits) */ 359 .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ 360 .quirks = 0, 361 .little_endian = true, /* little-endian */ 362 }; 363 364 static struct nxp_fspi_devtype_data imx8qxp_data = { 365 .rxfifo = SZ_512, /* (64 * 64 bits) */ 366 .txfifo = SZ_1K, /* (128 * 64 bits) */ 367 .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ 368 .quirks = 0, 369 .little_endian = true, /* little-endian */ 370 }; 371 372 static struct nxp_fspi_devtype_data imx8dxl_data = { 373 .rxfifo = SZ_512, /* (64 * 64 bits) */ 374 .txfifo = SZ_1K, /* (128 * 64 bits) */ 375 .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ 376 .quirks = FSPI_QUIRK_USE_IP_ONLY, 377 .little_endian = true, /* little-endian */ 378 }; 379 380 struct nxp_fspi { 381 void __iomem *iobase; 382 void __iomem *ahb_addr; 383 u32 memmap_phy; 384 u32 memmap_phy_size; 385 u32 memmap_start; 386 u32 memmap_len; 387 struct clk *clk, *clk_en; 388 struct device *dev; 389 struct completion c; 390 struct nxp_fspi_devtype_data *devtype_data; 391 struct mutex lock; 392 struct pm_qos_request pm_qos_req; 393 int selected; 394 }; 395 396 static inline int needs_ip_only(struct nxp_fspi *f) 397 { 398 return f->devtype_data->quirks & FSPI_QUIRK_USE_IP_ONLY; 399 } 400 401 /* 402 * R/W functions for big- or little-endian registers: 403 * The FSPI controller's endianness is independent of 404 * the CPU core's endianness. So far, although the CPU 405 * core is little-endian the FSPI controller can use 406 * big-endian or little-endian. 407 */ 408 static void fspi_writel(struct nxp_fspi *f, u32 val, void __iomem *addr) 409 { 410 if (f->devtype_data->little_endian) 411 iowrite32(val, addr); 412 else 413 iowrite32be(val, addr); 414 } 415 416 static u32 fspi_readl(struct nxp_fspi *f, void __iomem *addr) 417 { 418 if (f->devtype_data->little_endian) 419 return ioread32(addr); 420 else 421 return ioread32be(addr); 422 } 423 424 static irqreturn_t nxp_fspi_irq_handler(int irq, void *dev_id) 425 { 426 struct nxp_fspi *f = dev_id; 427 u32 reg; 428 429 /* clear interrupt */ 430 reg = fspi_readl(f, f->iobase + FSPI_INTR); 431 fspi_writel(f, FSPI_INTR_IPCMDDONE, f->iobase + FSPI_INTR); 432 433 if (reg & FSPI_INTR_IPCMDDONE) 434 complete(&f->c); 435 436 return IRQ_HANDLED; 437 } 438 439 static int nxp_fspi_check_buswidth(struct nxp_fspi *f, u8 width) 440 { 441 switch (width) { 442 case 1: 443 case 2: 444 case 4: 445 case 8: 446 return 0; 447 } 448 449 return -ENOTSUPP; 450 } 451 452 static bool nxp_fspi_supports_op(struct spi_mem *mem, 453 const struct spi_mem_op *op) 454 { 455 struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master); 456 int ret; 457 458 ret = nxp_fspi_check_buswidth(f, op->cmd.buswidth); 459 460 if (op->addr.nbytes) 461 ret |= nxp_fspi_check_buswidth(f, op->addr.buswidth); 462 463 if (op->dummy.nbytes) 464 ret |= nxp_fspi_check_buswidth(f, op->dummy.buswidth); 465 466 if (op->data.nbytes) 467 ret |= nxp_fspi_check_buswidth(f, op->data.buswidth); 468 469 if (ret) 470 return false; 471 472 /* 473 * The number of address bytes should be equal to or less than 4 bytes. 474 */ 475 if (op->addr.nbytes > 4) 476 return false; 477 478 /* 479 * If requested address value is greater than controller assigned 480 * memory mapped space, return error as it didn't fit in the range 481 * of assigned address space. 482 */ 483 if (op->addr.val >= f->memmap_phy_size) 484 return false; 485 486 /* Max 64 dummy clock cycles supported */ 487 if (op->dummy.buswidth && 488 (op->dummy.nbytes * 8 / op->dummy.buswidth > 64)) 489 return false; 490 491 /* Max data length, check controller limits and alignment */ 492 if (op->data.dir == SPI_MEM_DATA_IN && 493 (op->data.nbytes > f->devtype_data->ahb_buf_size || 494 (op->data.nbytes > f->devtype_data->rxfifo - 4 && 495 !IS_ALIGNED(op->data.nbytes, 8)))) 496 return false; 497 498 if (op->data.dir == SPI_MEM_DATA_OUT && 499 op->data.nbytes > f->devtype_data->txfifo) 500 return false; 501 502 return spi_mem_default_supports_op(mem, op); 503 } 504 505 /* Instead of busy looping invoke readl_poll_timeout functionality. */ 506 static int fspi_readl_poll_tout(struct nxp_fspi *f, void __iomem *base, 507 u32 mask, u32 delay_us, 508 u32 timeout_us, bool c) 509 { 510 u32 reg; 511 512 if (!f->devtype_data->little_endian) 513 mask = (u32)cpu_to_be32(mask); 514 515 if (c) 516 return readl_poll_timeout(base, reg, (reg & mask), 517 delay_us, timeout_us); 518 else 519 return readl_poll_timeout(base, reg, !(reg & mask), 520 delay_us, timeout_us); 521 } 522 523 /* 524 * If the slave device content being changed by Write/Erase, need to 525 * invalidate the AHB buffer. This can be achieved by doing the reset 526 * of controller after setting MCR0[SWRESET] bit. 527 */ 528 static inline void nxp_fspi_invalid(struct nxp_fspi *f) 529 { 530 u32 reg; 531 int ret; 532 533 reg = fspi_readl(f, f->iobase + FSPI_MCR0); 534 fspi_writel(f, reg | FSPI_MCR0_SWRST, f->iobase + FSPI_MCR0); 535 536 /* w1c register, wait unit clear */ 537 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0, 538 FSPI_MCR0_SWRST, 0, POLL_TOUT, false); 539 WARN_ON(ret); 540 } 541 542 static void nxp_fspi_prepare_lut(struct nxp_fspi *f, 543 const struct spi_mem_op *op) 544 { 545 void __iomem *base = f->iobase; 546 u32 lutval[4] = {}; 547 int lutidx = 1, i; 548 549 /* cmd */ 550 lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth), 551 op->cmd.opcode); 552 553 /* addr bytes */ 554 if (op->addr.nbytes) { 555 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_ADDR, 556 LUT_PAD(op->addr.buswidth), 557 op->addr.nbytes * 8); 558 lutidx++; 559 } 560 561 /* dummy bytes, if needed */ 562 if (op->dummy.nbytes) { 563 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY, 564 /* 565 * Due to FlexSPI controller limitation number of PAD for dummy 566 * buswidth needs to be programmed as equal to data buswidth. 567 */ 568 LUT_PAD(op->data.buswidth), 569 op->dummy.nbytes * 8 / 570 op->dummy.buswidth); 571 lutidx++; 572 } 573 574 /* read/write data bytes */ 575 if (op->data.nbytes) { 576 lutval[lutidx / 2] |= LUT_DEF(lutidx, 577 op->data.dir == SPI_MEM_DATA_IN ? 578 LUT_NXP_READ : LUT_NXP_WRITE, 579 LUT_PAD(op->data.buswidth), 580 0); 581 lutidx++; 582 } 583 584 /* stop condition. */ 585 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0); 586 587 /* unlock LUT */ 588 fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY); 589 fspi_writel(f, FSPI_LCKER_UNLOCK, f->iobase + FSPI_LCKCR); 590 591 /* fill LUT */ 592 for (i = 0; i < ARRAY_SIZE(lutval); i++) 593 fspi_writel(f, lutval[i], base + FSPI_LUT_REG(i)); 594 595 dev_dbg(f->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x], size: 0x%08x\n", 596 op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3], op->data.nbytes); 597 598 /* lock LUT */ 599 fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY); 600 fspi_writel(f, FSPI_LCKER_LOCK, f->iobase + FSPI_LCKCR); 601 } 602 603 static int nxp_fspi_clk_prep_enable(struct nxp_fspi *f) 604 { 605 int ret; 606 607 if (is_acpi_node(dev_fwnode(f->dev))) 608 return 0; 609 610 ret = clk_prepare_enable(f->clk_en); 611 if (ret) 612 return ret; 613 614 ret = clk_prepare_enable(f->clk); 615 if (ret) { 616 clk_disable_unprepare(f->clk_en); 617 return ret; 618 } 619 620 return 0; 621 } 622 623 static int nxp_fspi_clk_disable_unprep(struct nxp_fspi *f) 624 { 625 if (is_acpi_node(dev_fwnode(f->dev))) 626 return 0; 627 628 clk_disable_unprepare(f->clk); 629 clk_disable_unprepare(f->clk_en); 630 631 return 0; 632 } 633 634 static void nxp_fspi_dll_calibration(struct nxp_fspi *f) 635 { 636 int ret; 637 638 /* Reset the DLL, set the DLLRESET to 1 and then set to 0 */ 639 fspi_writel(f, FSPI_DLLACR_DLLRESET, f->iobase + FSPI_DLLACR); 640 fspi_writel(f, FSPI_DLLBCR_DLLRESET, f->iobase + FSPI_DLLBCR); 641 fspi_writel(f, 0, f->iobase + FSPI_DLLACR); 642 fspi_writel(f, 0, f->iobase + FSPI_DLLBCR); 643 644 /* 645 * Enable the DLL calibration mode. 646 * The delay target for slave delay line is: 647 * ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock. 648 * When clock rate > 100MHz, recommend SLVDLYTARGET is 0xF, which 649 * means half of clock cycle of reference clock. 650 */ 651 fspi_writel(f, FSPI_DLLACR_DLLEN | FSPI_DLLACR_SLVDLY(0xF), 652 f->iobase + FSPI_DLLACR); 653 fspi_writel(f, FSPI_DLLBCR_DLLEN | FSPI_DLLBCR_SLVDLY(0xF), 654 f->iobase + FSPI_DLLBCR); 655 656 /* Wait to get REF/SLV lock */ 657 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_STS2, FSPI_STS2_AB_LOCK, 658 0, POLL_TOUT, true); 659 if (ret) 660 dev_warn(f->dev, "DLL lock failed, please fix it!\n"); 661 } 662 663 /* 664 * In FlexSPI controller, flash access is based on value of FSPI_FLSHXXCR0 665 * register and start base address of the slave device. 666 * 667 * (Higher address) 668 * -------- <-- FLSHB2CR0 669 * | B2 | 670 * | | 671 * B2 start address --> -------- <-- FLSHB1CR0 672 * | B1 | 673 * | | 674 * B1 start address --> -------- <-- FLSHA2CR0 675 * | A2 | 676 * | | 677 * A2 start address --> -------- <-- FLSHA1CR0 678 * | A1 | 679 * | | 680 * A1 start address --> -------- (Lower address) 681 * 682 * 683 * Start base address defines the starting address range for given CS and 684 * FSPI_FLSHXXCR0 defines the size of the slave device connected at given CS. 685 * 686 * But, different targets are having different combinations of number of CS, 687 * some targets only have single CS or two CS covering controller's full 688 * memory mapped space area. 689 * Thus, implementation is being done as independent of the size and number 690 * of the connected slave device. 691 * Assign controller memory mapped space size as the size to the connected 692 * slave device. 693 * Mark FLSHxxCR0 as zero initially and then assign value only to the selected 694 * chip-select Flash configuration register. 695 * 696 * For e.g. to access CS2 (B1), FLSHB1CR0 register would be equal to the 697 * memory mapped size of the controller. 698 * Value for rest of the CS FLSHxxCR0 register would be zero. 699 * 700 */ 701 static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi) 702 { 703 unsigned long rate = spi->max_speed_hz; 704 int ret; 705 uint64_t size_kb; 706 707 /* 708 * Return, if previously selected slave device is same as current 709 * requested slave device. 710 */ 711 if (f->selected == spi_get_chipselect(spi, 0)) 712 return; 713 714 /* Reset FLSHxxCR0 registers */ 715 fspi_writel(f, 0, f->iobase + FSPI_FLSHA1CR0); 716 fspi_writel(f, 0, f->iobase + FSPI_FLSHA2CR0); 717 fspi_writel(f, 0, f->iobase + FSPI_FLSHB1CR0); 718 fspi_writel(f, 0, f->iobase + FSPI_FLSHB2CR0); 719 720 /* Assign controller memory mapped space as size, KBytes, of flash. */ 721 size_kb = FSPI_FLSHXCR0_SZ(f->memmap_phy_size); 722 723 fspi_writel(f, size_kb, f->iobase + FSPI_FLSHA1CR0 + 724 4 * spi_get_chipselect(spi, 0)); 725 726 dev_dbg(f->dev, "Slave device [CS:%x] selected\n", spi_get_chipselect(spi, 0)); 727 728 nxp_fspi_clk_disable_unprep(f); 729 730 ret = clk_set_rate(f->clk, rate); 731 if (ret) 732 return; 733 734 ret = nxp_fspi_clk_prep_enable(f); 735 if (ret) 736 return; 737 738 /* 739 * If clock rate > 100MHz, then switch from DLL override mode to 740 * DLL calibration mode. 741 */ 742 if (rate > 100000000) 743 nxp_fspi_dll_calibration(f); 744 745 f->selected = spi_get_chipselect(spi, 0); 746 } 747 748 static int nxp_fspi_read_ahb(struct nxp_fspi *f, const struct spi_mem_op *op) 749 { 750 u32 start = op->addr.val; 751 u32 len = op->data.nbytes; 752 753 /* if necessary, ioremap before AHB read */ 754 if ((!f->ahb_addr) || start < f->memmap_start || 755 start + len > f->memmap_start + f->memmap_len) { 756 if (f->ahb_addr) 757 iounmap(f->ahb_addr); 758 759 f->memmap_start = start; 760 f->memmap_len = len > NXP_FSPI_MIN_IOMAP ? 761 len : NXP_FSPI_MIN_IOMAP; 762 763 f->ahb_addr = ioremap_wc(f->memmap_phy + f->memmap_start, 764 f->memmap_len); 765 766 if (!f->ahb_addr) { 767 dev_err(f->dev, "failed to alloc memory\n"); 768 return -ENOMEM; 769 } 770 } 771 772 /* Read out the data directly from the AHB buffer. */ 773 memcpy_fromio(op->data.buf.in, 774 f->ahb_addr + start - f->memmap_start, len); 775 776 return 0; 777 } 778 779 static void nxp_fspi_fill_txfifo(struct nxp_fspi *f, 780 const struct spi_mem_op *op) 781 { 782 void __iomem *base = f->iobase; 783 int i, ret; 784 u8 *buf = (u8 *) op->data.buf.out; 785 786 /* clear the TX FIFO. */ 787 fspi_writel(f, FSPI_IPTXFCR_CLR, base + FSPI_IPTXFCR); 788 789 /* 790 * Default value of water mark level is 8 bytes, hence in single 791 * write request controller can write max 8 bytes of data. 792 */ 793 794 for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 8); i += 8) { 795 /* Wait for TXFIFO empty */ 796 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, 797 FSPI_INTR_IPTXWE, 0, 798 POLL_TOUT, true); 799 WARN_ON(ret); 800 801 fspi_writel(f, *(u32 *) (buf + i), base + FSPI_TFDR); 802 fspi_writel(f, *(u32 *) (buf + i + 4), base + FSPI_TFDR + 4); 803 fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR); 804 } 805 806 if (i < op->data.nbytes) { 807 u32 data = 0; 808 int j; 809 /* Wait for TXFIFO empty */ 810 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, 811 FSPI_INTR_IPTXWE, 0, 812 POLL_TOUT, true); 813 WARN_ON(ret); 814 815 for (j = 0; j < ALIGN(op->data.nbytes - i, 4); j += 4) { 816 memcpy(&data, buf + i + j, 4); 817 fspi_writel(f, data, base + FSPI_TFDR + j); 818 } 819 fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR); 820 } 821 } 822 823 static void nxp_fspi_read_rxfifo(struct nxp_fspi *f, 824 const struct spi_mem_op *op) 825 { 826 void __iomem *base = f->iobase; 827 int i, ret; 828 int len = op->data.nbytes; 829 u8 *buf = (u8 *) op->data.buf.in; 830 831 /* 832 * Default value of water mark level is 8 bytes, hence in single 833 * read request controller can read max 8 bytes of data. 834 */ 835 for (i = 0; i < ALIGN_DOWN(len, 8); i += 8) { 836 /* Wait for RXFIFO available */ 837 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, 838 FSPI_INTR_IPRXWA, 0, 839 POLL_TOUT, true); 840 WARN_ON(ret); 841 842 *(u32 *)(buf + i) = fspi_readl(f, base + FSPI_RFDR); 843 *(u32 *)(buf + i + 4) = fspi_readl(f, base + FSPI_RFDR + 4); 844 /* move the FIFO pointer */ 845 fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR); 846 } 847 848 if (i < len) { 849 u32 tmp; 850 int size, j; 851 852 buf = op->data.buf.in + i; 853 /* Wait for RXFIFO available */ 854 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, 855 FSPI_INTR_IPRXWA, 0, 856 POLL_TOUT, true); 857 WARN_ON(ret); 858 859 len = op->data.nbytes - i; 860 for (j = 0; j < op->data.nbytes - i; j += 4) { 861 tmp = fspi_readl(f, base + FSPI_RFDR + j); 862 size = min(len, 4); 863 memcpy(buf + j, &tmp, size); 864 len -= size; 865 } 866 } 867 868 /* invalid the RXFIFO */ 869 fspi_writel(f, FSPI_IPRXFCR_CLR, base + FSPI_IPRXFCR); 870 /* move the FIFO pointer */ 871 fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR); 872 } 873 874 static int nxp_fspi_do_op(struct nxp_fspi *f, const struct spi_mem_op *op) 875 { 876 void __iomem *base = f->iobase; 877 int seqnum = 0; 878 int err = 0; 879 u32 reg; 880 881 reg = fspi_readl(f, base + FSPI_IPRXFCR); 882 /* invalid RXFIFO first */ 883 reg &= ~FSPI_IPRXFCR_DMA_EN; 884 reg = reg | FSPI_IPRXFCR_CLR; 885 fspi_writel(f, reg, base + FSPI_IPRXFCR); 886 887 init_completion(&f->c); 888 889 fspi_writel(f, op->addr.val, base + FSPI_IPCR0); 890 /* 891 * Always start the sequence at the same index since we update 892 * the LUT at each exec_op() call. And also specify the DATA 893 * length, since it's has not been specified in the LUT. 894 */ 895 fspi_writel(f, op->data.nbytes | 896 (SEQID_LUT << FSPI_IPCR1_SEQID_SHIFT) | 897 (seqnum << FSPI_IPCR1_SEQNUM_SHIFT), 898 base + FSPI_IPCR1); 899 900 /* Trigger the LUT now. */ 901 fspi_writel(f, FSPI_IPCMD_TRG, base + FSPI_IPCMD); 902 903 /* Wait for the interrupt. */ 904 if (!wait_for_completion_timeout(&f->c, msecs_to_jiffies(1000))) 905 err = -ETIMEDOUT; 906 907 /* Invoke IP data read, if request is of data read. */ 908 if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN) 909 nxp_fspi_read_rxfifo(f, op); 910 911 return err; 912 } 913 914 static int nxp_fspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) 915 { 916 struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master); 917 int err = 0; 918 919 mutex_lock(&f->lock); 920 921 /* Wait for controller being ready. */ 922 err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0, 923 FSPI_STS0_ARB_IDLE, 1, POLL_TOUT, true); 924 WARN_ON(err); 925 926 nxp_fspi_select_mem(f, mem->spi); 927 928 nxp_fspi_prepare_lut(f, op); 929 /* 930 * If we have large chunks of data, we read them through the AHB bus by 931 * accessing the mapped memory. In all other cases we use IP commands 932 * to access the flash. Read via AHB bus may be corrupted due to 933 * existence of an errata and therefore discard AHB read in such cases. 934 */ 935 if (op->data.nbytes > (f->devtype_data->rxfifo - 4) && 936 op->data.dir == SPI_MEM_DATA_IN && 937 !needs_ip_only(f)) { 938 err = nxp_fspi_read_ahb(f, op); 939 } else { 940 if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) 941 nxp_fspi_fill_txfifo(f, op); 942 943 err = nxp_fspi_do_op(f, op); 944 } 945 946 /* Invalidate the data in the AHB buffer. */ 947 nxp_fspi_invalid(f); 948 949 mutex_unlock(&f->lock); 950 951 return err; 952 } 953 954 static int nxp_fspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) 955 { 956 struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master); 957 958 if (op->data.dir == SPI_MEM_DATA_OUT) { 959 if (op->data.nbytes > f->devtype_data->txfifo) 960 op->data.nbytes = f->devtype_data->txfifo; 961 } else { 962 if (op->data.nbytes > f->devtype_data->ahb_buf_size) 963 op->data.nbytes = f->devtype_data->ahb_buf_size; 964 else if (op->data.nbytes > (f->devtype_data->rxfifo - 4)) 965 op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8); 966 } 967 968 /* Limit data bytes to RX FIFO in case of IP read only */ 969 if (op->data.dir == SPI_MEM_DATA_IN && 970 needs_ip_only(f) && 971 op->data.nbytes > f->devtype_data->rxfifo) 972 op->data.nbytes = f->devtype_data->rxfifo; 973 974 return 0; 975 } 976 977 static void erratum_err050568(struct nxp_fspi *f) 978 { 979 static const struct soc_device_attribute ls1028a_soc_attr[] = { 980 { .family = "QorIQ LS1028A" }, 981 { /* sentinel */ } 982 }; 983 struct regmap *map; 984 u32 val, sys_pll_ratio; 985 int ret; 986 987 /* Check for LS1028A family */ 988 if (!soc_device_match(ls1028a_soc_attr)) { 989 dev_dbg(f->dev, "Errata applicable only for LS1028A\n"); 990 return; 991 } 992 993 map = syscon_regmap_lookup_by_compatible("fsl,ls1028a-dcfg"); 994 if (IS_ERR(map)) { 995 dev_err(f->dev, "No syscon regmap\n"); 996 goto err; 997 } 998 999 ret = regmap_read(map, DCFG_RCWSR1, &val); 1000 if (ret < 0) 1001 goto err; 1002 1003 sys_pll_ratio = FIELD_GET(SYS_PLL_RAT, val); 1004 dev_dbg(f->dev, "val: 0x%08x, sys_pll_ratio: %d\n", val, sys_pll_ratio); 1005 1006 /* Use IP bus only if platform clock is 300MHz */ 1007 if (sys_pll_ratio == 3) 1008 f->devtype_data->quirks |= FSPI_QUIRK_USE_IP_ONLY; 1009 1010 return; 1011 1012 err: 1013 dev_err(f->dev, "Errata cannot be executed. Read via IP bus may not work\n"); 1014 } 1015 1016 static int nxp_fspi_default_setup(struct nxp_fspi *f) 1017 { 1018 void __iomem *base = f->iobase; 1019 int ret, i; 1020 u32 reg; 1021 1022 /* disable and unprepare clock to avoid glitch pass to controller */ 1023 nxp_fspi_clk_disable_unprep(f); 1024 1025 /* the default frequency, we will change it later if necessary. */ 1026 ret = clk_set_rate(f->clk, 20000000); 1027 if (ret) 1028 return ret; 1029 1030 ret = nxp_fspi_clk_prep_enable(f); 1031 if (ret) 1032 return ret; 1033 1034 /* 1035 * ERR050568: Flash access by FlexSPI AHB command may not work with 1036 * platform frequency equal to 300 MHz on LS1028A. 1037 * LS1028A reuses LX2160A compatible entry. Make errata applicable for 1038 * Layerscape LS1028A platform. 1039 */ 1040 if (of_device_is_compatible(f->dev->of_node, "nxp,lx2160a-fspi")) 1041 erratum_err050568(f); 1042 1043 /* Reset the module */ 1044 /* w1c register, wait unit clear */ 1045 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0, 1046 FSPI_MCR0_SWRST, 0, POLL_TOUT, false); 1047 WARN_ON(ret); 1048 1049 /* Disable the module */ 1050 fspi_writel(f, FSPI_MCR0_MDIS, base + FSPI_MCR0); 1051 1052 /* 1053 * Config the DLL register to default value, enable the slave clock delay 1054 * line delay cell override mode, and use 1 fixed delay cell in DLL delay 1055 * chain, this is the suggested setting when clock rate < 100MHz. 1056 */ 1057 fspi_writel(f, FSPI_DLLACR_OVRDEN, base + FSPI_DLLACR); 1058 fspi_writel(f, FSPI_DLLBCR_OVRDEN, base + FSPI_DLLBCR); 1059 1060 /* enable module */ 1061 fspi_writel(f, FSPI_MCR0_AHB_TIMEOUT(0xFF) | 1062 FSPI_MCR0_IP_TIMEOUT(0xFF) | (u32) FSPI_MCR0_OCTCOMB_EN, 1063 base + FSPI_MCR0); 1064 1065 /* 1066 * Disable same device enable bit and configure all slave devices 1067 * independently. 1068 */ 1069 reg = fspi_readl(f, f->iobase + FSPI_MCR2); 1070 reg = reg & ~(FSPI_MCR2_SAMEDEVICEEN); 1071 fspi_writel(f, reg, base + FSPI_MCR2); 1072 1073 /* AHB configuration for access buffer 0~7. */ 1074 for (i = 0; i < 7; i++) 1075 fspi_writel(f, 0, base + FSPI_AHBRX_BUF0CR0 + 4 * i); 1076 1077 /* 1078 * Set ADATSZ with the maximum AHB buffer size to improve the read 1079 * performance. 1080 */ 1081 fspi_writel(f, (f->devtype_data->ahb_buf_size / 8 | 1082 FSPI_AHBRXBUF0CR7_PREF), base + FSPI_AHBRX_BUF7CR0); 1083 1084 /* prefetch and no start address alignment limitation */ 1085 fspi_writel(f, FSPI_AHBCR_PREF_EN | FSPI_AHBCR_RDADDROPT, 1086 base + FSPI_AHBCR); 1087 1088 /* AHB Read - Set lut sequence ID for all CS. */ 1089 fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA1CR2); 1090 fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA2CR2); 1091 fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB1CR2); 1092 fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB2CR2); 1093 1094 f->selected = -1; 1095 1096 /* enable the interrupt */ 1097 fspi_writel(f, FSPI_INTEN_IPCMDDONE, base + FSPI_INTEN); 1098 1099 return 0; 1100 } 1101 1102 static const char *nxp_fspi_get_name(struct spi_mem *mem) 1103 { 1104 struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master); 1105 struct device *dev = &mem->spi->dev; 1106 const char *name; 1107 1108 // Set custom name derived from the platform_device of the controller. 1109 if (of_get_available_child_count(f->dev->of_node) == 1) 1110 return dev_name(f->dev); 1111 1112 name = devm_kasprintf(dev, GFP_KERNEL, 1113 "%s-%d", dev_name(f->dev), 1114 spi_get_chipselect(mem->spi, 0)); 1115 1116 if (!name) { 1117 dev_err(dev, "failed to get memory for custom flash name\n"); 1118 return ERR_PTR(-ENOMEM); 1119 } 1120 1121 return name; 1122 } 1123 1124 static const struct spi_controller_mem_ops nxp_fspi_mem_ops = { 1125 .adjust_op_size = nxp_fspi_adjust_op_size, 1126 .supports_op = nxp_fspi_supports_op, 1127 .exec_op = nxp_fspi_exec_op, 1128 .get_name = nxp_fspi_get_name, 1129 }; 1130 1131 static int nxp_fspi_probe(struct platform_device *pdev) 1132 { 1133 struct spi_controller *ctlr; 1134 struct device *dev = &pdev->dev; 1135 struct device_node *np = dev->of_node; 1136 struct resource *res; 1137 struct nxp_fspi *f; 1138 int ret; 1139 u32 reg; 1140 1141 ctlr = spi_alloc_master(&pdev->dev, sizeof(*f)); 1142 if (!ctlr) 1143 return -ENOMEM; 1144 1145 ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL | 1146 SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL; 1147 1148 f = spi_controller_get_devdata(ctlr); 1149 f->dev = dev; 1150 f->devtype_data = (struct nxp_fspi_devtype_data *)device_get_match_data(dev); 1151 if (!f->devtype_data) { 1152 ret = -ENODEV; 1153 goto err_put_ctrl; 1154 } 1155 1156 platform_set_drvdata(pdev, f); 1157 1158 /* find the resources - configuration register address space */ 1159 if (is_acpi_node(dev_fwnode(f->dev))) 1160 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1161 else 1162 res = platform_get_resource_byname(pdev, 1163 IORESOURCE_MEM, "fspi_base"); 1164 1165 f->iobase = devm_ioremap_resource(dev, res); 1166 if (IS_ERR(f->iobase)) { 1167 ret = PTR_ERR(f->iobase); 1168 goto err_put_ctrl; 1169 } 1170 1171 /* find the resources - controller memory mapped space */ 1172 if (is_acpi_node(dev_fwnode(f->dev))) 1173 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1174 else 1175 res = platform_get_resource_byname(pdev, 1176 IORESOURCE_MEM, "fspi_mmap"); 1177 1178 if (!res) { 1179 ret = -ENODEV; 1180 goto err_put_ctrl; 1181 } 1182 1183 /* assign memory mapped starting address and mapped size. */ 1184 f->memmap_phy = res->start; 1185 f->memmap_phy_size = resource_size(res); 1186 1187 /* find the clocks */ 1188 if (dev_of_node(&pdev->dev)) { 1189 f->clk_en = devm_clk_get(dev, "fspi_en"); 1190 if (IS_ERR(f->clk_en)) { 1191 ret = PTR_ERR(f->clk_en); 1192 goto err_put_ctrl; 1193 } 1194 1195 f->clk = devm_clk_get(dev, "fspi"); 1196 if (IS_ERR(f->clk)) { 1197 ret = PTR_ERR(f->clk); 1198 goto err_put_ctrl; 1199 } 1200 1201 ret = nxp_fspi_clk_prep_enable(f); 1202 if (ret) { 1203 dev_err(dev, "can not enable the clock\n"); 1204 goto err_put_ctrl; 1205 } 1206 } 1207 1208 /* Clear potential interrupts */ 1209 reg = fspi_readl(f, f->iobase + FSPI_INTR); 1210 if (reg) 1211 fspi_writel(f, reg, f->iobase + FSPI_INTR); 1212 1213 /* find the irq */ 1214 ret = platform_get_irq(pdev, 0); 1215 if (ret < 0) 1216 goto err_disable_clk; 1217 1218 ret = devm_request_irq(dev, ret, 1219 nxp_fspi_irq_handler, 0, pdev->name, f); 1220 if (ret) { 1221 dev_err(dev, "failed to request irq: %d\n", ret); 1222 goto err_disable_clk; 1223 } 1224 1225 mutex_init(&f->lock); 1226 1227 ctlr->bus_num = -1; 1228 ctlr->num_chipselect = NXP_FSPI_MAX_CHIPSELECT; 1229 ctlr->mem_ops = &nxp_fspi_mem_ops; 1230 1231 nxp_fspi_default_setup(f); 1232 1233 ctlr->dev.of_node = np; 1234 1235 ret = devm_spi_register_controller(&pdev->dev, ctlr); 1236 if (ret) 1237 goto err_destroy_mutex; 1238 1239 return 0; 1240 1241 err_destroy_mutex: 1242 mutex_destroy(&f->lock); 1243 1244 err_disable_clk: 1245 nxp_fspi_clk_disable_unprep(f); 1246 1247 err_put_ctrl: 1248 spi_controller_put(ctlr); 1249 1250 dev_err(dev, "NXP FSPI probe failed\n"); 1251 return ret; 1252 } 1253 1254 static void nxp_fspi_remove(struct platform_device *pdev) 1255 { 1256 struct nxp_fspi *f = platform_get_drvdata(pdev); 1257 1258 /* disable the hardware */ 1259 fspi_writel(f, FSPI_MCR0_MDIS, f->iobase + FSPI_MCR0); 1260 1261 nxp_fspi_clk_disable_unprep(f); 1262 1263 mutex_destroy(&f->lock); 1264 1265 if (f->ahb_addr) 1266 iounmap(f->ahb_addr); 1267 } 1268 1269 static int nxp_fspi_suspend(struct device *dev) 1270 { 1271 return 0; 1272 } 1273 1274 static int nxp_fspi_resume(struct device *dev) 1275 { 1276 struct nxp_fspi *f = dev_get_drvdata(dev); 1277 1278 nxp_fspi_default_setup(f); 1279 1280 return 0; 1281 } 1282 1283 static const struct of_device_id nxp_fspi_dt_ids[] = { 1284 { .compatible = "nxp,lx2160a-fspi", .data = (void *)&lx2160a_data, }, 1285 { .compatible = "nxp,imx8mm-fspi", .data = (void *)&imx8mm_data, }, 1286 { .compatible = "nxp,imx8mp-fspi", .data = (void *)&imx8mm_data, }, 1287 { .compatible = "nxp,imx8qxp-fspi", .data = (void *)&imx8qxp_data, }, 1288 { .compatible = "nxp,imx8dxl-fspi", .data = (void *)&imx8dxl_data, }, 1289 { /* sentinel */ } 1290 }; 1291 MODULE_DEVICE_TABLE(of, nxp_fspi_dt_ids); 1292 1293 #ifdef CONFIG_ACPI 1294 static const struct acpi_device_id nxp_fspi_acpi_ids[] = { 1295 { "NXP0009", .driver_data = (kernel_ulong_t)&lx2160a_data, }, 1296 {} 1297 }; 1298 MODULE_DEVICE_TABLE(acpi, nxp_fspi_acpi_ids); 1299 #endif 1300 1301 static const struct dev_pm_ops nxp_fspi_pm_ops = { 1302 .suspend = nxp_fspi_suspend, 1303 .resume = nxp_fspi_resume, 1304 }; 1305 1306 static struct platform_driver nxp_fspi_driver = { 1307 .driver = { 1308 .name = "nxp-fspi", 1309 .of_match_table = nxp_fspi_dt_ids, 1310 .acpi_match_table = ACPI_PTR(nxp_fspi_acpi_ids), 1311 .pm = &nxp_fspi_pm_ops, 1312 }, 1313 .probe = nxp_fspi_probe, 1314 .remove_new = nxp_fspi_remove, 1315 }; 1316 module_platform_driver(nxp_fspi_driver); 1317 1318 MODULE_DESCRIPTION("NXP FSPI Controller Driver"); 1319 MODULE_AUTHOR("NXP Semiconductor"); 1320 MODULE_AUTHOR("Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>"); 1321 MODULE_AUTHOR("Boris Brezillon <bbrezillon@kernel.org>"); 1322 MODULE_AUTHOR("Frieder Schrempf <frieder.schrempf@kontron.de>"); 1323 MODULE_LICENSE("GPL v2"); 1324