1a5356aefSYogesh Narayan Gaur // SPDX-License-Identifier: GPL-2.0+ 2a5356aefSYogesh Narayan Gaur 3a5356aefSYogesh Narayan Gaur /* 4a5356aefSYogesh Narayan Gaur * NXP FlexSPI(FSPI) controller driver. 5a5356aefSYogesh Narayan Gaur * 655ab8487Skuldip dwivedi * Copyright 2019-2020 NXP 755ab8487Skuldip dwivedi * Copyright 2020 Puresoftware Ltd. 8a5356aefSYogesh Narayan Gaur * 9a5356aefSYogesh Narayan Gaur * FlexSPI is a flexsible SPI host controller which supports two SPI 10a5356aefSYogesh Narayan Gaur * channels and up to 4 external devices. Each channel supports 11a5356aefSYogesh Narayan Gaur * Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional 12a5356aefSYogesh Narayan Gaur * data lines). 13a5356aefSYogesh Narayan Gaur * 14a5356aefSYogesh Narayan Gaur * FlexSPI controller is driven by the LUT(Look-up Table) registers 15a5356aefSYogesh Narayan Gaur * LUT registers are a look-up-table for sequences of instructions. 16a5356aefSYogesh Narayan Gaur * A valid sequence consists of four LUT registers. 17a5356aefSYogesh Narayan Gaur * Maximum 32 LUT sequences can be programmed simultaneously. 18a5356aefSYogesh Narayan Gaur * 19a5356aefSYogesh Narayan Gaur * LUTs are being created at run-time based on the commands passed 20a5356aefSYogesh Narayan Gaur * from the spi-mem framework, thus using single LUT index. 21a5356aefSYogesh Narayan Gaur * 22a5356aefSYogesh Narayan Gaur * Software triggered Flash read/write access by IP Bus. 23a5356aefSYogesh Narayan Gaur * 24a5356aefSYogesh Narayan Gaur * Memory mapped read access by AHB Bus. 25a5356aefSYogesh Narayan Gaur * 26a5356aefSYogesh Narayan Gaur * Based on SPI MEM interface and spi-fsl-qspi.c driver. 27a5356aefSYogesh Narayan Gaur * 28a5356aefSYogesh Narayan Gaur * Author: 29a5356aefSYogesh Narayan Gaur * Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com> 30ce6f0697SYogesh Narayan Gaur * Boris Brezillon <bbrezillon@kernel.org> 31a5356aefSYogesh Narayan Gaur * Frieder Schrempf <frieder.schrempf@kontron.de> 32a5356aefSYogesh Narayan Gaur */ 33a5356aefSYogesh Narayan Gaur 3455ab8487Skuldip dwivedi #include <linux/acpi.h> 35a5356aefSYogesh Narayan Gaur #include <linux/bitops.h> 36a5356aefSYogesh Narayan Gaur #include <linux/clk.h> 37a5356aefSYogesh Narayan Gaur #include <linux/completion.h> 38a5356aefSYogesh Narayan Gaur #include <linux/delay.h> 39a5356aefSYogesh Narayan Gaur #include <linux/err.h> 40a5356aefSYogesh Narayan Gaur #include <linux/errno.h> 41a5356aefSYogesh Narayan Gaur #include <linux/interrupt.h> 42a5356aefSYogesh Narayan Gaur #include <linux/io.h> 43a5356aefSYogesh Narayan Gaur #include <linux/iopoll.h> 44a5356aefSYogesh Narayan Gaur #include <linux/jiffies.h> 45a5356aefSYogesh Narayan Gaur #include <linux/kernel.h> 46a5356aefSYogesh Narayan Gaur #include <linux/module.h> 47a5356aefSYogesh Narayan Gaur #include <linux/mutex.h> 48a5356aefSYogesh Narayan Gaur #include <linux/of.h> 49a5356aefSYogesh Narayan Gaur #include <linux/of_device.h> 50a5356aefSYogesh Narayan Gaur #include <linux/platform_device.h> 51a5356aefSYogesh Narayan Gaur #include <linux/pm_qos.h> 5282ce7d0eSKuldeep Singh #include <linux/regmap.h> 53a5356aefSYogesh Narayan Gaur #include <linux/sizes.h> 5482ce7d0eSKuldeep Singh #include <linux/sys_soc.h> 55a5356aefSYogesh Narayan Gaur 5682ce7d0eSKuldeep Singh #include <linux/mfd/syscon.h> 57a5356aefSYogesh Narayan Gaur #include <linux/spi/spi.h> 58a5356aefSYogesh Narayan Gaur #include <linux/spi/spi-mem.h> 59a5356aefSYogesh Narayan Gaur 60a5356aefSYogesh Narayan Gaur /* 61a5356aefSYogesh Narayan Gaur * The driver only uses one single LUT entry, that is updated on 62a5356aefSYogesh Narayan Gaur * each call of exec_op(). Index 0 is preset at boot with a basic 63a5356aefSYogesh Narayan Gaur * read operation, so let's use the last entry (31). 64a5356aefSYogesh Narayan Gaur */ 65a5356aefSYogesh Narayan Gaur #define SEQID_LUT 31 66a5356aefSYogesh Narayan Gaur 67a5356aefSYogesh Narayan Gaur /* Registers used by the driver */ 68a5356aefSYogesh Narayan Gaur #define FSPI_MCR0 0x00 69a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_AHB_TIMEOUT(x) ((x) << 24) 70a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_IP_TIMEOUT(x) ((x) << 16) 71a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_LEARN_EN BIT(15) 72a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_SCRFRUN_EN BIT(14) 73a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_OCTCOMB_EN BIT(13) 74a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_DOZE_EN BIT(12) 75a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_HSEN BIT(11) 76a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_SERCLKDIV BIT(8) 77a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_ATDF_EN BIT(7) 78a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_ARDF_EN BIT(6) 79a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_RXCLKSRC(x) ((x) << 4) 80a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_END_CFG(x) ((x) << 2) 81a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_MDIS BIT(1) 82a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_SWRST BIT(0) 83a5356aefSYogesh Narayan Gaur 84a5356aefSYogesh Narayan Gaur #define FSPI_MCR1 0x04 85a5356aefSYogesh Narayan Gaur #define FSPI_MCR1_SEQ_TIMEOUT(x) ((x) << 16) 86a5356aefSYogesh Narayan Gaur #define FSPI_MCR1_AHB_TIMEOUT(x) (x) 87a5356aefSYogesh Narayan Gaur 88a5356aefSYogesh Narayan Gaur #define FSPI_MCR2 0x08 89a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_IDLE_WAIT(x) ((x) << 24) 90a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_SAMEDEVICEEN BIT(15) 91a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_CLRLRPHS BIT(14) 92a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_ABRDATSZ BIT(8) 93a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_ABRLEARN BIT(7) 94a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_ABR_READ BIT(6) 95a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_ABRWRITE BIT(5) 96a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_ABRDUMMY BIT(4) 97a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_ABR_MODE BIT(3) 98a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_ABRCADDR BIT(2) 99a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_ABRRADDR BIT(1) 100a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_ABR_CMD BIT(0) 101a5356aefSYogesh Narayan Gaur 102a5356aefSYogesh Narayan Gaur #define FSPI_AHBCR 0x0c 103a5356aefSYogesh Narayan Gaur #define FSPI_AHBCR_RDADDROPT BIT(6) 104a5356aefSYogesh Narayan Gaur #define FSPI_AHBCR_PREF_EN BIT(5) 105a5356aefSYogesh Narayan Gaur #define FSPI_AHBCR_BUFF_EN BIT(4) 106a5356aefSYogesh Narayan Gaur #define FSPI_AHBCR_CACH_EN BIT(3) 107a5356aefSYogesh Narayan Gaur #define FSPI_AHBCR_CLRTXBUF BIT(2) 108a5356aefSYogesh Narayan Gaur #define FSPI_AHBCR_CLRRXBUF BIT(1) 109a5356aefSYogesh Narayan Gaur #define FSPI_AHBCR_PAR_EN BIT(0) 110a5356aefSYogesh Narayan Gaur 111a5356aefSYogesh Narayan Gaur #define FSPI_INTEN 0x10 112a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_SCLKSBWR BIT(9) 113a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_SCLKSBRD BIT(8) 114a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_DATALRNFL BIT(7) 115a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_IPTXWE BIT(6) 116a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_IPRXWA BIT(5) 117a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_AHBCMDERR BIT(4) 118a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_IPCMDERR BIT(3) 119a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_AHBCMDGE BIT(2) 120a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_IPCMDGE BIT(1) 121a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_IPCMDDONE BIT(0) 122a5356aefSYogesh Narayan Gaur 123a5356aefSYogesh Narayan Gaur #define FSPI_INTR 0x14 124a5356aefSYogesh Narayan Gaur #define FSPI_INTR_SCLKSBWR BIT(9) 125a5356aefSYogesh Narayan Gaur #define FSPI_INTR_SCLKSBRD BIT(8) 126a5356aefSYogesh Narayan Gaur #define FSPI_INTR_DATALRNFL BIT(7) 127a5356aefSYogesh Narayan Gaur #define FSPI_INTR_IPTXWE BIT(6) 128a5356aefSYogesh Narayan Gaur #define FSPI_INTR_IPRXWA BIT(5) 129a5356aefSYogesh Narayan Gaur #define FSPI_INTR_AHBCMDERR BIT(4) 130a5356aefSYogesh Narayan Gaur #define FSPI_INTR_IPCMDERR BIT(3) 131a5356aefSYogesh Narayan Gaur #define FSPI_INTR_AHBCMDGE BIT(2) 132a5356aefSYogesh Narayan Gaur #define FSPI_INTR_IPCMDGE BIT(1) 133a5356aefSYogesh Narayan Gaur #define FSPI_INTR_IPCMDDONE BIT(0) 134a5356aefSYogesh Narayan Gaur 135a5356aefSYogesh Narayan Gaur #define FSPI_LUTKEY 0x18 136a5356aefSYogesh Narayan Gaur #define FSPI_LUTKEY_VALUE 0x5AF05AF0 137a5356aefSYogesh Narayan Gaur 138a5356aefSYogesh Narayan Gaur #define FSPI_LCKCR 0x1C 139a5356aefSYogesh Narayan Gaur 140a5356aefSYogesh Narayan Gaur #define FSPI_LCKER_LOCK 0x1 141a5356aefSYogesh Narayan Gaur #define FSPI_LCKER_UNLOCK 0x2 142a5356aefSYogesh Narayan Gaur 143a5356aefSYogesh Narayan Gaur #define FSPI_BUFXCR_INVALID_MSTRID 0xE 144a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF0CR0 0x20 145a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF1CR0 0x24 146a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF2CR0 0x28 147a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF3CR0 0x2C 148a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF4CR0 0x30 149a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF5CR0 0x34 150a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF6CR0 0x38 151a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF7CR0 0x3C 152a5356aefSYogesh Narayan Gaur #define FSPI_AHBRXBUF0CR7_PREF BIT(31) 153a5356aefSYogesh Narayan Gaur 154a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF0CR1 0x40 155a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF1CR1 0x44 156a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF2CR1 0x48 157a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF3CR1 0x4C 158a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF4CR1 0x50 159a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF5CR1 0x54 160a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF6CR1 0x58 161a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF7CR1 0x5C 162a5356aefSYogesh Narayan Gaur 163a5356aefSYogesh Narayan Gaur #define FSPI_FLSHA1CR0 0x60 164a5356aefSYogesh Narayan Gaur #define FSPI_FLSHA2CR0 0x64 165a5356aefSYogesh Narayan Gaur #define FSPI_FLSHB1CR0 0x68 166a5356aefSYogesh Narayan Gaur #define FSPI_FLSHB2CR0 0x6C 167a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR0_SZ_KB 10 168a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR0_SZ(x) ((x) >> FSPI_FLSHXCR0_SZ_KB) 169a5356aefSYogesh Narayan Gaur 170a5356aefSYogesh Narayan Gaur #define FSPI_FLSHA1CR1 0x70 171a5356aefSYogesh Narayan Gaur #define FSPI_FLSHA2CR1 0x74 172a5356aefSYogesh Narayan Gaur #define FSPI_FLSHB1CR1 0x78 173a5356aefSYogesh Narayan Gaur #define FSPI_FLSHB2CR1 0x7C 174a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR1_CSINTR(x) ((x) << 16) 175a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR1_CAS(x) ((x) << 11) 176a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR1_WA BIT(10) 177a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR1_TCSH(x) ((x) << 5) 178a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR1_TCSS(x) (x) 179a5356aefSYogesh Narayan Gaur 180a5356aefSYogesh Narayan Gaur #define FSPI_FLSHA1CR2 0x80 181a5356aefSYogesh Narayan Gaur #define FSPI_FLSHA2CR2 0x84 182a5356aefSYogesh Narayan Gaur #define FSPI_FLSHB1CR2 0x88 183a5356aefSYogesh Narayan Gaur #define FSPI_FLSHB2CR2 0x8C 184a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR2_CLRINSP BIT(24) 185a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR2_AWRWAIT BIT(16) 186a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR2_AWRSEQN_SHIFT 13 187a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR2_AWRSEQI_SHIFT 8 188a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR2_ARDSEQN_SHIFT 5 189a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR2_ARDSEQI_SHIFT 0 190a5356aefSYogesh Narayan Gaur 191a5356aefSYogesh Narayan Gaur #define FSPI_IPCR0 0xA0 192a5356aefSYogesh Narayan Gaur 193a5356aefSYogesh Narayan Gaur #define FSPI_IPCR1 0xA4 194a5356aefSYogesh Narayan Gaur #define FSPI_IPCR1_IPAREN BIT(31) 195a5356aefSYogesh Narayan Gaur #define FSPI_IPCR1_SEQNUM_SHIFT 24 196a5356aefSYogesh Narayan Gaur #define FSPI_IPCR1_SEQID_SHIFT 16 197a5356aefSYogesh Narayan Gaur #define FSPI_IPCR1_IDATSZ(x) (x) 198a5356aefSYogesh Narayan Gaur 199a5356aefSYogesh Narayan Gaur #define FSPI_IPCMD 0xB0 200a5356aefSYogesh Narayan Gaur #define FSPI_IPCMD_TRG BIT(0) 201a5356aefSYogesh Narayan Gaur 202a5356aefSYogesh Narayan Gaur #define FSPI_DLPR 0xB4 203a5356aefSYogesh Narayan Gaur 204a5356aefSYogesh Narayan Gaur #define FSPI_IPRXFCR 0xB8 205a5356aefSYogesh Narayan Gaur #define FSPI_IPRXFCR_CLR BIT(0) 206a5356aefSYogesh Narayan Gaur #define FSPI_IPRXFCR_DMA_EN BIT(1) 207a5356aefSYogesh Narayan Gaur #define FSPI_IPRXFCR_WMRK(x) ((x) << 2) 208a5356aefSYogesh Narayan Gaur 209a5356aefSYogesh Narayan Gaur #define FSPI_IPTXFCR 0xBC 210a5356aefSYogesh Narayan Gaur #define FSPI_IPTXFCR_CLR BIT(0) 211a5356aefSYogesh Narayan Gaur #define FSPI_IPTXFCR_DMA_EN BIT(1) 212a5356aefSYogesh Narayan Gaur #define FSPI_IPTXFCR_WMRK(x) ((x) << 2) 213a5356aefSYogesh Narayan Gaur 214a5356aefSYogesh Narayan Gaur #define FSPI_DLLACR 0xC0 215a5356aefSYogesh Narayan Gaur #define FSPI_DLLACR_OVRDEN BIT(8) 216a5356aefSYogesh Narayan Gaur 217a5356aefSYogesh Narayan Gaur #define FSPI_DLLBCR 0xC4 218a5356aefSYogesh Narayan Gaur #define FSPI_DLLBCR_OVRDEN BIT(8) 219a5356aefSYogesh Narayan Gaur 220a5356aefSYogesh Narayan Gaur #define FSPI_STS0 0xE0 221a5356aefSYogesh Narayan Gaur #define FSPI_STS0_DLPHB(x) ((x) << 8) 222a5356aefSYogesh Narayan Gaur #define FSPI_STS0_DLPHA(x) ((x) << 4) 223a5356aefSYogesh Narayan Gaur #define FSPI_STS0_CMD_SRC(x) ((x) << 2) 224a5356aefSYogesh Narayan Gaur #define FSPI_STS0_ARB_IDLE BIT(1) 225a5356aefSYogesh Narayan Gaur #define FSPI_STS0_SEQ_IDLE BIT(0) 226a5356aefSYogesh Narayan Gaur 227a5356aefSYogesh Narayan Gaur #define FSPI_STS1 0xE4 228a5356aefSYogesh Narayan Gaur #define FSPI_STS1_IP_ERRCD(x) ((x) << 24) 229a5356aefSYogesh Narayan Gaur #define FSPI_STS1_IP_ERRID(x) ((x) << 16) 230a5356aefSYogesh Narayan Gaur #define FSPI_STS1_AHB_ERRCD(x) ((x) << 8) 231a5356aefSYogesh Narayan Gaur #define FSPI_STS1_AHB_ERRID(x) (x) 232a5356aefSYogesh Narayan Gaur 233a5356aefSYogesh Narayan Gaur #define FSPI_AHBSPNST 0xEC 234a5356aefSYogesh Narayan Gaur #define FSPI_AHBSPNST_DATLFT(x) ((x) << 16) 235a5356aefSYogesh Narayan Gaur #define FSPI_AHBSPNST_BUFID(x) ((x) << 1) 236a5356aefSYogesh Narayan Gaur #define FSPI_AHBSPNST_ACTIVE BIT(0) 237a5356aefSYogesh Narayan Gaur 238a5356aefSYogesh Narayan Gaur #define FSPI_IPRXFSTS 0xF0 239a5356aefSYogesh Narayan Gaur #define FSPI_IPRXFSTS_RDCNTR(x) ((x) << 16) 240a5356aefSYogesh Narayan Gaur #define FSPI_IPRXFSTS_FILL(x) (x) 241a5356aefSYogesh Narayan Gaur 242a5356aefSYogesh Narayan Gaur #define FSPI_IPTXFSTS 0xF4 243a5356aefSYogesh Narayan Gaur #define FSPI_IPTXFSTS_WRCNTR(x) ((x) << 16) 244a5356aefSYogesh Narayan Gaur #define FSPI_IPTXFSTS_FILL(x) (x) 245a5356aefSYogesh Narayan Gaur 246a5356aefSYogesh Narayan Gaur #define FSPI_RFDR 0x100 247a5356aefSYogesh Narayan Gaur #define FSPI_TFDR 0x180 248a5356aefSYogesh Narayan Gaur 249a5356aefSYogesh Narayan Gaur #define FSPI_LUT_BASE 0x200 250a5356aefSYogesh Narayan Gaur #define FSPI_LUT_OFFSET (SEQID_LUT * 4 * 4) 251a5356aefSYogesh Narayan Gaur #define FSPI_LUT_REG(idx) \ 252a5356aefSYogesh Narayan Gaur (FSPI_LUT_BASE + FSPI_LUT_OFFSET + (idx) * 4) 253a5356aefSYogesh Narayan Gaur 254a5356aefSYogesh Narayan Gaur /* register map end */ 255a5356aefSYogesh Narayan Gaur 256a5356aefSYogesh Narayan Gaur /* Instruction set for the LUT register. */ 257a5356aefSYogesh Narayan Gaur #define LUT_STOP 0x00 258a5356aefSYogesh Narayan Gaur #define LUT_CMD 0x01 259a5356aefSYogesh Narayan Gaur #define LUT_ADDR 0x02 260a5356aefSYogesh Narayan Gaur #define LUT_CADDR_SDR 0x03 261a5356aefSYogesh Narayan Gaur #define LUT_MODE 0x04 262a5356aefSYogesh Narayan Gaur #define LUT_MODE2 0x05 263a5356aefSYogesh Narayan Gaur #define LUT_MODE4 0x06 264a5356aefSYogesh Narayan Gaur #define LUT_MODE8 0x07 265a5356aefSYogesh Narayan Gaur #define LUT_NXP_WRITE 0x08 266a5356aefSYogesh Narayan Gaur #define LUT_NXP_READ 0x09 267a5356aefSYogesh Narayan Gaur #define LUT_LEARN_SDR 0x0A 268a5356aefSYogesh Narayan Gaur #define LUT_DATSZ_SDR 0x0B 269a5356aefSYogesh Narayan Gaur #define LUT_DUMMY 0x0C 270a5356aefSYogesh Narayan Gaur #define LUT_DUMMY_RWDS_SDR 0x0D 271a5356aefSYogesh Narayan Gaur #define LUT_JMP_ON_CS 0x1F 272a5356aefSYogesh Narayan Gaur #define LUT_CMD_DDR 0x21 273a5356aefSYogesh Narayan Gaur #define LUT_ADDR_DDR 0x22 274a5356aefSYogesh Narayan Gaur #define LUT_CADDR_DDR 0x23 275a5356aefSYogesh Narayan Gaur #define LUT_MODE_DDR 0x24 276a5356aefSYogesh Narayan Gaur #define LUT_MODE2_DDR 0x25 277a5356aefSYogesh Narayan Gaur #define LUT_MODE4_DDR 0x26 278a5356aefSYogesh Narayan Gaur #define LUT_MODE8_DDR 0x27 279a5356aefSYogesh Narayan Gaur #define LUT_WRITE_DDR 0x28 280a5356aefSYogesh Narayan Gaur #define LUT_READ_DDR 0x29 281a5356aefSYogesh Narayan Gaur #define LUT_LEARN_DDR 0x2A 282a5356aefSYogesh Narayan Gaur #define LUT_DATSZ_DDR 0x2B 283a5356aefSYogesh Narayan Gaur #define LUT_DUMMY_DDR 0x2C 284a5356aefSYogesh Narayan Gaur #define LUT_DUMMY_RWDS_DDR 0x2D 285a5356aefSYogesh Narayan Gaur 286a5356aefSYogesh Narayan Gaur /* 287a5356aefSYogesh Narayan Gaur * Calculate number of required PAD bits for LUT register. 288a5356aefSYogesh Narayan Gaur * 289a5356aefSYogesh Narayan Gaur * The pad stands for the number of IO lines [0:7]. 290a5356aefSYogesh Narayan Gaur * For example, the octal read needs eight IO lines, 291a5356aefSYogesh Narayan Gaur * so you should use LUT_PAD(8). This macro 292a5356aefSYogesh Narayan Gaur * returns 3 i.e. use eight (2^3) IP lines for read. 293a5356aefSYogesh Narayan Gaur */ 294a5356aefSYogesh Narayan Gaur #define LUT_PAD(x) (fls(x) - 1) 295a5356aefSYogesh Narayan Gaur 296a5356aefSYogesh Narayan Gaur /* 297a5356aefSYogesh Narayan Gaur * Macro for constructing the LUT entries with the following 298a5356aefSYogesh Narayan Gaur * register layout: 299a5356aefSYogesh Narayan Gaur * 300a5356aefSYogesh Narayan Gaur * --------------------------------------------------- 301a5356aefSYogesh Narayan Gaur * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 | 302a5356aefSYogesh Narayan Gaur * --------------------------------------------------- 303a5356aefSYogesh Narayan Gaur */ 304a5356aefSYogesh Narayan Gaur #define PAD_SHIFT 8 305a5356aefSYogesh Narayan Gaur #define INSTR_SHIFT 10 306a5356aefSYogesh Narayan Gaur #define OPRND_SHIFT 16 307a5356aefSYogesh Narayan Gaur 308a5356aefSYogesh Narayan Gaur /* Macros for constructing the LUT register. */ 309a5356aefSYogesh Narayan Gaur #define LUT_DEF(idx, ins, pad, opr) \ 310a5356aefSYogesh Narayan Gaur ((((ins) << INSTR_SHIFT) | ((pad) << PAD_SHIFT) | \ 311a5356aefSYogesh Narayan Gaur (opr)) << (((idx) % 2) * OPRND_SHIFT)) 312a5356aefSYogesh Narayan Gaur 313a5356aefSYogesh Narayan Gaur #define POLL_TOUT 5000 314a5356aefSYogesh Narayan Gaur #define NXP_FSPI_MAX_CHIPSELECT 4 315d166a735SHan Xu #define NXP_FSPI_MIN_IOMAP SZ_4M 316a5356aefSYogesh Narayan Gaur 31782ce7d0eSKuldeep Singh #define DCFG_RCWSR1 0x100 31882ce7d0eSKuldeep Singh 31931e92cbfSKuldeep Singh /* Access flash memory using IP bus only */ 32031e92cbfSKuldeep Singh #define FSPI_QUIRK_USE_IP_ONLY BIT(0) 32131e92cbfSKuldeep Singh 322a5356aefSYogesh Narayan Gaur struct nxp_fspi_devtype_data { 323a5356aefSYogesh Narayan Gaur unsigned int rxfifo; 324a5356aefSYogesh Narayan Gaur unsigned int txfifo; 325a5356aefSYogesh Narayan Gaur unsigned int ahb_buf_size; 326a5356aefSYogesh Narayan Gaur unsigned int quirks; 327a5356aefSYogesh Narayan Gaur bool little_endian; 328a5356aefSYogesh Narayan Gaur }; 329a5356aefSYogesh Narayan Gaur 33082ce7d0eSKuldeep Singh static struct nxp_fspi_devtype_data lx2160a_data = { 331a5356aefSYogesh Narayan Gaur .rxfifo = SZ_512, /* (64 * 64 bits) */ 332a5356aefSYogesh Narayan Gaur .txfifo = SZ_1K, /* (128 * 64 bits) */ 333a5356aefSYogesh Narayan Gaur .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ 334a5356aefSYogesh Narayan Gaur .quirks = 0, 335a5356aefSYogesh Narayan Gaur .little_endian = true, /* little-endian */ 336a5356aefSYogesh Narayan Gaur }; 337a5356aefSYogesh Narayan Gaur 33882ce7d0eSKuldeep Singh static struct nxp_fspi_devtype_data imx8mm_data = { 339941be8a7SHan Xu .rxfifo = SZ_512, /* (64 * 64 bits) */ 340941be8a7SHan Xu .txfifo = SZ_1K, /* (128 * 64 bits) */ 341941be8a7SHan Xu .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ 342941be8a7SHan Xu .quirks = 0, 343941be8a7SHan Xu .little_endian = true, /* little-endian */ 344941be8a7SHan Xu }; 345941be8a7SHan Xu 34682ce7d0eSKuldeep Singh static struct nxp_fspi_devtype_data imx8qxp_data = { 347941be8a7SHan Xu .rxfifo = SZ_512, /* (64 * 64 bits) */ 348941be8a7SHan Xu .txfifo = SZ_1K, /* (128 * 64 bits) */ 349941be8a7SHan Xu .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ 350941be8a7SHan Xu .quirks = 0, 351941be8a7SHan Xu .little_endian = true, /* little-endian */ 352941be8a7SHan Xu }; 353941be8a7SHan Xu 35482ce7d0eSKuldeep Singh static struct nxp_fspi_devtype_data imx8dxl_data = { 355c791e3c3SHan Xu .rxfifo = SZ_512, /* (64 * 64 bits) */ 356c791e3c3SHan Xu .txfifo = SZ_1K, /* (128 * 64 bits) */ 357c791e3c3SHan Xu .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ 358c791e3c3SHan Xu .quirks = FSPI_QUIRK_USE_IP_ONLY, 359c791e3c3SHan Xu .little_endian = true, /* little-endian */ 360c791e3c3SHan Xu }; 361c791e3c3SHan Xu 362a5356aefSYogesh Narayan Gaur struct nxp_fspi { 363a5356aefSYogesh Narayan Gaur void __iomem *iobase; 364a5356aefSYogesh Narayan Gaur void __iomem *ahb_addr; 365a5356aefSYogesh Narayan Gaur u32 memmap_phy; 366a5356aefSYogesh Narayan Gaur u32 memmap_phy_size; 367d166a735SHan Xu u32 memmap_start; 368d166a735SHan Xu u32 memmap_len; 369a5356aefSYogesh Narayan Gaur struct clk *clk, *clk_en; 370a5356aefSYogesh Narayan Gaur struct device *dev; 371a5356aefSYogesh Narayan Gaur struct completion c; 37282ce7d0eSKuldeep Singh struct nxp_fspi_devtype_data *devtype_data; 373a5356aefSYogesh Narayan Gaur struct mutex lock; 374a5356aefSYogesh Narayan Gaur struct pm_qos_request pm_qos_req; 375a5356aefSYogesh Narayan Gaur int selected; 376a5356aefSYogesh Narayan Gaur }; 377a5356aefSYogesh Narayan Gaur 37831e92cbfSKuldeep Singh static inline int needs_ip_only(struct nxp_fspi *f) 37931e92cbfSKuldeep Singh { 38031e92cbfSKuldeep Singh return f->devtype_data->quirks & FSPI_QUIRK_USE_IP_ONLY; 38131e92cbfSKuldeep Singh } 38231e92cbfSKuldeep Singh 383a5356aefSYogesh Narayan Gaur /* 384a5356aefSYogesh Narayan Gaur * R/W functions for big- or little-endian registers: 385a5356aefSYogesh Narayan Gaur * The FSPI controller's endianness is independent of 386a5356aefSYogesh Narayan Gaur * the CPU core's endianness. So far, although the CPU 387a5356aefSYogesh Narayan Gaur * core is little-endian the FSPI controller can use 388a5356aefSYogesh Narayan Gaur * big-endian or little-endian. 389a5356aefSYogesh Narayan Gaur */ 390a5356aefSYogesh Narayan Gaur static void fspi_writel(struct nxp_fspi *f, u32 val, void __iomem *addr) 391a5356aefSYogesh Narayan Gaur { 392a5356aefSYogesh Narayan Gaur if (f->devtype_data->little_endian) 393a5356aefSYogesh Narayan Gaur iowrite32(val, addr); 394a5356aefSYogesh Narayan Gaur else 395a5356aefSYogesh Narayan Gaur iowrite32be(val, addr); 396a5356aefSYogesh Narayan Gaur } 397a5356aefSYogesh Narayan Gaur 398a5356aefSYogesh Narayan Gaur static u32 fspi_readl(struct nxp_fspi *f, void __iomem *addr) 399a5356aefSYogesh Narayan Gaur { 400a5356aefSYogesh Narayan Gaur if (f->devtype_data->little_endian) 401a5356aefSYogesh Narayan Gaur return ioread32(addr); 402a5356aefSYogesh Narayan Gaur else 403a5356aefSYogesh Narayan Gaur return ioread32be(addr); 404a5356aefSYogesh Narayan Gaur } 405a5356aefSYogesh Narayan Gaur 406a5356aefSYogesh Narayan Gaur static irqreturn_t nxp_fspi_irq_handler(int irq, void *dev_id) 407a5356aefSYogesh Narayan Gaur { 408a5356aefSYogesh Narayan Gaur struct nxp_fspi *f = dev_id; 409a5356aefSYogesh Narayan Gaur u32 reg; 410a5356aefSYogesh Narayan Gaur 411a5356aefSYogesh Narayan Gaur /* clear interrupt */ 412a5356aefSYogesh Narayan Gaur reg = fspi_readl(f, f->iobase + FSPI_INTR); 413a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_INTR_IPCMDDONE, f->iobase + FSPI_INTR); 414a5356aefSYogesh Narayan Gaur 415a5356aefSYogesh Narayan Gaur if (reg & FSPI_INTR_IPCMDDONE) 416a5356aefSYogesh Narayan Gaur complete(&f->c); 417a5356aefSYogesh Narayan Gaur 418a5356aefSYogesh Narayan Gaur return IRQ_HANDLED; 419a5356aefSYogesh Narayan Gaur } 420a5356aefSYogesh Narayan Gaur 421a5356aefSYogesh Narayan Gaur static int nxp_fspi_check_buswidth(struct nxp_fspi *f, u8 width) 422a5356aefSYogesh Narayan Gaur { 423a5356aefSYogesh Narayan Gaur switch (width) { 424a5356aefSYogesh Narayan Gaur case 1: 425a5356aefSYogesh Narayan Gaur case 2: 426a5356aefSYogesh Narayan Gaur case 4: 427a5356aefSYogesh Narayan Gaur case 8: 428a5356aefSYogesh Narayan Gaur return 0; 429a5356aefSYogesh Narayan Gaur } 430a5356aefSYogesh Narayan Gaur 431a5356aefSYogesh Narayan Gaur return -ENOTSUPP; 432a5356aefSYogesh Narayan Gaur } 433a5356aefSYogesh Narayan Gaur 434a5356aefSYogesh Narayan Gaur static bool nxp_fspi_supports_op(struct spi_mem *mem, 435a5356aefSYogesh Narayan Gaur const struct spi_mem_op *op) 436a5356aefSYogesh Narayan Gaur { 437a5356aefSYogesh Narayan Gaur struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master); 438a5356aefSYogesh Narayan Gaur int ret; 439a5356aefSYogesh Narayan Gaur 440a5356aefSYogesh Narayan Gaur ret = nxp_fspi_check_buswidth(f, op->cmd.buswidth); 441a5356aefSYogesh Narayan Gaur 442a5356aefSYogesh Narayan Gaur if (op->addr.nbytes) 443a5356aefSYogesh Narayan Gaur ret |= nxp_fspi_check_buswidth(f, op->addr.buswidth); 444a5356aefSYogesh Narayan Gaur 445a5356aefSYogesh Narayan Gaur if (op->dummy.nbytes) 446a5356aefSYogesh Narayan Gaur ret |= nxp_fspi_check_buswidth(f, op->dummy.buswidth); 447a5356aefSYogesh Narayan Gaur 448a5356aefSYogesh Narayan Gaur if (op->data.nbytes) 449a5356aefSYogesh Narayan Gaur ret |= nxp_fspi_check_buswidth(f, op->data.buswidth); 450a5356aefSYogesh Narayan Gaur 451a5356aefSYogesh Narayan Gaur if (ret) 452a5356aefSYogesh Narayan Gaur return false; 453a5356aefSYogesh Narayan Gaur 454a5356aefSYogesh Narayan Gaur /* 455a5356aefSYogesh Narayan Gaur * The number of address bytes should be equal to or less than 4 bytes. 456a5356aefSYogesh Narayan Gaur */ 457a5356aefSYogesh Narayan Gaur if (op->addr.nbytes > 4) 458a5356aefSYogesh Narayan Gaur return false; 459a5356aefSYogesh Narayan Gaur 460a5356aefSYogesh Narayan Gaur /* 461a5356aefSYogesh Narayan Gaur * If requested address value is greater than controller assigned 462a5356aefSYogesh Narayan Gaur * memory mapped space, return error as it didn't fit in the range 463a5356aefSYogesh Narayan Gaur * of assigned address space. 464a5356aefSYogesh Narayan Gaur */ 465a5356aefSYogesh Narayan Gaur if (op->addr.val >= f->memmap_phy_size) 466a5356aefSYogesh Narayan Gaur return false; 467a5356aefSYogesh Narayan Gaur 468a5356aefSYogesh Narayan Gaur /* Max 64 dummy clock cycles supported */ 469a5356aefSYogesh Narayan Gaur if (op->dummy.buswidth && 470a5356aefSYogesh Narayan Gaur (op->dummy.nbytes * 8 / op->dummy.buswidth > 64)) 471a5356aefSYogesh Narayan Gaur return false; 472a5356aefSYogesh Narayan Gaur 473a5356aefSYogesh Narayan Gaur /* Max data length, check controller limits and alignment */ 474a5356aefSYogesh Narayan Gaur if (op->data.dir == SPI_MEM_DATA_IN && 475a5356aefSYogesh Narayan Gaur (op->data.nbytes > f->devtype_data->ahb_buf_size || 476a5356aefSYogesh Narayan Gaur (op->data.nbytes > f->devtype_data->rxfifo - 4 && 477a5356aefSYogesh Narayan Gaur !IS_ALIGNED(op->data.nbytes, 8)))) 478a5356aefSYogesh Narayan Gaur return false; 479a5356aefSYogesh Narayan Gaur 480a5356aefSYogesh Narayan Gaur if (op->data.dir == SPI_MEM_DATA_OUT && 481a5356aefSYogesh Narayan Gaur op->data.nbytes > f->devtype_data->txfifo) 482a5356aefSYogesh Narayan Gaur return false; 483a5356aefSYogesh Narayan Gaur 484007773e1SMichael Walle return spi_mem_default_supports_op(mem, op); 485a5356aefSYogesh Narayan Gaur } 486a5356aefSYogesh Narayan Gaur 487a5356aefSYogesh Narayan Gaur /* Instead of busy looping invoke readl_poll_timeout functionality. */ 488a5356aefSYogesh Narayan Gaur static int fspi_readl_poll_tout(struct nxp_fspi *f, void __iomem *base, 489a5356aefSYogesh Narayan Gaur u32 mask, u32 delay_us, 490a5356aefSYogesh Narayan Gaur u32 timeout_us, bool c) 491a5356aefSYogesh Narayan Gaur { 492a5356aefSYogesh Narayan Gaur u32 reg; 493a5356aefSYogesh Narayan Gaur 494a5356aefSYogesh Narayan Gaur if (!f->devtype_data->little_endian) 495a5356aefSYogesh Narayan Gaur mask = (u32)cpu_to_be32(mask); 496a5356aefSYogesh Narayan Gaur 497a5356aefSYogesh Narayan Gaur if (c) 498a5356aefSYogesh Narayan Gaur return readl_poll_timeout(base, reg, (reg & mask), 499a5356aefSYogesh Narayan Gaur delay_us, timeout_us); 500a5356aefSYogesh Narayan Gaur else 501a5356aefSYogesh Narayan Gaur return readl_poll_timeout(base, reg, !(reg & mask), 502a5356aefSYogesh Narayan Gaur delay_us, timeout_us); 503a5356aefSYogesh Narayan Gaur } 504a5356aefSYogesh Narayan Gaur 505a5356aefSYogesh Narayan Gaur /* 506a5356aefSYogesh Narayan Gaur * If the slave device content being changed by Write/Erase, need to 507a5356aefSYogesh Narayan Gaur * invalidate the AHB buffer. This can be achieved by doing the reset 508a5356aefSYogesh Narayan Gaur * of controller after setting MCR0[SWRESET] bit. 509a5356aefSYogesh Narayan Gaur */ 510a5356aefSYogesh Narayan Gaur static inline void nxp_fspi_invalid(struct nxp_fspi *f) 511a5356aefSYogesh Narayan Gaur { 512a5356aefSYogesh Narayan Gaur u32 reg; 513a5356aefSYogesh Narayan Gaur int ret; 514a5356aefSYogesh Narayan Gaur 515a5356aefSYogesh Narayan Gaur reg = fspi_readl(f, f->iobase + FSPI_MCR0); 516a5356aefSYogesh Narayan Gaur fspi_writel(f, reg | FSPI_MCR0_SWRST, f->iobase + FSPI_MCR0); 517a5356aefSYogesh Narayan Gaur 518a5356aefSYogesh Narayan Gaur /* w1c register, wait unit clear */ 519a5356aefSYogesh Narayan Gaur ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0, 520a5356aefSYogesh Narayan Gaur FSPI_MCR0_SWRST, 0, POLL_TOUT, false); 521a5356aefSYogesh Narayan Gaur WARN_ON(ret); 522a5356aefSYogesh Narayan Gaur } 523a5356aefSYogesh Narayan Gaur 524a5356aefSYogesh Narayan Gaur static void nxp_fspi_prepare_lut(struct nxp_fspi *f, 525a5356aefSYogesh Narayan Gaur const struct spi_mem_op *op) 526a5356aefSYogesh Narayan Gaur { 527a5356aefSYogesh Narayan Gaur void __iomem *base = f->iobase; 528a5356aefSYogesh Narayan Gaur u32 lutval[4] = {}; 529a5356aefSYogesh Narayan Gaur int lutidx = 1, i; 530a5356aefSYogesh Narayan Gaur 531a5356aefSYogesh Narayan Gaur /* cmd */ 532a5356aefSYogesh Narayan Gaur lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth), 533a5356aefSYogesh Narayan Gaur op->cmd.opcode); 534a5356aefSYogesh Narayan Gaur 535a5356aefSYogesh Narayan Gaur /* addr bytes */ 536a5356aefSYogesh Narayan Gaur if (op->addr.nbytes) { 537a5356aefSYogesh Narayan Gaur lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_ADDR, 538a5356aefSYogesh Narayan Gaur LUT_PAD(op->addr.buswidth), 539a5356aefSYogesh Narayan Gaur op->addr.nbytes * 8); 540a5356aefSYogesh Narayan Gaur lutidx++; 541a5356aefSYogesh Narayan Gaur } 542a5356aefSYogesh Narayan Gaur 543a5356aefSYogesh Narayan Gaur /* dummy bytes, if needed */ 544a5356aefSYogesh Narayan Gaur if (op->dummy.nbytes) { 545a5356aefSYogesh Narayan Gaur lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY, 546a5356aefSYogesh Narayan Gaur /* 547a5356aefSYogesh Narayan Gaur * Due to FlexSPI controller limitation number of PAD for dummy 548a5356aefSYogesh Narayan Gaur * buswidth needs to be programmed as equal to data buswidth. 549a5356aefSYogesh Narayan Gaur */ 550a5356aefSYogesh Narayan Gaur LUT_PAD(op->data.buswidth), 551a5356aefSYogesh Narayan Gaur op->dummy.nbytes * 8 / 552a5356aefSYogesh Narayan Gaur op->dummy.buswidth); 553a5356aefSYogesh Narayan Gaur lutidx++; 554a5356aefSYogesh Narayan Gaur } 555a5356aefSYogesh Narayan Gaur 556a5356aefSYogesh Narayan Gaur /* read/write data bytes */ 557a5356aefSYogesh Narayan Gaur if (op->data.nbytes) { 558a5356aefSYogesh Narayan Gaur lutval[lutidx / 2] |= LUT_DEF(lutidx, 559a5356aefSYogesh Narayan Gaur op->data.dir == SPI_MEM_DATA_IN ? 560a5356aefSYogesh Narayan Gaur LUT_NXP_READ : LUT_NXP_WRITE, 561a5356aefSYogesh Narayan Gaur LUT_PAD(op->data.buswidth), 562a5356aefSYogesh Narayan Gaur 0); 563a5356aefSYogesh Narayan Gaur lutidx++; 564a5356aefSYogesh Narayan Gaur } 565a5356aefSYogesh Narayan Gaur 566a5356aefSYogesh Narayan Gaur /* stop condition. */ 567a5356aefSYogesh Narayan Gaur lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0); 568a5356aefSYogesh Narayan Gaur 569a5356aefSYogesh Narayan Gaur /* unlock LUT */ 570a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY); 571a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_LCKER_UNLOCK, f->iobase + FSPI_LCKCR); 572a5356aefSYogesh Narayan Gaur 573a5356aefSYogesh Narayan Gaur /* fill LUT */ 574a5356aefSYogesh Narayan Gaur for (i = 0; i < ARRAY_SIZE(lutval); i++) 575a5356aefSYogesh Narayan Gaur fspi_writel(f, lutval[i], base + FSPI_LUT_REG(i)); 576a5356aefSYogesh Narayan Gaur 57731e92cbfSKuldeep Singh dev_dbg(f->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x], size: 0x%08x\n", 57831e92cbfSKuldeep Singh op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3], op->data.nbytes); 579a5356aefSYogesh Narayan Gaur 580a5356aefSYogesh Narayan Gaur /* lock LUT */ 581a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY); 582a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_LCKER_LOCK, f->iobase + FSPI_LCKCR); 583a5356aefSYogesh Narayan Gaur } 584a5356aefSYogesh Narayan Gaur 585a5356aefSYogesh Narayan Gaur static int nxp_fspi_clk_prep_enable(struct nxp_fspi *f) 586a5356aefSYogesh Narayan Gaur { 587a5356aefSYogesh Narayan Gaur int ret; 588a5356aefSYogesh Narayan Gaur 58955ab8487Skuldip dwivedi if (is_acpi_node(f->dev->fwnode)) 59055ab8487Skuldip dwivedi return 0; 59155ab8487Skuldip dwivedi 592a5356aefSYogesh Narayan Gaur ret = clk_prepare_enable(f->clk_en); 593a5356aefSYogesh Narayan Gaur if (ret) 594a5356aefSYogesh Narayan Gaur return ret; 595a5356aefSYogesh Narayan Gaur 596a5356aefSYogesh Narayan Gaur ret = clk_prepare_enable(f->clk); 597a5356aefSYogesh Narayan Gaur if (ret) { 598a5356aefSYogesh Narayan Gaur clk_disable_unprepare(f->clk_en); 599a5356aefSYogesh Narayan Gaur return ret; 600a5356aefSYogesh Narayan Gaur } 601a5356aefSYogesh Narayan Gaur 602a5356aefSYogesh Narayan Gaur return 0; 603a5356aefSYogesh Narayan Gaur } 604a5356aefSYogesh Narayan Gaur 60555ab8487Skuldip dwivedi static int nxp_fspi_clk_disable_unprep(struct nxp_fspi *f) 606a5356aefSYogesh Narayan Gaur { 60755ab8487Skuldip dwivedi if (is_acpi_node(f->dev->fwnode)) 60855ab8487Skuldip dwivedi return 0; 60955ab8487Skuldip dwivedi 610a5356aefSYogesh Narayan Gaur clk_disable_unprepare(f->clk); 611a5356aefSYogesh Narayan Gaur clk_disable_unprepare(f->clk_en); 61255ab8487Skuldip dwivedi 61355ab8487Skuldip dwivedi return 0; 614a5356aefSYogesh Narayan Gaur } 615a5356aefSYogesh Narayan Gaur 616a5356aefSYogesh Narayan Gaur /* 617a5356aefSYogesh Narayan Gaur * In FlexSPI controller, flash access is based on value of FSPI_FLSHXXCR0 618a5356aefSYogesh Narayan Gaur * register and start base address of the slave device. 619a5356aefSYogesh Narayan Gaur * 620a5356aefSYogesh Narayan Gaur * (Higher address) 621a5356aefSYogesh Narayan Gaur * -------- <-- FLSHB2CR0 622a5356aefSYogesh Narayan Gaur * | B2 | 623a5356aefSYogesh Narayan Gaur * | | 624a5356aefSYogesh Narayan Gaur * B2 start address --> -------- <-- FLSHB1CR0 625a5356aefSYogesh Narayan Gaur * | B1 | 626a5356aefSYogesh Narayan Gaur * | | 627a5356aefSYogesh Narayan Gaur * B1 start address --> -------- <-- FLSHA2CR0 628a5356aefSYogesh Narayan Gaur * | A2 | 629a5356aefSYogesh Narayan Gaur * | | 630a5356aefSYogesh Narayan Gaur * A2 start address --> -------- <-- FLSHA1CR0 631a5356aefSYogesh Narayan Gaur * | A1 | 632a5356aefSYogesh Narayan Gaur * | | 633a5356aefSYogesh Narayan Gaur * A1 start address --> -------- (Lower address) 634a5356aefSYogesh Narayan Gaur * 635a5356aefSYogesh Narayan Gaur * 636a5356aefSYogesh Narayan Gaur * Start base address defines the starting address range for given CS and 637a5356aefSYogesh Narayan Gaur * FSPI_FLSHXXCR0 defines the size of the slave device connected at given CS. 638a5356aefSYogesh Narayan Gaur * 639a5356aefSYogesh Narayan Gaur * But, different targets are having different combinations of number of CS, 640a5356aefSYogesh Narayan Gaur * some targets only have single CS or two CS covering controller's full 641a5356aefSYogesh Narayan Gaur * memory mapped space area. 642a5356aefSYogesh Narayan Gaur * Thus, implementation is being done as independent of the size and number 643a5356aefSYogesh Narayan Gaur * of the connected slave device. 644a5356aefSYogesh Narayan Gaur * Assign controller memory mapped space size as the size to the connected 645a5356aefSYogesh Narayan Gaur * slave device. 646a5356aefSYogesh Narayan Gaur * Mark FLSHxxCR0 as zero initially and then assign value only to the selected 647a5356aefSYogesh Narayan Gaur * chip-select Flash configuration register. 648a5356aefSYogesh Narayan Gaur * 649a5356aefSYogesh Narayan Gaur * For e.g. to access CS2 (B1), FLSHB1CR0 register would be equal to the 650a5356aefSYogesh Narayan Gaur * memory mapped size of the controller. 651a5356aefSYogesh Narayan Gaur * Value for rest of the CS FLSHxxCR0 register would be zero. 652a5356aefSYogesh Narayan Gaur * 653a5356aefSYogesh Narayan Gaur */ 654a5356aefSYogesh Narayan Gaur static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi) 655a5356aefSYogesh Narayan Gaur { 656a5356aefSYogesh Narayan Gaur unsigned long rate = spi->max_speed_hz; 657a5356aefSYogesh Narayan Gaur int ret; 658a5356aefSYogesh Narayan Gaur uint64_t size_kb; 659a5356aefSYogesh Narayan Gaur 660a5356aefSYogesh Narayan Gaur /* 661a5356aefSYogesh Narayan Gaur * Return, if previously selected slave device is same as current 662a5356aefSYogesh Narayan Gaur * requested slave device. 663a5356aefSYogesh Narayan Gaur */ 664a5356aefSYogesh Narayan Gaur if (f->selected == spi->chip_select) 665a5356aefSYogesh Narayan Gaur return; 666a5356aefSYogesh Narayan Gaur 667a5356aefSYogesh Narayan Gaur /* Reset FLSHxxCR0 registers */ 668a5356aefSYogesh Narayan Gaur fspi_writel(f, 0, f->iobase + FSPI_FLSHA1CR0); 669a5356aefSYogesh Narayan Gaur fspi_writel(f, 0, f->iobase + FSPI_FLSHA2CR0); 670a5356aefSYogesh Narayan Gaur fspi_writel(f, 0, f->iobase + FSPI_FLSHB1CR0); 671a5356aefSYogesh Narayan Gaur fspi_writel(f, 0, f->iobase + FSPI_FLSHB2CR0); 672a5356aefSYogesh Narayan Gaur 673a5356aefSYogesh Narayan Gaur /* Assign controller memory mapped space as size, KBytes, of flash. */ 674a5356aefSYogesh Narayan Gaur size_kb = FSPI_FLSHXCR0_SZ(f->memmap_phy_size); 675a5356aefSYogesh Narayan Gaur 676a5356aefSYogesh Narayan Gaur fspi_writel(f, size_kb, f->iobase + FSPI_FLSHA1CR0 + 677a5356aefSYogesh Narayan Gaur 4 * spi->chip_select); 678a5356aefSYogesh Narayan Gaur 679a5356aefSYogesh Narayan Gaur dev_dbg(f->dev, "Slave device [CS:%x] selected\n", spi->chip_select); 680a5356aefSYogesh Narayan Gaur 681a5356aefSYogesh Narayan Gaur nxp_fspi_clk_disable_unprep(f); 682a5356aefSYogesh Narayan Gaur 683a5356aefSYogesh Narayan Gaur ret = clk_set_rate(f->clk, rate); 684a5356aefSYogesh Narayan Gaur if (ret) 685a5356aefSYogesh Narayan Gaur return; 686a5356aefSYogesh Narayan Gaur 687a5356aefSYogesh Narayan Gaur ret = nxp_fspi_clk_prep_enable(f); 688a5356aefSYogesh Narayan Gaur if (ret) 689a5356aefSYogesh Narayan Gaur return; 690a5356aefSYogesh Narayan Gaur 691a5356aefSYogesh Narayan Gaur f->selected = spi->chip_select; 692a5356aefSYogesh Narayan Gaur } 693a5356aefSYogesh Narayan Gaur 694d166a735SHan Xu static int nxp_fspi_read_ahb(struct nxp_fspi *f, const struct spi_mem_op *op) 695a5356aefSYogesh Narayan Gaur { 696d166a735SHan Xu u32 start = op->addr.val; 697a5356aefSYogesh Narayan Gaur u32 len = op->data.nbytes; 698a5356aefSYogesh Narayan Gaur 699d166a735SHan Xu /* if necessary, ioremap before AHB read */ 700d166a735SHan Xu if ((!f->ahb_addr) || start < f->memmap_start || 701d166a735SHan Xu start + len > f->memmap_start + f->memmap_len) { 702d166a735SHan Xu if (f->ahb_addr) 703d166a735SHan Xu iounmap(f->ahb_addr); 704d166a735SHan Xu 705d166a735SHan Xu f->memmap_start = start; 706d166a735SHan Xu f->memmap_len = len > NXP_FSPI_MIN_IOMAP ? 707d166a735SHan Xu len : NXP_FSPI_MIN_IOMAP; 708d166a735SHan Xu 709d166a735SHan Xu f->ahb_addr = ioremap_wc(f->memmap_phy + f->memmap_start, 710d166a735SHan Xu f->memmap_len); 711d166a735SHan Xu 712d166a735SHan Xu if (!f->ahb_addr) { 713d166a735SHan Xu dev_err(f->dev, "failed to alloc memory\n"); 714d166a735SHan Xu return -ENOMEM; 715d166a735SHan Xu } 716d166a735SHan Xu } 717d166a735SHan Xu 718a5356aefSYogesh Narayan Gaur /* Read out the data directly from the AHB buffer. */ 719d166a735SHan Xu memcpy_fromio(op->data.buf.in, 720d166a735SHan Xu f->ahb_addr + start - f->memmap_start, len); 721d166a735SHan Xu 722d166a735SHan Xu return 0; 723a5356aefSYogesh Narayan Gaur } 724a5356aefSYogesh Narayan Gaur 725a5356aefSYogesh Narayan Gaur static void nxp_fspi_fill_txfifo(struct nxp_fspi *f, 726a5356aefSYogesh Narayan Gaur const struct spi_mem_op *op) 727a5356aefSYogesh Narayan Gaur { 728a5356aefSYogesh Narayan Gaur void __iomem *base = f->iobase; 729a5356aefSYogesh Narayan Gaur int i, ret; 730a5356aefSYogesh Narayan Gaur u8 *buf = (u8 *) op->data.buf.out; 731a5356aefSYogesh Narayan Gaur 732a5356aefSYogesh Narayan Gaur /* clear the TX FIFO. */ 733a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_IPTXFCR_CLR, base + FSPI_IPTXFCR); 734a5356aefSYogesh Narayan Gaur 735a5356aefSYogesh Narayan Gaur /* 736a5356aefSYogesh Narayan Gaur * Default value of water mark level is 8 bytes, hence in single 737a5356aefSYogesh Narayan Gaur * write request controller can write max 8 bytes of data. 738a5356aefSYogesh Narayan Gaur */ 739a5356aefSYogesh Narayan Gaur 740a5356aefSYogesh Narayan Gaur for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 8); i += 8) { 741a5356aefSYogesh Narayan Gaur /* Wait for TXFIFO empty */ 742a5356aefSYogesh Narayan Gaur ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, 743a5356aefSYogesh Narayan Gaur FSPI_INTR_IPTXWE, 0, 744a5356aefSYogesh Narayan Gaur POLL_TOUT, true); 745a5356aefSYogesh Narayan Gaur WARN_ON(ret); 746a5356aefSYogesh Narayan Gaur 747a5356aefSYogesh Narayan Gaur fspi_writel(f, *(u32 *) (buf + i), base + FSPI_TFDR); 748a5356aefSYogesh Narayan Gaur fspi_writel(f, *(u32 *) (buf + i + 4), base + FSPI_TFDR + 4); 749a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR); 750a5356aefSYogesh Narayan Gaur } 751a5356aefSYogesh Narayan Gaur 752a5356aefSYogesh Narayan Gaur if (i < op->data.nbytes) { 753a5356aefSYogesh Narayan Gaur u32 data = 0; 754a5356aefSYogesh Narayan Gaur int j; 755a5356aefSYogesh Narayan Gaur /* Wait for TXFIFO empty */ 756a5356aefSYogesh Narayan Gaur ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, 757a5356aefSYogesh Narayan Gaur FSPI_INTR_IPTXWE, 0, 758a5356aefSYogesh Narayan Gaur POLL_TOUT, true); 759a5356aefSYogesh Narayan Gaur WARN_ON(ret); 760a5356aefSYogesh Narayan Gaur 761a5356aefSYogesh Narayan Gaur for (j = 0; j < ALIGN(op->data.nbytes - i, 4); j += 4) { 762a5356aefSYogesh Narayan Gaur memcpy(&data, buf + i + j, 4); 763a5356aefSYogesh Narayan Gaur fspi_writel(f, data, base + FSPI_TFDR + j); 764a5356aefSYogesh Narayan Gaur } 765a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR); 766a5356aefSYogesh Narayan Gaur } 767a5356aefSYogesh Narayan Gaur } 768a5356aefSYogesh Narayan Gaur 769a5356aefSYogesh Narayan Gaur static void nxp_fspi_read_rxfifo(struct nxp_fspi *f, 770a5356aefSYogesh Narayan Gaur const struct spi_mem_op *op) 771a5356aefSYogesh Narayan Gaur { 772a5356aefSYogesh Narayan Gaur void __iomem *base = f->iobase; 773a5356aefSYogesh Narayan Gaur int i, ret; 774a5356aefSYogesh Narayan Gaur int len = op->data.nbytes; 775a5356aefSYogesh Narayan Gaur u8 *buf = (u8 *) op->data.buf.in; 776a5356aefSYogesh Narayan Gaur 777a5356aefSYogesh Narayan Gaur /* 778a5356aefSYogesh Narayan Gaur * Default value of water mark level is 8 bytes, hence in single 779a5356aefSYogesh Narayan Gaur * read request controller can read max 8 bytes of data. 780a5356aefSYogesh Narayan Gaur */ 781a5356aefSYogesh Narayan Gaur for (i = 0; i < ALIGN_DOWN(len, 8); i += 8) { 782a5356aefSYogesh Narayan Gaur /* Wait for RXFIFO available */ 783a5356aefSYogesh Narayan Gaur ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, 784a5356aefSYogesh Narayan Gaur FSPI_INTR_IPRXWA, 0, 785a5356aefSYogesh Narayan Gaur POLL_TOUT, true); 786a5356aefSYogesh Narayan Gaur WARN_ON(ret); 787a5356aefSYogesh Narayan Gaur 788a5356aefSYogesh Narayan Gaur *(u32 *)(buf + i) = fspi_readl(f, base + FSPI_RFDR); 789a5356aefSYogesh Narayan Gaur *(u32 *)(buf + i + 4) = fspi_readl(f, base + FSPI_RFDR + 4); 790a5356aefSYogesh Narayan Gaur /* move the FIFO pointer */ 791a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR); 792a5356aefSYogesh Narayan Gaur } 793a5356aefSYogesh Narayan Gaur 794a5356aefSYogesh Narayan Gaur if (i < len) { 795a5356aefSYogesh Narayan Gaur u32 tmp; 796a5356aefSYogesh Narayan Gaur int size, j; 797a5356aefSYogesh Narayan Gaur 798a5356aefSYogesh Narayan Gaur buf = op->data.buf.in + i; 799a5356aefSYogesh Narayan Gaur /* Wait for RXFIFO available */ 800a5356aefSYogesh Narayan Gaur ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, 801a5356aefSYogesh Narayan Gaur FSPI_INTR_IPRXWA, 0, 802a5356aefSYogesh Narayan Gaur POLL_TOUT, true); 803a5356aefSYogesh Narayan Gaur WARN_ON(ret); 804a5356aefSYogesh Narayan Gaur 805a5356aefSYogesh Narayan Gaur len = op->data.nbytes - i; 806a5356aefSYogesh Narayan Gaur for (j = 0; j < op->data.nbytes - i; j += 4) { 807a5356aefSYogesh Narayan Gaur tmp = fspi_readl(f, base + FSPI_RFDR + j); 808a5356aefSYogesh Narayan Gaur size = min(len, 4); 809a5356aefSYogesh Narayan Gaur memcpy(buf + j, &tmp, size); 810a5356aefSYogesh Narayan Gaur len -= size; 811a5356aefSYogesh Narayan Gaur } 812a5356aefSYogesh Narayan Gaur } 813a5356aefSYogesh Narayan Gaur 814a5356aefSYogesh Narayan Gaur /* invalid the RXFIFO */ 815a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_IPRXFCR_CLR, base + FSPI_IPRXFCR); 816a5356aefSYogesh Narayan Gaur /* move the FIFO pointer */ 817a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR); 818a5356aefSYogesh Narayan Gaur } 819a5356aefSYogesh Narayan Gaur 820a5356aefSYogesh Narayan Gaur static int nxp_fspi_do_op(struct nxp_fspi *f, const struct spi_mem_op *op) 821a5356aefSYogesh Narayan Gaur { 822a5356aefSYogesh Narayan Gaur void __iomem *base = f->iobase; 823a5356aefSYogesh Narayan Gaur int seqnum = 0; 824a5356aefSYogesh Narayan Gaur int err = 0; 825a5356aefSYogesh Narayan Gaur u32 reg; 826a5356aefSYogesh Narayan Gaur 827a5356aefSYogesh Narayan Gaur reg = fspi_readl(f, base + FSPI_IPRXFCR); 828a5356aefSYogesh Narayan Gaur /* invalid RXFIFO first */ 829a5356aefSYogesh Narayan Gaur reg &= ~FSPI_IPRXFCR_DMA_EN; 830a5356aefSYogesh Narayan Gaur reg = reg | FSPI_IPRXFCR_CLR; 831a5356aefSYogesh Narayan Gaur fspi_writel(f, reg, base + FSPI_IPRXFCR); 832a5356aefSYogesh Narayan Gaur 833a5356aefSYogesh Narayan Gaur init_completion(&f->c); 834a5356aefSYogesh Narayan Gaur 835a5356aefSYogesh Narayan Gaur fspi_writel(f, op->addr.val, base + FSPI_IPCR0); 836a5356aefSYogesh Narayan Gaur /* 837a5356aefSYogesh Narayan Gaur * Always start the sequence at the same index since we update 838a5356aefSYogesh Narayan Gaur * the LUT at each exec_op() call. And also specify the DATA 839a5356aefSYogesh Narayan Gaur * length, since it's has not been specified in the LUT. 840a5356aefSYogesh Narayan Gaur */ 841a5356aefSYogesh Narayan Gaur fspi_writel(f, op->data.nbytes | 842a5356aefSYogesh Narayan Gaur (SEQID_LUT << FSPI_IPCR1_SEQID_SHIFT) | 843a5356aefSYogesh Narayan Gaur (seqnum << FSPI_IPCR1_SEQNUM_SHIFT), 844a5356aefSYogesh Narayan Gaur base + FSPI_IPCR1); 845a5356aefSYogesh Narayan Gaur 846a5356aefSYogesh Narayan Gaur /* Trigger the LUT now. */ 847a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_IPCMD_TRG, base + FSPI_IPCMD); 848a5356aefSYogesh Narayan Gaur 849a5356aefSYogesh Narayan Gaur /* Wait for the interrupt. */ 850a5356aefSYogesh Narayan Gaur if (!wait_for_completion_timeout(&f->c, msecs_to_jiffies(1000))) 851a5356aefSYogesh Narayan Gaur err = -ETIMEDOUT; 852a5356aefSYogesh Narayan Gaur 853a5356aefSYogesh Narayan Gaur /* Invoke IP data read, if request is of data read. */ 854a5356aefSYogesh Narayan Gaur if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN) 855a5356aefSYogesh Narayan Gaur nxp_fspi_read_rxfifo(f, op); 856a5356aefSYogesh Narayan Gaur 857a5356aefSYogesh Narayan Gaur return err; 858a5356aefSYogesh Narayan Gaur } 859a5356aefSYogesh Narayan Gaur 860a5356aefSYogesh Narayan Gaur static int nxp_fspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) 861a5356aefSYogesh Narayan Gaur { 862a5356aefSYogesh Narayan Gaur struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master); 863a5356aefSYogesh Narayan Gaur int err = 0; 864a5356aefSYogesh Narayan Gaur 865a5356aefSYogesh Narayan Gaur mutex_lock(&f->lock); 866a5356aefSYogesh Narayan Gaur 867a5356aefSYogesh Narayan Gaur /* Wait for controller being ready. */ 868a5356aefSYogesh Narayan Gaur err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0, 869a5356aefSYogesh Narayan Gaur FSPI_STS0_ARB_IDLE, 1, POLL_TOUT, true); 870a5356aefSYogesh Narayan Gaur WARN_ON(err); 871a5356aefSYogesh Narayan Gaur 872a5356aefSYogesh Narayan Gaur nxp_fspi_select_mem(f, mem->spi); 873a5356aefSYogesh Narayan Gaur 874a5356aefSYogesh Narayan Gaur nxp_fspi_prepare_lut(f, op); 875a5356aefSYogesh Narayan Gaur /* 87631e92cbfSKuldeep Singh * If we have large chunks of data, we read them through the AHB bus by 87731e92cbfSKuldeep Singh * accessing the mapped memory. In all other cases we use IP commands 87831e92cbfSKuldeep Singh * to access the flash. Read via AHB bus may be corrupted due to 87931e92cbfSKuldeep Singh * existence of an errata and therefore discard AHB read in such cases. 880a5356aefSYogesh Narayan Gaur */ 881a5356aefSYogesh Narayan Gaur if (op->data.nbytes > (f->devtype_data->rxfifo - 4) && 88231e92cbfSKuldeep Singh op->data.dir == SPI_MEM_DATA_IN && 88331e92cbfSKuldeep Singh !needs_ip_only(f)) { 884d166a735SHan Xu err = nxp_fspi_read_ahb(f, op); 885a5356aefSYogesh Narayan Gaur } else { 886a5356aefSYogesh Narayan Gaur if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) 887a5356aefSYogesh Narayan Gaur nxp_fspi_fill_txfifo(f, op); 888a5356aefSYogesh Narayan Gaur 889a5356aefSYogesh Narayan Gaur err = nxp_fspi_do_op(f, op); 890a5356aefSYogesh Narayan Gaur } 891a5356aefSYogesh Narayan Gaur 892a5356aefSYogesh Narayan Gaur /* Invalidate the data in the AHB buffer. */ 893a5356aefSYogesh Narayan Gaur nxp_fspi_invalid(f); 894a5356aefSYogesh Narayan Gaur 895a5356aefSYogesh Narayan Gaur mutex_unlock(&f->lock); 896a5356aefSYogesh Narayan Gaur 897a5356aefSYogesh Narayan Gaur return err; 898a5356aefSYogesh Narayan Gaur } 899a5356aefSYogesh Narayan Gaur 900a5356aefSYogesh Narayan Gaur static int nxp_fspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) 901a5356aefSYogesh Narayan Gaur { 902a5356aefSYogesh Narayan Gaur struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master); 903a5356aefSYogesh Narayan Gaur 904a5356aefSYogesh Narayan Gaur if (op->data.dir == SPI_MEM_DATA_OUT) { 905a5356aefSYogesh Narayan Gaur if (op->data.nbytes > f->devtype_data->txfifo) 906a5356aefSYogesh Narayan Gaur op->data.nbytes = f->devtype_data->txfifo; 907a5356aefSYogesh Narayan Gaur } else { 908a5356aefSYogesh Narayan Gaur if (op->data.nbytes > f->devtype_data->ahb_buf_size) 909a5356aefSYogesh Narayan Gaur op->data.nbytes = f->devtype_data->ahb_buf_size; 910a5356aefSYogesh Narayan Gaur else if (op->data.nbytes > (f->devtype_data->rxfifo - 4)) 911a5356aefSYogesh Narayan Gaur op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8); 912a5356aefSYogesh Narayan Gaur } 913a5356aefSYogesh Narayan Gaur 91431e92cbfSKuldeep Singh /* Limit data bytes to RX FIFO in case of IP read only */ 91531e92cbfSKuldeep Singh if (op->data.dir == SPI_MEM_DATA_IN && 91631e92cbfSKuldeep Singh needs_ip_only(f) && 91731e92cbfSKuldeep Singh op->data.nbytes > f->devtype_data->rxfifo) 91831e92cbfSKuldeep Singh op->data.nbytes = f->devtype_data->rxfifo; 91931e92cbfSKuldeep Singh 920a5356aefSYogesh Narayan Gaur return 0; 921a5356aefSYogesh Narayan Gaur } 922a5356aefSYogesh Narayan Gaur 92382ce7d0eSKuldeep Singh static void erratum_err050568(struct nxp_fspi *f) 92482ce7d0eSKuldeep Singh { 92582ce7d0eSKuldeep Singh const struct soc_device_attribute ls1028a_soc_attr[] = { 92682ce7d0eSKuldeep Singh { .family = "QorIQ LS1028A" }, 92782ce7d0eSKuldeep Singh { /* sentinel */ } 92882ce7d0eSKuldeep Singh }; 92982ce7d0eSKuldeep Singh struct device_node *np; 93082ce7d0eSKuldeep Singh struct regmap *map; 93182ce7d0eSKuldeep Singh u32 val = 0, sysclk = 0; 93282ce7d0eSKuldeep Singh int ret; 93382ce7d0eSKuldeep Singh 93482ce7d0eSKuldeep Singh /* Check for LS1028A family */ 93582ce7d0eSKuldeep Singh if (!soc_device_match(ls1028a_soc_attr)) { 93682ce7d0eSKuldeep Singh dev_dbg(f->dev, "Errata applicable only for LS1028A\n"); 93782ce7d0eSKuldeep Singh return; 93882ce7d0eSKuldeep Singh } 93982ce7d0eSKuldeep Singh 94082ce7d0eSKuldeep Singh /* Compute system clock frequency multiplier ratio */ 94182ce7d0eSKuldeep Singh map = syscon_regmap_lookup_by_compatible("fsl,ls1028a-dcfg"); 94282ce7d0eSKuldeep Singh if (IS_ERR(map)) { 94382ce7d0eSKuldeep Singh dev_err(f->dev, "No syscon regmap\n"); 94482ce7d0eSKuldeep Singh goto err; 94582ce7d0eSKuldeep Singh } 94682ce7d0eSKuldeep Singh 94782ce7d0eSKuldeep Singh ret = regmap_read(map, DCFG_RCWSR1, &val); 94882ce7d0eSKuldeep Singh if (ret < 0) 94982ce7d0eSKuldeep Singh goto err; 95082ce7d0eSKuldeep Singh 95182ce7d0eSKuldeep Singh /* Strap bits 6:2 define SYS_PLL_RAT i.e frequency multiplier ratio */ 95282ce7d0eSKuldeep Singh val = (val >> 2) & 0x1F; 95382ce7d0eSKuldeep Singh WARN(val == 0, "Strapping is zero: Cannot determine ratio"); 95482ce7d0eSKuldeep Singh 95582ce7d0eSKuldeep Singh /* Compute system clock frequency */ 95682ce7d0eSKuldeep Singh np = of_find_node_by_name(NULL, "clock-sysclk"); 95782ce7d0eSKuldeep Singh if (!np) 95882ce7d0eSKuldeep Singh goto err; 95982ce7d0eSKuldeep Singh 96082ce7d0eSKuldeep Singh if (of_property_read_u32(np, "clock-frequency", &sysclk)) 96182ce7d0eSKuldeep Singh goto err; 96282ce7d0eSKuldeep Singh 96382ce7d0eSKuldeep Singh sysclk = (sysclk * val) / 1000000; /* Convert sysclk to Mhz */ 96482ce7d0eSKuldeep Singh dev_dbg(f->dev, "val: 0x%08x, sysclk: %dMhz\n", val, sysclk); 96582ce7d0eSKuldeep Singh 96682ce7d0eSKuldeep Singh /* Use IP bus only if PLL is 300MHz */ 96782ce7d0eSKuldeep Singh if (sysclk == 300) 96882ce7d0eSKuldeep Singh f->devtype_data->quirks |= FSPI_QUIRK_USE_IP_ONLY; 96982ce7d0eSKuldeep Singh 97082ce7d0eSKuldeep Singh return; 97182ce7d0eSKuldeep Singh 97282ce7d0eSKuldeep Singh err: 97382ce7d0eSKuldeep Singh dev_err(f->dev, "Errata cannot be executed. Read via IP bus may not work\n"); 97482ce7d0eSKuldeep Singh } 97582ce7d0eSKuldeep Singh 976a5356aefSYogesh Narayan Gaur static int nxp_fspi_default_setup(struct nxp_fspi *f) 977a5356aefSYogesh Narayan Gaur { 978a5356aefSYogesh Narayan Gaur void __iomem *base = f->iobase; 979a5356aefSYogesh Narayan Gaur int ret, i; 980a5356aefSYogesh Narayan Gaur u32 reg; 981a5356aefSYogesh Narayan Gaur 982a5356aefSYogesh Narayan Gaur /* disable and unprepare clock to avoid glitch pass to controller */ 983a5356aefSYogesh Narayan Gaur nxp_fspi_clk_disable_unprep(f); 984a5356aefSYogesh Narayan Gaur 985a5356aefSYogesh Narayan Gaur /* the default frequency, we will change it later if necessary. */ 986a5356aefSYogesh Narayan Gaur ret = clk_set_rate(f->clk, 20000000); 987a5356aefSYogesh Narayan Gaur if (ret) 988a5356aefSYogesh Narayan Gaur return ret; 989a5356aefSYogesh Narayan Gaur 990a5356aefSYogesh Narayan Gaur ret = nxp_fspi_clk_prep_enable(f); 991a5356aefSYogesh Narayan Gaur if (ret) 992a5356aefSYogesh Narayan Gaur return ret; 993a5356aefSYogesh Narayan Gaur 99482ce7d0eSKuldeep Singh /* 99582ce7d0eSKuldeep Singh * ERR050568: Flash access by FlexSPI AHB command may not work with 99682ce7d0eSKuldeep Singh * platform frequency equal to 300 MHz on LS1028A. 99782ce7d0eSKuldeep Singh * LS1028A reuses LX2160A compatible entry. Make errata applicable for 99882ce7d0eSKuldeep Singh * Layerscape LS1028A platform. 99982ce7d0eSKuldeep Singh */ 100082ce7d0eSKuldeep Singh if (of_device_is_compatible(f->dev->of_node, "nxp,lx2160a-fspi")) 100182ce7d0eSKuldeep Singh erratum_err050568(f); 100282ce7d0eSKuldeep Singh 1003a5356aefSYogesh Narayan Gaur /* Reset the module */ 1004a5356aefSYogesh Narayan Gaur /* w1c register, wait unit clear */ 1005a5356aefSYogesh Narayan Gaur ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0, 1006a5356aefSYogesh Narayan Gaur FSPI_MCR0_SWRST, 0, POLL_TOUT, false); 1007a5356aefSYogesh Narayan Gaur WARN_ON(ret); 1008a5356aefSYogesh Narayan Gaur 1009a5356aefSYogesh Narayan Gaur /* Disable the module */ 1010a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_MCR0_MDIS, base + FSPI_MCR0); 1011a5356aefSYogesh Narayan Gaur 1012a5356aefSYogesh Narayan Gaur /* Reset the DLL register to default value */ 1013a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_DLLACR_OVRDEN, base + FSPI_DLLACR); 1014a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_DLLBCR_OVRDEN, base + FSPI_DLLBCR); 1015a5356aefSYogesh Narayan Gaur 1016a5356aefSYogesh Narayan Gaur /* enable module */ 1017b7461fa5SHan Xu fspi_writel(f, FSPI_MCR0_AHB_TIMEOUT(0xFF) | 1018b7461fa5SHan Xu FSPI_MCR0_IP_TIMEOUT(0xFF) | (u32) FSPI_MCR0_OCTCOMB_EN, 1019a5356aefSYogesh Narayan Gaur base + FSPI_MCR0); 1020a5356aefSYogesh Narayan Gaur 1021a5356aefSYogesh Narayan Gaur /* 1022a5356aefSYogesh Narayan Gaur * Disable same device enable bit and configure all slave devices 1023a5356aefSYogesh Narayan Gaur * independently. 1024a5356aefSYogesh Narayan Gaur */ 1025a5356aefSYogesh Narayan Gaur reg = fspi_readl(f, f->iobase + FSPI_MCR2); 1026a5356aefSYogesh Narayan Gaur reg = reg & ~(FSPI_MCR2_SAMEDEVICEEN); 1027a5356aefSYogesh Narayan Gaur fspi_writel(f, reg, base + FSPI_MCR2); 1028a5356aefSYogesh Narayan Gaur 1029a5356aefSYogesh Narayan Gaur /* AHB configuration for access buffer 0~7. */ 1030a5356aefSYogesh Narayan Gaur for (i = 0; i < 7; i++) 1031a5356aefSYogesh Narayan Gaur fspi_writel(f, 0, base + FSPI_AHBRX_BUF0CR0 + 4 * i); 1032a5356aefSYogesh Narayan Gaur 1033a5356aefSYogesh Narayan Gaur /* 1034a5356aefSYogesh Narayan Gaur * Set ADATSZ with the maximum AHB buffer size to improve the read 1035a5356aefSYogesh Narayan Gaur * performance. 1036a5356aefSYogesh Narayan Gaur */ 1037a5356aefSYogesh Narayan Gaur fspi_writel(f, (f->devtype_data->ahb_buf_size / 8 | 1038a5356aefSYogesh Narayan Gaur FSPI_AHBRXBUF0CR7_PREF), base + FSPI_AHBRX_BUF7CR0); 1039a5356aefSYogesh Narayan Gaur 1040a5356aefSYogesh Narayan Gaur /* prefetch and no start address alignment limitation */ 1041a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_AHBCR_PREF_EN | FSPI_AHBCR_RDADDROPT, 1042a5356aefSYogesh Narayan Gaur base + FSPI_AHBCR); 1043a5356aefSYogesh Narayan Gaur 1044a5356aefSYogesh Narayan Gaur /* AHB Read - Set lut sequence ID for all CS. */ 1045a5356aefSYogesh Narayan Gaur fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA1CR2); 1046a5356aefSYogesh Narayan Gaur fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA2CR2); 1047a5356aefSYogesh Narayan Gaur fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB1CR2); 1048a5356aefSYogesh Narayan Gaur fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB2CR2); 1049a5356aefSYogesh Narayan Gaur 1050a5356aefSYogesh Narayan Gaur f->selected = -1; 1051a5356aefSYogesh Narayan Gaur 1052a5356aefSYogesh Narayan Gaur /* enable the interrupt */ 1053a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_INTEN_IPCMDDONE, base + FSPI_INTEN); 1054a5356aefSYogesh Narayan Gaur 1055a5356aefSYogesh Narayan Gaur return 0; 1056a5356aefSYogesh Narayan Gaur } 1057a5356aefSYogesh Narayan Gaur 1058a5356aefSYogesh Narayan Gaur static const char *nxp_fspi_get_name(struct spi_mem *mem) 1059a5356aefSYogesh Narayan Gaur { 1060a5356aefSYogesh Narayan Gaur struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master); 1061a5356aefSYogesh Narayan Gaur struct device *dev = &mem->spi->dev; 1062a5356aefSYogesh Narayan Gaur const char *name; 1063a5356aefSYogesh Narayan Gaur 1064a5356aefSYogesh Narayan Gaur // Set custom name derived from the platform_device of the controller. 1065a5356aefSYogesh Narayan Gaur if (of_get_available_child_count(f->dev->of_node) == 1) 1066a5356aefSYogesh Narayan Gaur return dev_name(f->dev); 1067a5356aefSYogesh Narayan Gaur 1068a5356aefSYogesh Narayan Gaur name = devm_kasprintf(dev, GFP_KERNEL, 1069a5356aefSYogesh Narayan Gaur "%s-%d", dev_name(f->dev), 1070a5356aefSYogesh Narayan Gaur mem->spi->chip_select); 1071a5356aefSYogesh Narayan Gaur 1072a5356aefSYogesh Narayan Gaur if (!name) { 1073a5356aefSYogesh Narayan Gaur dev_err(dev, "failed to get memory for custom flash name\n"); 1074a5356aefSYogesh Narayan Gaur return ERR_PTR(-ENOMEM); 1075a5356aefSYogesh Narayan Gaur } 1076a5356aefSYogesh Narayan Gaur 1077a5356aefSYogesh Narayan Gaur return name; 1078a5356aefSYogesh Narayan Gaur } 1079a5356aefSYogesh Narayan Gaur 1080a5356aefSYogesh Narayan Gaur static const struct spi_controller_mem_ops nxp_fspi_mem_ops = { 1081a5356aefSYogesh Narayan Gaur .adjust_op_size = nxp_fspi_adjust_op_size, 1082a5356aefSYogesh Narayan Gaur .supports_op = nxp_fspi_supports_op, 1083a5356aefSYogesh Narayan Gaur .exec_op = nxp_fspi_exec_op, 1084a5356aefSYogesh Narayan Gaur .get_name = nxp_fspi_get_name, 1085a5356aefSYogesh Narayan Gaur }; 1086a5356aefSYogesh Narayan Gaur 1087a5356aefSYogesh Narayan Gaur static int nxp_fspi_probe(struct platform_device *pdev) 1088a5356aefSYogesh Narayan Gaur { 1089a5356aefSYogesh Narayan Gaur struct spi_controller *ctlr; 1090a5356aefSYogesh Narayan Gaur struct device *dev = &pdev->dev; 1091a5356aefSYogesh Narayan Gaur struct device_node *np = dev->of_node; 1092a5356aefSYogesh Narayan Gaur struct resource *res; 1093a5356aefSYogesh Narayan Gaur struct nxp_fspi *f; 1094a5356aefSYogesh Narayan Gaur int ret; 109571d80563SRan Wang u32 reg; 1096a5356aefSYogesh Narayan Gaur 1097a5356aefSYogesh Narayan Gaur ctlr = spi_alloc_master(&pdev->dev, sizeof(*f)); 1098a5356aefSYogesh Narayan Gaur if (!ctlr) 1099a5356aefSYogesh Narayan Gaur return -ENOMEM; 1100a5356aefSYogesh Narayan Gaur 1101b3281794SYogesh Narayan Gaur ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL | 1102b3281794SYogesh Narayan Gaur SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL; 1103a5356aefSYogesh Narayan Gaur 1104a5356aefSYogesh Narayan Gaur f = spi_controller_get_devdata(ctlr); 1105a5356aefSYogesh Narayan Gaur f->dev = dev; 110682ce7d0eSKuldeep Singh f->devtype_data = (struct nxp_fspi_devtype_data *)device_get_match_data(dev); 1107a5356aefSYogesh Narayan Gaur if (!f->devtype_data) { 1108a5356aefSYogesh Narayan Gaur ret = -ENODEV; 1109a5356aefSYogesh Narayan Gaur goto err_put_ctrl; 1110a5356aefSYogesh Narayan Gaur } 1111a5356aefSYogesh Narayan Gaur 1112a5356aefSYogesh Narayan Gaur platform_set_drvdata(pdev, f); 1113a5356aefSYogesh Narayan Gaur 1114a5356aefSYogesh Narayan Gaur /* find the resources - configuration register address space */ 111555ab8487Skuldip dwivedi if (is_acpi_node(f->dev->fwnode)) 111655ab8487Skuldip dwivedi res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 111755ab8487Skuldip dwivedi else 111855ab8487Skuldip dwivedi res = platform_get_resource_byname(pdev, 111955ab8487Skuldip dwivedi IORESOURCE_MEM, "fspi_base"); 112055ab8487Skuldip dwivedi 1121a5356aefSYogesh Narayan Gaur f->iobase = devm_ioremap_resource(dev, res); 1122a5356aefSYogesh Narayan Gaur if (IS_ERR(f->iobase)) { 1123a5356aefSYogesh Narayan Gaur ret = PTR_ERR(f->iobase); 1124a5356aefSYogesh Narayan Gaur goto err_put_ctrl; 1125a5356aefSYogesh Narayan Gaur } 1126a5356aefSYogesh Narayan Gaur 1127a5356aefSYogesh Narayan Gaur /* find the resources - controller memory mapped space */ 112855ab8487Skuldip dwivedi if (is_acpi_node(f->dev->fwnode)) 112955ab8487Skuldip dwivedi res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 113055ab8487Skuldip dwivedi else 113155ab8487Skuldip dwivedi res = platform_get_resource_byname(pdev, 113255ab8487Skuldip dwivedi IORESOURCE_MEM, "fspi_mmap"); 113355ab8487Skuldip dwivedi 11341a421ebaSDan Carpenter if (!res) { 11351a421ebaSDan Carpenter ret = -ENODEV; 1136a5356aefSYogesh Narayan Gaur goto err_put_ctrl; 1137a5356aefSYogesh Narayan Gaur } 1138a5356aefSYogesh Narayan Gaur 1139a5356aefSYogesh Narayan Gaur /* assign memory mapped starting address and mapped size. */ 1140a5356aefSYogesh Narayan Gaur f->memmap_phy = res->start; 1141a5356aefSYogesh Narayan Gaur f->memmap_phy_size = resource_size(res); 1142a5356aefSYogesh Narayan Gaur 1143a5356aefSYogesh Narayan Gaur /* find the clocks */ 114455ab8487Skuldip dwivedi if (dev_of_node(&pdev->dev)) { 1145a5356aefSYogesh Narayan Gaur f->clk_en = devm_clk_get(dev, "fspi_en"); 1146a5356aefSYogesh Narayan Gaur if (IS_ERR(f->clk_en)) { 1147a5356aefSYogesh Narayan Gaur ret = PTR_ERR(f->clk_en); 1148a5356aefSYogesh Narayan Gaur goto err_put_ctrl; 1149a5356aefSYogesh Narayan Gaur } 1150a5356aefSYogesh Narayan Gaur 1151a5356aefSYogesh Narayan Gaur f->clk = devm_clk_get(dev, "fspi"); 1152a5356aefSYogesh Narayan Gaur if (IS_ERR(f->clk)) { 1153a5356aefSYogesh Narayan Gaur ret = PTR_ERR(f->clk); 1154a5356aefSYogesh Narayan Gaur goto err_put_ctrl; 1155a5356aefSYogesh Narayan Gaur } 1156a5356aefSYogesh Narayan Gaur 1157a5356aefSYogesh Narayan Gaur ret = nxp_fspi_clk_prep_enable(f); 1158a5356aefSYogesh Narayan Gaur if (ret) { 1159a5356aefSYogesh Narayan Gaur dev_err(dev, "can not enable the clock\n"); 1160a5356aefSYogesh Narayan Gaur goto err_put_ctrl; 1161a5356aefSYogesh Narayan Gaur } 116255ab8487Skuldip dwivedi } 1163a5356aefSYogesh Narayan Gaur 1164*f422316cSHaibo Chen /* Clear potential interrupts */ 1165*f422316cSHaibo Chen reg = fspi_readl(f, f->iobase + FSPI_INTR); 1166*f422316cSHaibo Chen if (reg) 1167*f422316cSHaibo Chen fspi_writel(f, reg, f->iobase + FSPI_INTR); 1168*f422316cSHaibo Chen 1169a5356aefSYogesh Narayan Gaur /* find the irq */ 1170a5356aefSYogesh Narayan Gaur ret = platform_get_irq(pdev, 0); 11716b8ac10eSStephen Boyd if (ret < 0) 1172a5356aefSYogesh Narayan Gaur goto err_disable_clk; 1173a5356aefSYogesh Narayan Gaur 1174a5356aefSYogesh Narayan Gaur ret = devm_request_irq(dev, ret, 1175a5356aefSYogesh Narayan Gaur nxp_fspi_irq_handler, 0, pdev->name, f); 1176a5356aefSYogesh Narayan Gaur if (ret) { 1177a5356aefSYogesh Narayan Gaur dev_err(dev, "failed to request irq: %d\n", ret); 1178a5356aefSYogesh Narayan Gaur goto err_disable_clk; 1179a5356aefSYogesh Narayan Gaur } 1180a5356aefSYogesh Narayan Gaur 1181a5356aefSYogesh Narayan Gaur mutex_init(&f->lock); 1182a5356aefSYogesh Narayan Gaur 1183a5356aefSYogesh Narayan Gaur ctlr->bus_num = -1; 1184a5356aefSYogesh Narayan Gaur ctlr->num_chipselect = NXP_FSPI_MAX_CHIPSELECT; 1185a5356aefSYogesh Narayan Gaur ctlr->mem_ops = &nxp_fspi_mem_ops; 1186a5356aefSYogesh Narayan Gaur 1187a5356aefSYogesh Narayan Gaur nxp_fspi_default_setup(f); 1188a5356aefSYogesh Narayan Gaur 1189a5356aefSYogesh Narayan Gaur ctlr->dev.of_node = np; 1190a5356aefSYogesh Narayan Gaur 119169c23dbfSChuhong Yuan ret = devm_spi_register_controller(&pdev->dev, ctlr); 1192a5356aefSYogesh Narayan Gaur if (ret) 1193a5356aefSYogesh Narayan Gaur goto err_destroy_mutex; 1194a5356aefSYogesh Narayan Gaur 1195a5356aefSYogesh Narayan Gaur return 0; 1196a5356aefSYogesh Narayan Gaur 1197a5356aefSYogesh Narayan Gaur err_destroy_mutex: 1198a5356aefSYogesh Narayan Gaur mutex_destroy(&f->lock); 1199a5356aefSYogesh Narayan Gaur 1200a5356aefSYogesh Narayan Gaur err_disable_clk: 1201a5356aefSYogesh Narayan Gaur nxp_fspi_clk_disable_unprep(f); 1202a5356aefSYogesh Narayan Gaur 1203a5356aefSYogesh Narayan Gaur err_put_ctrl: 1204a5356aefSYogesh Narayan Gaur spi_controller_put(ctlr); 1205a5356aefSYogesh Narayan Gaur 1206a5356aefSYogesh Narayan Gaur dev_err(dev, "NXP FSPI probe failed\n"); 1207a5356aefSYogesh Narayan Gaur return ret; 1208a5356aefSYogesh Narayan Gaur } 1209a5356aefSYogesh Narayan Gaur 1210a5356aefSYogesh Narayan Gaur static int nxp_fspi_remove(struct platform_device *pdev) 1211a5356aefSYogesh Narayan Gaur { 1212a5356aefSYogesh Narayan Gaur struct nxp_fspi *f = platform_get_drvdata(pdev); 1213a5356aefSYogesh Narayan Gaur 1214a5356aefSYogesh Narayan Gaur /* disable the hardware */ 1215a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_MCR0_MDIS, f->iobase + FSPI_MCR0); 1216a5356aefSYogesh Narayan Gaur 1217a5356aefSYogesh Narayan Gaur nxp_fspi_clk_disable_unprep(f); 1218a5356aefSYogesh Narayan Gaur 1219a5356aefSYogesh Narayan Gaur mutex_destroy(&f->lock); 1220a5356aefSYogesh Narayan Gaur 1221d166a735SHan Xu if (f->ahb_addr) 1222d166a735SHan Xu iounmap(f->ahb_addr); 1223d166a735SHan Xu 1224a5356aefSYogesh Narayan Gaur return 0; 1225a5356aefSYogesh Narayan Gaur } 1226a5356aefSYogesh Narayan Gaur 1227a5356aefSYogesh Narayan Gaur static int nxp_fspi_suspend(struct device *dev) 1228a5356aefSYogesh Narayan Gaur { 1229a5356aefSYogesh Narayan Gaur return 0; 1230a5356aefSYogesh Narayan Gaur } 1231a5356aefSYogesh Narayan Gaur 1232a5356aefSYogesh Narayan Gaur static int nxp_fspi_resume(struct device *dev) 1233a5356aefSYogesh Narayan Gaur { 1234a5356aefSYogesh Narayan Gaur struct nxp_fspi *f = dev_get_drvdata(dev); 1235a5356aefSYogesh Narayan Gaur 1236a5356aefSYogesh Narayan Gaur nxp_fspi_default_setup(f); 1237a5356aefSYogesh Narayan Gaur 1238a5356aefSYogesh Narayan Gaur return 0; 1239a5356aefSYogesh Narayan Gaur } 1240a5356aefSYogesh Narayan Gaur 1241a5356aefSYogesh Narayan Gaur static const struct of_device_id nxp_fspi_dt_ids[] = { 1242a5356aefSYogesh Narayan Gaur { .compatible = "nxp,lx2160a-fspi", .data = (void *)&lx2160a_data, }, 1243941be8a7SHan Xu { .compatible = "nxp,imx8mm-fspi", .data = (void *)&imx8mm_data, }, 12440467a973SHeiko Schocher { .compatible = "nxp,imx8mp-fspi", .data = (void *)&imx8mm_data, }, 1245941be8a7SHan Xu { .compatible = "nxp,imx8qxp-fspi", .data = (void *)&imx8qxp_data, }, 1246c791e3c3SHan Xu { .compatible = "nxp,imx8dxl-fspi", .data = (void *)&imx8dxl_data, }, 1247a5356aefSYogesh Narayan Gaur { /* sentinel */ } 1248a5356aefSYogesh Narayan Gaur }; 1249a5356aefSYogesh Narayan Gaur MODULE_DEVICE_TABLE(of, nxp_fspi_dt_ids); 1250a5356aefSYogesh Narayan Gaur 125155ab8487Skuldip dwivedi #ifdef CONFIG_ACPI 125255ab8487Skuldip dwivedi static const struct acpi_device_id nxp_fspi_acpi_ids[] = { 125355ab8487Skuldip dwivedi { "NXP0009", .driver_data = (kernel_ulong_t)&lx2160a_data, }, 125455ab8487Skuldip dwivedi {} 125555ab8487Skuldip dwivedi }; 125655ab8487Skuldip dwivedi MODULE_DEVICE_TABLE(acpi, nxp_fspi_acpi_ids); 125755ab8487Skuldip dwivedi #endif 125855ab8487Skuldip dwivedi 1259a5356aefSYogesh Narayan Gaur static const struct dev_pm_ops nxp_fspi_pm_ops = { 1260a5356aefSYogesh Narayan Gaur .suspend = nxp_fspi_suspend, 1261a5356aefSYogesh Narayan Gaur .resume = nxp_fspi_resume, 1262a5356aefSYogesh Narayan Gaur }; 1263a5356aefSYogesh Narayan Gaur 1264a5356aefSYogesh Narayan Gaur static struct platform_driver nxp_fspi_driver = { 1265a5356aefSYogesh Narayan Gaur .driver = { 1266a5356aefSYogesh Narayan Gaur .name = "nxp-fspi", 1267a5356aefSYogesh Narayan Gaur .of_match_table = nxp_fspi_dt_ids, 126855ab8487Skuldip dwivedi .acpi_match_table = ACPI_PTR(nxp_fspi_acpi_ids), 1269a5356aefSYogesh Narayan Gaur .pm = &nxp_fspi_pm_ops, 1270a5356aefSYogesh Narayan Gaur }, 1271a5356aefSYogesh Narayan Gaur .probe = nxp_fspi_probe, 1272a5356aefSYogesh Narayan Gaur .remove = nxp_fspi_remove, 1273a5356aefSYogesh Narayan Gaur }; 1274a5356aefSYogesh Narayan Gaur module_platform_driver(nxp_fspi_driver); 1275a5356aefSYogesh Narayan Gaur 1276a5356aefSYogesh Narayan Gaur MODULE_DESCRIPTION("NXP FSPI Controller Driver"); 1277a5356aefSYogesh Narayan Gaur MODULE_AUTHOR("NXP Semiconductor"); 1278a5356aefSYogesh Narayan Gaur MODULE_AUTHOR("Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>"); 1279ce6f0697SYogesh Narayan Gaur MODULE_AUTHOR("Boris Brezillon <bbrezillon@kernel.org>"); 1280a5356aefSYogesh Narayan Gaur MODULE_AUTHOR("Frieder Schrempf <frieder.schrempf@kontron.de>"); 1281ce6f0697SYogesh Narayan Gaur MODULE_LICENSE("GPL v2"); 1282