1a5356aefSYogesh Narayan Gaur // SPDX-License-Identifier: GPL-2.0+ 2a5356aefSYogesh Narayan Gaur 3a5356aefSYogesh Narayan Gaur /* 4a5356aefSYogesh Narayan Gaur * NXP FlexSPI(FSPI) controller driver. 5a5356aefSYogesh Narayan Gaur * 655ab8487Skuldip dwivedi * Copyright 2019-2020 NXP 755ab8487Skuldip dwivedi * Copyright 2020 Puresoftware Ltd. 8a5356aefSYogesh Narayan Gaur * 9a5356aefSYogesh Narayan Gaur * FlexSPI is a flexsible SPI host controller which supports two SPI 10a5356aefSYogesh Narayan Gaur * channels and up to 4 external devices. Each channel supports 11a5356aefSYogesh Narayan Gaur * Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional 12a5356aefSYogesh Narayan Gaur * data lines). 13a5356aefSYogesh Narayan Gaur * 14a5356aefSYogesh Narayan Gaur * FlexSPI controller is driven by the LUT(Look-up Table) registers 15a5356aefSYogesh Narayan Gaur * LUT registers are a look-up-table for sequences of instructions. 16a5356aefSYogesh Narayan Gaur * A valid sequence consists of four LUT registers. 17a5356aefSYogesh Narayan Gaur * Maximum 32 LUT sequences can be programmed simultaneously. 18a5356aefSYogesh Narayan Gaur * 19a5356aefSYogesh Narayan Gaur * LUTs are being created at run-time based on the commands passed 20a5356aefSYogesh Narayan Gaur * from the spi-mem framework, thus using single LUT index. 21a5356aefSYogesh Narayan Gaur * 22a5356aefSYogesh Narayan Gaur * Software triggered Flash read/write access by IP Bus. 23a5356aefSYogesh Narayan Gaur * 24a5356aefSYogesh Narayan Gaur * Memory mapped read access by AHB Bus. 25a5356aefSYogesh Narayan Gaur * 26a5356aefSYogesh Narayan Gaur * Based on SPI MEM interface and spi-fsl-qspi.c driver. 27a5356aefSYogesh Narayan Gaur * 28a5356aefSYogesh Narayan Gaur * Author: 29a5356aefSYogesh Narayan Gaur * Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com> 30ce6f0697SYogesh Narayan Gaur * Boris Brezillon <bbrezillon@kernel.org> 31a5356aefSYogesh Narayan Gaur * Frieder Schrempf <frieder.schrempf@kontron.de> 32a5356aefSYogesh Narayan Gaur */ 33a5356aefSYogesh Narayan Gaur 3455ab8487Skuldip dwivedi #include <linux/acpi.h> 35a5356aefSYogesh Narayan Gaur #include <linux/bitops.h> 3667a12ae5SMichael Walle #include <linux/bitfield.h> 37a5356aefSYogesh Narayan Gaur #include <linux/clk.h> 38a5356aefSYogesh Narayan Gaur #include <linux/completion.h> 39a5356aefSYogesh Narayan Gaur #include <linux/delay.h> 40a5356aefSYogesh Narayan Gaur #include <linux/err.h> 41a5356aefSYogesh Narayan Gaur #include <linux/errno.h> 42a5356aefSYogesh Narayan Gaur #include <linux/interrupt.h> 43a5356aefSYogesh Narayan Gaur #include <linux/io.h> 44a5356aefSYogesh Narayan Gaur #include <linux/iopoll.h> 45a5356aefSYogesh Narayan Gaur #include <linux/jiffies.h> 46a5356aefSYogesh Narayan Gaur #include <linux/kernel.h> 47a5356aefSYogesh Narayan Gaur #include <linux/module.h> 48a5356aefSYogesh Narayan Gaur #include <linux/mutex.h> 49a5356aefSYogesh Narayan Gaur #include <linux/of.h> 50a5356aefSYogesh Narayan Gaur #include <linux/platform_device.h> 51a5356aefSYogesh Narayan Gaur #include <linux/pm_qos.h> 5282ce7d0eSKuldeep Singh #include <linux/regmap.h> 53a5356aefSYogesh Narayan Gaur #include <linux/sizes.h> 5482ce7d0eSKuldeep Singh #include <linux/sys_soc.h> 55a5356aefSYogesh Narayan Gaur 5682ce7d0eSKuldeep Singh #include <linux/mfd/syscon.h> 57a5356aefSYogesh Narayan Gaur #include <linux/spi/spi.h> 58a5356aefSYogesh Narayan Gaur #include <linux/spi/spi-mem.h> 59a5356aefSYogesh Narayan Gaur 60a5356aefSYogesh Narayan Gaur /* 61a5356aefSYogesh Narayan Gaur * The driver only uses one single LUT entry, that is updated on 62a5356aefSYogesh Narayan Gaur * each call of exec_op(). Index 0 is preset at boot with a basic 63a5356aefSYogesh Narayan Gaur * read operation, so let's use the last entry (31). 64a5356aefSYogesh Narayan Gaur */ 65a5356aefSYogesh Narayan Gaur #define SEQID_LUT 31 66a5356aefSYogesh Narayan Gaur 67a5356aefSYogesh Narayan Gaur /* Registers used by the driver */ 68a5356aefSYogesh Narayan Gaur #define FSPI_MCR0 0x00 69a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_AHB_TIMEOUT(x) ((x) << 24) 70a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_IP_TIMEOUT(x) ((x) << 16) 71a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_LEARN_EN BIT(15) 72a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_SCRFRUN_EN BIT(14) 73a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_OCTCOMB_EN BIT(13) 74a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_DOZE_EN BIT(12) 75a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_HSEN BIT(11) 76a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_SERCLKDIV BIT(8) 77a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_ATDF_EN BIT(7) 78a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_ARDF_EN BIT(6) 79a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_RXCLKSRC(x) ((x) << 4) 80a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_END_CFG(x) ((x) << 2) 81a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_MDIS BIT(1) 82a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_SWRST BIT(0) 83a5356aefSYogesh Narayan Gaur 84a5356aefSYogesh Narayan Gaur #define FSPI_MCR1 0x04 85a5356aefSYogesh Narayan Gaur #define FSPI_MCR1_SEQ_TIMEOUT(x) ((x) << 16) 86a5356aefSYogesh Narayan Gaur #define FSPI_MCR1_AHB_TIMEOUT(x) (x) 87a5356aefSYogesh Narayan Gaur 88a5356aefSYogesh Narayan Gaur #define FSPI_MCR2 0x08 89a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_IDLE_WAIT(x) ((x) << 24) 90a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_SAMEDEVICEEN BIT(15) 91a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_CLRLRPHS BIT(14) 92a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_ABRDATSZ BIT(8) 93a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_ABRLEARN BIT(7) 94a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_ABR_READ BIT(6) 95a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_ABRWRITE BIT(5) 96a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_ABRDUMMY BIT(4) 97a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_ABR_MODE BIT(3) 98a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_ABRCADDR BIT(2) 99a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_ABRRADDR BIT(1) 100a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_ABR_CMD BIT(0) 101a5356aefSYogesh Narayan Gaur 102a5356aefSYogesh Narayan Gaur #define FSPI_AHBCR 0x0c 103a5356aefSYogesh Narayan Gaur #define FSPI_AHBCR_RDADDROPT BIT(6) 104a5356aefSYogesh Narayan Gaur #define FSPI_AHBCR_PREF_EN BIT(5) 105a5356aefSYogesh Narayan Gaur #define FSPI_AHBCR_BUFF_EN BIT(4) 106a5356aefSYogesh Narayan Gaur #define FSPI_AHBCR_CACH_EN BIT(3) 107a5356aefSYogesh Narayan Gaur #define FSPI_AHBCR_CLRTXBUF BIT(2) 108a5356aefSYogesh Narayan Gaur #define FSPI_AHBCR_CLRRXBUF BIT(1) 109a5356aefSYogesh Narayan Gaur #define FSPI_AHBCR_PAR_EN BIT(0) 110a5356aefSYogesh Narayan Gaur 111a5356aefSYogesh Narayan Gaur #define FSPI_INTEN 0x10 112a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_SCLKSBWR BIT(9) 113a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_SCLKSBRD BIT(8) 114a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_DATALRNFL BIT(7) 115a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_IPTXWE BIT(6) 116a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_IPRXWA BIT(5) 117a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_AHBCMDERR BIT(4) 118a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_IPCMDERR BIT(3) 119a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_AHBCMDGE BIT(2) 120a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_IPCMDGE BIT(1) 121a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_IPCMDDONE BIT(0) 122a5356aefSYogesh Narayan Gaur 123a5356aefSYogesh Narayan Gaur #define FSPI_INTR 0x14 124a5356aefSYogesh Narayan Gaur #define FSPI_INTR_SCLKSBWR BIT(9) 125a5356aefSYogesh Narayan Gaur #define FSPI_INTR_SCLKSBRD BIT(8) 126a5356aefSYogesh Narayan Gaur #define FSPI_INTR_DATALRNFL BIT(7) 127a5356aefSYogesh Narayan Gaur #define FSPI_INTR_IPTXWE BIT(6) 128a5356aefSYogesh Narayan Gaur #define FSPI_INTR_IPRXWA BIT(5) 129a5356aefSYogesh Narayan Gaur #define FSPI_INTR_AHBCMDERR BIT(4) 130a5356aefSYogesh Narayan Gaur #define FSPI_INTR_IPCMDERR BIT(3) 131a5356aefSYogesh Narayan Gaur #define FSPI_INTR_AHBCMDGE BIT(2) 132a5356aefSYogesh Narayan Gaur #define FSPI_INTR_IPCMDGE BIT(1) 133a5356aefSYogesh Narayan Gaur #define FSPI_INTR_IPCMDDONE BIT(0) 134a5356aefSYogesh Narayan Gaur 135a5356aefSYogesh Narayan Gaur #define FSPI_LUTKEY 0x18 136a5356aefSYogesh Narayan Gaur #define FSPI_LUTKEY_VALUE 0x5AF05AF0 137a5356aefSYogesh Narayan Gaur 138a5356aefSYogesh Narayan Gaur #define FSPI_LCKCR 0x1C 139a5356aefSYogesh Narayan Gaur 140a5356aefSYogesh Narayan Gaur #define FSPI_LCKER_LOCK 0x1 141a5356aefSYogesh Narayan Gaur #define FSPI_LCKER_UNLOCK 0x2 142a5356aefSYogesh Narayan Gaur 143a5356aefSYogesh Narayan Gaur #define FSPI_BUFXCR_INVALID_MSTRID 0xE 144a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF0CR0 0x20 145a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF1CR0 0x24 146a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF2CR0 0x28 147a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF3CR0 0x2C 148a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF4CR0 0x30 149a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF5CR0 0x34 150a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF6CR0 0x38 151a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF7CR0 0x3C 152a5356aefSYogesh Narayan Gaur #define FSPI_AHBRXBUF0CR7_PREF BIT(31) 153a5356aefSYogesh Narayan Gaur 154a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF0CR1 0x40 155a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF1CR1 0x44 156a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF2CR1 0x48 157a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF3CR1 0x4C 158a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF4CR1 0x50 159a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF5CR1 0x54 160a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF6CR1 0x58 161a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF7CR1 0x5C 162a5356aefSYogesh Narayan Gaur 163a5356aefSYogesh Narayan Gaur #define FSPI_FLSHA1CR0 0x60 164a5356aefSYogesh Narayan Gaur #define FSPI_FLSHA2CR0 0x64 165a5356aefSYogesh Narayan Gaur #define FSPI_FLSHB1CR0 0x68 166a5356aefSYogesh Narayan Gaur #define FSPI_FLSHB2CR0 0x6C 167a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR0_SZ_KB 10 168a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR0_SZ(x) ((x) >> FSPI_FLSHXCR0_SZ_KB) 169a5356aefSYogesh Narayan Gaur 170a5356aefSYogesh Narayan Gaur #define FSPI_FLSHA1CR1 0x70 171a5356aefSYogesh Narayan Gaur #define FSPI_FLSHA2CR1 0x74 172a5356aefSYogesh Narayan Gaur #define FSPI_FLSHB1CR1 0x78 173a5356aefSYogesh Narayan Gaur #define FSPI_FLSHB2CR1 0x7C 174a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR1_CSINTR(x) ((x) << 16) 175a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR1_CAS(x) ((x) << 11) 176a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR1_WA BIT(10) 177a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR1_TCSH(x) ((x) << 5) 178a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR1_TCSS(x) (x) 179a5356aefSYogesh Narayan Gaur 180a5356aefSYogesh Narayan Gaur #define FSPI_FLSHA1CR2 0x80 181a5356aefSYogesh Narayan Gaur #define FSPI_FLSHA2CR2 0x84 182a5356aefSYogesh Narayan Gaur #define FSPI_FLSHB1CR2 0x88 183a5356aefSYogesh Narayan Gaur #define FSPI_FLSHB2CR2 0x8C 184a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR2_CLRINSP BIT(24) 185a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR2_AWRWAIT BIT(16) 186a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR2_AWRSEQN_SHIFT 13 187a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR2_AWRSEQI_SHIFT 8 188a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR2_ARDSEQN_SHIFT 5 189a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR2_ARDSEQI_SHIFT 0 190a5356aefSYogesh Narayan Gaur 191a5356aefSYogesh Narayan Gaur #define FSPI_IPCR0 0xA0 192a5356aefSYogesh Narayan Gaur 193a5356aefSYogesh Narayan Gaur #define FSPI_IPCR1 0xA4 194a5356aefSYogesh Narayan Gaur #define FSPI_IPCR1_IPAREN BIT(31) 195a5356aefSYogesh Narayan Gaur #define FSPI_IPCR1_SEQNUM_SHIFT 24 196a5356aefSYogesh Narayan Gaur #define FSPI_IPCR1_SEQID_SHIFT 16 197a5356aefSYogesh Narayan Gaur #define FSPI_IPCR1_IDATSZ(x) (x) 198a5356aefSYogesh Narayan Gaur 199a5356aefSYogesh Narayan Gaur #define FSPI_IPCMD 0xB0 200a5356aefSYogesh Narayan Gaur #define FSPI_IPCMD_TRG BIT(0) 201a5356aefSYogesh Narayan Gaur 202a5356aefSYogesh Narayan Gaur #define FSPI_DLPR 0xB4 203a5356aefSYogesh Narayan Gaur 204a5356aefSYogesh Narayan Gaur #define FSPI_IPRXFCR 0xB8 205a5356aefSYogesh Narayan Gaur #define FSPI_IPRXFCR_CLR BIT(0) 206a5356aefSYogesh Narayan Gaur #define FSPI_IPRXFCR_DMA_EN BIT(1) 207a5356aefSYogesh Narayan Gaur #define FSPI_IPRXFCR_WMRK(x) ((x) << 2) 208a5356aefSYogesh Narayan Gaur 209a5356aefSYogesh Narayan Gaur #define FSPI_IPTXFCR 0xBC 210a5356aefSYogesh Narayan Gaur #define FSPI_IPTXFCR_CLR BIT(0) 211a5356aefSYogesh Narayan Gaur #define FSPI_IPTXFCR_DMA_EN BIT(1) 212a5356aefSYogesh Narayan Gaur #define FSPI_IPTXFCR_WMRK(x) ((x) << 2) 213a5356aefSYogesh Narayan Gaur 214a5356aefSYogesh Narayan Gaur #define FSPI_DLLACR 0xC0 215a5356aefSYogesh Narayan Gaur #define FSPI_DLLACR_OVRDEN BIT(8) 21699d822b3SHaibo Chen #define FSPI_DLLACR_SLVDLY(x) ((x) << 3) 21799d822b3SHaibo Chen #define FSPI_DLLACR_DLLRESET BIT(1) 21899d822b3SHaibo Chen #define FSPI_DLLACR_DLLEN BIT(0) 219a5356aefSYogesh Narayan Gaur 220a5356aefSYogesh Narayan Gaur #define FSPI_DLLBCR 0xC4 221a5356aefSYogesh Narayan Gaur #define FSPI_DLLBCR_OVRDEN BIT(8) 22299d822b3SHaibo Chen #define FSPI_DLLBCR_SLVDLY(x) ((x) << 3) 22399d822b3SHaibo Chen #define FSPI_DLLBCR_DLLRESET BIT(1) 22499d822b3SHaibo Chen #define FSPI_DLLBCR_DLLEN BIT(0) 225a5356aefSYogesh Narayan Gaur 226a5356aefSYogesh Narayan Gaur #define FSPI_STS0 0xE0 227a5356aefSYogesh Narayan Gaur #define FSPI_STS0_DLPHB(x) ((x) << 8) 228a5356aefSYogesh Narayan Gaur #define FSPI_STS0_DLPHA(x) ((x) << 4) 229a5356aefSYogesh Narayan Gaur #define FSPI_STS0_CMD_SRC(x) ((x) << 2) 230a5356aefSYogesh Narayan Gaur #define FSPI_STS0_ARB_IDLE BIT(1) 231a5356aefSYogesh Narayan Gaur #define FSPI_STS0_SEQ_IDLE BIT(0) 232a5356aefSYogesh Narayan Gaur 233a5356aefSYogesh Narayan Gaur #define FSPI_STS1 0xE4 234a5356aefSYogesh Narayan Gaur #define FSPI_STS1_IP_ERRCD(x) ((x) << 24) 235a5356aefSYogesh Narayan Gaur #define FSPI_STS1_IP_ERRID(x) ((x) << 16) 236a5356aefSYogesh Narayan Gaur #define FSPI_STS1_AHB_ERRCD(x) ((x) << 8) 237a5356aefSYogesh Narayan Gaur #define FSPI_STS1_AHB_ERRID(x) (x) 238a5356aefSYogesh Narayan Gaur 23999d822b3SHaibo Chen #define FSPI_STS2 0xE8 24099d822b3SHaibo Chen #define FSPI_STS2_BREFLOCK BIT(17) 24199d822b3SHaibo Chen #define FSPI_STS2_BSLVLOCK BIT(16) 24299d822b3SHaibo Chen #define FSPI_STS2_AREFLOCK BIT(1) 24399d822b3SHaibo Chen #define FSPI_STS2_ASLVLOCK BIT(0) 24499d822b3SHaibo Chen #define FSPI_STS2_AB_LOCK (FSPI_STS2_BREFLOCK | \ 24599d822b3SHaibo Chen FSPI_STS2_BSLVLOCK | \ 24699d822b3SHaibo Chen FSPI_STS2_AREFLOCK | \ 24799d822b3SHaibo Chen FSPI_STS2_ASLVLOCK) 24899d822b3SHaibo Chen 249a5356aefSYogesh Narayan Gaur #define FSPI_AHBSPNST 0xEC 250a5356aefSYogesh Narayan Gaur #define FSPI_AHBSPNST_DATLFT(x) ((x) << 16) 251a5356aefSYogesh Narayan Gaur #define FSPI_AHBSPNST_BUFID(x) ((x) << 1) 252a5356aefSYogesh Narayan Gaur #define FSPI_AHBSPNST_ACTIVE BIT(0) 253a5356aefSYogesh Narayan Gaur 254a5356aefSYogesh Narayan Gaur #define FSPI_IPRXFSTS 0xF0 255a5356aefSYogesh Narayan Gaur #define FSPI_IPRXFSTS_RDCNTR(x) ((x) << 16) 256a5356aefSYogesh Narayan Gaur #define FSPI_IPRXFSTS_FILL(x) (x) 257a5356aefSYogesh Narayan Gaur 258a5356aefSYogesh Narayan Gaur #define FSPI_IPTXFSTS 0xF4 259a5356aefSYogesh Narayan Gaur #define FSPI_IPTXFSTS_WRCNTR(x) ((x) << 16) 260a5356aefSYogesh Narayan Gaur #define FSPI_IPTXFSTS_FILL(x) (x) 261a5356aefSYogesh Narayan Gaur 262a5356aefSYogesh Narayan Gaur #define FSPI_RFDR 0x100 263a5356aefSYogesh Narayan Gaur #define FSPI_TFDR 0x180 264a5356aefSYogesh Narayan Gaur 265a5356aefSYogesh Narayan Gaur #define FSPI_LUT_BASE 0x200 266a5356aefSYogesh Narayan Gaur #define FSPI_LUT_OFFSET (SEQID_LUT * 4 * 4) 267a5356aefSYogesh Narayan Gaur #define FSPI_LUT_REG(idx) \ 268a5356aefSYogesh Narayan Gaur (FSPI_LUT_BASE + FSPI_LUT_OFFSET + (idx) * 4) 269a5356aefSYogesh Narayan Gaur 270a5356aefSYogesh Narayan Gaur /* register map end */ 271a5356aefSYogesh Narayan Gaur 272a5356aefSYogesh Narayan Gaur /* Instruction set for the LUT register. */ 273a5356aefSYogesh Narayan Gaur #define LUT_STOP 0x00 274a5356aefSYogesh Narayan Gaur #define LUT_CMD 0x01 275a5356aefSYogesh Narayan Gaur #define LUT_ADDR 0x02 276a5356aefSYogesh Narayan Gaur #define LUT_CADDR_SDR 0x03 277a5356aefSYogesh Narayan Gaur #define LUT_MODE 0x04 278a5356aefSYogesh Narayan Gaur #define LUT_MODE2 0x05 279a5356aefSYogesh Narayan Gaur #define LUT_MODE4 0x06 280a5356aefSYogesh Narayan Gaur #define LUT_MODE8 0x07 281a5356aefSYogesh Narayan Gaur #define LUT_NXP_WRITE 0x08 282a5356aefSYogesh Narayan Gaur #define LUT_NXP_READ 0x09 283a5356aefSYogesh Narayan Gaur #define LUT_LEARN_SDR 0x0A 284a5356aefSYogesh Narayan Gaur #define LUT_DATSZ_SDR 0x0B 285a5356aefSYogesh Narayan Gaur #define LUT_DUMMY 0x0C 286a5356aefSYogesh Narayan Gaur #define LUT_DUMMY_RWDS_SDR 0x0D 287a5356aefSYogesh Narayan Gaur #define LUT_JMP_ON_CS 0x1F 288a5356aefSYogesh Narayan Gaur #define LUT_CMD_DDR 0x21 289a5356aefSYogesh Narayan Gaur #define LUT_ADDR_DDR 0x22 290a5356aefSYogesh Narayan Gaur #define LUT_CADDR_DDR 0x23 291a5356aefSYogesh Narayan Gaur #define LUT_MODE_DDR 0x24 292a5356aefSYogesh Narayan Gaur #define LUT_MODE2_DDR 0x25 293a5356aefSYogesh Narayan Gaur #define LUT_MODE4_DDR 0x26 294a5356aefSYogesh Narayan Gaur #define LUT_MODE8_DDR 0x27 295a5356aefSYogesh Narayan Gaur #define LUT_WRITE_DDR 0x28 296a5356aefSYogesh Narayan Gaur #define LUT_READ_DDR 0x29 297a5356aefSYogesh Narayan Gaur #define LUT_LEARN_DDR 0x2A 298a5356aefSYogesh Narayan Gaur #define LUT_DATSZ_DDR 0x2B 299a5356aefSYogesh Narayan Gaur #define LUT_DUMMY_DDR 0x2C 300a5356aefSYogesh Narayan Gaur #define LUT_DUMMY_RWDS_DDR 0x2D 301a5356aefSYogesh Narayan Gaur 302a5356aefSYogesh Narayan Gaur /* 303a5356aefSYogesh Narayan Gaur * Calculate number of required PAD bits for LUT register. 304a5356aefSYogesh Narayan Gaur * 305a5356aefSYogesh Narayan Gaur * The pad stands for the number of IO lines [0:7]. 306a5356aefSYogesh Narayan Gaur * For example, the octal read needs eight IO lines, 307a5356aefSYogesh Narayan Gaur * so you should use LUT_PAD(8). This macro 308a5356aefSYogesh Narayan Gaur * returns 3 i.e. use eight (2^3) IP lines for read. 309a5356aefSYogesh Narayan Gaur */ 310a5356aefSYogesh Narayan Gaur #define LUT_PAD(x) (fls(x) - 1) 311a5356aefSYogesh Narayan Gaur 312a5356aefSYogesh Narayan Gaur /* 313a5356aefSYogesh Narayan Gaur * Macro for constructing the LUT entries with the following 314a5356aefSYogesh Narayan Gaur * register layout: 315a5356aefSYogesh Narayan Gaur * 316a5356aefSYogesh Narayan Gaur * --------------------------------------------------- 317a5356aefSYogesh Narayan Gaur * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 | 318a5356aefSYogesh Narayan Gaur * --------------------------------------------------- 319a5356aefSYogesh Narayan Gaur */ 320a5356aefSYogesh Narayan Gaur #define PAD_SHIFT 8 321a5356aefSYogesh Narayan Gaur #define INSTR_SHIFT 10 322a5356aefSYogesh Narayan Gaur #define OPRND_SHIFT 16 323a5356aefSYogesh Narayan Gaur 324a5356aefSYogesh Narayan Gaur /* Macros for constructing the LUT register. */ 325a5356aefSYogesh Narayan Gaur #define LUT_DEF(idx, ins, pad, opr) \ 326a5356aefSYogesh Narayan Gaur ((((ins) << INSTR_SHIFT) | ((pad) << PAD_SHIFT) | \ 327a5356aefSYogesh Narayan Gaur (opr)) << (((idx) % 2) * OPRND_SHIFT)) 328a5356aefSYogesh Narayan Gaur 329a5356aefSYogesh Narayan Gaur #define POLL_TOUT 5000 330a5356aefSYogesh Narayan Gaur #define NXP_FSPI_MAX_CHIPSELECT 4 331d166a735SHan Xu #define NXP_FSPI_MIN_IOMAP SZ_4M 332a5356aefSYogesh Narayan Gaur 33382ce7d0eSKuldeep Singh #define DCFG_RCWSR1 0x100 33467a12ae5SMichael Walle #define SYS_PLL_RAT GENMASK(6, 2) 33582ce7d0eSKuldeep Singh 33631e92cbfSKuldeep Singh /* Access flash memory using IP bus only */ 33731e92cbfSKuldeep Singh #define FSPI_QUIRK_USE_IP_ONLY BIT(0) 33831e92cbfSKuldeep Singh 339a5356aefSYogesh Narayan Gaur struct nxp_fspi_devtype_data { 340a5356aefSYogesh Narayan Gaur unsigned int rxfifo; 341a5356aefSYogesh Narayan Gaur unsigned int txfifo; 342a5356aefSYogesh Narayan Gaur unsigned int ahb_buf_size; 343a5356aefSYogesh Narayan Gaur unsigned int quirks; 344a5356aefSYogesh Narayan Gaur bool little_endian; 345a5356aefSYogesh Narayan Gaur }; 346a5356aefSYogesh Narayan Gaur 34782ce7d0eSKuldeep Singh static struct nxp_fspi_devtype_data lx2160a_data = { 348a5356aefSYogesh Narayan Gaur .rxfifo = SZ_512, /* (64 * 64 bits) */ 349a5356aefSYogesh Narayan Gaur .txfifo = SZ_1K, /* (128 * 64 bits) */ 350a5356aefSYogesh Narayan Gaur .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ 351a5356aefSYogesh Narayan Gaur .quirks = 0, 352a5356aefSYogesh Narayan Gaur .little_endian = true, /* little-endian */ 353a5356aefSYogesh Narayan Gaur }; 354a5356aefSYogesh Narayan Gaur 35582ce7d0eSKuldeep Singh static struct nxp_fspi_devtype_data imx8mm_data = { 356941be8a7SHan Xu .rxfifo = SZ_512, /* (64 * 64 bits) */ 357941be8a7SHan Xu .txfifo = SZ_1K, /* (128 * 64 bits) */ 358941be8a7SHan Xu .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ 359941be8a7SHan Xu .quirks = 0, 360941be8a7SHan Xu .little_endian = true, /* little-endian */ 361941be8a7SHan Xu }; 362941be8a7SHan Xu 36382ce7d0eSKuldeep Singh static struct nxp_fspi_devtype_data imx8qxp_data = { 364941be8a7SHan Xu .rxfifo = SZ_512, /* (64 * 64 bits) */ 365941be8a7SHan Xu .txfifo = SZ_1K, /* (128 * 64 bits) */ 366941be8a7SHan Xu .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ 367941be8a7SHan Xu .quirks = 0, 368941be8a7SHan Xu .little_endian = true, /* little-endian */ 369941be8a7SHan Xu }; 370941be8a7SHan Xu 37182ce7d0eSKuldeep Singh static struct nxp_fspi_devtype_data imx8dxl_data = { 372c791e3c3SHan Xu .rxfifo = SZ_512, /* (64 * 64 bits) */ 373c791e3c3SHan Xu .txfifo = SZ_1K, /* (128 * 64 bits) */ 374c791e3c3SHan Xu .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ 375c791e3c3SHan Xu .quirks = FSPI_QUIRK_USE_IP_ONLY, 376c791e3c3SHan Xu .little_endian = true, /* little-endian */ 377c791e3c3SHan Xu }; 378c791e3c3SHan Xu 379a5356aefSYogesh Narayan Gaur struct nxp_fspi { 380a5356aefSYogesh Narayan Gaur void __iomem *iobase; 381a5356aefSYogesh Narayan Gaur void __iomem *ahb_addr; 382a5356aefSYogesh Narayan Gaur u32 memmap_phy; 383a5356aefSYogesh Narayan Gaur u32 memmap_phy_size; 384d166a735SHan Xu u32 memmap_start; 385d166a735SHan Xu u32 memmap_len; 386a5356aefSYogesh Narayan Gaur struct clk *clk, *clk_en; 387a5356aefSYogesh Narayan Gaur struct device *dev; 388a5356aefSYogesh Narayan Gaur struct completion c; 38982ce7d0eSKuldeep Singh struct nxp_fspi_devtype_data *devtype_data; 390a5356aefSYogesh Narayan Gaur struct mutex lock; 391a5356aefSYogesh Narayan Gaur struct pm_qos_request pm_qos_req; 392a5356aefSYogesh Narayan Gaur int selected; 393a5356aefSYogesh Narayan Gaur }; 394a5356aefSYogesh Narayan Gaur 39531e92cbfSKuldeep Singh static inline int needs_ip_only(struct nxp_fspi *f) 39631e92cbfSKuldeep Singh { 39731e92cbfSKuldeep Singh return f->devtype_data->quirks & FSPI_QUIRK_USE_IP_ONLY; 39831e92cbfSKuldeep Singh } 39931e92cbfSKuldeep Singh 400a5356aefSYogesh Narayan Gaur /* 401a5356aefSYogesh Narayan Gaur * R/W functions for big- or little-endian registers: 402a5356aefSYogesh Narayan Gaur * The FSPI controller's endianness is independent of 403a5356aefSYogesh Narayan Gaur * the CPU core's endianness. So far, although the CPU 404a5356aefSYogesh Narayan Gaur * core is little-endian the FSPI controller can use 405a5356aefSYogesh Narayan Gaur * big-endian or little-endian. 406a5356aefSYogesh Narayan Gaur */ 407a5356aefSYogesh Narayan Gaur static void fspi_writel(struct nxp_fspi *f, u32 val, void __iomem *addr) 408a5356aefSYogesh Narayan Gaur { 409a5356aefSYogesh Narayan Gaur if (f->devtype_data->little_endian) 410a5356aefSYogesh Narayan Gaur iowrite32(val, addr); 411a5356aefSYogesh Narayan Gaur else 412a5356aefSYogesh Narayan Gaur iowrite32be(val, addr); 413a5356aefSYogesh Narayan Gaur } 414a5356aefSYogesh Narayan Gaur 415a5356aefSYogesh Narayan Gaur static u32 fspi_readl(struct nxp_fspi *f, void __iomem *addr) 416a5356aefSYogesh Narayan Gaur { 417a5356aefSYogesh Narayan Gaur if (f->devtype_data->little_endian) 418a5356aefSYogesh Narayan Gaur return ioread32(addr); 419a5356aefSYogesh Narayan Gaur else 420a5356aefSYogesh Narayan Gaur return ioread32be(addr); 421a5356aefSYogesh Narayan Gaur } 422a5356aefSYogesh Narayan Gaur 423a5356aefSYogesh Narayan Gaur static irqreturn_t nxp_fspi_irq_handler(int irq, void *dev_id) 424a5356aefSYogesh Narayan Gaur { 425a5356aefSYogesh Narayan Gaur struct nxp_fspi *f = dev_id; 426a5356aefSYogesh Narayan Gaur u32 reg; 427a5356aefSYogesh Narayan Gaur 428a5356aefSYogesh Narayan Gaur /* clear interrupt */ 429a5356aefSYogesh Narayan Gaur reg = fspi_readl(f, f->iobase + FSPI_INTR); 430a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_INTR_IPCMDDONE, f->iobase + FSPI_INTR); 431a5356aefSYogesh Narayan Gaur 432a5356aefSYogesh Narayan Gaur if (reg & FSPI_INTR_IPCMDDONE) 433a5356aefSYogesh Narayan Gaur complete(&f->c); 434a5356aefSYogesh Narayan Gaur 435a5356aefSYogesh Narayan Gaur return IRQ_HANDLED; 436a5356aefSYogesh Narayan Gaur } 437a5356aefSYogesh Narayan Gaur 438a5356aefSYogesh Narayan Gaur static int nxp_fspi_check_buswidth(struct nxp_fspi *f, u8 width) 439a5356aefSYogesh Narayan Gaur { 440a5356aefSYogesh Narayan Gaur switch (width) { 441a5356aefSYogesh Narayan Gaur case 1: 442a5356aefSYogesh Narayan Gaur case 2: 443a5356aefSYogesh Narayan Gaur case 4: 444a5356aefSYogesh Narayan Gaur case 8: 445a5356aefSYogesh Narayan Gaur return 0; 446a5356aefSYogesh Narayan Gaur } 447a5356aefSYogesh Narayan Gaur 448a5356aefSYogesh Narayan Gaur return -ENOTSUPP; 449a5356aefSYogesh Narayan Gaur } 450a5356aefSYogesh Narayan Gaur 451a5356aefSYogesh Narayan Gaur static bool nxp_fspi_supports_op(struct spi_mem *mem, 452a5356aefSYogesh Narayan Gaur const struct spi_mem_op *op) 453a5356aefSYogesh Narayan Gaur { 454a5356aefSYogesh Narayan Gaur struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master); 455a5356aefSYogesh Narayan Gaur int ret; 456a5356aefSYogesh Narayan Gaur 457a5356aefSYogesh Narayan Gaur ret = nxp_fspi_check_buswidth(f, op->cmd.buswidth); 458a5356aefSYogesh Narayan Gaur 459a5356aefSYogesh Narayan Gaur if (op->addr.nbytes) 460a5356aefSYogesh Narayan Gaur ret |= nxp_fspi_check_buswidth(f, op->addr.buswidth); 461a5356aefSYogesh Narayan Gaur 462a5356aefSYogesh Narayan Gaur if (op->dummy.nbytes) 463a5356aefSYogesh Narayan Gaur ret |= nxp_fspi_check_buswidth(f, op->dummy.buswidth); 464a5356aefSYogesh Narayan Gaur 465a5356aefSYogesh Narayan Gaur if (op->data.nbytes) 466a5356aefSYogesh Narayan Gaur ret |= nxp_fspi_check_buswidth(f, op->data.buswidth); 467a5356aefSYogesh Narayan Gaur 468a5356aefSYogesh Narayan Gaur if (ret) 469a5356aefSYogesh Narayan Gaur return false; 470a5356aefSYogesh Narayan Gaur 471a5356aefSYogesh Narayan Gaur /* 472a5356aefSYogesh Narayan Gaur * The number of address bytes should be equal to or less than 4 bytes. 473a5356aefSYogesh Narayan Gaur */ 474a5356aefSYogesh Narayan Gaur if (op->addr.nbytes > 4) 475a5356aefSYogesh Narayan Gaur return false; 476a5356aefSYogesh Narayan Gaur 477a5356aefSYogesh Narayan Gaur /* 478a5356aefSYogesh Narayan Gaur * If requested address value is greater than controller assigned 479a5356aefSYogesh Narayan Gaur * memory mapped space, return error as it didn't fit in the range 480a5356aefSYogesh Narayan Gaur * of assigned address space. 481a5356aefSYogesh Narayan Gaur */ 482a5356aefSYogesh Narayan Gaur if (op->addr.val >= f->memmap_phy_size) 483a5356aefSYogesh Narayan Gaur return false; 484a5356aefSYogesh Narayan Gaur 485a5356aefSYogesh Narayan Gaur /* Max 64 dummy clock cycles supported */ 486a5356aefSYogesh Narayan Gaur if (op->dummy.buswidth && 487a5356aefSYogesh Narayan Gaur (op->dummy.nbytes * 8 / op->dummy.buswidth > 64)) 488a5356aefSYogesh Narayan Gaur return false; 489a5356aefSYogesh Narayan Gaur 490a5356aefSYogesh Narayan Gaur /* Max data length, check controller limits and alignment */ 491a5356aefSYogesh Narayan Gaur if (op->data.dir == SPI_MEM_DATA_IN && 492a5356aefSYogesh Narayan Gaur (op->data.nbytes > f->devtype_data->ahb_buf_size || 493a5356aefSYogesh Narayan Gaur (op->data.nbytes > f->devtype_data->rxfifo - 4 && 494a5356aefSYogesh Narayan Gaur !IS_ALIGNED(op->data.nbytes, 8)))) 495a5356aefSYogesh Narayan Gaur return false; 496a5356aefSYogesh Narayan Gaur 497a5356aefSYogesh Narayan Gaur if (op->data.dir == SPI_MEM_DATA_OUT && 498a5356aefSYogesh Narayan Gaur op->data.nbytes > f->devtype_data->txfifo) 499a5356aefSYogesh Narayan Gaur return false; 500a5356aefSYogesh Narayan Gaur 501007773e1SMichael Walle return spi_mem_default_supports_op(mem, op); 502a5356aefSYogesh Narayan Gaur } 503a5356aefSYogesh Narayan Gaur 504a5356aefSYogesh Narayan Gaur /* Instead of busy looping invoke readl_poll_timeout functionality. */ 505a5356aefSYogesh Narayan Gaur static int fspi_readl_poll_tout(struct nxp_fspi *f, void __iomem *base, 506a5356aefSYogesh Narayan Gaur u32 mask, u32 delay_us, 507a5356aefSYogesh Narayan Gaur u32 timeout_us, bool c) 508a5356aefSYogesh Narayan Gaur { 509a5356aefSYogesh Narayan Gaur u32 reg; 510a5356aefSYogesh Narayan Gaur 511a5356aefSYogesh Narayan Gaur if (!f->devtype_data->little_endian) 512a5356aefSYogesh Narayan Gaur mask = (u32)cpu_to_be32(mask); 513a5356aefSYogesh Narayan Gaur 514a5356aefSYogesh Narayan Gaur if (c) 515a5356aefSYogesh Narayan Gaur return readl_poll_timeout(base, reg, (reg & mask), 516a5356aefSYogesh Narayan Gaur delay_us, timeout_us); 517a5356aefSYogesh Narayan Gaur else 518a5356aefSYogesh Narayan Gaur return readl_poll_timeout(base, reg, !(reg & mask), 519a5356aefSYogesh Narayan Gaur delay_us, timeout_us); 520a5356aefSYogesh Narayan Gaur } 521a5356aefSYogesh Narayan Gaur 522a5356aefSYogesh Narayan Gaur /* 523a5356aefSYogesh Narayan Gaur * If the slave device content being changed by Write/Erase, need to 524a5356aefSYogesh Narayan Gaur * invalidate the AHB buffer. This can be achieved by doing the reset 525a5356aefSYogesh Narayan Gaur * of controller after setting MCR0[SWRESET] bit. 526a5356aefSYogesh Narayan Gaur */ 527a5356aefSYogesh Narayan Gaur static inline void nxp_fspi_invalid(struct nxp_fspi *f) 528a5356aefSYogesh Narayan Gaur { 529a5356aefSYogesh Narayan Gaur u32 reg; 530a5356aefSYogesh Narayan Gaur int ret; 531a5356aefSYogesh Narayan Gaur 532a5356aefSYogesh Narayan Gaur reg = fspi_readl(f, f->iobase + FSPI_MCR0); 533a5356aefSYogesh Narayan Gaur fspi_writel(f, reg | FSPI_MCR0_SWRST, f->iobase + FSPI_MCR0); 534a5356aefSYogesh Narayan Gaur 535a5356aefSYogesh Narayan Gaur /* w1c register, wait unit clear */ 536a5356aefSYogesh Narayan Gaur ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0, 537a5356aefSYogesh Narayan Gaur FSPI_MCR0_SWRST, 0, POLL_TOUT, false); 538a5356aefSYogesh Narayan Gaur WARN_ON(ret); 539a5356aefSYogesh Narayan Gaur } 540a5356aefSYogesh Narayan Gaur 541a5356aefSYogesh Narayan Gaur static void nxp_fspi_prepare_lut(struct nxp_fspi *f, 542a5356aefSYogesh Narayan Gaur const struct spi_mem_op *op) 543a5356aefSYogesh Narayan Gaur { 544a5356aefSYogesh Narayan Gaur void __iomem *base = f->iobase; 545a5356aefSYogesh Narayan Gaur u32 lutval[4] = {}; 546a5356aefSYogesh Narayan Gaur int lutidx = 1, i; 547a5356aefSYogesh Narayan Gaur 548a5356aefSYogesh Narayan Gaur /* cmd */ 549a5356aefSYogesh Narayan Gaur lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth), 550a5356aefSYogesh Narayan Gaur op->cmd.opcode); 551a5356aefSYogesh Narayan Gaur 552a5356aefSYogesh Narayan Gaur /* addr bytes */ 553a5356aefSYogesh Narayan Gaur if (op->addr.nbytes) { 554a5356aefSYogesh Narayan Gaur lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_ADDR, 555a5356aefSYogesh Narayan Gaur LUT_PAD(op->addr.buswidth), 556a5356aefSYogesh Narayan Gaur op->addr.nbytes * 8); 557a5356aefSYogesh Narayan Gaur lutidx++; 558a5356aefSYogesh Narayan Gaur } 559a5356aefSYogesh Narayan Gaur 560a5356aefSYogesh Narayan Gaur /* dummy bytes, if needed */ 561a5356aefSYogesh Narayan Gaur if (op->dummy.nbytes) { 562a5356aefSYogesh Narayan Gaur lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY, 563a5356aefSYogesh Narayan Gaur /* 564a5356aefSYogesh Narayan Gaur * Due to FlexSPI controller limitation number of PAD for dummy 565a5356aefSYogesh Narayan Gaur * buswidth needs to be programmed as equal to data buswidth. 566a5356aefSYogesh Narayan Gaur */ 567a5356aefSYogesh Narayan Gaur LUT_PAD(op->data.buswidth), 568a5356aefSYogesh Narayan Gaur op->dummy.nbytes * 8 / 569a5356aefSYogesh Narayan Gaur op->dummy.buswidth); 570a5356aefSYogesh Narayan Gaur lutidx++; 571a5356aefSYogesh Narayan Gaur } 572a5356aefSYogesh Narayan Gaur 573a5356aefSYogesh Narayan Gaur /* read/write data bytes */ 574a5356aefSYogesh Narayan Gaur if (op->data.nbytes) { 575a5356aefSYogesh Narayan Gaur lutval[lutidx / 2] |= LUT_DEF(lutidx, 576a5356aefSYogesh Narayan Gaur op->data.dir == SPI_MEM_DATA_IN ? 577a5356aefSYogesh Narayan Gaur LUT_NXP_READ : LUT_NXP_WRITE, 578a5356aefSYogesh Narayan Gaur LUT_PAD(op->data.buswidth), 579a5356aefSYogesh Narayan Gaur 0); 580a5356aefSYogesh Narayan Gaur lutidx++; 581a5356aefSYogesh Narayan Gaur } 582a5356aefSYogesh Narayan Gaur 583a5356aefSYogesh Narayan Gaur /* stop condition. */ 584a5356aefSYogesh Narayan Gaur lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0); 585a5356aefSYogesh Narayan Gaur 586a5356aefSYogesh Narayan Gaur /* unlock LUT */ 587a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY); 588a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_LCKER_UNLOCK, f->iobase + FSPI_LCKCR); 589a5356aefSYogesh Narayan Gaur 590a5356aefSYogesh Narayan Gaur /* fill LUT */ 591a5356aefSYogesh Narayan Gaur for (i = 0; i < ARRAY_SIZE(lutval); i++) 592a5356aefSYogesh Narayan Gaur fspi_writel(f, lutval[i], base + FSPI_LUT_REG(i)); 593a5356aefSYogesh Narayan Gaur 59431e92cbfSKuldeep Singh dev_dbg(f->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x], size: 0x%08x\n", 59531e92cbfSKuldeep Singh op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3], op->data.nbytes); 596a5356aefSYogesh Narayan Gaur 597a5356aefSYogesh Narayan Gaur /* lock LUT */ 598a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY); 599a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_LCKER_LOCK, f->iobase + FSPI_LCKCR); 600a5356aefSYogesh Narayan Gaur } 601a5356aefSYogesh Narayan Gaur 602a5356aefSYogesh Narayan Gaur static int nxp_fspi_clk_prep_enable(struct nxp_fspi *f) 603a5356aefSYogesh Narayan Gaur { 604a5356aefSYogesh Narayan Gaur int ret; 605a5356aefSYogesh Narayan Gaur 6064b9ef436SAndy Shevchenko if (is_acpi_node(dev_fwnode(f->dev))) 60755ab8487Skuldip dwivedi return 0; 60855ab8487Skuldip dwivedi 609a5356aefSYogesh Narayan Gaur ret = clk_prepare_enable(f->clk_en); 610a5356aefSYogesh Narayan Gaur if (ret) 611a5356aefSYogesh Narayan Gaur return ret; 612a5356aefSYogesh Narayan Gaur 613a5356aefSYogesh Narayan Gaur ret = clk_prepare_enable(f->clk); 614a5356aefSYogesh Narayan Gaur if (ret) { 615a5356aefSYogesh Narayan Gaur clk_disable_unprepare(f->clk_en); 616a5356aefSYogesh Narayan Gaur return ret; 617a5356aefSYogesh Narayan Gaur } 618a5356aefSYogesh Narayan Gaur 619a5356aefSYogesh Narayan Gaur return 0; 620a5356aefSYogesh Narayan Gaur } 621a5356aefSYogesh Narayan Gaur 62255ab8487Skuldip dwivedi static int nxp_fspi_clk_disable_unprep(struct nxp_fspi *f) 623a5356aefSYogesh Narayan Gaur { 6244b9ef436SAndy Shevchenko if (is_acpi_node(dev_fwnode(f->dev))) 62555ab8487Skuldip dwivedi return 0; 62655ab8487Skuldip dwivedi 627a5356aefSYogesh Narayan Gaur clk_disable_unprepare(f->clk); 628a5356aefSYogesh Narayan Gaur clk_disable_unprepare(f->clk_en); 62955ab8487Skuldip dwivedi 63055ab8487Skuldip dwivedi return 0; 631a5356aefSYogesh Narayan Gaur } 632a5356aefSYogesh Narayan Gaur 63399d822b3SHaibo Chen static void nxp_fspi_dll_calibration(struct nxp_fspi *f) 63499d822b3SHaibo Chen { 63599d822b3SHaibo Chen int ret; 63699d822b3SHaibo Chen 63799d822b3SHaibo Chen /* Reset the DLL, set the DLLRESET to 1 and then set to 0 */ 63899d822b3SHaibo Chen fspi_writel(f, FSPI_DLLACR_DLLRESET, f->iobase + FSPI_DLLACR); 63999d822b3SHaibo Chen fspi_writel(f, FSPI_DLLBCR_DLLRESET, f->iobase + FSPI_DLLBCR); 64099d822b3SHaibo Chen fspi_writel(f, 0, f->iobase + FSPI_DLLACR); 64199d822b3SHaibo Chen fspi_writel(f, 0, f->iobase + FSPI_DLLBCR); 64299d822b3SHaibo Chen 64399d822b3SHaibo Chen /* 64499d822b3SHaibo Chen * Enable the DLL calibration mode. 64599d822b3SHaibo Chen * The delay target for slave delay line is: 64699d822b3SHaibo Chen * ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock. 64799d822b3SHaibo Chen * When clock rate > 100MHz, recommend SLVDLYTARGET is 0xF, which 64899d822b3SHaibo Chen * means half of clock cycle of reference clock. 64999d822b3SHaibo Chen */ 65099d822b3SHaibo Chen fspi_writel(f, FSPI_DLLACR_DLLEN | FSPI_DLLACR_SLVDLY(0xF), 65199d822b3SHaibo Chen f->iobase + FSPI_DLLACR); 65299d822b3SHaibo Chen fspi_writel(f, FSPI_DLLBCR_DLLEN | FSPI_DLLBCR_SLVDLY(0xF), 65399d822b3SHaibo Chen f->iobase + FSPI_DLLBCR); 65499d822b3SHaibo Chen 65599d822b3SHaibo Chen /* Wait to get REF/SLV lock */ 65699d822b3SHaibo Chen ret = fspi_readl_poll_tout(f, f->iobase + FSPI_STS2, FSPI_STS2_AB_LOCK, 65799d822b3SHaibo Chen 0, POLL_TOUT, true); 65899d822b3SHaibo Chen if (ret) 65999d822b3SHaibo Chen dev_warn(f->dev, "DLL lock failed, please fix it!\n"); 66099d822b3SHaibo Chen } 66199d822b3SHaibo Chen 662a5356aefSYogesh Narayan Gaur /* 663a5356aefSYogesh Narayan Gaur * In FlexSPI controller, flash access is based on value of FSPI_FLSHXXCR0 664a5356aefSYogesh Narayan Gaur * register and start base address of the slave device. 665a5356aefSYogesh Narayan Gaur * 666a5356aefSYogesh Narayan Gaur * (Higher address) 667a5356aefSYogesh Narayan Gaur * -------- <-- FLSHB2CR0 668a5356aefSYogesh Narayan Gaur * | B2 | 669a5356aefSYogesh Narayan Gaur * | | 670a5356aefSYogesh Narayan Gaur * B2 start address --> -------- <-- FLSHB1CR0 671a5356aefSYogesh Narayan Gaur * | B1 | 672a5356aefSYogesh Narayan Gaur * | | 673a5356aefSYogesh Narayan Gaur * B1 start address --> -------- <-- FLSHA2CR0 674a5356aefSYogesh Narayan Gaur * | A2 | 675a5356aefSYogesh Narayan Gaur * | | 676a5356aefSYogesh Narayan Gaur * A2 start address --> -------- <-- FLSHA1CR0 677a5356aefSYogesh Narayan Gaur * | A1 | 678a5356aefSYogesh Narayan Gaur * | | 679a5356aefSYogesh Narayan Gaur * A1 start address --> -------- (Lower address) 680a5356aefSYogesh Narayan Gaur * 681a5356aefSYogesh Narayan Gaur * 682a5356aefSYogesh Narayan Gaur * Start base address defines the starting address range for given CS and 683a5356aefSYogesh Narayan Gaur * FSPI_FLSHXXCR0 defines the size of the slave device connected at given CS. 684a5356aefSYogesh Narayan Gaur * 685a5356aefSYogesh Narayan Gaur * But, different targets are having different combinations of number of CS, 686a5356aefSYogesh Narayan Gaur * some targets only have single CS or two CS covering controller's full 687a5356aefSYogesh Narayan Gaur * memory mapped space area. 688a5356aefSYogesh Narayan Gaur * Thus, implementation is being done as independent of the size and number 689a5356aefSYogesh Narayan Gaur * of the connected slave device. 690a5356aefSYogesh Narayan Gaur * Assign controller memory mapped space size as the size to the connected 691a5356aefSYogesh Narayan Gaur * slave device. 692a5356aefSYogesh Narayan Gaur * Mark FLSHxxCR0 as zero initially and then assign value only to the selected 693a5356aefSYogesh Narayan Gaur * chip-select Flash configuration register. 694a5356aefSYogesh Narayan Gaur * 695a5356aefSYogesh Narayan Gaur * For e.g. to access CS2 (B1), FLSHB1CR0 register would be equal to the 696a5356aefSYogesh Narayan Gaur * memory mapped size of the controller. 697a5356aefSYogesh Narayan Gaur * Value for rest of the CS FLSHxxCR0 register would be zero. 698a5356aefSYogesh Narayan Gaur * 699a5356aefSYogesh Narayan Gaur */ 700a5356aefSYogesh Narayan Gaur static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi) 701a5356aefSYogesh Narayan Gaur { 702a5356aefSYogesh Narayan Gaur unsigned long rate = spi->max_speed_hz; 703a5356aefSYogesh Narayan Gaur int ret; 704a5356aefSYogesh Narayan Gaur uint64_t size_kb; 705a5356aefSYogesh Narayan Gaur 706a5356aefSYogesh Narayan Gaur /* 707a5356aefSYogesh Narayan Gaur * Return, if previously selected slave device is same as current 708a5356aefSYogesh Narayan Gaur * requested slave device. 709a5356aefSYogesh Narayan Gaur */ 7109e264f3fSAmit Kumar Mahapatra via Alsa-devel if (f->selected == spi_get_chipselect(spi, 0)) 711a5356aefSYogesh Narayan Gaur return; 712a5356aefSYogesh Narayan Gaur 713a5356aefSYogesh Narayan Gaur /* Reset FLSHxxCR0 registers */ 714a5356aefSYogesh Narayan Gaur fspi_writel(f, 0, f->iobase + FSPI_FLSHA1CR0); 715a5356aefSYogesh Narayan Gaur fspi_writel(f, 0, f->iobase + FSPI_FLSHA2CR0); 716a5356aefSYogesh Narayan Gaur fspi_writel(f, 0, f->iobase + FSPI_FLSHB1CR0); 717a5356aefSYogesh Narayan Gaur fspi_writel(f, 0, f->iobase + FSPI_FLSHB2CR0); 718a5356aefSYogesh Narayan Gaur 719a5356aefSYogesh Narayan Gaur /* Assign controller memory mapped space as size, KBytes, of flash. */ 720a5356aefSYogesh Narayan Gaur size_kb = FSPI_FLSHXCR0_SZ(f->memmap_phy_size); 721a5356aefSYogesh Narayan Gaur 722a5356aefSYogesh Narayan Gaur fspi_writel(f, size_kb, f->iobase + FSPI_FLSHA1CR0 + 7239e264f3fSAmit Kumar Mahapatra via Alsa-devel 4 * spi_get_chipselect(spi, 0)); 724a5356aefSYogesh Narayan Gaur 7259e264f3fSAmit Kumar Mahapatra via Alsa-devel dev_dbg(f->dev, "Slave device [CS:%x] selected\n", spi_get_chipselect(spi, 0)); 726a5356aefSYogesh Narayan Gaur 727a5356aefSYogesh Narayan Gaur nxp_fspi_clk_disable_unprep(f); 728a5356aefSYogesh Narayan Gaur 729a5356aefSYogesh Narayan Gaur ret = clk_set_rate(f->clk, rate); 730a5356aefSYogesh Narayan Gaur if (ret) 731a5356aefSYogesh Narayan Gaur return; 732a5356aefSYogesh Narayan Gaur 733a5356aefSYogesh Narayan Gaur ret = nxp_fspi_clk_prep_enable(f); 734a5356aefSYogesh Narayan Gaur if (ret) 735a5356aefSYogesh Narayan Gaur return; 736a5356aefSYogesh Narayan Gaur 73799d822b3SHaibo Chen /* 73899d822b3SHaibo Chen * If clock rate > 100MHz, then switch from DLL override mode to 73999d822b3SHaibo Chen * DLL calibration mode. 74099d822b3SHaibo Chen */ 74199d822b3SHaibo Chen if (rate > 100000000) 74299d822b3SHaibo Chen nxp_fspi_dll_calibration(f); 74399d822b3SHaibo Chen 7449e264f3fSAmit Kumar Mahapatra via Alsa-devel f->selected = spi_get_chipselect(spi, 0); 745a5356aefSYogesh Narayan Gaur } 746a5356aefSYogesh Narayan Gaur 747d166a735SHan Xu static int nxp_fspi_read_ahb(struct nxp_fspi *f, const struct spi_mem_op *op) 748a5356aefSYogesh Narayan Gaur { 749d166a735SHan Xu u32 start = op->addr.val; 750a5356aefSYogesh Narayan Gaur u32 len = op->data.nbytes; 751a5356aefSYogesh Narayan Gaur 752d166a735SHan Xu /* if necessary, ioremap before AHB read */ 753d166a735SHan Xu if ((!f->ahb_addr) || start < f->memmap_start || 754d166a735SHan Xu start + len > f->memmap_start + f->memmap_len) { 755d166a735SHan Xu if (f->ahb_addr) 756d166a735SHan Xu iounmap(f->ahb_addr); 757d166a735SHan Xu 758d166a735SHan Xu f->memmap_start = start; 759d166a735SHan Xu f->memmap_len = len > NXP_FSPI_MIN_IOMAP ? 760d166a735SHan Xu len : NXP_FSPI_MIN_IOMAP; 761d166a735SHan Xu 762*dab501d3SHan Xu f->ahb_addr = ioremap(f->memmap_phy + f->memmap_start, 763d166a735SHan Xu f->memmap_len); 764d166a735SHan Xu 765d166a735SHan Xu if (!f->ahb_addr) { 766d166a735SHan Xu dev_err(f->dev, "failed to alloc memory\n"); 767d166a735SHan Xu return -ENOMEM; 768d166a735SHan Xu } 769d166a735SHan Xu } 770d166a735SHan Xu 771a5356aefSYogesh Narayan Gaur /* Read out the data directly from the AHB buffer. */ 772d166a735SHan Xu memcpy_fromio(op->data.buf.in, 773d166a735SHan Xu f->ahb_addr + start - f->memmap_start, len); 774d166a735SHan Xu 775d166a735SHan Xu return 0; 776a5356aefSYogesh Narayan Gaur } 777a5356aefSYogesh Narayan Gaur 778a5356aefSYogesh Narayan Gaur static void nxp_fspi_fill_txfifo(struct nxp_fspi *f, 779a5356aefSYogesh Narayan Gaur const struct spi_mem_op *op) 780a5356aefSYogesh Narayan Gaur { 781a5356aefSYogesh Narayan Gaur void __iomem *base = f->iobase; 782a5356aefSYogesh Narayan Gaur int i, ret; 783a5356aefSYogesh Narayan Gaur u8 *buf = (u8 *) op->data.buf.out; 784a5356aefSYogesh Narayan Gaur 785a5356aefSYogesh Narayan Gaur /* clear the TX FIFO. */ 786a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_IPTXFCR_CLR, base + FSPI_IPTXFCR); 787a5356aefSYogesh Narayan Gaur 788a5356aefSYogesh Narayan Gaur /* 789a5356aefSYogesh Narayan Gaur * Default value of water mark level is 8 bytes, hence in single 790a5356aefSYogesh Narayan Gaur * write request controller can write max 8 bytes of data. 791a5356aefSYogesh Narayan Gaur */ 792a5356aefSYogesh Narayan Gaur 793a5356aefSYogesh Narayan Gaur for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 8); i += 8) { 794a5356aefSYogesh Narayan Gaur /* Wait for TXFIFO empty */ 795a5356aefSYogesh Narayan Gaur ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, 796a5356aefSYogesh Narayan Gaur FSPI_INTR_IPTXWE, 0, 797a5356aefSYogesh Narayan Gaur POLL_TOUT, true); 798a5356aefSYogesh Narayan Gaur WARN_ON(ret); 799a5356aefSYogesh Narayan Gaur 800a5356aefSYogesh Narayan Gaur fspi_writel(f, *(u32 *) (buf + i), base + FSPI_TFDR); 801a5356aefSYogesh Narayan Gaur fspi_writel(f, *(u32 *) (buf + i + 4), base + FSPI_TFDR + 4); 802a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR); 803a5356aefSYogesh Narayan Gaur } 804a5356aefSYogesh Narayan Gaur 805a5356aefSYogesh Narayan Gaur if (i < op->data.nbytes) { 806a5356aefSYogesh Narayan Gaur u32 data = 0; 807a5356aefSYogesh Narayan Gaur int j; 808a5356aefSYogesh Narayan Gaur /* Wait for TXFIFO empty */ 809a5356aefSYogesh Narayan Gaur ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, 810a5356aefSYogesh Narayan Gaur FSPI_INTR_IPTXWE, 0, 811a5356aefSYogesh Narayan Gaur POLL_TOUT, true); 812a5356aefSYogesh Narayan Gaur WARN_ON(ret); 813a5356aefSYogesh Narayan Gaur 814a5356aefSYogesh Narayan Gaur for (j = 0; j < ALIGN(op->data.nbytes - i, 4); j += 4) { 815a5356aefSYogesh Narayan Gaur memcpy(&data, buf + i + j, 4); 816a5356aefSYogesh Narayan Gaur fspi_writel(f, data, base + FSPI_TFDR + j); 817a5356aefSYogesh Narayan Gaur } 818a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR); 819a5356aefSYogesh Narayan Gaur } 820a5356aefSYogesh Narayan Gaur } 821a5356aefSYogesh Narayan Gaur 822a5356aefSYogesh Narayan Gaur static void nxp_fspi_read_rxfifo(struct nxp_fspi *f, 823a5356aefSYogesh Narayan Gaur const struct spi_mem_op *op) 824a5356aefSYogesh Narayan Gaur { 825a5356aefSYogesh Narayan Gaur void __iomem *base = f->iobase; 826a5356aefSYogesh Narayan Gaur int i, ret; 827a5356aefSYogesh Narayan Gaur int len = op->data.nbytes; 828a5356aefSYogesh Narayan Gaur u8 *buf = (u8 *) op->data.buf.in; 829a5356aefSYogesh Narayan Gaur 830a5356aefSYogesh Narayan Gaur /* 831a5356aefSYogesh Narayan Gaur * Default value of water mark level is 8 bytes, hence in single 832a5356aefSYogesh Narayan Gaur * read request controller can read max 8 bytes of data. 833a5356aefSYogesh Narayan Gaur */ 834a5356aefSYogesh Narayan Gaur for (i = 0; i < ALIGN_DOWN(len, 8); i += 8) { 835a5356aefSYogesh Narayan Gaur /* Wait for RXFIFO available */ 836a5356aefSYogesh Narayan Gaur ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, 837a5356aefSYogesh Narayan Gaur FSPI_INTR_IPRXWA, 0, 838a5356aefSYogesh Narayan Gaur POLL_TOUT, true); 839a5356aefSYogesh Narayan Gaur WARN_ON(ret); 840a5356aefSYogesh Narayan Gaur 841a5356aefSYogesh Narayan Gaur *(u32 *)(buf + i) = fspi_readl(f, base + FSPI_RFDR); 842a5356aefSYogesh Narayan Gaur *(u32 *)(buf + i + 4) = fspi_readl(f, base + FSPI_RFDR + 4); 843a5356aefSYogesh Narayan Gaur /* move the FIFO pointer */ 844a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR); 845a5356aefSYogesh Narayan Gaur } 846a5356aefSYogesh Narayan Gaur 847a5356aefSYogesh Narayan Gaur if (i < len) { 848a5356aefSYogesh Narayan Gaur u32 tmp; 849a5356aefSYogesh Narayan Gaur int size, j; 850a5356aefSYogesh Narayan Gaur 851a5356aefSYogesh Narayan Gaur buf = op->data.buf.in + i; 852a5356aefSYogesh Narayan Gaur /* Wait for RXFIFO available */ 853a5356aefSYogesh Narayan Gaur ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, 854a5356aefSYogesh Narayan Gaur FSPI_INTR_IPRXWA, 0, 855a5356aefSYogesh Narayan Gaur POLL_TOUT, true); 856a5356aefSYogesh Narayan Gaur WARN_ON(ret); 857a5356aefSYogesh Narayan Gaur 858a5356aefSYogesh Narayan Gaur len = op->data.nbytes - i; 859a5356aefSYogesh Narayan Gaur for (j = 0; j < op->data.nbytes - i; j += 4) { 860a5356aefSYogesh Narayan Gaur tmp = fspi_readl(f, base + FSPI_RFDR + j); 861a5356aefSYogesh Narayan Gaur size = min(len, 4); 862a5356aefSYogesh Narayan Gaur memcpy(buf + j, &tmp, size); 863a5356aefSYogesh Narayan Gaur len -= size; 864a5356aefSYogesh Narayan Gaur } 865a5356aefSYogesh Narayan Gaur } 866a5356aefSYogesh Narayan Gaur 867a5356aefSYogesh Narayan Gaur /* invalid the RXFIFO */ 868a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_IPRXFCR_CLR, base + FSPI_IPRXFCR); 869a5356aefSYogesh Narayan Gaur /* move the FIFO pointer */ 870a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR); 871a5356aefSYogesh Narayan Gaur } 872a5356aefSYogesh Narayan Gaur 873a5356aefSYogesh Narayan Gaur static int nxp_fspi_do_op(struct nxp_fspi *f, const struct spi_mem_op *op) 874a5356aefSYogesh Narayan Gaur { 875a5356aefSYogesh Narayan Gaur void __iomem *base = f->iobase; 876a5356aefSYogesh Narayan Gaur int seqnum = 0; 877a5356aefSYogesh Narayan Gaur int err = 0; 878a5356aefSYogesh Narayan Gaur u32 reg; 879a5356aefSYogesh Narayan Gaur 880a5356aefSYogesh Narayan Gaur reg = fspi_readl(f, base + FSPI_IPRXFCR); 881a5356aefSYogesh Narayan Gaur /* invalid RXFIFO first */ 882a5356aefSYogesh Narayan Gaur reg &= ~FSPI_IPRXFCR_DMA_EN; 883a5356aefSYogesh Narayan Gaur reg = reg | FSPI_IPRXFCR_CLR; 884a5356aefSYogesh Narayan Gaur fspi_writel(f, reg, base + FSPI_IPRXFCR); 885a5356aefSYogesh Narayan Gaur 886a5356aefSYogesh Narayan Gaur init_completion(&f->c); 887a5356aefSYogesh Narayan Gaur 888a5356aefSYogesh Narayan Gaur fspi_writel(f, op->addr.val, base + FSPI_IPCR0); 889a5356aefSYogesh Narayan Gaur /* 890a5356aefSYogesh Narayan Gaur * Always start the sequence at the same index since we update 891a5356aefSYogesh Narayan Gaur * the LUT at each exec_op() call. And also specify the DATA 892a5356aefSYogesh Narayan Gaur * length, since it's has not been specified in the LUT. 893a5356aefSYogesh Narayan Gaur */ 894a5356aefSYogesh Narayan Gaur fspi_writel(f, op->data.nbytes | 895a5356aefSYogesh Narayan Gaur (SEQID_LUT << FSPI_IPCR1_SEQID_SHIFT) | 896a5356aefSYogesh Narayan Gaur (seqnum << FSPI_IPCR1_SEQNUM_SHIFT), 897a5356aefSYogesh Narayan Gaur base + FSPI_IPCR1); 898a5356aefSYogesh Narayan Gaur 899a5356aefSYogesh Narayan Gaur /* Trigger the LUT now. */ 900a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_IPCMD_TRG, base + FSPI_IPCMD); 901a5356aefSYogesh Narayan Gaur 902a5356aefSYogesh Narayan Gaur /* Wait for the interrupt. */ 903a5356aefSYogesh Narayan Gaur if (!wait_for_completion_timeout(&f->c, msecs_to_jiffies(1000))) 904a5356aefSYogesh Narayan Gaur err = -ETIMEDOUT; 905a5356aefSYogesh Narayan Gaur 906a5356aefSYogesh Narayan Gaur /* Invoke IP data read, if request is of data read. */ 907a5356aefSYogesh Narayan Gaur if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN) 908a5356aefSYogesh Narayan Gaur nxp_fspi_read_rxfifo(f, op); 909a5356aefSYogesh Narayan Gaur 910a5356aefSYogesh Narayan Gaur return err; 911a5356aefSYogesh Narayan Gaur } 912a5356aefSYogesh Narayan Gaur 913a5356aefSYogesh Narayan Gaur static int nxp_fspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) 914a5356aefSYogesh Narayan Gaur { 915a5356aefSYogesh Narayan Gaur struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master); 916a5356aefSYogesh Narayan Gaur int err = 0; 917a5356aefSYogesh Narayan Gaur 918a5356aefSYogesh Narayan Gaur mutex_lock(&f->lock); 919a5356aefSYogesh Narayan Gaur 920a5356aefSYogesh Narayan Gaur /* Wait for controller being ready. */ 921a5356aefSYogesh Narayan Gaur err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0, 922a5356aefSYogesh Narayan Gaur FSPI_STS0_ARB_IDLE, 1, POLL_TOUT, true); 923a5356aefSYogesh Narayan Gaur WARN_ON(err); 924a5356aefSYogesh Narayan Gaur 925a5356aefSYogesh Narayan Gaur nxp_fspi_select_mem(f, mem->spi); 926a5356aefSYogesh Narayan Gaur 927a5356aefSYogesh Narayan Gaur nxp_fspi_prepare_lut(f, op); 928a5356aefSYogesh Narayan Gaur /* 92931e92cbfSKuldeep Singh * If we have large chunks of data, we read them through the AHB bus by 93031e92cbfSKuldeep Singh * accessing the mapped memory. In all other cases we use IP commands 93131e92cbfSKuldeep Singh * to access the flash. Read via AHB bus may be corrupted due to 93231e92cbfSKuldeep Singh * existence of an errata and therefore discard AHB read in such cases. 933a5356aefSYogesh Narayan Gaur */ 934a5356aefSYogesh Narayan Gaur if (op->data.nbytes > (f->devtype_data->rxfifo - 4) && 93531e92cbfSKuldeep Singh op->data.dir == SPI_MEM_DATA_IN && 93631e92cbfSKuldeep Singh !needs_ip_only(f)) { 937d166a735SHan Xu err = nxp_fspi_read_ahb(f, op); 938a5356aefSYogesh Narayan Gaur } else { 939a5356aefSYogesh Narayan Gaur if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) 940a5356aefSYogesh Narayan Gaur nxp_fspi_fill_txfifo(f, op); 941a5356aefSYogesh Narayan Gaur 942a5356aefSYogesh Narayan Gaur err = nxp_fspi_do_op(f, op); 943a5356aefSYogesh Narayan Gaur } 944a5356aefSYogesh Narayan Gaur 945a5356aefSYogesh Narayan Gaur /* Invalidate the data in the AHB buffer. */ 946a5356aefSYogesh Narayan Gaur nxp_fspi_invalid(f); 947a5356aefSYogesh Narayan Gaur 948a5356aefSYogesh Narayan Gaur mutex_unlock(&f->lock); 949a5356aefSYogesh Narayan Gaur 950a5356aefSYogesh Narayan Gaur return err; 951a5356aefSYogesh Narayan Gaur } 952a5356aefSYogesh Narayan Gaur 953a5356aefSYogesh Narayan Gaur static int nxp_fspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) 954a5356aefSYogesh Narayan Gaur { 955a5356aefSYogesh Narayan Gaur struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master); 956a5356aefSYogesh Narayan Gaur 957a5356aefSYogesh Narayan Gaur if (op->data.dir == SPI_MEM_DATA_OUT) { 958a5356aefSYogesh Narayan Gaur if (op->data.nbytes > f->devtype_data->txfifo) 959a5356aefSYogesh Narayan Gaur op->data.nbytes = f->devtype_data->txfifo; 960a5356aefSYogesh Narayan Gaur } else { 961a5356aefSYogesh Narayan Gaur if (op->data.nbytes > f->devtype_data->ahb_buf_size) 962a5356aefSYogesh Narayan Gaur op->data.nbytes = f->devtype_data->ahb_buf_size; 963a5356aefSYogesh Narayan Gaur else if (op->data.nbytes > (f->devtype_data->rxfifo - 4)) 964a5356aefSYogesh Narayan Gaur op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8); 965a5356aefSYogesh Narayan Gaur } 966a5356aefSYogesh Narayan Gaur 96731e92cbfSKuldeep Singh /* Limit data bytes to RX FIFO in case of IP read only */ 96831e92cbfSKuldeep Singh if (op->data.dir == SPI_MEM_DATA_IN && 96931e92cbfSKuldeep Singh needs_ip_only(f) && 97031e92cbfSKuldeep Singh op->data.nbytes > f->devtype_data->rxfifo) 97131e92cbfSKuldeep Singh op->data.nbytes = f->devtype_data->rxfifo; 97231e92cbfSKuldeep Singh 973a5356aefSYogesh Narayan Gaur return 0; 974a5356aefSYogesh Narayan Gaur } 975a5356aefSYogesh Narayan Gaur 97682ce7d0eSKuldeep Singh static void erratum_err050568(struct nxp_fspi *f) 97782ce7d0eSKuldeep Singh { 9786c6c49f2SColin Ian King static const struct soc_device_attribute ls1028a_soc_attr[] = { 97982ce7d0eSKuldeep Singh { .family = "QorIQ LS1028A" }, 98082ce7d0eSKuldeep Singh { /* sentinel */ } 98182ce7d0eSKuldeep Singh }; 98282ce7d0eSKuldeep Singh struct regmap *map; 98367a12ae5SMichael Walle u32 val, sys_pll_ratio; 98482ce7d0eSKuldeep Singh int ret; 98582ce7d0eSKuldeep Singh 98682ce7d0eSKuldeep Singh /* Check for LS1028A family */ 98782ce7d0eSKuldeep Singh if (!soc_device_match(ls1028a_soc_attr)) { 98882ce7d0eSKuldeep Singh dev_dbg(f->dev, "Errata applicable only for LS1028A\n"); 98982ce7d0eSKuldeep Singh return; 99082ce7d0eSKuldeep Singh } 99182ce7d0eSKuldeep Singh 99282ce7d0eSKuldeep Singh map = syscon_regmap_lookup_by_compatible("fsl,ls1028a-dcfg"); 99382ce7d0eSKuldeep Singh if (IS_ERR(map)) { 99482ce7d0eSKuldeep Singh dev_err(f->dev, "No syscon regmap\n"); 99582ce7d0eSKuldeep Singh goto err; 99682ce7d0eSKuldeep Singh } 99782ce7d0eSKuldeep Singh 99882ce7d0eSKuldeep Singh ret = regmap_read(map, DCFG_RCWSR1, &val); 99982ce7d0eSKuldeep Singh if (ret < 0) 100082ce7d0eSKuldeep Singh goto err; 100182ce7d0eSKuldeep Singh 100267a12ae5SMichael Walle sys_pll_ratio = FIELD_GET(SYS_PLL_RAT, val); 100367a12ae5SMichael Walle dev_dbg(f->dev, "val: 0x%08x, sys_pll_ratio: %d\n", val, sys_pll_ratio); 100482ce7d0eSKuldeep Singh 100567a12ae5SMichael Walle /* Use IP bus only if platform clock is 300MHz */ 100667a12ae5SMichael Walle if (sys_pll_ratio == 3) 100782ce7d0eSKuldeep Singh f->devtype_data->quirks |= FSPI_QUIRK_USE_IP_ONLY; 100882ce7d0eSKuldeep Singh 100982ce7d0eSKuldeep Singh return; 101082ce7d0eSKuldeep Singh 101182ce7d0eSKuldeep Singh err: 101282ce7d0eSKuldeep Singh dev_err(f->dev, "Errata cannot be executed. Read via IP bus may not work\n"); 101382ce7d0eSKuldeep Singh } 101482ce7d0eSKuldeep Singh 1015a5356aefSYogesh Narayan Gaur static int nxp_fspi_default_setup(struct nxp_fspi *f) 1016a5356aefSYogesh Narayan Gaur { 1017a5356aefSYogesh Narayan Gaur void __iomem *base = f->iobase; 1018a5356aefSYogesh Narayan Gaur int ret, i; 1019a5356aefSYogesh Narayan Gaur u32 reg; 1020a5356aefSYogesh Narayan Gaur 1021a5356aefSYogesh Narayan Gaur /* disable and unprepare clock to avoid glitch pass to controller */ 1022a5356aefSYogesh Narayan Gaur nxp_fspi_clk_disable_unprep(f); 1023a5356aefSYogesh Narayan Gaur 1024a5356aefSYogesh Narayan Gaur /* the default frequency, we will change it later if necessary. */ 1025a5356aefSYogesh Narayan Gaur ret = clk_set_rate(f->clk, 20000000); 1026a5356aefSYogesh Narayan Gaur if (ret) 1027a5356aefSYogesh Narayan Gaur return ret; 1028a5356aefSYogesh Narayan Gaur 1029a5356aefSYogesh Narayan Gaur ret = nxp_fspi_clk_prep_enable(f); 1030a5356aefSYogesh Narayan Gaur if (ret) 1031a5356aefSYogesh Narayan Gaur return ret; 1032a5356aefSYogesh Narayan Gaur 103382ce7d0eSKuldeep Singh /* 103482ce7d0eSKuldeep Singh * ERR050568: Flash access by FlexSPI AHB command may not work with 103582ce7d0eSKuldeep Singh * platform frequency equal to 300 MHz on LS1028A. 103682ce7d0eSKuldeep Singh * LS1028A reuses LX2160A compatible entry. Make errata applicable for 103782ce7d0eSKuldeep Singh * Layerscape LS1028A platform. 103882ce7d0eSKuldeep Singh */ 103982ce7d0eSKuldeep Singh if (of_device_is_compatible(f->dev->of_node, "nxp,lx2160a-fspi")) 104082ce7d0eSKuldeep Singh erratum_err050568(f); 104182ce7d0eSKuldeep Singh 1042a5356aefSYogesh Narayan Gaur /* Reset the module */ 1043a5356aefSYogesh Narayan Gaur /* w1c register, wait unit clear */ 1044a5356aefSYogesh Narayan Gaur ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0, 1045a5356aefSYogesh Narayan Gaur FSPI_MCR0_SWRST, 0, POLL_TOUT, false); 1046a5356aefSYogesh Narayan Gaur WARN_ON(ret); 1047a5356aefSYogesh Narayan Gaur 1048a5356aefSYogesh Narayan Gaur /* Disable the module */ 1049a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_MCR0_MDIS, base + FSPI_MCR0); 1050a5356aefSYogesh Narayan Gaur 10511ab09f1dSHaibo Chen /* 10521ab09f1dSHaibo Chen * Config the DLL register to default value, enable the slave clock delay 10531ab09f1dSHaibo Chen * line delay cell override mode, and use 1 fixed delay cell in DLL delay 10541ab09f1dSHaibo Chen * chain, this is the suggested setting when clock rate < 100MHz. 10551ab09f1dSHaibo Chen */ 1056a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_DLLACR_OVRDEN, base + FSPI_DLLACR); 1057a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_DLLBCR_OVRDEN, base + FSPI_DLLBCR); 1058a5356aefSYogesh Narayan Gaur 1059a5356aefSYogesh Narayan Gaur /* enable module */ 1060b7461fa5SHan Xu fspi_writel(f, FSPI_MCR0_AHB_TIMEOUT(0xFF) | 1061b7461fa5SHan Xu FSPI_MCR0_IP_TIMEOUT(0xFF) | (u32) FSPI_MCR0_OCTCOMB_EN, 1062a5356aefSYogesh Narayan Gaur base + FSPI_MCR0); 1063a5356aefSYogesh Narayan Gaur 1064a5356aefSYogesh Narayan Gaur /* 1065a5356aefSYogesh Narayan Gaur * Disable same device enable bit and configure all slave devices 1066a5356aefSYogesh Narayan Gaur * independently. 1067a5356aefSYogesh Narayan Gaur */ 1068a5356aefSYogesh Narayan Gaur reg = fspi_readl(f, f->iobase + FSPI_MCR2); 1069a5356aefSYogesh Narayan Gaur reg = reg & ~(FSPI_MCR2_SAMEDEVICEEN); 1070a5356aefSYogesh Narayan Gaur fspi_writel(f, reg, base + FSPI_MCR2); 1071a5356aefSYogesh Narayan Gaur 1072a5356aefSYogesh Narayan Gaur /* AHB configuration for access buffer 0~7. */ 1073a5356aefSYogesh Narayan Gaur for (i = 0; i < 7; i++) 1074a5356aefSYogesh Narayan Gaur fspi_writel(f, 0, base + FSPI_AHBRX_BUF0CR0 + 4 * i); 1075a5356aefSYogesh Narayan Gaur 1076a5356aefSYogesh Narayan Gaur /* 1077a5356aefSYogesh Narayan Gaur * Set ADATSZ with the maximum AHB buffer size to improve the read 1078a5356aefSYogesh Narayan Gaur * performance. 1079a5356aefSYogesh Narayan Gaur */ 1080a5356aefSYogesh Narayan Gaur fspi_writel(f, (f->devtype_data->ahb_buf_size / 8 | 1081a5356aefSYogesh Narayan Gaur FSPI_AHBRXBUF0CR7_PREF), base + FSPI_AHBRX_BUF7CR0); 1082a5356aefSYogesh Narayan Gaur 1083a5356aefSYogesh Narayan Gaur /* prefetch and no start address alignment limitation */ 1084a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_AHBCR_PREF_EN | FSPI_AHBCR_RDADDROPT, 1085a5356aefSYogesh Narayan Gaur base + FSPI_AHBCR); 1086a5356aefSYogesh Narayan Gaur 108718495676SHan Xu /* Reset the FLSHxCR1 registers. */ 108818495676SHan Xu reg = FSPI_FLSHXCR1_TCSH(0x3) | FSPI_FLSHXCR1_TCSS(0x3); 108918495676SHan Xu fspi_writel(f, reg, base + FSPI_FLSHA1CR1); 109018495676SHan Xu fspi_writel(f, reg, base + FSPI_FLSHA2CR1); 109118495676SHan Xu fspi_writel(f, reg, base + FSPI_FLSHB1CR1); 109218495676SHan Xu fspi_writel(f, reg, base + FSPI_FLSHB2CR1); 109318495676SHan Xu 1094a5356aefSYogesh Narayan Gaur /* AHB Read - Set lut sequence ID for all CS. */ 1095a5356aefSYogesh Narayan Gaur fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA1CR2); 1096a5356aefSYogesh Narayan Gaur fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA2CR2); 1097a5356aefSYogesh Narayan Gaur fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB1CR2); 1098a5356aefSYogesh Narayan Gaur fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB2CR2); 1099a5356aefSYogesh Narayan Gaur 1100a5356aefSYogesh Narayan Gaur f->selected = -1; 1101a5356aefSYogesh Narayan Gaur 1102a5356aefSYogesh Narayan Gaur /* enable the interrupt */ 1103a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_INTEN_IPCMDDONE, base + FSPI_INTEN); 1104a5356aefSYogesh Narayan Gaur 1105a5356aefSYogesh Narayan Gaur return 0; 1106a5356aefSYogesh Narayan Gaur } 1107a5356aefSYogesh Narayan Gaur 1108a5356aefSYogesh Narayan Gaur static const char *nxp_fspi_get_name(struct spi_mem *mem) 1109a5356aefSYogesh Narayan Gaur { 1110a5356aefSYogesh Narayan Gaur struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master); 1111a5356aefSYogesh Narayan Gaur struct device *dev = &mem->spi->dev; 1112a5356aefSYogesh Narayan Gaur const char *name; 1113a5356aefSYogesh Narayan Gaur 1114a5356aefSYogesh Narayan Gaur // Set custom name derived from the platform_device of the controller. 1115a5356aefSYogesh Narayan Gaur if (of_get_available_child_count(f->dev->of_node) == 1) 1116a5356aefSYogesh Narayan Gaur return dev_name(f->dev); 1117a5356aefSYogesh Narayan Gaur 1118a5356aefSYogesh Narayan Gaur name = devm_kasprintf(dev, GFP_KERNEL, 1119a5356aefSYogesh Narayan Gaur "%s-%d", dev_name(f->dev), 11209e264f3fSAmit Kumar Mahapatra via Alsa-devel spi_get_chipselect(mem->spi, 0)); 1121a5356aefSYogesh Narayan Gaur 1122a5356aefSYogesh Narayan Gaur if (!name) { 1123a5356aefSYogesh Narayan Gaur dev_err(dev, "failed to get memory for custom flash name\n"); 1124a5356aefSYogesh Narayan Gaur return ERR_PTR(-ENOMEM); 1125a5356aefSYogesh Narayan Gaur } 1126a5356aefSYogesh Narayan Gaur 1127a5356aefSYogesh Narayan Gaur return name; 1128a5356aefSYogesh Narayan Gaur } 1129a5356aefSYogesh Narayan Gaur 1130a5356aefSYogesh Narayan Gaur static const struct spi_controller_mem_ops nxp_fspi_mem_ops = { 1131a5356aefSYogesh Narayan Gaur .adjust_op_size = nxp_fspi_adjust_op_size, 1132a5356aefSYogesh Narayan Gaur .supports_op = nxp_fspi_supports_op, 1133a5356aefSYogesh Narayan Gaur .exec_op = nxp_fspi_exec_op, 1134a5356aefSYogesh Narayan Gaur .get_name = nxp_fspi_get_name, 1135a5356aefSYogesh Narayan Gaur }; 1136a5356aefSYogesh Narayan Gaur 1137a5356aefSYogesh Narayan Gaur static int nxp_fspi_probe(struct platform_device *pdev) 1138a5356aefSYogesh Narayan Gaur { 1139a5356aefSYogesh Narayan Gaur struct spi_controller *ctlr; 1140a5356aefSYogesh Narayan Gaur struct device *dev = &pdev->dev; 1141a5356aefSYogesh Narayan Gaur struct device_node *np = dev->of_node; 1142a5356aefSYogesh Narayan Gaur struct resource *res; 1143a5356aefSYogesh Narayan Gaur struct nxp_fspi *f; 1144a5356aefSYogesh Narayan Gaur int ret; 114571d80563SRan Wang u32 reg; 1146a5356aefSYogesh Narayan Gaur 1147a5356aefSYogesh Narayan Gaur ctlr = spi_alloc_master(&pdev->dev, sizeof(*f)); 1148a5356aefSYogesh Narayan Gaur if (!ctlr) 1149a5356aefSYogesh Narayan Gaur return -ENOMEM; 1150a5356aefSYogesh Narayan Gaur 1151b3281794SYogesh Narayan Gaur ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL | 1152b3281794SYogesh Narayan Gaur SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL; 1153a5356aefSYogesh Narayan Gaur 1154a5356aefSYogesh Narayan Gaur f = spi_controller_get_devdata(ctlr); 1155a5356aefSYogesh Narayan Gaur f->dev = dev; 115682ce7d0eSKuldeep Singh f->devtype_data = (struct nxp_fspi_devtype_data *)device_get_match_data(dev); 1157a5356aefSYogesh Narayan Gaur if (!f->devtype_data) { 1158a5356aefSYogesh Narayan Gaur ret = -ENODEV; 1159a5356aefSYogesh Narayan Gaur goto err_put_ctrl; 1160a5356aefSYogesh Narayan Gaur } 1161a5356aefSYogesh Narayan Gaur 1162a5356aefSYogesh Narayan Gaur platform_set_drvdata(pdev, f); 1163a5356aefSYogesh Narayan Gaur 1164a5356aefSYogesh Narayan Gaur /* find the resources - configuration register address space */ 11654b9ef436SAndy Shevchenko if (is_acpi_node(dev_fwnode(f->dev))) 11668c8e947bSYangtao Li f->iobase = devm_platform_ioremap_resource(pdev, 0); 116755ab8487Skuldip dwivedi else 11688c8e947bSYangtao Li f->iobase = devm_platform_ioremap_resource_byname(pdev, "fspi_base"); 116955ab8487Skuldip dwivedi 1170a5356aefSYogesh Narayan Gaur if (IS_ERR(f->iobase)) { 1171a5356aefSYogesh Narayan Gaur ret = PTR_ERR(f->iobase); 1172a5356aefSYogesh Narayan Gaur goto err_put_ctrl; 1173a5356aefSYogesh Narayan Gaur } 1174a5356aefSYogesh Narayan Gaur 1175a5356aefSYogesh Narayan Gaur /* find the resources - controller memory mapped space */ 11764b9ef436SAndy Shevchenko if (is_acpi_node(dev_fwnode(f->dev))) 117755ab8487Skuldip dwivedi res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 117855ab8487Skuldip dwivedi else 117955ab8487Skuldip dwivedi res = platform_get_resource_byname(pdev, 118055ab8487Skuldip dwivedi IORESOURCE_MEM, "fspi_mmap"); 118155ab8487Skuldip dwivedi 11821a421ebaSDan Carpenter if (!res) { 11831a421ebaSDan Carpenter ret = -ENODEV; 1184a5356aefSYogesh Narayan Gaur goto err_put_ctrl; 1185a5356aefSYogesh Narayan Gaur } 1186a5356aefSYogesh Narayan Gaur 1187a5356aefSYogesh Narayan Gaur /* assign memory mapped starting address and mapped size. */ 1188a5356aefSYogesh Narayan Gaur f->memmap_phy = res->start; 1189a5356aefSYogesh Narayan Gaur f->memmap_phy_size = resource_size(res); 1190a5356aefSYogesh Narayan Gaur 1191a5356aefSYogesh Narayan Gaur /* find the clocks */ 119255ab8487Skuldip dwivedi if (dev_of_node(&pdev->dev)) { 1193a5356aefSYogesh Narayan Gaur f->clk_en = devm_clk_get(dev, "fspi_en"); 1194a5356aefSYogesh Narayan Gaur if (IS_ERR(f->clk_en)) { 1195a5356aefSYogesh Narayan Gaur ret = PTR_ERR(f->clk_en); 1196a5356aefSYogesh Narayan Gaur goto err_put_ctrl; 1197a5356aefSYogesh Narayan Gaur } 1198a5356aefSYogesh Narayan Gaur 1199a5356aefSYogesh Narayan Gaur f->clk = devm_clk_get(dev, "fspi"); 1200a5356aefSYogesh Narayan Gaur if (IS_ERR(f->clk)) { 1201a5356aefSYogesh Narayan Gaur ret = PTR_ERR(f->clk); 1202a5356aefSYogesh Narayan Gaur goto err_put_ctrl; 1203a5356aefSYogesh Narayan Gaur } 1204a5356aefSYogesh Narayan Gaur 1205a5356aefSYogesh Narayan Gaur ret = nxp_fspi_clk_prep_enable(f); 1206a5356aefSYogesh Narayan Gaur if (ret) { 1207a5356aefSYogesh Narayan Gaur dev_err(dev, "can not enable the clock\n"); 1208a5356aefSYogesh Narayan Gaur goto err_put_ctrl; 1209a5356aefSYogesh Narayan Gaur } 121055ab8487Skuldip dwivedi } 1211a5356aefSYogesh Narayan Gaur 1212f422316cSHaibo Chen /* Clear potential interrupts */ 1213f422316cSHaibo Chen reg = fspi_readl(f, f->iobase + FSPI_INTR); 1214f422316cSHaibo Chen if (reg) 1215f422316cSHaibo Chen fspi_writel(f, reg, f->iobase + FSPI_INTR); 1216f422316cSHaibo Chen 1217a5356aefSYogesh Narayan Gaur /* find the irq */ 1218a5356aefSYogesh Narayan Gaur ret = platform_get_irq(pdev, 0); 12196b8ac10eSStephen Boyd if (ret < 0) 1220a5356aefSYogesh Narayan Gaur goto err_disable_clk; 1221a5356aefSYogesh Narayan Gaur 1222a5356aefSYogesh Narayan Gaur ret = devm_request_irq(dev, ret, 1223a5356aefSYogesh Narayan Gaur nxp_fspi_irq_handler, 0, pdev->name, f); 1224a5356aefSYogesh Narayan Gaur if (ret) { 1225a5356aefSYogesh Narayan Gaur dev_err(dev, "failed to request irq: %d\n", ret); 1226a5356aefSYogesh Narayan Gaur goto err_disable_clk; 1227a5356aefSYogesh Narayan Gaur } 1228a5356aefSYogesh Narayan Gaur 1229a5356aefSYogesh Narayan Gaur mutex_init(&f->lock); 1230a5356aefSYogesh Narayan Gaur 1231a5356aefSYogesh Narayan Gaur ctlr->bus_num = -1; 1232a5356aefSYogesh Narayan Gaur ctlr->num_chipselect = NXP_FSPI_MAX_CHIPSELECT; 1233a5356aefSYogesh Narayan Gaur ctlr->mem_ops = &nxp_fspi_mem_ops; 1234a5356aefSYogesh Narayan Gaur 1235a5356aefSYogesh Narayan Gaur nxp_fspi_default_setup(f); 1236a5356aefSYogesh Narayan Gaur 1237a5356aefSYogesh Narayan Gaur ctlr->dev.of_node = np; 1238a5356aefSYogesh Narayan Gaur 123969c23dbfSChuhong Yuan ret = devm_spi_register_controller(&pdev->dev, ctlr); 1240a5356aefSYogesh Narayan Gaur if (ret) 1241a5356aefSYogesh Narayan Gaur goto err_destroy_mutex; 1242a5356aefSYogesh Narayan Gaur 1243a5356aefSYogesh Narayan Gaur return 0; 1244a5356aefSYogesh Narayan Gaur 1245a5356aefSYogesh Narayan Gaur err_destroy_mutex: 1246a5356aefSYogesh Narayan Gaur mutex_destroy(&f->lock); 1247a5356aefSYogesh Narayan Gaur 1248a5356aefSYogesh Narayan Gaur err_disable_clk: 1249a5356aefSYogesh Narayan Gaur nxp_fspi_clk_disable_unprep(f); 1250a5356aefSYogesh Narayan Gaur 1251a5356aefSYogesh Narayan Gaur err_put_ctrl: 1252a5356aefSYogesh Narayan Gaur spi_controller_put(ctlr); 1253a5356aefSYogesh Narayan Gaur 1254a5356aefSYogesh Narayan Gaur dev_err(dev, "NXP FSPI probe failed\n"); 1255a5356aefSYogesh Narayan Gaur return ret; 1256a5356aefSYogesh Narayan Gaur } 1257a5356aefSYogesh Narayan Gaur 12582dd82e32SUwe Kleine-König static void nxp_fspi_remove(struct platform_device *pdev) 1259a5356aefSYogesh Narayan Gaur { 1260a5356aefSYogesh Narayan Gaur struct nxp_fspi *f = platform_get_drvdata(pdev); 1261a5356aefSYogesh Narayan Gaur 1262a5356aefSYogesh Narayan Gaur /* disable the hardware */ 1263a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_MCR0_MDIS, f->iobase + FSPI_MCR0); 1264a5356aefSYogesh Narayan Gaur 1265a5356aefSYogesh Narayan Gaur nxp_fspi_clk_disable_unprep(f); 1266a5356aefSYogesh Narayan Gaur 1267a5356aefSYogesh Narayan Gaur mutex_destroy(&f->lock); 1268a5356aefSYogesh Narayan Gaur 1269d166a735SHan Xu if (f->ahb_addr) 1270d166a735SHan Xu iounmap(f->ahb_addr); 1271a5356aefSYogesh Narayan Gaur } 1272a5356aefSYogesh Narayan Gaur 1273a5356aefSYogesh Narayan Gaur static int nxp_fspi_suspend(struct device *dev) 1274a5356aefSYogesh Narayan Gaur { 1275a5356aefSYogesh Narayan Gaur return 0; 1276a5356aefSYogesh Narayan Gaur } 1277a5356aefSYogesh Narayan Gaur 1278a5356aefSYogesh Narayan Gaur static int nxp_fspi_resume(struct device *dev) 1279a5356aefSYogesh Narayan Gaur { 1280a5356aefSYogesh Narayan Gaur struct nxp_fspi *f = dev_get_drvdata(dev); 1281a5356aefSYogesh Narayan Gaur 1282a5356aefSYogesh Narayan Gaur nxp_fspi_default_setup(f); 1283a5356aefSYogesh Narayan Gaur 1284a5356aefSYogesh Narayan Gaur return 0; 1285a5356aefSYogesh Narayan Gaur } 1286a5356aefSYogesh Narayan Gaur 1287a5356aefSYogesh Narayan Gaur static const struct of_device_id nxp_fspi_dt_ids[] = { 1288a5356aefSYogesh Narayan Gaur { .compatible = "nxp,lx2160a-fspi", .data = (void *)&lx2160a_data, }, 1289941be8a7SHan Xu { .compatible = "nxp,imx8mm-fspi", .data = (void *)&imx8mm_data, }, 12900467a973SHeiko Schocher { .compatible = "nxp,imx8mp-fspi", .data = (void *)&imx8mm_data, }, 1291941be8a7SHan Xu { .compatible = "nxp,imx8qxp-fspi", .data = (void *)&imx8qxp_data, }, 1292c791e3c3SHan Xu { .compatible = "nxp,imx8dxl-fspi", .data = (void *)&imx8dxl_data, }, 1293a5356aefSYogesh Narayan Gaur { /* sentinel */ } 1294a5356aefSYogesh Narayan Gaur }; 1295a5356aefSYogesh Narayan Gaur MODULE_DEVICE_TABLE(of, nxp_fspi_dt_ids); 1296a5356aefSYogesh Narayan Gaur 129755ab8487Skuldip dwivedi #ifdef CONFIG_ACPI 129855ab8487Skuldip dwivedi static const struct acpi_device_id nxp_fspi_acpi_ids[] = { 129955ab8487Skuldip dwivedi { "NXP0009", .driver_data = (kernel_ulong_t)&lx2160a_data, }, 130055ab8487Skuldip dwivedi {} 130155ab8487Skuldip dwivedi }; 130255ab8487Skuldip dwivedi MODULE_DEVICE_TABLE(acpi, nxp_fspi_acpi_ids); 130355ab8487Skuldip dwivedi #endif 130455ab8487Skuldip dwivedi 1305a5356aefSYogesh Narayan Gaur static const struct dev_pm_ops nxp_fspi_pm_ops = { 1306a5356aefSYogesh Narayan Gaur .suspend = nxp_fspi_suspend, 1307a5356aefSYogesh Narayan Gaur .resume = nxp_fspi_resume, 1308a5356aefSYogesh Narayan Gaur }; 1309a5356aefSYogesh Narayan Gaur 1310a5356aefSYogesh Narayan Gaur static struct platform_driver nxp_fspi_driver = { 1311a5356aefSYogesh Narayan Gaur .driver = { 1312a5356aefSYogesh Narayan Gaur .name = "nxp-fspi", 1313a5356aefSYogesh Narayan Gaur .of_match_table = nxp_fspi_dt_ids, 131455ab8487Skuldip dwivedi .acpi_match_table = ACPI_PTR(nxp_fspi_acpi_ids), 1315a5356aefSYogesh Narayan Gaur .pm = &nxp_fspi_pm_ops, 1316a5356aefSYogesh Narayan Gaur }, 1317a5356aefSYogesh Narayan Gaur .probe = nxp_fspi_probe, 13182dd82e32SUwe Kleine-König .remove_new = nxp_fspi_remove, 1319a5356aefSYogesh Narayan Gaur }; 1320a5356aefSYogesh Narayan Gaur module_platform_driver(nxp_fspi_driver); 1321a5356aefSYogesh Narayan Gaur 1322a5356aefSYogesh Narayan Gaur MODULE_DESCRIPTION("NXP FSPI Controller Driver"); 1323a5356aefSYogesh Narayan Gaur MODULE_AUTHOR("NXP Semiconductor"); 1324a5356aefSYogesh Narayan Gaur MODULE_AUTHOR("Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>"); 1325ce6f0697SYogesh Narayan Gaur MODULE_AUTHOR("Boris Brezillon <bbrezillon@kernel.org>"); 1326a5356aefSYogesh Narayan Gaur MODULE_AUTHOR("Frieder Schrempf <frieder.schrempf@kontron.de>"); 1327ce6f0697SYogesh Narayan Gaur MODULE_LICENSE("GPL v2"); 1328