1a5356aefSYogesh Narayan Gaur // SPDX-License-Identifier: GPL-2.0+ 2a5356aefSYogesh Narayan Gaur 3a5356aefSYogesh Narayan Gaur /* 4a5356aefSYogesh Narayan Gaur * NXP FlexSPI(FSPI) controller driver. 5a5356aefSYogesh Narayan Gaur * 6a5356aefSYogesh Narayan Gaur * Copyright 2019 NXP. 7a5356aefSYogesh Narayan Gaur * 8a5356aefSYogesh Narayan Gaur * FlexSPI is a flexsible SPI host controller which supports two SPI 9a5356aefSYogesh Narayan Gaur * channels and up to 4 external devices. Each channel supports 10a5356aefSYogesh Narayan Gaur * Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional 11a5356aefSYogesh Narayan Gaur * data lines). 12a5356aefSYogesh Narayan Gaur * 13a5356aefSYogesh Narayan Gaur * FlexSPI controller is driven by the LUT(Look-up Table) registers 14a5356aefSYogesh Narayan Gaur * LUT registers are a look-up-table for sequences of instructions. 15a5356aefSYogesh Narayan Gaur * A valid sequence consists of four LUT registers. 16a5356aefSYogesh Narayan Gaur * Maximum 32 LUT sequences can be programmed simultaneously. 17a5356aefSYogesh Narayan Gaur * 18a5356aefSYogesh Narayan Gaur * LUTs are being created at run-time based on the commands passed 19a5356aefSYogesh Narayan Gaur * from the spi-mem framework, thus using single LUT index. 20a5356aefSYogesh Narayan Gaur * 21a5356aefSYogesh Narayan Gaur * Software triggered Flash read/write access by IP Bus. 22a5356aefSYogesh Narayan Gaur * 23a5356aefSYogesh Narayan Gaur * Memory mapped read access by AHB Bus. 24a5356aefSYogesh Narayan Gaur * 25a5356aefSYogesh Narayan Gaur * Based on SPI MEM interface and spi-fsl-qspi.c driver. 26a5356aefSYogesh Narayan Gaur * 27a5356aefSYogesh Narayan Gaur * Author: 28a5356aefSYogesh Narayan Gaur * Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com> 29ce6f0697SYogesh Narayan Gaur * Boris Brezillon <bbrezillon@kernel.org> 30a5356aefSYogesh Narayan Gaur * Frieder Schrempf <frieder.schrempf@kontron.de> 31a5356aefSYogesh Narayan Gaur */ 32a5356aefSYogesh Narayan Gaur 33a5356aefSYogesh Narayan Gaur #include <linux/bitops.h> 34a5356aefSYogesh Narayan Gaur #include <linux/clk.h> 35a5356aefSYogesh Narayan Gaur #include <linux/completion.h> 36a5356aefSYogesh Narayan Gaur #include <linux/delay.h> 37a5356aefSYogesh Narayan Gaur #include <linux/err.h> 38a5356aefSYogesh Narayan Gaur #include <linux/errno.h> 39a5356aefSYogesh Narayan Gaur #include <linux/interrupt.h> 40a5356aefSYogesh Narayan Gaur #include <linux/io.h> 41a5356aefSYogesh Narayan Gaur #include <linux/iopoll.h> 42a5356aefSYogesh Narayan Gaur #include <linux/jiffies.h> 43a5356aefSYogesh Narayan Gaur #include <linux/kernel.h> 44a5356aefSYogesh Narayan Gaur #include <linux/module.h> 45a5356aefSYogesh Narayan Gaur #include <linux/mutex.h> 46a5356aefSYogesh Narayan Gaur #include <linux/of.h> 47a5356aefSYogesh Narayan Gaur #include <linux/of_device.h> 48a5356aefSYogesh Narayan Gaur #include <linux/platform_device.h> 49a5356aefSYogesh Narayan Gaur #include <linux/pm_qos.h> 50a5356aefSYogesh Narayan Gaur #include <linux/sizes.h> 51a5356aefSYogesh Narayan Gaur 52a5356aefSYogesh Narayan Gaur #include <linux/spi/spi.h> 53a5356aefSYogesh Narayan Gaur #include <linux/spi/spi-mem.h> 54a5356aefSYogesh Narayan Gaur 55a5356aefSYogesh Narayan Gaur /* 56a5356aefSYogesh Narayan Gaur * The driver only uses one single LUT entry, that is updated on 57a5356aefSYogesh Narayan Gaur * each call of exec_op(). Index 0 is preset at boot with a basic 58a5356aefSYogesh Narayan Gaur * read operation, so let's use the last entry (31). 59a5356aefSYogesh Narayan Gaur */ 60a5356aefSYogesh Narayan Gaur #define SEQID_LUT 31 61a5356aefSYogesh Narayan Gaur 62a5356aefSYogesh Narayan Gaur /* Registers used by the driver */ 63a5356aefSYogesh Narayan Gaur #define FSPI_MCR0 0x00 64a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_AHB_TIMEOUT(x) ((x) << 24) 65a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_IP_TIMEOUT(x) ((x) << 16) 66a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_LEARN_EN BIT(15) 67a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_SCRFRUN_EN BIT(14) 68a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_OCTCOMB_EN BIT(13) 69a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_DOZE_EN BIT(12) 70a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_HSEN BIT(11) 71a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_SERCLKDIV BIT(8) 72a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_ATDF_EN BIT(7) 73a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_ARDF_EN BIT(6) 74a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_RXCLKSRC(x) ((x) << 4) 75a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_END_CFG(x) ((x) << 2) 76a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_MDIS BIT(1) 77a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_SWRST BIT(0) 78a5356aefSYogesh Narayan Gaur 79a5356aefSYogesh Narayan Gaur #define FSPI_MCR1 0x04 80a5356aefSYogesh Narayan Gaur #define FSPI_MCR1_SEQ_TIMEOUT(x) ((x) << 16) 81a5356aefSYogesh Narayan Gaur #define FSPI_MCR1_AHB_TIMEOUT(x) (x) 82a5356aefSYogesh Narayan Gaur 83a5356aefSYogesh Narayan Gaur #define FSPI_MCR2 0x08 84a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_IDLE_WAIT(x) ((x) << 24) 85a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_SAMEDEVICEEN BIT(15) 86a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_CLRLRPHS BIT(14) 87a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_ABRDATSZ BIT(8) 88a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_ABRLEARN BIT(7) 89a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_ABR_READ BIT(6) 90a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_ABRWRITE BIT(5) 91a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_ABRDUMMY BIT(4) 92a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_ABR_MODE BIT(3) 93a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_ABRCADDR BIT(2) 94a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_ABRRADDR BIT(1) 95a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_ABR_CMD BIT(0) 96a5356aefSYogesh Narayan Gaur 97a5356aefSYogesh Narayan Gaur #define FSPI_AHBCR 0x0c 98a5356aefSYogesh Narayan Gaur #define FSPI_AHBCR_RDADDROPT BIT(6) 99a5356aefSYogesh Narayan Gaur #define FSPI_AHBCR_PREF_EN BIT(5) 100a5356aefSYogesh Narayan Gaur #define FSPI_AHBCR_BUFF_EN BIT(4) 101a5356aefSYogesh Narayan Gaur #define FSPI_AHBCR_CACH_EN BIT(3) 102a5356aefSYogesh Narayan Gaur #define FSPI_AHBCR_CLRTXBUF BIT(2) 103a5356aefSYogesh Narayan Gaur #define FSPI_AHBCR_CLRRXBUF BIT(1) 104a5356aefSYogesh Narayan Gaur #define FSPI_AHBCR_PAR_EN BIT(0) 105a5356aefSYogesh Narayan Gaur 106a5356aefSYogesh Narayan Gaur #define FSPI_INTEN 0x10 107a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_SCLKSBWR BIT(9) 108a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_SCLKSBRD BIT(8) 109a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_DATALRNFL BIT(7) 110a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_IPTXWE BIT(6) 111a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_IPRXWA BIT(5) 112a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_AHBCMDERR BIT(4) 113a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_IPCMDERR BIT(3) 114a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_AHBCMDGE BIT(2) 115a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_IPCMDGE BIT(1) 116a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_IPCMDDONE BIT(0) 117a5356aefSYogesh Narayan Gaur 118a5356aefSYogesh Narayan Gaur #define FSPI_INTR 0x14 119a5356aefSYogesh Narayan Gaur #define FSPI_INTR_SCLKSBWR BIT(9) 120a5356aefSYogesh Narayan Gaur #define FSPI_INTR_SCLKSBRD BIT(8) 121a5356aefSYogesh Narayan Gaur #define FSPI_INTR_DATALRNFL BIT(7) 122a5356aefSYogesh Narayan Gaur #define FSPI_INTR_IPTXWE BIT(6) 123a5356aefSYogesh Narayan Gaur #define FSPI_INTR_IPRXWA BIT(5) 124a5356aefSYogesh Narayan Gaur #define FSPI_INTR_AHBCMDERR BIT(4) 125a5356aefSYogesh Narayan Gaur #define FSPI_INTR_IPCMDERR BIT(3) 126a5356aefSYogesh Narayan Gaur #define FSPI_INTR_AHBCMDGE BIT(2) 127a5356aefSYogesh Narayan Gaur #define FSPI_INTR_IPCMDGE BIT(1) 128a5356aefSYogesh Narayan Gaur #define FSPI_INTR_IPCMDDONE BIT(0) 129a5356aefSYogesh Narayan Gaur 130a5356aefSYogesh Narayan Gaur #define FSPI_LUTKEY 0x18 131a5356aefSYogesh Narayan Gaur #define FSPI_LUTKEY_VALUE 0x5AF05AF0 132a5356aefSYogesh Narayan Gaur 133a5356aefSYogesh Narayan Gaur #define FSPI_LCKCR 0x1C 134a5356aefSYogesh Narayan Gaur 135a5356aefSYogesh Narayan Gaur #define FSPI_LCKER_LOCK 0x1 136a5356aefSYogesh Narayan Gaur #define FSPI_LCKER_UNLOCK 0x2 137a5356aefSYogesh Narayan Gaur 138a5356aefSYogesh Narayan Gaur #define FSPI_BUFXCR_INVALID_MSTRID 0xE 139a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF0CR0 0x20 140a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF1CR0 0x24 141a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF2CR0 0x28 142a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF3CR0 0x2C 143a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF4CR0 0x30 144a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF5CR0 0x34 145a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF6CR0 0x38 146a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF7CR0 0x3C 147a5356aefSYogesh Narayan Gaur #define FSPI_AHBRXBUF0CR7_PREF BIT(31) 148a5356aefSYogesh Narayan Gaur 149a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF0CR1 0x40 150a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF1CR1 0x44 151a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF2CR1 0x48 152a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF3CR1 0x4C 153a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF4CR1 0x50 154a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF5CR1 0x54 155a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF6CR1 0x58 156a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF7CR1 0x5C 157a5356aefSYogesh Narayan Gaur 158a5356aefSYogesh Narayan Gaur #define FSPI_FLSHA1CR0 0x60 159a5356aefSYogesh Narayan Gaur #define FSPI_FLSHA2CR0 0x64 160a5356aefSYogesh Narayan Gaur #define FSPI_FLSHB1CR0 0x68 161a5356aefSYogesh Narayan Gaur #define FSPI_FLSHB2CR0 0x6C 162a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR0_SZ_KB 10 163a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR0_SZ(x) ((x) >> FSPI_FLSHXCR0_SZ_KB) 164a5356aefSYogesh Narayan Gaur 165a5356aefSYogesh Narayan Gaur #define FSPI_FLSHA1CR1 0x70 166a5356aefSYogesh Narayan Gaur #define FSPI_FLSHA2CR1 0x74 167a5356aefSYogesh Narayan Gaur #define FSPI_FLSHB1CR1 0x78 168a5356aefSYogesh Narayan Gaur #define FSPI_FLSHB2CR1 0x7C 169a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR1_CSINTR(x) ((x) << 16) 170a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR1_CAS(x) ((x) << 11) 171a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR1_WA BIT(10) 172a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR1_TCSH(x) ((x) << 5) 173a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR1_TCSS(x) (x) 174a5356aefSYogesh Narayan Gaur 175a5356aefSYogesh Narayan Gaur #define FSPI_FLSHA1CR2 0x80 176a5356aefSYogesh Narayan Gaur #define FSPI_FLSHA2CR2 0x84 177a5356aefSYogesh Narayan Gaur #define FSPI_FLSHB1CR2 0x88 178a5356aefSYogesh Narayan Gaur #define FSPI_FLSHB2CR2 0x8C 179a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR2_CLRINSP BIT(24) 180a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR2_AWRWAIT BIT(16) 181a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR2_AWRSEQN_SHIFT 13 182a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR2_AWRSEQI_SHIFT 8 183a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR2_ARDSEQN_SHIFT 5 184a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR2_ARDSEQI_SHIFT 0 185a5356aefSYogesh Narayan Gaur 186a5356aefSYogesh Narayan Gaur #define FSPI_IPCR0 0xA0 187a5356aefSYogesh Narayan Gaur 188a5356aefSYogesh Narayan Gaur #define FSPI_IPCR1 0xA4 189a5356aefSYogesh Narayan Gaur #define FSPI_IPCR1_IPAREN BIT(31) 190a5356aefSYogesh Narayan Gaur #define FSPI_IPCR1_SEQNUM_SHIFT 24 191a5356aefSYogesh Narayan Gaur #define FSPI_IPCR1_SEQID_SHIFT 16 192a5356aefSYogesh Narayan Gaur #define FSPI_IPCR1_IDATSZ(x) (x) 193a5356aefSYogesh Narayan Gaur 194a5356aefSYogesh Narayan Gaur #define FSPI_IPCMD 0xB0 195a5356aefSYogesh Narayan Gaur #define FSPI_IPCMD_TRG BIT(0) 196a5356aefSYogesh Narayan Gaur 197a5356aefSYogesh Narayan Gaur #define FSPI_DLPR 0xB4 198a5356aefSYogesh Narayan Gaur 199a5356aefSYogesh Narayan Gaur #define FSPI_IPRXFCR 0xB8 200a5356aefSYogesh Narayan Gaur #define FSPI_IPRXFCR_CLR BIT(0) 201a5356aefSYogesh Narayan Gaur #define FSPI_IPRXFCR_DMA_EN BIT(1) 202a5356aefSYogesh Narayan Gaur #define FSPI_IPRXFCR_WMRK(x) ((x) << 2) 203a5356aefSYogesh Narayan Gaur 204a5356aefSYogesh Narayan Gaur #define FSPI_IPTXFCR 0xBC 205a5356aefSYogesh Narayan Gaur #define FSPI_IPTXFCR_CLR BIT(0) 206a5356aefSYogesh Narayan Gaur #define FSPI_IPTXFCR_DMA_EN BIT(1) 207a5356aefSYogesh Narayan Gaur #define FSPI_IPTXFCR_WMRK(x) ((x) << 2) 208a5356aefSYogesh Narayan Gaur 209a5356aefSYogesh Narayan Gaur #define FSPI_DLLACR 0xC0 210a5356aefSYogesh Narayan Gaur #define FSPI_DLLACR_OVRDEN BIT(8) 211a5356aefSYogesh Narayan Gaur 212a5356aefSYogesh Narayan Gaur #define FSPI_DLLBCR 0xC4 213a5356aefSYogesh Narayan Gaur #define FSPI_DLLBCR_OVRDEN BIT(8) 214a5356aefSYogesh Narayan Gaur 215a5356aefSYogesh Narayan Gaur #define FSPI_STS0 0xE0 216a5356aefSYogesh Narayan Gaur #define FSPI_STS0_DLPHB(x) ((x) << 8) 217a5356aefSYogesh Narayan Gaur #define FSPI_STS0_DLPHA(x) ((x) << 4) 218a5356aefSYogesh Narayan Gaur #define FSPI_STS0_CMD_SRC(x) ((x) << 2) 219a5356aefSYogesh Narayan Gaur #define FSPI_STS0_ARB_IDLE BIT(1) 220a5356aefSYogesh Narayan Gaur #define FSPI_STS0_SEQ_IDLE BIT(0) 221a5356aefSYogesh Narayan Gaur 222a5356aefSYogesh Narayan Gaur #define FSPI_STS1 0xE4 223a5356aefSYogesh Narayan Gaur #define FSPI_STS1_IP_ERRCD(x) ((x) << 24) 224a5356aefSYogesh Narayan Gaur #define FSPI_STS1_IP_ERRID(x) ((x) << 16) 225a5356aefSYogesh Narayan Gaur #define FSPI_STS1_AHB_ERRCD(x) ((x) << 8) 226a5356aefSYogesh Narayan Gaur #define FSPI_STS1_AHB_ERRID(x) (x) 227a5356aefSYogesh Narayan Gaur 228a5356aefSYogesh Narayan Gaur #define FSPI_AHBSPNST 0xEC 229a5356aefSYogesh Narayan Gaur #define FSPI_AHBSPNST_DATLFT(x) ((x) << 16) 230a5356aefSYogesh Narayan Gaur #define FSPI_AHBSPNST_BUFID(x) ((x) << 1) 231a5356aefSYogesh Narayan Gaur #define FSPI_AHBSPNST_ACTIVE BIT(0) 232a5356aefSYogesh Narayan Gaur 233a5356aefSYogesh Narayan Gaur #define FSPI_IPRXFSTS 0xF0 234a5356aefSYogesh Narayan Gaur #define FSPI_IPRXFSTS_RDCNTR(x) ((x) << 16) 235a5356aefSYogesh Narayan Gaur #define FSPI_IPRXFSTS_FILL(x) (x) 236a5356aefSYogesh Narayan Gaur 237a5356aefSYogesh Narayan Gaur #define FSPI_IPTXFSTS 0xF4 238a5356aefSYogesh Narayan Gaur #define FSPI_IPTXFSTS_WRCNTR(x) ((x) << 16) 239a5356aefSYogesh Narayan Gaur #define FSPI_IPTXFSTS_FILL(x) (x) 240a5356aefSYogesh Narayan Gaur 241a5356aefSYogesh Narayan Gaur #define FSPI_RFDR 0x100 242a5356aefSYogesh Narayan Gaur #define FSPI_TFDR 0x180 243a5356aefSYogesh Narayan Gaur 244a5356aefSYogesh Narayan Gaur #define FSPI_LUT_BASE 0x200 245a5356aefSYogesh Narayan Gaur #define FSPI_LUT_OFFSET (SEQID_LUT * 4 * 4) 246a5356aefSYogesh Narayan Gaur #define FSPI_LUT_REG(idx) \ 247a5356aefSYogesh Narayan Gaur (FSPI_LUT_BASE + FSPI_LUT_OFFSET + (idx) * 4) 248a5356aefSYogesh Narayan Gaur 249a5356aefSYogesh Narayan Gaur /* register map end */ 250a5356aefSYogesh Narayan Gaur 251a5356aefSYogesh Narayan Gaur /* Instruction set for the LUT register. */ 252a5356aefSYogesh Narayan Gaur #define LUT_STOP 0x00 253a5356aefSYogesh Narayan Gaur #define LUT_CMD 0x01 254a5356aefSYogesh Narayan Gaur #define LUT_ADDR 0x02 255a5356aefSYogesh Narayan Gaur #define LUT_CADDR_SDR 0x03 256a5356aefSYogesh Narayan Gaur #define LUT_MODE 0x04 257a5356aefSYogesh Narayan Gaur #define LUT_MODE2 0x05 258a5356aefSYogesh Narayan Gaur #define LUT_MODE4 0x06 259a5356aefSYogesh Narayan Gaur #define LUT_MODE8 0x07 260a5356aefSYogesh Narayan Gaur #define LUT_NXP_WRITE 0x08 261a5356aefSYogesh Narayan Gaur #define LUT_NXP_READ 0x09 262a5356aefSYogesh Narayan Gaur #define LUT_LEARN_SDR 0x0A 263a5356aefSYogesh Narayan Gaur #define LUT_DATSZ_SDR 0x0B 264a5356aefSYogesh Narayan Gaur #define LUT_DUMMY 0x0C 265a5356aefSYogesh Narayan Gaur #define LUT_DUMMY_RWDS_SDR 0x0D 266a5356aefSYogesh Narayan Gaur #define LUT_JMP_ON_CS 0x1F 267a5356aefSYogesh Narayan Gaur #define LUT_CMD_DDR 0x21 268a5356aefSYogesh Narayan Gaur #define LUT_ADDR_DDR 0x22 269a5356aefSYogesh Narayan Gaur #define LUT_CADDR_DDR 0x23 270a5356aefSYogesh Narayan Gaur #define LUT_MODE_DDR 0x24 271a5356aefSYogesh Narayan Gaur #define LUT_MODE2_DDR 0x25 272a5356aefSYogesh Narayan Gaur #define LUT_MODE4_DDR 0x26 273a5356aefSYogesh Narayan Gaur #define LUT_MODE8_DDR 0x27 274a5356aefSYogesh Narayan Gaur #define LUT_WRITE_DDR 0x28 275a5356aefSYogesh Narayan Gaur #define LUT_READ_DDR 0x29 276a5356aefSYogesh Narayan Gaur #define LUT_LEARN_DDR 0x2A 277a5356aefSYogesh Narayan Gaur #define LUT_DATSZ_DDR 0x2B 278a5356aefSYogesh Narayan Gaur #define LUT_DUMMY_DDR 0x2C 279a5356aefSYogesh Narayan Gaur #define LUT_DUMMY_RWDS_DDR 0x2D 280a5356aefSYogesh Narayan Gaur 281a5356aefSYogesh Narayan Gaur /* 282a5356aefSYogesh Narayan Gaur * Calculate number of required PAD bits for LUT register. 283a5356aefSYogesh Narayan Gaur * 284a5356aefSYogesh Narayan Gaur * The pad stands for the number of IO lines [0:7]. 285a5356aefSYogesh Narayan Gaur * For example, the octal read needs eight IO lines, 286a5356aefSYogesh Narayan Gaur * so you should use LUT_PAD(8). This macro 287a5356aefSYogesh Narayan Gaur * returns 3 i.e. use eight (2^3) IP lines for read. 288a5356aefSYogesh Narayan Gaur */ 289a5356aefSYogesh Narayan Gaur #define LUT_PAD(x) (fls(x) - 1) 290a5356aefSYogesh Narayan Gaur 291a5356aefSYogesh Narayan Gaur /* 292a5356aefSYogesh Narayan Gaur * Macro for constructing the LUT entries with the following 293a5356aefSYogesh Narayan Gaur * register layout: 294a5356aefSYogesh Narayan Gaur * 295a5356aefSYogesh Narayan Gaur * --------------------------------------------------- 296a5356aefSYogesh Narayan Gaur * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 | 297a5356aefSYogesh Narayan Gaur * --------------------------------------------------- 298a5356aefSYogesh Narayan Gaur */ 299a5356aefSYogesh Narayan Gaur #define PAD_SHIFT 8 300a5356aefSYogesh Narayan Gaur #define INSTR_SHIFT 10 301a5356aefSYogesh Narayan Gaur #define OPRND_SHIFT 16 302a5356aefSYogesh Narayan Gaur 303a5356aefSYogesh Narayan Gaur /* Macros for constructing the LUT register. */ 304a5356aefSYogesh Narayan Gaur #define LUT_DEF(idx, ins, pad, opr) \ 305a5356aefSYogesh Narayan Gaur ((((ins) << INSTR_SHIFT) | ((pad) << PAD_SHIFT) | \ 306a5356aefSYogesh Narayan Gaur (opr)) << (((idx) % 2) * OPRND_SHIFT)) 307a5356aefSYogesh Narayan Gaur 308a5356aefSYogesh Narayan Gaur #define POLL_TOUT 5000 309a5356aefSYogesh Narayan Gaur #define NXP_FSPI_MAX_CHIPSELECT 4 310d166a735SHan Xu #define NXP_FSPI_MIN_IOMAP SZ_4M 311a5356aefSYogesh Narayan Gaur 312a5356aefSYogesh Narayan Gaur struct nxp_fspi_devtype_data { 313a5356aefSYogesh Narayan Gaur unsigned int rxfifo; 314a5356aefSYogesh Narayan Gaur unsigned int txfifo; 315a5356aefSYogesh Narayan Gaur unsigned int ahb_buf_size; 316a5356aefSYogesh Narayan Gaur unsigned int quirks; 317a5356aefSYogesh Narayan Gaur bool little_endian; 318a5356aefSYogesh Narayan Gaur }; 319a5356aefSYogesh Narayan Gaur 320a5356aefSYogesh Narayan Gaur static const struct nxp_fspi_devtype_data lx2160a_data = { 321a5356aefSYogesh Narayan Gaur .rxfifo = SZ_512, /* (64 * 64 bits) */ 322a5356aefSYogesh Narayan Gaur .txfifo = SZ_1K, /* (128 * 64 bits) */ 323a5356aefSYogesh Narayan Gaur .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ 324a5356aefSYogesh Narayan Gaur .quirks = 0, 325a5356aefSYogesh Narayan Gaur .little_endian = true, /* little-endian */ 326a5356aefSYogesh Narayan Gaur }; 327a5356aefSYogesh Narayan Gaur 328941be8a7SHan Xu static const struct nxp_fspi_devtype_data imx8mm_data = { 329941be8a7SHan Xu .rxfifo = SZ_512, /* (64 * 64 bits) */ 330941be8a7SHan Xu .txfifo = SZ_1K, /* (128 * 64 bits) */ 331941be8a7SHan Xu .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ 332941be8a7SHan Xu .quirks = 0, 333941be8a7SHan Xu .little_endian = true, /* little-endian */ 334941be8a7SHan Xu }; 335941be8a7SHan Xu 336941be8a7SHan Xu static const struct nxp_fspi_devtype_data imx8qxp_data = { 337941be8a7SHan Xu .rxfifo = SZ_512, /* (64 * 64 bits) */ 338941be8a7SHan Xu .txfifo = SZ_1K, /* (128 * 64 bits) */ 339941be8a7SHan Xu .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ 340941be8a7SHan Xu .quirks = 0, 341941be8a7SHan Xu .little_endian = true, /* little-endian */ 342941be8a7SHan Xu }; 343941be8a7SHan Xu 344a5356aefSYogesh Narayan Gaur struct nxp_fspi { 345a5356aefSYogesh Narayan Gaur void __iomem *iobase; 346a5356aefSYogesh Narayan Gaur void __iomem *ahb_addr; 347a5356aefSYogesh Narayan Gaur u32 memmap_phy; 348a5356aefSYogesh Narayan Gaur u32 memmap_phy_size; 349d166a735SHan Xu u32 memmap_start; 350d166a735SHan Xu u32 memmap_len; 351a5356aefSYogesh Narayan Gaur struct clk *clk, *clk_en; 352a5356aefSYogesh Narayan Gaur struct device *dev; 353a5356aefSYogesh Narayan Gaur struct completion c; 354a5356aefSYogesh Narayan Gaur const struct nxp_fspi_devtype_data *devtype_data; 355a5356aefSYogesh Narayan Gaur struct mutex lock; 356a5356aefSYogesh Narayan Gaur struct pm_qos_request pm_qos_req; 357a5356aefSYogesh Narayan Gaur int selected; 358a5356aefSYogesh Narayan Gaur }; 359a5356aefSYogesh Narayan Gaur 360a5356aefSYogesh Narayan Gaur /* 361a5356aefSYogesh Narayan Gaur * R/W functions for big- or little-endian registers: 362a5356aefSYogesh Narayan Gaur * The FSPI controller's endianness is independent of 363a5356aefSYogesh Narayan Gaur * the CPU core's endianness. So far, although the CPU 364a5356aefSYogesh Narayan Gaur * core is little-endian the FSPI controller can use 365a5356aefSYogesh Narayan Gaur * big-endian or little-endian. 366a5356aefSYogesh Narayan Gaur */ 367a5356aefSYogesh Narayan Gaur static void fspi_writel(struct nxp_fspi *f, u32 val, void __iomem *addr) 368a5356aefSYogesh Narayan Gaur { 369a5356aefSYogesh Narayan Gaur if (f->devtype_data->little_endian) 370a5356aefSYogesh Narayan Gaur iowrite32(val, addr); 371a5356aefSYogesh Narayan Gaur else 372a5356aefSYogesh Narayan Gaur iowrite32be(val, addr); 373a5356aefSYogesh Narayan Gaur } 374a5356aefSYogesh Narayan Gaur 375a5356aefSYogesh Narayan Gaur static u32 fspi_readl(struct nxp_fspi *f, void __iomem *addr) 376a5356aefSYogesh Narayan Gaur { 377a5356aefSYogesh Narayan Gaur if (f->devtype_data->little_endian) 378a5356aefSYogesh Narayan Gaur return ioread32(addr); 379a5356aefSYogesh Narayan Gaur else 380a5356aefSYogesh Narayan Gaur return ioread32be(addr); 381a5356aefSYogesh Narayan Gaur } 382a5356aefSYogesh Narayan Gaur 383a5356aefSYogesh Narayan Gaur static irqreturn_t nxp_fspi_irq_handler(int irq, void *dev_id) 384a5356aefSYogesh Narayan Gaur { 385a5356aefSYogesh Narayan Gaur struct nxp_fspi *f = dev_id; 386a5356aefSYogesh Narayan Gaur u32 reg; 387a5356aefSYogesh Narayan Gaur 388a5356aefSYogesh Narayan Gaur /* clear interrupt */ 389a5356aefSYogesh Narayan Gaur reg = fspi_readl(f, f->iobase + FSPI_INTR); 390a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_INTR_IPCMDDONE, f->iobase + FSPI_INTR); 391a5356aefSYogesh Narayan Gaur 392a5356aefSYogesh Narayan Gaur if (reg & FSPI_INTR_IPCMDDONE) 393a5356aefSYogesh Narayan Gaur complete(&f->c); 394a5356aefSYogesh Narayan Gaur 395a5356aefSYogesh Narayan Gaur return IRQ_HANDLED; 396a5356aefSYogesh Narayan Gaur } 397a5356aefSYogesh Narayan Gaur 398a5356aefSYogesh Narayan Gaur static int nxp_fspi_check_buswidth(struct nxp_fspi *f, u8 width) 399a5356aefSYogesh Narayan Gaur { 400a5356aefSYogesh Narayan Gaur switch (width) { 401a5356aefSYogesh Narayan Gaur case 1: 402a5356aefSYogesh Narayan Gaur case 2: 403a5356aefSYogesh Narayan Gaur case 4: 404a5356aefSYogesh Narayan Gaur case 8: 405a5356aefSYogesh Narayan Gaur return 0; 406a5356aefSYogesh Narayan Gaur } 407a5356aefSYogesh Narayan Gaur 408a5356aefSYogesh Narayan Gaur return -ENOTSUPP; 409a5356aefSYogesh Narayan Gaur } 410a5356aefSYogesh Narayan Gaur 411a5356aefSYogesh Narayan Gaur static bool nxp_fspi_supports_op(struct spi_mem *mem, 412a5356aefSYogesh Narayan Gaur const struct spi_mem_op *op) 413a5356aefSYogesh Narayan Gaur { 414a5356aefSYogesh Narayan Gaur struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master); 415a5356aefSYogesh Narayan Gaur int ret; 416a5356aefSYogesh Narayan Gaur 417a5356aefSYogesh Narayan Gaur ret = nxp_fspi_check_buswidth(f, op->cmd.buswidth); 418a5356aefSYogesh Narayan Gaur 419a5356aefSYogesh Narayan Gaur if (op->addr.nbytes) 420a5356aefSYogesh Narayan Gaur ret |= nxp_fspi_check_buswidth(f, op->addr.buswidth); 421a5356aefSYogesh Narayan Gaur 422a5356aefSYogesh Narayan Gaur if (op->dummy.nbytes) 423a5356aefSYogesh Narayan Gaur ret |= nxp_fspi_check_buswidth(f, op->dummy.buswidth); 424a5356aefSYogesh Narayan Gaur 425a5356aefSYogesh Narayan Gaur if (op->data.nbytes) 426a5356aefSYogesh Narayan Gaur ret |= nxp_fspi_check_buswidth(f, op->data.buswidth); 427a5356aefSYogesh Narayan Gaur 428a5356aefSYogesh Narayan Gaur if (ret) 429a5356aefSYogesh Narayan Gaur return false; 430a5356aefSYogesh Narayan Gaur 431a5356aefSYogesh Narayan Gaur /* 432a5356aefSYogesh Narayan Gaur * The number of address bytes should be equal to or less than 4 bytes. 433a5356aefSYogesh Narayan Gaur */ 434a5356aefSYogesh Narayan Gaur if (op->addr.nbytes > 4) 435a5356aefSYogesh Narayan Gaur return false; 436a5356aefSYogesh Narayan Gaur 437a5356aefSYogesh Narayan Gaur /* 438a5356aefSYogesh Narayan Gaur * If requested address value is greater than controller assigned 439a5356aefSYogesh Narayan Gaur * memory mapped space, return error as it didn't fit in the range 440a5356aefSYogesh Narayan Gaur * of assigned address space. 441a5356aefSYogesh Narayan Gaur */ 442a5356aefSYogesh Narayan Gaur if (op->addr.val >= f->memmap_phy_size) 443a5356aefSYogesh Narayan Gaur return false; 444a5356aefSYogesh Narayan Gaur 445a5356aefSYogesh Narayan Gaur /* Max 64 dummy clock cycles supported */ 446a5356aefSYogesh Narayan Gaur if (op->dummy.buswidth && 447a5356aefSYogesh Narayan Gaur (op->dummy.nbytes * 8 / op->dummy.buswidth > 64)) 448a5356aefSYogesh Narayan Gaur return false; 449a5356aefSYogesh Narayan Gaur 450a5356aefSYogesh Narayan Gaur /* Max data length, check controller limits and alignment */ 451a5356aefSYogesh Narayan Gaur if (op->data.dir == SPI_MEM_DATA_IN && 452a5356aefSYogesh Narayan Gaur (op->data.nbytes > f->devtype_data->ahb_buf_size || 453a5356aefSYogesh Narayan Gaur (op->data.nbytes > f->devtype_data->rxfifo - 4 && 454a5356aefSYogesh Narayan Gaur !IS_ALIGNED(op->data.nbytes, 8)))) 455a5356aefSYogesh Narayan Gaur return false; 456a5356aefSYogesh Narayan Gaur 457a5356aefSYogesh Narayan Gaur if (op->data.dir == SPI_MEM_DATA_OUT && 458a5356aefSYogesh Narayan Gaur op->data.nbytes > f->devtype_data->txfifo) 459a5356aefSYogesh Narayan Gaur return false; 460a5356aefSYogesh Narayan Gaur 461007773e1SMichael Walle return spi_mem_default_supports_op(mem, op); 462a5356aefSYogesh Narayan Gaur } 463a5356aefSYogesh Narayan Gaur 464a5356aefSYogesh Narayan Gaur /* Instead of busy looping invoke readl_poll_timeout functionality. */ 465a5356aefSYogesh Narayan Gaur static int fspi_readl_poll_tout(struct nxp_fspi *f, void __iomem *base, 466a5356aefSYogesh Narayan Gaur u32 mask, u32 delay_us, 467a5356aefSYogesh Narayan Gaur u32 timeout_us, bool c) 468a5356aefSYogesh Narayan Gaur { 469a5356aefSYogesh Narayan Gaur u32 reg; 470a5356aefSYogesh Narayan Gaur 471a5356aefSYogesh Narayan Gaur if (!f->devtype_data->little_endian) 472a5356aefSYogesh Narayan Gaur mask = (u32)cpu_to_be32(mask); 473a5356aefSYogesh Narayan Gaur 474a5356aefSYogesh Narayan Gaur if (c) 475a5356aefSYogesh Narayan Gaur return readl_poll_timeout(base, reg, (reg & mask), 476a5356aefSYogesh Narayan Gaur delay_us, timeout_us); 477a5356aefSYogesh Narayan Gaur else 478a5356aefSYogesh Narayan Gaur return readl_poll_timeout(base, reg, !(reg & mask), 479a5356aefSYogesh Narayan Gaur delay_us, timeout_us); 480a5356aefSYogesh Narayan Gaur } 481a5356aefSYogesh Narayan Gaur 482a5356aefSYogesh Narayan Gaur /* 483a5356aefSYogesh Narayan Gaur * If the slave device content being changed by Write/Erase, need to 484a5356aefSYogesh Narayan Gaur * invalidate the AHB buffer. This can be achieved by doing the reset 485a5356aefSYogesh Narayan Gaur * of controller after setting MCR0[SWRESET] bit. 486a5356aefSYogesh Narayan Gaur */ 487a5356aefSYogesh Narayan Gaur static inline void nxp_fspi_invalid(struct nxp_fspi *f) 488a5356aefSYogesh Narayan Gaur { 489a5356aefSYogesh Narayan Gaur u32 reg; 490a5356aefSYogesh Narayan Gaur int ret; 491a5356aefSYogesh Narayan Gaur 492a5356aefSYogesh Narayan Gaur reg = fspi_readl(f, f->iobase + FSPI_MCR0); 493a5356aefSYogesh Narayan Gaur fspi_writel(f, reg | FSPI_MCR0_SWRST, f->iobase + FSPI_MCR0); 494a5356aefSYogesh Narayan Gaur 495a5356aefSYogesh Narayan Gaur /* w1c register, wait unit clear */ 496a5356aefSYogesh Narayan Gaur ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0, 497a5356aefSYogesh Narayan Gaur FSPI_MCR0_SWRST, 0, POLL_TOUT, false); 498a5356aefSYogesh Narayan Gaur WARN_ON(ret); 499a5356aefSYogesh Narayan Gaur } 500a5356aefSYogesh Narayan Gaur 501a5356aefSYogesh Narayan Gaur static void nxp_fspi_prepare_lut(struct nxp_fspi *f, 502a5356aefSYogesh Narayan Gaur const struct spi_mem_op *op) 503a5356aefSYogesh Narayan Gaur { 504a5356aefSYogesh Narayan Gaur void __iomem *base = f->iobase; 505a5356aefSYogesh Narayan Gaur u32 lutval[4] = {}; 506a5356aefSYogesh Narayan Gaur int lutidx = 1, i; 507a5356aefSYogesh Narayan Gaur 508a5356aefSYogesh Narayan Gaur /* cmd */ 509a5356aefSYogesh Narayan Gaur lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth), 510a5356aefSYogesh Narayan Gaur op->cmd.opcode); 511a5356aefSYogesh Narayan Gaur 512a5356aefSYogesh Narayan Gaur /* addr bytes */ 513a5356aefSYogesh Narayan Gaur if (op->addr.nbytes) { 514a5356aefSYogesh Narayan Gaur lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_ADDR, 515a5356aefSYogesh Narayan Gaur LUT_PAD(op->addr.buswidth), 516a5356aefSYogesh Narayan Gaur op->addr.nbytes * 8); 517a5356aefSYogesh Narayan Gaur lutidx++; 518a5356aefSYogesh Narayan Gaur } 519a5356aefSYogesh Narayan Gaur 520a5356aefSYogesh Narayan Gaur /* dummy bytes, if needed */ 521a5356aefSYogesh Narayan Gaur if (op->dummy.nbytes) { 522a5356aefSYogesh Narayan Gaur lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY, 523a5356aefSYogesh Narayan Gaur /* 524a5356aefSYogesh Narayan Gaur * Due to FlexSPI controller limitation number of PAD for dummy 525a5356aefSYogesh Narayan Gaur * buswidth needs to be programmed as equal to data buswidth. 526a5356aefSYogesh Narayan Gaur */ 527a5356aefSYogesh Narayan Gaur LUT_PAD(op->data.buswidth), 528a5356aefSYogesh Narayan Gaur op->dummy.nbytes * 8 / 529a5356aefSYogesh Narayan Gaur op->dummy.buswidth); 530a5356aefSYogesh Narayan Gaur lutidx++; 531a5356aefSYogesh Narayan Gaur } 532a5356aefSYogesh Narayan Gaur 533a5356aefSYogesh Narayan Gaur /* read/write data bytes */ 534a5356aefSYogesh Narayan Gaur if (op->data.nbytes) { 535a5356aefSYogesh Narayan Gaur lutval[lutidx / 2] |= LUT_DEF(lutidx, 536a5356aefSYogesh Narayan Gaur op->data.dir == SPI_MEM_DATA_IN ? 537a5356aefSYogesh Narayan Gaur LUT_NXP_READ : LUT_NXP_WRITE, 538a5356aefSYogesh Narayan Gaur LUT_PAD(op->data.buswidth), 539a5356aefSYogesh Narayan Gaur 0); 540a5356aefSYogesh Narayan Gaur lutidx++; 541a5356aefSYogesh Narayan Gaur } 542a5356aefSYogesh Narayan Gaur 543a5356aefSYogesh Narayan Gaur /* stop condition. */ 544a5356aefSYogesh Narayan Gaur lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0); 545a5356aefSYogesh Narayan Gaur 546a5356aefSYogesh Narayan Gaur /* unlock LUT */ 547a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY); 548a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_LCKER_UNLOCK, f->iobase + FSPI_LCKCR); 549a5356aefSYogesh Narayan Gaur 550a5356aefSYogesh Narayan Gaur /* fill LUT */ 551a5356aefSYogesh Narayan Gaur for (i = 0; i < ARRAY_SIZE(lutval); i++) 552a5356aefSYogesh Narayan Gaur fspi_writel(f, lutval[i], base + FSPI_LUT_REG(i)); 553a5356aefSYogesh Narayan Gaur 554a5356aefSYogesh Narayan Gaur dev_dbg(f->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x]\n", 555a5356aefSYogesh Narayan Gaur op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3]); 556a5356aefSYogesh Narayan Gaur 557a5356aefSYogesh Narayan Gaur /* lock LUT */ 558a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY); 559a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_LCKER_LOCK, f->iobase + FSPI_LCKCR); 560a5356aefSYogesh Narayan Gaur } 561a5356aefSYogesh Narayan Gaur 562a5356aefSYogesh Narayan Gaur static int nxp_fspi_clk_prep_enable(struct nxp_fspi *f) 563a5356aefSYogesh Narayan Gaur { 564a5356aefSYogesh Narayan Gaur int ret; 565a5356aefSYogesh Narayan Gaur 566a5356aefSYogesh Narayan Gaur ret = clk_prepare_enable(f->clk_en); 567a5356aefSYogesh Narayan Gaur if (ret) 568a5356aefSYogesh Narayan Gaur return ret; 569a5356aefSYogesh Narayan Gaur 570a5356aefSYogesh Narayan Gaur ret = clk_prepare_enable(f->clk); 571a5356aefSYogesh Narayan Gaur if (ret) { 572a5356aefSYogesh Narayan Gaur clk_disable_unprepare(f->clk_en); 573a5356aefSYogesh Narayan Gaur return ret; 574a5356aefSYogesh Narayan Gaur } 575a5356aefSYogesh Narayan Gaur 576a5356aefSYogesh Narayan Gaur return 0; 577a5356aefSYogesh Narayan Gaur } 578a5356aefSYogesh Narayan Gaur 579a5356aefSYogesh Narayan Gaur static void nxp_fspi_clk_disable_unprep(struct nxp_fspi *f) 580a5356aefSYogesh Narayan Gaur { 581a5356aefSYogesh Narayan Gaur clk_disable_unprepare(f->clk); 582a5356aefSYogesh Narayan Gaur clk_disable_unprepare(f->clk_en); 583a5356aefSYogesh Narayan Gaur } 584a5356aefSYogesh Narayan Gaur 585a5356aefSYogesh Narayan Gaur /* 586a5356aefSYogesh Narayan Gaur * In FlexSPI controller, flash access is based on value of FSPI_FLSHXXCR0 587a5356aefSYogesh Narayan Gaur * register and start base address of the slave device. 588a5356aefSYogesh Narayan Gaur * 589a5356aefSYogesh Narayan Gaur * (Higher address) 590a5356aefSYogesh Narayan Gaur * -------- <-- FLSHB2CR0 591a5356aefSYogesh Narayan Gaur * | B2 | 592a5356aefSYogesh Narayan Gaur * | | 593a5356aefSYogesh Narayan Gaur * B2 start address --> -------- <-- FLSHB1CR0 594a5356aefSYogesh Narayan Gaur * | B1 | 595a5356aefSYogesh Narayan Gaur * | | 596a5356aefSYogesh Narayan Gaur * B1 start address --> -------- <-- FLSHA2CR0 597a5356aefSYogesh Narayan Gaur * | A2 | 598a5356aefSYogesh Narayan Gaur * | | 599a5356aefSYogesh Narayan Gaur * A2 start address --> -------- <-- FLSHA1CR0 600a5356aefSYogesh Narayan Gaur * | A1 | 601a5356aefSYogesh Narayan Gaur * | | 602a5356aefSYogesh Narayan Gaur * A1 start address --> -------- (Lower address) 603a5356aefSYogesh Narayan Gaur * 604a5356aefSYogesh Narayan Gaur * 605a5356aefSYogesh Narayan Gaur * Start base address defines the starting address range for given CS and 606a5356aefSYogesh Narayan Gaur * FSPI_FLSHXXCR0 defines the size of the slave device connected at given CS. 607a5356aefSYogesh Narayan Gaur * 608a5356aefSYogesh Narayan Gaur * But, different targets are having different combinations of number of CS, 609a5356aefSYogesh Narayan Gaur * some targets only have single CS or two CS covering controller's full 610a5356aefSYogesh Narayan Gaur * memory mapped space area. 611a5356aefSYogesh Narayan Gaur * Thus, implementation is being done as independent of the size and number 612a5356aefSYogesh Narayan Gaur * of the connected slave device. 613a5356aefSYogesh Narayan Gaur * Assign controller memory mapped space size as the size to the connected 614a5356aefSYogesh Narayan Gaur * slave device. 615a5356aefSYogesh Narayan Gaur * Mark FLSHxxCR0 as zero initially and then assign value only to the selected 616a5356aefSYogesh Narayan Gaur * chip-select Flash configuration register. 617a5356aefSYogesh Narayan Gaur * 618a5356aefSYogesh Narayan Gaur * For e.g. to access CS2 (B1), FLSHB1CR0 register would be equal to the 619a5356aefSYogesh Narayan Gaur * memory mapped size of the controller. 620a5356aefSYogesh Narayan Gaur * Value for rest of the CS FLSHxxCR0 register would be zero. 621a5356aefSYogesh Narayan Gaur * 622a5356aefSYogesh Narayan Gaur */ 623a5356aefSYogesh Narayan Gaur static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi) 624a5356aefSYogesh Narayan Gaur { 625a5356aefSYogesh Narayan Gaur unsigned long rate = spi->max_speed_hz; 626a5356aefSYogesh Narayan Gaur int ret; 627a5356aefSYogesh Narayan Gaur uint64_t size_kb; 628a5356aefSYogesh Narayan Gaur 629a5356aefSYogesh Narayan Gaur /* 630a5356aefSYogesh Narayan Gaur * Return, if previously selected slave device is same as current 631a5356aefSYogesh Narayan Gaur * requested slave device. 632a5356aefSYogesh Narayan Gaur */ 633a5356aefSYogesh Narayan Gaur if (f->selected == spi->chip_select) 634a5356aefSYogesh Narayan Gaur return; 635a5356aefSYogesh Narayan Gaur 636a5356aefSYogesh Narayan Gaur /* Reset FLSHxxCR0 registers */ 637a5356aefSYogesh Narayan Gaur fspi_writel(f, 0, f->iobase + FSPI_FLSHA1CR0); 638a5356aefSYogesh Narayan Gaur fspi_writel(f, 0, f->iobase + FSPI_FLSHA2CR0); 639a5356aefSYogesh Narayan Gaur fspi_writel(f, 0, f->iobase + FSPI_FLSHB1CR0); 640a5356aefSYogesh Narayan Gaur fspi_writel(f, 0, f->iobase + FSPI_FLSHB2CR0); 641a5356aefSYogesh Narayan Gaur 642a5356aefSYogesh Narayan Gaur /* Assign controller memory mapped space as size, KBytes, of flash. */ 643a5356aefSYogesh Narayan Gaur size_kb = FSPI_FLSHXCR0_SZ(f->memmap_phy_size); 644a5356aefSYogesh Narayan Gaur 645a5356aefSYogesh Narayan Gaur fspi_writel(f, size_kb, f->iobase + FSPI_FLSHA1CR0 + 646a5356aefSYogesh Narayan Gaur 4 * spi->chip_select); 647a5356aefSYogesh Narayan Gaur 648a5356aefSYogesh Narayan Gaur dev_dbg(f->dev, "Slave device [CS:%x] selected\n", spi->chip_select); 649a5356aefSYogesh Narayan Gaur 650a5356aefSYogesh Narayan Gaur nxp_fspi_clk_disable_unprep(f); 651a5356aefSYogesh Narayan Gaur 652a5356aefSYogesh Narayan Gaur ret = clk_set_rate(f->clk, rate); 653a5356aefSYogesh Narayan Gaur if (ret) 654a5356aefSYogesh Narayan Gaur return; 655a5356aefSYogesh Narayan Gaur 656a5356aefSYogesh Narayan Gaur ret = nxp_fspi_clk_prep_enable(f); 657a5356aefSYogesh Narayan Gaur if (ret) 658a5356aefSYogesh Narayan Gaur return; 659a5356aefSYogesh Narayan Gaur 660a5356aefSYogesh Narayan Gaur f->selected = spi->chip_select; 661a5356aefSYogesh Narayan Gaur } 662a5356aefSYogesh Narayan Gaur 663d166a735SHan Xu static int nxp_fspi_read_ahb(struct nxp_fspi *f, const struct spi_mem_op *op) 664a5356aefSYogesh Narayan Gaur { 665d166a735SHan Xu u32 start = op->addr.val; 666a5356aefSYogesh Narayan Gaur u32 len = op->data.nbytes; 667a5356aefSYogesh Narayan Gaur 668d166a735SHan Xu /* if necessary, ioremap before AHB read */ 669d166a735SHan Xu if ((!f->ahb_addr) || start < f->memmap_start || 670d166a735SHan Xu start + len > f->memmap_start + f->memmap_len) { 671d166a735SHan Xu if (f->ahb_addr) 672d166a735SHan Xu iounmap(f->ahb_addr); 673d166a735SHan Xu 674d166a735SHan Xu f->memmap_start = start; 675d166a735SHan Xu f->memmap_len = len > NXP_FSPI_MIN_IOMAP ? 676d166a735SHan Xu len : NXP_FSPI_MIN_IOMAP; 677d166a735SHan Xu 678d166a735SHan Xu f->ahb_addr = ioremap_wc(f->memmap_phy + f->memmap_start, 679d166a735SHan Xu f->memmap_len); 680d166a735SHan Xu 681d166a735SHan Xu if (!f->ahb_addr) { 682d166a735SHan Xu dev_err(f->dev, "failed to alloc memory\n"); 683d166a735SHan Xu return -ENOMEM; 684d166a735SHan Xu } 685d166a735SHan Xu } 686d166a735SHan Xu 687a5356aefSYogesh Narayan Gaur /* Read out the data directly from the AHB buffer. */ 688d166a735SHan Xu memcpy_fromio(op->data.buf.in, 689d166a735SHan Xu f->ahb_addr + start - f->memmap_start, len); 690d166a735SHan Xu 691d166a735SHan Xu return 0; 692a5356aefSYogesh Narayan Gaur } 693a5356aefSYogesh Narayan Gaur 694a5356aefSYogesh Narayan Gaur static void nxp_fspi_fill_txfifo(struct nxp_fspi *f, 695a5356aefSYogesh Narayan Gaur const struct spi_mem_op *op) 696a5356aefSYogesh Narayan Gaur { 697a5356aefSYogesh Narayan Gaur void __iomem *base = f->iobase; 698a5356aefSYogesh Narayan Gaur int i, ret; 699a5356aefSYogesh Narayan Gaur u8 *buf = (u8 *) op->data.buf.out; 700a5356aefSYogesh Narayan Gaur 701a5356aefSYogesh Narayan Gaur /* clear the TX FIFO. */ 702a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_IPTXFCR_CLR, base + FSPI_IPTXFCR); 703a5356aefSYogesh Narayan Gaur 704a5356aefSYogesh Narayan Gaur /* 705a5356aefSYogesh Narayan Gaur * Default value of water mark level is 8 bytes, hence in single 706a5356aefSYogesh Narayan Gaur * write request controller can write max 8 bytes of data. 707a5356aefSYogesh Narayan Gaur */ 708a5356aefSYogesh Narayan Gaur 709a5356aefSYogesh Narayan Gaur for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 8); i += 8) { 710a5356aefSYogesh Narayan Gaur /* Wait for TXFIFO empty */ 711a5356aefSYogesh Narayan Gaur ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, 712a5356aefSYogesh Narayan Gaur FSPI_INTR_IPTXWE, 0, 713a5356aefSYogesh Narayan Gaur POLL_TOUT, true); 714a5356aefSYogesh Narayan Gaur WARN_ON(ret); 715a5356aefSYogesh Narayan Gaur 716a5356aefSYogesh Narayan Gaur fspi_writel(f, *(u32 *) (buf + i), base + FSPI_TFDR); 717a5356aefSYogesh Narayan Gaur fspi_writel(f, *(u32 *) (buf + i + 4), base + FSPI_TFDR + 4); 718a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR); 719a5356aefSYogesh Narayan Gaur } 720a5356aefSYogesh Narayan Gaur 721a5356aefSYogesh Narayan Gaur if (i < op->data.nbytes) { 722a5356aefSYogesh Narayan Gaur u32 data = 0; 723a5356aefSYogesh Narayan Gaur int j; 724a5356aefSYogesh Narayan Gaur /* Wait for TXFIFO empty */ 725a5356aefSYogesh Narayan Gaur ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, 726a5356aefSYogesh Narayan Gaur FSPI_INTR_IPTXWE, 0, 727a5356aefSYogesh Narayan Gaur POLL_TOUT, true); 728a5356aefSYogesh Narayan Gaur WARN_ON(ret); 729a5356aefSYogesh Narayan Gaur 730a5356aefSYogesh Narayan Gaur for (j = 0; j < ALIGN(op->data.nbytes - i, 4); j += 4) { 731a5356aefSYogesh Narayan Gaur memcpy(&data, buf + i + j, 4); 732a5356aefSYogesh Narayan Gaur fspi_writel(f, data, base + FSPI_TFDR + j); 733a5356aefSYogesh Narayan Gaur } 734a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR); 735a5356aefSYogesh Narayan Gaur } 736a5356aefSYogesh Narayan Gaur } 737a5356aefSYogesh Narayan Gaur 738a5356aefSYogesh Narayan Gaur static void nxp_fspi_read_rxfifo(struct nxp_fspi *f, 739a5356aefSYogesh Narayan Gaur const struct spi_mem_op *op) 740a5356aefSYogesh Narayan Gaur { 741a5356aefSYogesh Narayan Gaur void __iomem *base = f->iobase; 742a5356aefSYogesh Narayan Gaur int i, ret; 743a5356aefSYogesh Narayan Gaur int len = op->data.nbytes; 744a5356aefSYogesh Narayan Gaur u8 *buf = (u8 *) op->data.buf.in; 745a5356aefSYogesh Narayan Gaur 746a5356aefSYogesh Narayan Gaur /* 747a5356aefSYogesh Narayan Gaur * Default value of water mark level is 8 bytes, hence in single 748a5356aefSYogesh Narayan Gaur * read request controller can read max 8 bytes of data. 749a5356aefSYogesh Narayan Gaur */ 750a5356aefSYogesh Narayan Gaur for (i = 0; i < ALIGN_DOWN(len, 8); i += 8) { 751a5356aefSYogesh Narayan Gaur /* Wait for RXFIFO available */ 752a5356aefSYogesh Narayan Gaur ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, 753a5356aefSYogesh Narayan Gaur FSPI_INTR_IPRXWA, 0, 754a5356aefSYogesh Narayan Gaur POLL_TOUT, true); 755a5356aefSYogesh Narayan Gaur WARN_ON(ret); 756a5356aefSYogesh Narayan Gaur 757a5356aefSYogesh Narayan Gaur *(u32 *)(buf + i) = fspi_readl(f, base + FSPI_RFDR); 758a5356aefSYogesh Narayan Gaur *(u32 *)(buf + i + 4) = fspi_readl(f, base + FSPI_RFDR + 4); 759a5356aefSYogesh Narayan Gaur /* move the FIFO pointer */ 760a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR); 761a5356aefSYogesh Narayan Gaur } 762a5356aefSYogesh Narayan Gaur 763a5356aefSYogesh Narayan Gaur if (i < len) { 764a5356aefSYogesh Narayan Gaur u32 tmp; 765a5356aefSYogesh Narayan Gaur int size, j; 766a5356aefSYogesh Narayan Gaur 767a5356aefSYogesh Narayan Gaur buf = op->data.buf.in + i; 768a5356aefSYogesh Narayan Gaur /* Wait for RXFIFO available */ 769a5356aefSYogesh Narayan Gaur ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, 770a5356aefSYogesh Narayan Gaur FSPI_INTR_IPRXWA, 0, 771a5356aefSYogesh Narayan Gaur POLL_TOUT, true); 772a5356aefSYogesh Narayan Gaur WARN_ON(ret); 773a5356aefSYogesh Narayan Gaur 774a5356aefSYogesh Narayan Gaur len = op->data.nbytes - i; 775a5356aefSYogesh Narayan Gaur for (j = 0; j < op->data.nbytes - i; j += 4) { 776a5356aefSYogesh Narayan Gaur tmp = fspi_readl(f, base + FSPI_RFDR + j); 777a5356aefSYogesh Narayan Gaur size = min(len, 4); 778a5356aefSYogesh Narayan Gaur memcpy(buf + j, &tmp, size); 779a5356aefSYogesh Narayan Gaur len -= size; 780a5356aefSYogesh Narayan Gaur } 781a5356aefSYogesh Narayan Gaur } 782a5356aefSYogesh Narayan Gaur 783a5356aefSYogesh Narayan Gaur /* invalid the RXFIFO */ 784a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_IPRXFCR_CLR, base + FSPI_IPRXFCR); 785a5356aefSYogesh Narayan Gaur /* move the FIFO pointer */ 786a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR); 787a5356aefSYogesh Narayan Gaur } 788a5356aefSYogesh Narayan Gaur 789a5356aefSYogesh Narayan Gaur static int nxp_fspi_do_op(struct nxp_fspi *f, const struct spi_mem_op *op) 790a5356aefSYogesh Narayan Gaur { 791a5356aefSYogesh Narayan Gaur void __iomem *base = f->iobase; 792a5356aefSYogesh Narayan Gaur int seqnum = 0; 793a5356aefSYogesh Narayan Gaur int err = 0; 794a5356aefSYogesh Narayan Gaur u32 reg; 795a5356aefSYogesh Narayan Gaur 796a5356aefSYogesh Narayan Gaur reg = fspi_readl(f, base + FSPI_IPRXFCR); 797a5356aefSYogesh Narayan Gaur /* invalid RXFIFO first */ 798a5356aefSYogesh Narayan Gaur reg &= ~FSPI_IPRXFCR_DMA_EN; 799a5356aefSYogesh Narayan Gaur reg = reg | FSPI_IPRXFCR_CLR; 800a5356aefSYogesh Narayan Gaur fspi_writel(f, reg, base + FSPI_IPRXFCR); 801a5356aefSYogesh Narayan Gaur 802a5356aefSYogesh Narayan Gaur init_completion(&f->c); 803a5356aefSYogesh Narayan Gaur 804a5356aefSYogesh Narayan Gaur fspi_writel(f, op->addr.val, base + FSPI_IPCR0); 805a5356aefSYogesh Narayan Gaur /* 806a5356aefSYogesh Narayan Gaur * Always start the sequence at the same index since we update 807a5356aefSYogesh Narayan Gaur * the LUT at each exec_op() call. And also specify the DATA 808a5356aefSYogesh Narayan Gaur * length, since it's has not been specified in the LUT. 809a5356aefSYogesh Narayan Gaur */ 810a5356aefSYogesh Narayan Gaur fspi_writel(f, op->data.nbytes | 811a5356aefSYogesh Narayan Gaur (SEQID_LUT << FSPI_IPCR1_SEQID_SHIFT) | 812a5356aefSYogesh Narayan Gaur (seqnum << FSPI_IPCR1_SEQNUM_SHIFT), 813a5356aefSYogesh Narayan Gaur base + FSPI_IPCR1); 814a5356aefSYogesh Narayan Gaur 815a5356aefSYogesh Narayan Gaur /* Trigger the LUT now. */ 816a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_IPCMD_TRG, base + FSPI_IPCMD); 817a5356aefSYogesh Narayan Gaur 818a5356aefSYogesh Narayan Gaur /* Wait for the interrupt. */ 819a5356aefSYogesh Narayan Gaur if (!wait_for_completion_timeout(&f->c, msecs_to_jiffies(1000))) 820a5356aefSYogesh Narayan Gaur err = -ETIMEDOUT; 821a5356aefSYogesh Narayan Gaur 822a5356aefSYogesh Narayan Gaur /* Invoke IP data read, if request is of data read. */ 823a5356aefSYogesh Narayan Gaur if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN) 824a5356aefSYogesh Narayan Gaur nxp_fspi_read_rxfifo(f, op); 825a5356aefSYogesh Narayan Gaur 826a5356aefSYogesh Narayan Gaur return err; 827a5356aefSYogesh Narayan Gaur } 828a5356aefSYogesh Narayan Gaur 829a5356aefSYogesh Narayan Gaur static int nxp_fspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) 830a5356aefSYogesh Narayan Gaur { 831a5356aefSYogesh Narayan Gaur struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master); 832a5356aefSYogesh Narayan Gaur int err = 0; 833a5356aefSYogesh Narayan Gaur 834a5356aefSYogesh Narayan Gaur mutex_lock(&f->lock); 835a5356aefSYogesh Narayan Gaur 836a5356aefSYogesh Narayan Gaur /* Wait for controller being ready. */ 837a5356aefSYogesh Narayan Gaur err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0, 838a5356aefSYogesh Narayan Gaur FSPI_STS0_ARB_IDLE, 1, POLL_TOUT, true); 839a5356aefSYogesh Narayan Gaur WARN_ON(err); 840a5356aefSYogesh Narayan Gaur 841a5356aefSYogesh Narayan Gaur nxp_fspi_select_mem(f, mem->spi); 842a5356aefSYogesh Narayan Gaur 843a5356aefSYogesh Narayan Gaur nxp_fspi_prepare_lut(f, op); 844a5356aefSYogesh Narayan Gaur /* 845a5356aefSYogesh Narayan Gaur * If we have large chunks of data, we read them through the AHB bus 846a5356aefSYogesh Narayan Gaur * by accessing the mapped memory. In all other cases we use 847a5356aefSYogesh Narayan Gaur * IP commands to access the flash. 848a5356aefSYogesh Narayan Gaur */ 849a5356aefSYogesh Narayan Gaur if (op->data.nbytes > (f->devtype_data->rxfifo - 4) && 850a5356aefSYogesh Narayan Gaur op->data.dir == SPI_MEM_DATA_IN) { 851d166a735SHan Xu err = nxp_fspi_read_ahb(f, op); 852a5356aefSYogesh Narayan Gaur } else { 853a5356aefSYogesh Narayan Gaur if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) 854a5356aefSYogesh Narayan Gaur nxp_fspi_fill_txfifo(f, op); 855a5356aefSYogesh Narayan Gaur 856a5356aefSYogesh Narayan Gaur err = nxp_fspi_do_op(f, op); 857a5356aefSYogesh Narayan Gaur } 858a5356aefSYogesh Narayan Gaur 859a5356aefSYogesh Narayan Gaur /* Invalidate the data in the AHB buffer. */ 860a5356aefSYogesh Narayan Gaur nxp_fspi_invalid(f); 861a5356aefSYogesh Narayan Gaur 862a5356aefSYogesh Narayan Gaur mutex_unlock(&f->lock); 863a5356aefSYogesh Narayan Gaur 864a5356aefSYogesh Narayan Gaur return err; 865a5356aefSYogesh Narayan Gaur } 866a5356aefSYogesh Narayan Gaur 867a5356aefSYogesh Narayan Gaur static int nxp_fspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) 868a5356aefSYogesh Narayan Gaur { 869a5356aefSYogesh Narayan Gaur struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master); 870a5356aefSYogesh Narayan Gaur 871a5356aefSYogesh Narayan Gaur if (op->data.dir == SPI_MEM_DATA_OUT) { 872a5356aefSYogesh Narayan Gaur if (op->data.nbytes > f->devtype_data->txfifo) 873a5356aefSYogesh Narayan Gaur op->data.nbytes = f->devtype_data->txfifo; 874a5356aefSYogesh Narayan Gaur } else { 875a5356aefSYogesh Narayan Gaur if (op->data.nbytes > f->devtype_data->ahb_buf_size) 876a5356aefSYogesh Narayan Gaur op->data.nbytes = f->devtype_data->ahb_buf_size; 877a5356aefSYogesh Narayan Gaur else if (op->data.nbytes > (f->devtype_data->rxfifo - 4)) 878a5356aefSYogesh Narayan Gaur op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8); 879a5356aefSYogesh Narayan Gaur } 880a5356aefSYogesh Narayan Gaur 881a5356aefSYogesh Narayan Gaur return 0; 882a5356aefSYogesh Narayan Gaur } 883a5356aefSYogesh Narayan Gaur 884a5356aefSYogesh Narayan Gaur static int nxp_fspi_default_setup(struct nxp_fspi *f) 885a5356aefSYogesh Narayan Gaur { 886a5356aefSYogesh Narayan Gaur void __iomem *base = f->iobase; 887a5356aefSYogesh Narayan Gaur int ret, i; 888a5356aefSYogesh Narayan Gaur u32 reg; 889a5356aefSYogesh Narayan Gaur 890a5356aefSYogesh Narayan Gaur /* disable and unprepare clock to avoid glitch pass to controller */ 891a5356aefSYogesh Narayan Gaur nxp_fspi_clk_disable_unprep(f); 892a5356aefSYogesh Narayan Gaur 893a5356aefSYogesh Narayan Gaur /* the default frequency, we will change it later if necessary. */ 894a5356aefSYogesh Narayan Gaur ret = clk_set_rate(f->clk, 20000000); 895a5356aefSYogesh Narayan Gaur if (ret) 896a5356aefSYogesh Narayan Gaur return ret; 897a5356aefSYogesh Narayan Gaur 898a5356aefSYogesh Narayan Gaur ret = nxp_fspi_clk_prep_enable(f); 899a5356aefSYogesh Narayan Gaur if (ret) 900a5356aefSYogesh Narayan Gaur return ret; 901a5356aefSYogesh Narayan Gaur 902a5356aefSYogesh Narayan Gaur /* Reset the module */ 903a5356aefSYogesh Narayan Gaur /* w1c register, wait unit clear */ 904a5356aefSYogesh Narayan Gaur ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0, 905a5356aefSYogesh Narayan Gaur FSPI_MCR0_SWRST, 0, POLL_TOUT, false); 906a5356aefSYogesh Narayan Gaur WARN_ON(ret); 907a5356aefSYogesh Narayan Gaur 908a5356aefSYogesh Narayan Gaur /* Disable the module */ 909a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_MCR0_MDIS, base + FSPI_MCR0); 910a5356aefSYogesh Narayan Gaur 911a5356aefSYogesh Narayan Gaur /* Reset the DLL register to default value */ 912a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_DLLACR_OVRDEN, base + FSPI_DLLACR); 913a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_DLLBCR_OVRDEN, base + FSPI_DLLBCR); 914a5356aefSYogesh Narayan Gaur 915a5356aefSYogesh Narayan Gaur /* enable module */ 916a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_MCR0_AHB_TIMEOUT(0xFF) | FSPI_MCR0_IP_TIMEOUT(0xFF), 917a5356aefSYogesh Narayan Gaur base + FSPI_MCR0); 918a5356aefSYogesh Narayan Gaur 919a5356aefSYogesh Narayan Gaur /* 920a5356aefSYogesh Narayan Gaur * Disable same device enable bit and configure all slave devices 921a5356aefSYogesh Narayan Gaur * independently. 922a5356aefSYogesh Narayan Gaur */ 923a5356aefSYogesh Narayan Gaur reg = fspi_readl(f, f->iobase + FSPI_MCR2); 924a5356aefSYogesh Narayan Gaur reg = reg & ~(FSPI_MCR2_SAMEDEVICEEN); 925a5356aefSYogesh Narayan Gaur fspi_writel(f, reg, base + FSPI_MCR2); 926a5356aefSYogesh Narayan Gaur 927a5356aefSYogesh Narayan Gaur /* AHB configuration for access buffer 0~7. */ 928a5356aefSYogesh Narayan Gaur for (i = 0; i < 7; i++) 929a5356aefSYogesh Narayan Gaur fspi_writel(f, 0, base + FSPI_AHBRX_BUF0CR0 + 4 * i); 930a5356aefSYogesh Narayan Gaur 931a5356aefSYogesh Narayan Gaur /* 932a5356aefSYogesh Narayan Gaur * Set ADATSZ with the maximum AHB buffer size to improve the read 933a5356aefSYogesh Narayan Gaur * performance. 934a5356aefSYogesh Narayan Gaur */ 935a5356aefSYogesh Narayan Gaur fspi_writel(f, (f->devtype_data->ahb_buf_size / 8 | 936a5356aefSYogesh Narayan Gaur FSPI_AHBRXBUF0CR7_PREF), base + FSPI_AHBRX_BUF7CR0); 937a5356aefSYogesh Narayan Gaur 938a5356aefSYogesh Narayan Gaur /* prefetch and no start address alignment limitation */ 939a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_AHBCR_PREF_EN | FSPI_AHBCR_RDADDROPT, 940a5356aefSYogesh Narayan Gaur base + FSPI_AHBCR); 941a5356aefSYogesh Narayan Gaur 942a5356aefSYogesh Narayan Gaur /* AHB Read - Set lut sequence ID for all CS. */ 943a5356aefSYogesh Narayan Gaur fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA1CR2); 944a5356aefSYogesh Narayan Gaur fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA2CR2); 945a5356aefSYogesh Narayan Gaur fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB1CR2); 946a5356aefSYogesh Narayan Gaur fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB2CR2); 947a5356aefSYogesh Narayan Gaur 948a5356aefSYogesh Narayan Gaur f->selected = -1; 949a5356aefSYogesh Narayan Gaur 950a5356aefSYogesh Narayan Gaur /* enable the interrupt */ 951a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_INTEN_IPCMDDONE, base + FSPI_INTEN); 952a5356aefSYogesh Narayan Gaur 953a5356aefSYogesh Narayan Gaur return 0; 954a5356aefSYogesh Narayan Gaur } 955a5356aefSYogesh Narayan Gaur 956a5356aefSYogesh Narayan Gaur static const char *nxp_fspi_get_name(struct spi_mem *mem) 957a5356aefSYogesh Narayan Gaur { 958a5356aefSYogesh Narayan Gaur struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master); 959a5356aefSYogesh Narayan Gaur struct device *dev = &mem->spi->dev; 960a5356aefSYogesh Narayan Gaur const char *name; 961a5356aefSYogesh Narayan Gaur 962a5356aefSYogesh Narayan Gaur // Set custom name derived from the platform_device of the controller. 963a5356aefSYogesh Narayan Gaur if (of_get_available_child_count(f->dev->of_node) == 1) 964a5356aefSYogesh Narayan Gaur return dev_name(f->dev); 965a5356aefSYogesh Narayan Gaur 966a5356aefSYogesh Narayan Gaur name = devm_kasprintf(dev, GFP_KERNEL, 967a5356aefSYogesh Narayan Gaur "%s-%d", dev_name(f->dev), 968a5356aefSYogesh Narayan Gaur mem->spi->chip_select); 969a5356aefSYogesh Narayan Gaur 970a5356aefSYogesh Narayan Gaur if (!name) { 971a5356aefSYogesh Narayan Gaur dev_err(dev, "failed to get memory for custom flash name\n"); 972a5356aefSYogesh Narayan Gaur return ERR_PTR(-ENOMEM); 973a5356aefSYogesh Narayan Gaur } 974a5356aefSYogesh Narayan Gaur 975a5356aefSYogesh Narayan Gaur return name; 976a5356aefSYogesh Narayan Gaur } 977a5356aefSYogesh Narayan Gaur 978a5356aefSYogesh Narayan Gaur static const struct spi_controller_mem_ops nxp_fspi_mem_ops = { 979a5356aefSYogesh Narayan Gaur .adjust_op_size = nxp_fspi_adjust_op_size, 980a5356aefSYogesh Narayan Gaur .supports_op = nxp_fspi_supports_op, 981a5356aefSYogesh Narayan Gaur .exec_op = nxp_fspi_exec_op, 982a5356aefSYogesh Narayan Gaur .get_name = nxp_fspi_get_name, 983a5356aefSYogesh Narayan Gaur }; 984a5356aefSYogesh Narayan Gaur 985a5356aefSYogesh Narayan Gaur static int nxp_fspi_probe(struct platform_device *pdev) 986a5356aefSYogesh Narayan Gaur { 987a5356aefSYogesh Narayan Gaur struct spi_controller *ctlr; 988a5356aefSYogesh Narayan Gaur struct device *dev = &pdev->dev; 989a5356aefSYogesh Narayan Gaur struct device_node *np = dev->of_node; 990a5356aefSYogesh Narayan Gaur struct resource *res; 991a5356aefSYogesh Narayan Gaur struct nxp_fspi *f; 992a5356aefSYogesh Narayan Gaur int ret; 993a5356aefSYogesh Narayan Gaur 994a5356aefSYogesh Narayan Gaur ctlr = spi_alloc_master(&pdev->dev, sizeof(*f)); 995a5356aefSYogesh Narayan Gaur if (!ctlr) 996a5356aefSYogesh Narayan Gaur return -ENOMEM; 997a5356aefSYogesh Narayan Gaur 998b3281794SYogesh Narayan Gaur ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL | 999b3281794SYogesh Narayan Gaur SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL; 1000a5356aefSYogesh Narayan Gaur 1001a5356aefSYogesh Narayan Gaur f = spi_controller_get_devdata(ctlr); 1002a5356aefSYogesh Narayan Gaur f->dev = dev; 1003a5356aefSYogesh Narayan Gaur f->devtype_data = of_device_get_match_data(dev); 1004a5356aefSYogesh Narayan Gaur if (!f->devtype_data) { 1005a5356aefSYogesh Narayan Gaur ret = -ENODEV; 1006a5356aefSYogesh Narayan Gaur goto err_put_ctrl; 1007a5356aefSYogesh Narayan Gaur } 1008a5356aefSYogesh Narayan Gaur 1009a5356aefSYogesh Narayan Gaur platform_set_drvdata(pdev, f); 1010a5356aefSYogesh Narayan Gaur 1011a5356aefSYogesh Narayan Gaur /* find the resources - configuration register address space */ 1012a5356aefSYogesh Narayan Gaur res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fspi_base"); 1013a5356aefSYogesh Narayan Gaur f->iobase = devm_ioremap_resource(dev, res); 1014a5356aefSYogesh Narayan Gaur if (IS_ERR(f->iobase)) { 1015a5356aefSYogesh Narayan Gaur ret = PTR_ERR(f->iobase); 1016a5356aefSYogesh Narayan Gaur goto err_put_ctrl; 1017a5356aefSYogesh Narayan Gaur } 1018a5356aefSYogesh Narayan Gaur 1019a5356aefSYogesh Narayan Gaur /* find the resources - controller memory mapped space */ 1020a5356aefSYogesh Narayan Gaur res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fspi_mmap"); 1021d166a735SHan Xu if (IS_ERR(res)) { 1022d166a735SHan Xu ret = PTR_ERR(res); 1023a5356aefSYogesh Narayan Gaur goto err_put_ctrl; 1024a5356aefSYogesh Narayan Gaur } 1025a5356aefSYogesh Narayan Gaur 1026a5356aefSYogesh Narayan Gaur /* assign memory mapped starting address and mapped size. */ 1027a5356aefSYogesh Narayan Gaur f->memmap_phy = res->start; 1028a5356aefSYogesh Narayan Gaur f->memmap_phy_size = resource_size(res); 1029a5356aefSYogesh Narayan Gaur 1030a5356aefSYogesh Narayan Gaur /* find the clocks */ 1031a5356aefSYogesh Narayan Gaur f->clk_en = devm_clk_get(dev, "fspi_en"); 1032a5356aefSYogesh Narayan Gaur if (IS_ERR(f->clk_en)) { 1033a5356aefSYogesh Narayan Gaur ret = PTR_ERR(f->clk_en); 1034a5356aefSYogesh Narayan Gaur goto err_put_ctrl; 1035a5356aefSYogesh Narayan Gaur } 1036a5356aefSYogesh Narayan Gaur 1037a5356aefSYogesh Narayan Gaur f->clk = devm_clk_get(dev, "fspi"); 1038a5356aefSYogesh Narayan Gaur if (IS_ERR(f->clk)) { 1039a5356aefSYogesh Narayan Gaur ret = PTR_ERR(f->clk); 1040a5356aefSYogesh Narayan Gaur goto err_put_ctrl; 1041a5356aefSYogesh Narayan Gaur } 1042a5356aefSYogesh Narayan Gaur 1043a5356aefSYogesh Narayan Gaur ret = nxp_fspi_clk_prep_enable(f); 1044a5356aefSYogesh Narayan Gaur if (ret) { 1045a5356aefSYogesh Narayan Gaur dev_err(dev, "can not enable the clock\n"); 1046a5356aefSYogesh Narayan Gaur goto err_put_ctrl; 1047a5356aefSYogesh Narayan Gaur } 1048a5356aefSYogesh Narayan Gaur 1049a5356aefSYogesh Narayan Gaur /* find the irq */ 1050a5356aefSYogesh Narayan Gaur ret = platform_get_irq(pdev, 0); 10516b8ac10eSStephen Boyd if (ret < 0) 1052a5356aefSYogesh Narayan Gaur goto err_disable_clk; 1053a5356aefSYogesh Narayan Gaur 1054a5356aefSYogesh Narayan Gaur ret = devm_request_irq(dev, ret, 1055a5356aefSYogesh Narayan Gaur nxp_fspi_irq_handler, 0, pdev->name, f); 1056a5356aefSYogesh Narayan Gaur if (ret) { 1057a5356aefSYogesh Narayan Gaur dev_err(dev, "failed to request irq: %d\n", ret); 1058a5356aefSYogesh Narayan Gaur goto err_disable_clk; 1059a5356aefSYogesh Narayan Gaur } 1060a5356aefSYogesh Narayan Gaur 1061a5356aefSYogesh Narayan Gaur mutex_init(&f->lock); 1062a5356aefSYogesh Narayan Gaur 1063a5356aefSYogesh Narayan Gaur ctlr->bus_num = -1; 1064a5356aefSYogesh Narayan Gaur ctlr->num_chipselect = NXP_FSPI_MAX_CHIPSELECT; 1065a5356aefSYogesh Narayan Gaur ctlr->mem_ops = &nxp_fspi_mem_ops; 1066a5356aefSYogesh Narayan Gaur 1067a5356aefSYogesh Narayan Gaur nxp_fspi_default_setup(f); 1068a5356aefSYogesh Narayan Gaur 1069a5356aefSYogesh Narayan Gaur ctlr->dev.of_node = np; 1070a5356aefSYogesh Narayan Gaur 107169c23dbfSChuhong Yuan ret = devm_spi_register_controller(&pdev->dev, ctlr); 1072a5356aefSYogesh Narayan Gaur if (ret) 1073a5356aefSYogesh Narayan Gaur goto err_destroy_mutex; 1074a5356aefSYogesh Narayan Gaur 1075a5356aefSYogesh Narayan Gaur return 0; 1076a5356aefSYogesh Narayan Gaur 1077a5356aefSYogesh Narayan Gaur err_destroy_mutex: 1078a5356aefSYogesh Narayan Gaur mutex_destroy(&f->lock); 1079a5356aefSYogesh Narayan Gaur 1080a5356aefSYogesh Narayan Gaur err_disable_clk: 1081a5356aefSYogesh Narayan Gaur nxp_fspi_clk_disable_unprep(f); 1082a5356aefSYogesh Narayan Gaur 1083a5356aefSYogesh Narayan Gaur err_put_ctrl: 1084a5356aefSYogesh Narayan Gaur spi_controller_put(ctlr); 1085a5356aefSYogesh Narayan Gaur 1086a5356aefSYogesh Narayan Gaur dev_err(dev, "NXP FSPI probe failed\n"); 1087a5356aefSYogesh Narayan Gaur return ret; 1088a5356aefSYogesh Narayan Gaur } 1089a5356aefSYogesh Narayan Gaur 1090a5356aefSYogesh Narayan Gaur static int nxp_fspi_remove(struct platform_device *pdev) 1091a5356aefSYogesh Narayan Gaur { 1092a5356aefSYogesh Narayan Gaur struct nxp_fspi *f = platform_get_drvdata(pdev); 1093a5356aefSYogesh Narayan Gaur 1094a5356aefSYogesh Narayan Gaur /* disable the hardware */ 1095a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_MCR0_MDIS, f->iobase + FSPI_MCR0); 1096a5356aefSYogesh Narayan Gaur 1097a5356aefSYogesh Narayan Gaur nxp_fspi_clk_disable_unprep(f); 1098a5356aefSYogesh Narayan Gaur 1099a5356aefSYogesh Narayan Gaur mutex_destroy(&f->lock); 1100a5356aefSYogesh Narayan Gaur 1101d166a735SHan Xu if (f->ahb_addr) 1102d166a735SHan Xu iounmap(f->ahb_addr); 1103d166a735SHan Xu 1104a5356aefSYogesh Narayan Gaur return 0; 1105a5356aefSYogesh Narayan Gaur } 1106a5356aefSYogesh Narayan Gaur 1107a5356aefSYogesh Narayan Gaur static int nxp_fspi_suspend(struct device *dev) 1108a5356aefSYogesh Narayan Gaur { 1109a5356aefSYogesh Narayan Gaur return 0; 1110a5356aefSYogesh Narayan Gaur } 1111a5356aefSYogesh Narayan Gaur 1112a5356aefSYogesh Narayan Gaur static int nxp_fspi_resume(struct device *dev) 1113a5356aefSYogesh Narayan Gaur { 1114a5356aefSYogesh Narayan Gaur struct nxp_fspi *f = dev_get_drvdata(dev); 1115a5356aefSYogesh Narayan Gaur 1116a5356aefSYogesh Narayan Gaur nxp_fspi_default_setup(f); 1117a5356aefSYogesh Narayan Gaur 1118a5356aefSYogesh Narayan Gaur return 0; 1119a5356aefSYogesh Narayan Gaur } 1120a5356aefSYogesh Narayan Gaur 1121a5356aefSYogesh Narayan Gaur static const struct of_device_id nxp_fspi_dt_ids[] = { 1122a5356aefSYogesh Narayan Gaur { .compatible = "nxp,lx2160a-fspi", .data = (void *)&lx2160a_data, }, 1123941be8a7SHan Xu { .compatible = "nxp,imx8mm-fspi", .data = (void *)&imx8mm_data, }, 1124941be8a7SHan Xu { .compatible = "nxp,imx8qxp-fspi", .data = (void *)&imx8qxp_data, }, 1125a5356aefSYogesh Narayan Gaur { /* sentinel */ } 1126a5356aefSYogesh Narayan Gaur }; 1127a5356aefSYogesh Narayan Gaur MODULE_DEVICE_TABLE(of, nxp_fspi_dt_ids); 1128a5356aefSYogesh Narayan Gaur 1129a5356aefSYogesh Narayan Gaur static const struct dev_pm_ops nxp_fspi_pm_ops = { 1130a5356aefSYogesh Narayan Gaur .suspend = nxp_fspi_suspend, 1131a5356aefSYogesh Narayan Gaur .resume = nxp_fspi_resume, 1132a5356aefSYogesh Narayan Gaur }; 1133a5356aefSYogesh Narayan Gaur 1134a5356aefSYogesh Narayan Gaur static struct platform_driver nxp_fspi_driver = { 1135a5356aefSYogesh Narayan Gaur .driver = { 1136a5356aefSYogesh Narayan Gaur .name = "nxp-fspi", 1137a5356aefSYogesh Narayan Gaur .of_match_table = nxp_fspi_dt_ids, 1138a5356aefSYogesh Narayan Gaur .pm = &nxp_fspi_pm_ops, 1139a5356aefSYogesh Narayan Gaur }, 1140a5356aefSYogesh Narayan Gaur .probe = nxp_fspi_probe, 1141a5356aefSYogesh Narayan Gaur .remove = nxp_fspi_remove, 1142a5356aefSYogesh Narayan Gaur }; 1143a5356aefSYogesh Narayan Gaur module_platform_driver(nxp_fspi_driver); 1144a5356aefSYogesh Narayan Gaur 1145a5356aefSYogesh Narayan Gaur MODULE_DESCRIPTION("NXP FSPI Controller Driver"); 1146a5356aefSYogesh Narayan Gaur MODULE_AUTHOR("NXP Semiconductor"); 1147a5356aefSYogesh Narayan Gaur MODULE_AUTHOR("Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>"); 1148ce6f0697SYogesh Narayan Gaur MODULE_AUTHOR("Boris Brezillon <bbrezillon@kernel.org>"); 1149a5356aefSYogesh Narayan Gaur MODULE_AUTHOR("Frieder Schrempf <frieder.schrempf@kontron.de>"); 1150ce6f0697SYogesh Narayan Gaur MODULE_LICENSE("GPL v2"); 1151