1a5356aefSYogesh Narayan Gaur // SPDX-License-Identifier: GPL-2.0+ 2a5356aefSYogesh Narayan Gaur 3a5356aefSYogesh Narayan Gaur /* 4a5356aefSYogesh Narayan Gaur * NXP FlexSPI(FSPI) controller driver. 5a5356aefSYogesh Narayan Gaur * 655ab8487Skuldip dwivedi * Copyright 2019-2020 NXP 755ab8487Skuldip dwivedi * Copyright 2020 Puresoftware Ltd. 8a5356aefSYogesh Narayan Gaur * 9a5356aefSYogesh Narayan Gaur * FlexSPI is a flexsible SPI host controller which supports two SPI 10a5356aefSYogesh Narayan Gaur * channels and up to 4 external devices. Each channel supports 11a5356aefSYogesh Narayan Gaur * Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional 12a5356aefSYogesh Narayan Gaur * data lines). 13a5356aefSYogesh Narayan Gaur * 14a5356aefSYogesh Narayan Gaur * FlexSPI controller is driven by the LUT(Look-up Table) registers 15a5356aefSYogesh Narayan Gaur * LUT registers are a look-up-table for sequences of instructions. 16a5356aefSYogesh Narayan Gaur * A valid sequence consists of four LUT registers. 17a5356aefSYogesh Narayan Gaur * Maximum 32 LUT sequences can be programmed simultaneously. 18a5356aefSYogesh Narayan Gaur * 19a5356aefSYogesh Narayan Gaur * LUTs are being created at run-time based on the commands passed 20a5356aefSYogesh Narayan Gaur * from the spi-mem framework, thus using single LUT index. 21a5356aefSYogesh Narayan Gaur * 22a5356aefSYogesh Narayan Gaur * Software triggered Flash read/write access by IP Bus. 23a5356aefSYogesh Narayan Gaur * 24a5356aefSYogesh Narayan Gaur * Memory mapped read access by AHB Bus. 25a5356aefSYogesh Narayan Gaur * 26a5356aefSYogesh Narayan Gaur * Based on SPI MEM interface and spi-fsl-qspi.c driver. 27a5356aefSYogesh Narayan Gaur * 28a5356aefSYogesh Narayan Gaur * Author: 29a5356aefSYogesh Narayan Gaur * Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com> 30ce6f0697SYogesh Narayan Gaur * Boris Brezillon <bbrezillon@kernel.org> 31a5356aefSYogesh Narayan Gaur * Frieder Schrempf <frieder.schrempf@kontron.de> 32a5356aefSYogesh Narayan Gaur */ 33a5356aefSYogesh Narayan Gaur 3455ab8487Skuldip dwivedi #include <linux/acpi.h> 35a5356aefSYogesh Narayan Gaur #include <linux/bitops.h> 36a5356aefSYogesh Narayan Gaur #include <linux/clk.h> 37a5356aefSYogesh Narayan Gaur #include <linux/completion.h> 38a5356aefSYogesh Narayan Gaur #include <linux/delay.h> 39a5356aefSYogesh Narayan Gaur #include <linux/err.h> 40a5356aefSYogesh Narayan Gaur #include <linux/errno.h> 41a5356aefSYogesh Narayan Gaur #include <linux/interrupt.h> 42a5356aefSYogesh Narayan Gaur #include <linux/io.h> 43a5356aefSYogesh Narayan Gaur #include <linux/iopoll.h> 44a5356aefSYogesh Narayan Gaur #include <linux/jiffies.h> 45a5356aefSYogesh Narayan Gaur #include <linux/kernel.h> 46a5356aefSYogesh Narayan Gaur #include <linux/module.h> 47a5356aefSYogesh Narayan Gaur #include <linux/mutex.h> 48a5356aefSYogesh Narayan Gaur #include <linux/of.h> 49a5356aefSYogesh Narayan Gaur #include <linux/of_device.h> 50a5356aefSYogesh Narayan Gaur #include <linux/platform_device.h> 51a5356aefSYogesh Narayan Gaur #include <linux/pm_qos.h> 52a5356aefSYogesh Narayan Gaur #include <linux/sizes.h> 53a5356aefSYogesh Narayan Gaur 54a5356aefSYogesh Narayan Gaur #include <linux/spi/spi.h> 55a5356aefSYogesh Narayan Gaur #include <linux/spi/spi-mem.h> 56a5356aefSYogesh Narayan Gaur 57a5356aefSYogesh Narayan Gaur /* 58a5356aefSYogesh Narayan Gaur * The driver only uses one single LUT entry, that is updated on 59a5356aefSYogesh Narayan Gaur * each call of exec_op(). Index 0 is preset at boot with a basic 60a5356aefSYogesh Narayan Gaur * read operation, so let's use the last entry (31). 61a5356aefSYogesh Narayan Gaur */ 62a5356aefSYogesh Narayan Gaur #define SEQID_LUT 31 63a5356aefSYogesh Narayan Gaur 64a5356aefSYogesh Narayan Gaur /* Registers used by the driver */ 65a5356aefSYogesh Narayan Gaur #define FSPI_MCR0 0x00 66a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_AHB_TIMEOUT(x) ((x) << 24) 67a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_IP_TIMEOUT(x) ((x) << 16) 68a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_LEARN_EN BIT(15) 69a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_SCRFRUN_EN BIT(14) 70a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_OCTCOMB_EN BIT(13) 71a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_DOZE_EN BIT(12) 72a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_HSEN BIT(11) 73a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_SERCLKDIV BIT(8) 74a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_ATDF_EN BIT(7) 75a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_ARDF_EN BIT(6) 76a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_RXCLKSRC(x) ((x) << 4) 77a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_END_CFG(x) ((x) << 2) 78a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_MDIS BIT(1) 79a5356aefSYogesh Narayan Gaur #define FSPI_MCR0_SWRST BIT(0) 80a5356aefSYogesh Narayan Gaur 81a5356aefSYogesh Narayan Gaur #define FSPI_MCR1 0x04 82a5356aefSYogesh Narayan Gaur #define FSPI_MCR1_SEQ_TIMEOUT(x) ((x) << 16) 83a5356aefSYogesh Narayan Gaur #define FSPI_MCR1_AHB_TIMEOUT(x) (x) 84a5356aefSYogesh Narayan Gaur 85a5356aefSYogesh Narayan Gaur #define FSPI_MCR2 0x08 86a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_IDLE_WAIT(x) ((x) << 24) 87a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_SAMEDEVICEEN BIT(15) 88a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_CLRLRPHS BIT(14) 89a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_ABRDATSZ BIT(8) 90a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_ABRLEARN BIT(7) 91a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_ABR_READ BIT(6) 92a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_ABRWRITE BIT(5) 93a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_ABRDUMMY BIT(4) 94a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_ABR_MODE BIT(3) 95a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_ABRCADDR BIT(2) 96a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_ABRRADDR BIT(1) 97a5356aefSYogesh Narayan Gaur #define FSPI_MCR2_ABR_CMD BIT(0) 98a5356aefSYogesh Narayan Gaur 99a5356aefSYogesh Narayan Gaur #define FSPI_AHBCR 0x0c 100a5356aefSYogesh Narayan Gaur #define FSPI_AHBCR_RDADDROPT BIT(6) 101a5356aefSYogesh Narayan Gaur #define FSPI_AHBCR_PREF_EN BIT(5) 102a5356aefSYogesh Narayan Gaur #define FSPI_AHBCR_BUFF_EN BIT(4) 103a5356aefSYogesh Narayan Gaur #define FSPI_AHBCR_CACH_EN BIT(3) 104a5356aefSYogesh Narayan Gaur #define FSPI_AHBCR_CLRTXBUF BIT(2) 105a5356aefSYogesh Narayan Gaur #define FSPI_AHBCR_CLRRXBUF BIT(1) 106a5356aefSYogesh Narayan Gaur #define FSPI_AHBCR_PAR_EN BIT(0) 107a5356aefSYogesh Narayan Gaur 108a5356aefSYogesh Narayan Gaur #define FSPI_INTEN 0x10 109a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_SCLKSBWR BIT(9) 110a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_SCLKSBRD BIT(8) 111a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_DATALRNFL BIT(7) 112a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_IPTXWE BIT(6) 113a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_IPRXWA BIT(5) 114a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_AHBCMDERR BIT(4) 115a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_IPCMDERR BIT(3) 116a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_AHBCMDGE BIT(2) 117a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_IPCMDGE BIT(1) 118a5356aefSYogesh Narayan Gaur #define FSPI_INTEN_IPCMDDONE BIT(0) 119a5356aefSYogesh Narayan Gaur 120a5356aefSYogesh Narayan Gaur #define FSPI_INTR 0x14 121a5356aefSYogesh Narayan Gaur #define FSPI_INTR_SCLKSBWR BIT(9) 122a5356aefSYogesh Narayan Gaur #define FSPI_INTR_SCLKSBRD BIT(8) 123a5356aefSYogesh Narayan Gaur #define FSPI_INTR_DATALRNFL BIT(7) 124a5356aefSYogesh Narayan Gaur #define FSPI_INTR_IPTXWE BIT(6) 125a5356aefSYogesh Narayan Gaur #define FSPI_INTR_IPRXWA BIT(5) 126a5356aefSYogesh Narayan Gaur #define FSPI_INTR_AHBCMDERR BIT(4) 127a5356aefSYogesh Narayan Gaur #define FSPI_INTR_IPCMDERR BIT(3) 128a5356aefSYogesh Narayan Gaur #define FSPI_INTR_AHBCMDGE BIT(2) 129a5356aefSYogesh Narayan Gaur #define FSPI_INTR_IPCMDGE BIT(1) 130a5356aefSYogesh Narayan Gaur #define FSPI_INTR_IPCMDDONE BIT(0) 131a5356aefSYogesh Narayan Gaur 132a5356aefSYogesh Narayan Gaur #define FSPI_LUTKEY 0x18 133a5356aefSYogesh Narayan Gaur #define FSPI_LUTKEY_VALUE 0x5AF05AF0 134a5356aefSYogesh Narayan Gaur 135a5356aefSYogesh Narayan Gaur #define FSPI_LCKCR 0x1C 136a5356aefSYogesh Narayan Gaur 137a5356aefSYogesh Narayan Gaur #define FSPI_LCKER_LOCK 0x1 138a5356aefSYogesh Narayan Gaur #define FSPI_LCKER_UNLOCK 0x2 139a5356aefSYogesh Narayan Gaur 140a5356aefSYogesh Narayan Gaur #define FSPI_BUFXCR_INVALID_MSTRID 0xE 141a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF0CR0 0x20 142a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF1CR0 0x24 143a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF2CR0 0x28 144a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF3CR0 0x2C 145a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF4CR0 0x30 146a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF5CR0 0x34 147a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF6CR0 0x38 148a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF7CR0 0x3C 149a5356aefSYogesh Narayan Gaur #define FSPI_AHBRXBUF0CR7_PREF BIT(31) 150a5356aefSYogesh Narayan Gaur 151a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF0CR1 0x40 152a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF1CR1 0x44 153a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF2CR1 0x48 154a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF3CR1 0x4C 155a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF4CR1 0x50 156a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF5CR1 0x54 157a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF6CR1 0x58 158a5356aefSYogesh Narayan Gaur #define FSPI_AHBRX_BUF7CR1 0x5C 159a5356aefSYogesh Narayan Gaur 160a5356aefSYogesh Narayan Gaur #define FSPI_FLSHA1CR0 0x60 161a5356aefSYogesh Narayan Gaur #define FSPI_FLSHA2CR0 0x64 162a5356aefSYogesh Narayan Gaur #define FSPI_FLSHB1CR0 0x68 163a5356aefSYogesh Narayan Gaur #define FSPI_FLSHB2CR0 0x6C 164a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR0_SZ_KB 10 165a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR0_SZ(x) ((x) >> FSPI_FLSHXCR0_SZ_KB) 166a5356aefSYogesh Narayan Gaur 167a5356aefSYogesh Narayan Gaur #define FSPI_FLSHA1CR1 0x70 168a5356aefSYogesh Narayan Gaur #define FSPI_FLSHA2CR1 0x74 169a5356aefSYogesh Narayan Gaur #define FSPI_FLSHB1CR1 0x78 170a5356aefSYogesh Narayan Gaur #define FSPI_FLSHB2CR1 0x7C 171a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR1_CSINTR(x) ((x) << 16) 172a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR1_CAS(x) ((x) << 11) 173a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR1_WA BIT(10) 174a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR1_TCSH(x) ((x) << 5) 175a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR1_TCSS(x) (x) 176a5356aefSYogesh Narayan Gaur 177a5356aefSYogesh Narayan Gaur #define FSPI_FLSHA1CR2 0x80 178a5356aefSYogesh Narayan Gaur #define FSPI_FLSHA2CR2 0x84 179a5356aefSYogesh Narayan Gaur #define FSPI_FLSHB1CR2 0x88 180a5356aefSYogesh Narayan Gaur #define FSPI_FLSHB2CR2 0x8C 181a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR2_CLRINSP BIT(24) 182a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR2_AWRWAIT BIT(16) 183a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR2_AWRSEQN_SHIFT 13 184a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR2_AWRSEQI_SHIFT 8 185a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR2_ARDSEQN_SHIFT 5 186a5356aefSYogesh Narayan Gaur #define FSPI_FLSHXCR2_ARDSEQI_SHIFT 0 187a5356aefSYogesh Narayan Gaur 188a5356aefSYogesh Narayan Gaur #define FSPI_IPCR0 0xA0 189a5356aefSYogesh Narayan Gaur 190a5356aefSYogesh Narayan Gaur #define FSPI_IPCR1 0xA4 191a5356aefSYogesh Narayan Gaur #define FSPI_IPCR1_IPAREN BIT(31) 192a5356aefSYogesh Narayan Gaur #define FSPI_IPCR1_SEQNUM_SHIFT 24 193a5356aefSYogesh Narayan Gaur #define FSPI_IPCR1_SEQID_SHIFT 16 194a5356aefSYogesh Narayan Gaur #define FSPI_IPCR1_IDATSZ(x) (x) 195a5356aefSYogesh Narayan Gaur 196a5356aefSYogesh Narayan Gaur #define FSPI_IPCMD 0xB0 197a5356aefSYogesh Narayan Gaur #define FSPI_IPCMD_TRG BIT(0) 198a5356aefSYogesh Narayan Gaur 199a5356aefSYogesh Narayan Gaur #define FSPI_DLPR 0xB4 200a5356aefSYogesh Narayan Gaur 201a5356aefSYogesh Narayan Gaur #define FSPI_IPRXFCR 0xB8 202a5356aefSYogesh Narayan Gaur #define FSPI_IPRXFCR_CLR BIT(0) 203a5356aefSYogesh Narayan Gaur #define FSPI_IPRXFCR_DMA_EN BIT(1) 204a5356aefSYogesh Narayan Gaur #define FSPI_IPRXFCR_WMRK(x) ((x) << 2) 205a5356aefSYogesh Narayan Gaur 206a5356aefSYogesh Narayan Gaur #define FSPI_IPTXFCR 0xBC 207a5356aefSYogesh Narayan Gaur #define FSPI_IPTXFCR_CLR BIT(0) 208a5356aefSYogesh Narayan Gaur #define FSPI_IPTXFCR_DMA_EN BIT(1) 209a5356aefSYogesh Narayan Gaur #define FSPI_IPTXFCR_WMRK(x) ((x) << 2) 210a5356aefSYogesh Narayan Gaur 211a5356aefSYogesh Narayan Gaur #define FSPI_DLLACR 0xC0 212a5356aefSYogesh Narayan Gaur #define FSPI_DLLACR_OVRDEN BIT(8) 213a5356aefSYogesh Narayan Gaur 214a5356aefSYogesh Narayan Gaur #define FSPI_DLLBCR 0xC4 215a5356aefSYogesh Narayan Gaur #define FSPI_DLLBCR_OVRDEN BIT(8) 216a5356aefSYogesh Narayan Gaur 217a5356aefSYogesh Narayan Gaur #define FSPI_STS0 0xE0 218a5356aefSYogesh Narayan Gaur #define FSPI_STS0_DLPHB(x) ((x) << 8) 219a5356aefSYogesh Narayan Gaur #define FSPI_STS0_DLPHA(x) ((x) << 4) 220a5356aefSYogesh Narayan Gaur #define FSPI_STS0_CMD_SRC(x) ((x) << 2) 221a5356aefSYogesh Narayan Gaur #define FSPI_STS0_ARB_IDLE BIT(1) 222a5356aefSYogesh Narayan Gaur #define FSPI_STS0_SEQ_IDLE BIT(0) 223a5356aefSYogesh Narayan Gaur 224a5356aefSYogesh Narayan Gaur #define FSPI_STS1 0xE4 225a5356aefSYogesh Narayan Gaur #define FSPI_STS1_IP_ERRCD(x) ((x) << 24) 226a5356aefSYogesh Narayan Gaur #define FSPI_STS1_IP_ERRID(x) ((x) << 16) 227a5356aefSYogesh Narayan Gaur #define FSPI_STS1_AHB_ERRCD(x) ((x) << 8) 228a5356aefSYogesh Narayan Gaur #define FSPI_STS1_AHB_ERRID(x) (x) 229a5356aefSYogesh Narayan Gaur 230a5356aefSYogesh Narayan Gaur #define FSPI_AHBSPNST 0xEC 231a5356aefSYogesh Narayan Gaur #define FSPI_AHBSPNST_DATLFT(x) ((x) << 16) 232a5356aefSYogesh Narayan Gaur #define FSPI_AHBSPNST_BUFID(x) ((x) << 1) 233a5356aefSYogesh Narayan Gaur #define FSPI_AHBSPNST_ACTIVE BIT(0) 234a5356aefSYogesh Narayan Gaur 235a5356aefSYogesh Narayan Gaur #define FSPI_IPRXFSTS 0xF0 236a5356aefSYogesh Narayan Gaur #define FSPI_IPRXFSTS_RDCNTR(x) ((x) << 16) 237a5356aefSYogesh Narayan Gaur #define FSPI_IPRXFSTS_FILL(x) (x) 238a5356aefSYogesh Narayan Gaur 239a5356aefSYogesh Narayan Gaur #define FSPI_IPTXFSTS 0xF4 240a5356aefSYogesh Narayan Gaur #define FSPI_IPTXFSTS_WRCNTR(x) ((x) << 16) 241a5356aefSYogesh Narayan Gaur #define FSPI_IPTXFSTS_FILL(x) (x) 242a5356aefSYogesh Narayan Gaur 243a5356aefSYogesh Narayan Gaur #define FSPI_RFDR 0x100 244a5356aefSYogesh Narayan Gaur #define FSPI_TFDR 0x180 245a5356aefSYogesh Narayan Gaur 246a5356aefSYogesh Narayan Gaur #define FSPI_LUT_BASE 0x200 247a5356aefSYogesh Narayan Gaur #define FSPI_LUT_OFFSET (SEQID_LUT * 4 * 4) 248a5356aefSYogesh Narayan Gaur #define FSPI_LUT_REG(idx) \ 249a5356aefSYogesh Narayan Gaur (FSPI_LUT_BASE + FSPI_LUT_OFFSET + (idx) * 4) 250a5356aefSYogesh Narayan Gaur 251a5356aefSYogesh Narayan Gaur /* register map end */ 252a5356aefSYogesh Narayan Gaur 253a5356aefSYogesh Narayan Gaur /* Instruction set for the LUT register. */ 254a5356aefSYogesh Narayan Gaur #define LUT_STOP 0x00 255a5356aefSYogesh Narayan Gaur #define LUT_CMD 0x01 256a5356aefSYogesh Narayan Gaur #define LUT_ADDR 0x02 257a5356aefSYogesh Narayan Gaur #define LUT_CADDR_SDR 0x03 258a5356aefSYogesh Narayan Gaur #define LUT_MODE 0x04 259a5356aefSYogesh Narayan Gaur #define LUT_MODE2 0x05 260a5356aefSYogesh Narayan Gaur #define LUT_MODE4 0x06 261a5356aefSYogesh Narayan Gaur #define LUT_MODE8 0x07 262a5356aefSYogesh Narayan Gaur #define LUT_NXP_WRITE 0x08 263a5356aefSYogesh Narayan Gaur #define LUT_NXP_READ 0x09 264a5356aefSYogesh Narayan Gaur #define LUT_LEARN_SDR 0x0A 265a5356aefSYogesh Narayan Gaur #define LUT_DATSZ_SDR 0x0B 266a5356aefSYogesh Narayan Gaur #define LUT_DUMMY 0x0C 267a5356aefSYogesh Narayan Gaur #define LUT_DUMMY_RWDS_SDR 0x0D 268a5356aefSYogesh Narayan Gaur #define LUT_JMP_ON_CS 0x1F 269a5356aefSYogesh Narayan Gaur #define LUT_CMD_DDR 0x21 270a5356aefSYogesh Narayan Gaur #define LUT_ADDR_DDR 0x22 271a5356aefSYogesh Narayan Gaur #define LUT_CADDR_DDR 0x23 272a5356aefSYogesh Narayan Gaur #define LUT_MODE_DDR 0x24 273a5356aefSYogesh Narayan Gaur #define LUT_MODE2_DDR 0x25 274a5356aefSYogesh Narayan Gaur #define LUT_MODE4_DDR 0x26 275a5356aefSYogesh Narayan Gaur #define LUT_MODE8_DDR 0x27 276a5356aefSYogesh Narayan Gaur #define LUT_WRITE_DDR 0x28 277a5356aefSYogesh Narayan Gaur #define LUT_READ_DDR 0x29 278a5356aefSYogesh Narayan Gaur #define LUT_LEARN_DDR 0x2A 279a5356aefSYogesh Narayan Gaur #define LUT_DATSZ_DDR 0x2B 280a5356aefSYogesh Narayan Gaur #define LUT_DUMMY_DDR 0x2C 281a5356aefSYogesh Narayan Gaur #define LUT_DUMMY_RWDS_DDR 0x2D 282a5356aefSYogesh Narayan Gaur 283a5356aefSYogesh Narayan Gaur /* 284a5356aefSYogesh Narayan Gaur * Calculate number of required PAD bits for LUT register. 285a5356aefSYogesh Narayan Gaur * 286a5356aefSYogesh Narayan Gaur * The pad stands for the number of IO lines [0:7]. 287a5356aefSYogesh Narayan Gaur * For example, the octal read needs eight IO lines, 288a5356aefSYogesh Narayan Gaur * so you should use LUT_PAD(8). This macro 289a5356aefSYogesh Narayan Gaur * returns 3 i.e. use eight (2^3) IP lines for read. 290a5356aefSYogesh Narayan Gaur */ 291a5356aefSYogesh Narayan Gaur #define LUT_PAD(x) (fls(x) - 1) 292a5356aefSYogesh Narayan Gaur 293a5356aefSYogesh Narayan Gaur /* 294a5356aefSYogesh Narayan Gaur * Macro for constructing the LUT entries with the following 295a5356aefSYogesh Narayan Gaur * register layout: 296a5356aefSYogesh Narayan Gaur * 297a5356aefSYogesh Narayan Gaur * --------------------------------------------------- 298a5356aefSYogesh Narayan Gaur * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 | 299a5356aefSYogesh Narayan Gaur * --------------------------------------------------- 300a5356aefSYogesh Narayan Gaur */ 301a5356aefSYogesh Narayan Gaur #define PAD_SHIFT 8 302a5356aefSYogesh Narayan Gaur #define INSTR_SHIFT 10 303a5356aefSYogesh Narayan Gaur #define OPRND_SHIFT 16 304a5356aefSYogesh Narayan Gaur 305a5356aefSYogesh Narayan Gaur /* Macros for constructing the LUT register. */ 306a5356aefSYogesh Narayan Gaur #define LUT_DEF(idx, ins, pad, opr) \ 307a5356aefSYogesh Narayan Gaur ((((ins) << INSTR_SHIFT) | ((pad) << PAD_SHIFT) | \ 308a5356aefSYogesh Narayan Gaur (opr)) << (((idx) % 2) * OPRND_SHIFT)) 309a5356aefSYogesh Narayan Gaur 310a5356aefSYogesh Narayan Gaur #define POLL_TOUT 5000 311a5356aefSYogesh Narayan Gaur #define NXP_FSPI_MAX_CHIPSELECT 4 312d166a735SHan Xu #define NXP_FSPI_MIN_IOMAP SZ_4M 313a5356aefSYogesh Narayan Gaur 314a5356aefSYogesh Narayan Gaur struct nxp_fspi_devtype_data { 315a5356aefSYogesh Narayan Gaur unsigned int rxfifo; 316a5356aefSYogesh Narayan Gaur unsigned int txfifo; 317a5356aefSYogesh Narayan Gaur unsigned int ahb_buf_size; 318a5356aefSYogesh Narayan Gaur unsigned int quirks; 319a5356aefSYogesh Narayan Gaur bool little_endian; 320a5356aefSYogesh Narayan Gaur }; 321a5356aefSYogesh Narayan Gaur 322a5356aefSYogesh Narayan Gaur static const struct nxp_fspi_devtype_data lx2160a_data = { 323a5356aefSYogesh Narayan Gaur .rxfifo = SZ_512, /* (64 * 64 bits) */ 324a5356aefSYogesh Narayan Gaur .txfifo = SZ_1K, /* (128 * 64 bits) */ 325a5356aefSYogesh Narayan Gaur .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ 326a5356aefSYogesh Narayan Gaur .quirks = 0, 327a5356aefSYogesh Narayan Gaur .little_endian = true, /* little-endian */ 328a5356aefSYogesh Narayan Gaur }; 329a5356aefSYogesh Narayan Gaur 330941be8a7SHan Xu static const struct nxp_fspi_devtype_data imx8mm_data = { 331941be8a7SHan Xu .rxfifo = SZ_512, /* (64 * 64 bits) */ 332941be8a7SHan Xu .txfifo = SZ_1K, /* (128 * 64 bits) */ 333941be8a7SHan Xu .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ 334941be8a7SHan Xu .quirks = 0, 335941be8a7SHan Xu .little_endian = true, /* little-endian */ 336941be8a7SHan Xu }; 337941be8a7SHan Xu 338941be8a7SHan Xu static const struct nxp_fspi_devtype_data imx8qxp_data = { 339941be8a7SHan Xu .rxfifo = SZ_512, /* (64 * 64 bits) */ 340941be8a7SHan Xu .txfifo = SZ_1K, /* (128 * 64 bits) */ 341941be8a7SHan Xu .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ 342941be8a7SHan Xu .quirks = 0, 343941be8a7SHan Xu .little_endian = true, /* little-endian */ 344941be8a7SHan Xu }; 345941be8a7SHan Xu 346a5356aefSYogesh Narayan Gaur struct nxp_fspi { 347a5356aefSYogesh Narayan Gaur void __iomem *iobase; 348a5356aefSYogesh Narayan Gaur void __iomem *ahb_addr; 349a5356aefSYogesh Narayan Gaur u32 memmap_phy; 350a5356aefSYogesh Narayan Gaur u32 memmap_phy_size; 351d166a735SHan Xu u32 memmap_start; 352d166a735SHan Xu u32 memmap_len; 353a5356aefSYogesh Narayan Gaur struct clk *clk, *clk_en; 354a5356aefSYogesh Narayan Gaur struct device *dev; 355a5356aefSYogesh Narayan Gaur struct completion c; 356a5356aefSYogesh Narayan Gaur const struct nxp_fspi_devtype_data *devtype_data; 357a5356aefSYogesh Narayan Gaur struct mutex lock; 358a5356aefSYogesh Narayan Gaur struct pm_qos_request pm_qos_req; 359a5356aefSYogesh Narayan Gaur int selected; 360a5356aefSYogesh Narayan Gaur }; 361a5356aefSYogesh Narayan Gaur 362a5356aefSYogesh Narayan Gaur /* 363a5356aefSYogesh Narayan Gaur * R/W functions for big- or little-endian registers: 364a5356aefSYogesh Narayan Gaur * The FSPI controller's endianness is independent of 365a5356aefSYogesh Narayan Gaur * the CPU core's endianness. So far, although the CPU 366a5356aefSYogesh Narayan Gaur * core is little-endian the FSPI controller can use 367a5356aefSYogesh Narayan Gaur * big-endian or little-endian. 368a5356aefSYogesh Narayan Gaur */ 369a5356aefSYogesh Narayan Gaur static void fspi_writel(struct nxp_fspi *f, u32 val, void __iomem *addr) 370a5356aefSYogesh Narayan Gaur { 371a5356aefSYogesh Narayan Gaur if (f->devtype_data->little_endian) 372a5356aefSYogesh Narayan Gaur iowrite32(val, addr); 373a5356aefSYogesh Narayan Gaur else 374a5356aefSYogesh Narayan Gaur iowrite32be(val, addr); 375a5356aefSYogesh Narayan Gaur } 376a5356aefSYogesh Narayan Gaur 377a5356aefSYogesh Narayan Gaur static u32 fspi_readl(struct nxp_fspi *f, void __iomem *addr) 378a5356aefSYogesh Narayan Gaur { 379a5356aefSYogesh Narayan Gaur if (f->devtype_data->little_endian) 380a5356aefSYogesh Narayan Gaur return ioread32(addr); 381a5356aefSYogesh Narayan Gaur else 382a5356aefSYogesh Narayan Gaur return ioread32be(addr); 383a5356aefSYogesh Narayan Gaur } 384a5356aefSYogesh Narayan Gaur 385a5356aefSYogesh Narayan Gaur static irqreturn_t nxp_fspi_irq_handler(int irq, void *dev_id) 386a5356aefSYogesh Narayan Gaur { 387a5356aefSYogesh Narayan Gaur struct nxp_fspi *f = dev_id; 388a5356aefSYogesh Narayan Gaur u32 reg; 389a5356aefSYogesh Narayan Gaur 390a5356aefSYogesh Narayan Gaur /* clear interrupt */ 391a5356aefSYogesh Narayan Gaur reg = fspi_readl(f, f->iobase + FSPI_INTR); 392a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_INTR_IPCMDDONE, f->iobase + FSPI_INTR); 393a5356aefSYogesh Narayan Gaur 394a5356aefSYogesh Narayan Gaur if (reg & FSPI_INTR_IPCMDDONE) 395a5356aefSYogesh Narayan Gaur complete(&f->c); 396a5356aefSYogesh Narayan Gaur 397a5356aefSYogesh Narayan Gaur return IRQ_HANDLED; 398a5356aefSYogesh Narayan Gaur } 399a5356aefSYogesh Narayan Gaur 400a5356aefSYogesh Narayan Gaur static int nxp_fspi_check_buswidth(struct nxp_fspi *f, u8 width) 401a5356aefSYogesh Narayan Gaur { 402a5356aefSYogesh Narayan Gaur switch (width) { 403a5356aefSYogesh Narayan Gaur case 1: 404a5356aefSYogesh Narayan Gaur case 2: 405a5356aefSYogesh Narayan Gaur case 4: 406a5356aefSYogesh Narayan Gaur case 8: 407a5356aefSYogesh Narayan Gaur return 0; 408a5356aefSYogesh Narayan Gaur } 409a5356aefSYogesh Narayan Gaur 410a5356aefSYogesh Narayan Gaur return -ENOTSUPP; 411a5356aefSYogesh Narayan Gaur } 412a5356aefSYogesh Narayan Gaur 413a5356aefSYogesh Narayan Gaur static bool nxp_fspi_supports_op(struct spi_mem *mem, 414a5356aefSYogesh Narayan Gaur const struct spi_mem_op *op) 415a5356aefSYogesh Narayan Gaur { 416a5356aefSYogesh Narayan Gaur struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master); 417a5356aefSYogesh Narayan Gaur int ret; 418a5356aefSYogesh Narayan Gaur 419a5356aefSYogesh Narayan Gaur ret = nxp_fspi_check_buswidth(f, op->cmd.buswidth); 420a5356aefSYogesh Narayan Gaur 421a5356aefSYogesh Narayan Gaur if (op->addr.nbytes) 422a5356aefSYogesh Narayan Gaur ret |= nxp_fspi_check_buswidth(f, op->addr.buswidth); 423a5356aefSYogesh Narayan Gaur 424a5356aefSYogesh Narayan Gaur if (op->dummy.nbytes) 425a5356aefSYogesh Narayan Gaur ret |= nxp_fspi_check_buswidth(f, op->dummy.buswidth); 426a5356aefSYogesh Narayan Gaur 427a5356aefSYogesh Narayan Gaur if (op->data.nbytes) 428a5356aefSYogesh Narayan Gaur ret |= nxp_fspi_check_buswidth(f, op->data.buswidth); 429a5356aefSYogesh Narayan Gaur 430a5356aefSYogesh Narayan Gaur if (ret) 431a5356aefSYogesh Narayan Gaur return false; 432a5356aefSYogesh Narayan Gaur 433a5356aefSYogesh Narayan Gaur /* 434a5356aefSYogesh Narayan Gaur * The number of address bytes should be equal to or less than 4 bytes. 435a5356aefSYogesh Narayan Gaur */ 436a5356aefSYogesh Narayan Gaur if (op->addr.nbytes > 4) 437a5356aefSYogesh Narayan Gaur return false; 438a5356aefSYogesh Narayan Gaur 439a5356aefSYogesh Narayan Gaur /* 440a5356aefSYogesh Narayan Gaur * If requested address value is greater than controller assigned 441a5356aefSYogesh Narayan Gaur * memory mapped space, return error as it didn't fit in the range 442a5356aefSYogesh Narayan Gaur * of assigned address space. 443a5356aefSYogesh Narayan Gaur */ 444a5356aefSYogesh Narayan Gaur if (op->addr.val >= f->memmap_phy_size) 445a5356aefSYogesh Narayan Gaur return false; 446a5356aefSYogesh Narayan Gaur 447a5356aefSYogesh Narayan Gaur /* Max 64 dummy clock cycles supported */ 448a5356aefSYogesh Narayan Gaur if (op->dummy.buswidth && 449a5356aefSYogesh Narayan Gaur (op->dummy.nbytes * 8 / op->dummy.buswidth > 64)) 450a5356aefSYogesh Narayan Gaur return false; 451a5356aefSYogesh Narayan Gaur 452a5356aefSYogesh Narayan Gaur /* Max data length, check controller limits and alignment */ 453a5356aefSYogesh Narayan Gaur if (op->data.dir == SPI_MEM_DATA_IN && 454a5356aefSYogesh Narayan Gaur (op->data.nbytes > f->devtype_data->ahb_buf_size || 455a5356aefSYogesh Narayan Gaur (op->data.nbytes > f->devtype_data->rxfifo - 4 && 456a5356aefSYogesh Narayan Gaur !IS_ALIGNED(op->data.nbytes, 8)))) 457a5356aefSYogesh Narayan Gaur return false; 458a5356aefSYogesh Narayan Gaur 459a5356aefSYogesh Narayan Gaur if (op->data.dir == SPI_MEM_DATA_OUT && 460a5356aefSYogesh Narayan Gaur op->data.nbytes > f->devtype_data->txfifo) 461a5356aefSYogesh Narayan Gaur return false; 462a5356aefSYogesh Narayan Gaur 463007773e1SMichael Walle return spi_mem_default_supports_op(mem, op); 464a5356aefSYogesh Narayan Gaur } 465a5356aefSYogesh Narayan Gaur 466a5356aefSYogesh Narayan Gaur /* Instead of busy looping invoke readl_poll_timeout functionality. */ 467a5356aefSYogesh Narayan Gaur static int fspi_readl_poll_tout(struct nxp_fspi *f, void __iomem *base, 468a5356aefSYogesh Narayan Gaur u32 mask, u32 delay_us, 469a5356aefSYogesh Narayan Gaur u32 timeout_us, bool c) 470a5356aefSYogesh Narayan Gaur { 471a5356aefSYogesh Narayan Gaur u32 reg; 472a5356aefSYogesh Narayan Gaur 473a5356aefSYogesh Narayan Gaur if (!f->devtype_data->little_endian) 474a5356aefSYogesh Narayan Gaur mask = (u32)cpu_to_be32(mask); 475a5356aefSYogesh Narayan Gaur 476a5356aefSYogesh Narayan Gaur if (c) 477a5356aefSYogesh Narayan Gaur return readl_poll_timeout(base, reg, (reg & mask), 478a5356aefSYogesh Narayan Gaur delay_us, timeout_us); 479a5356aefSYogesh Narayan Gaur else 480a5356aefSYogesh Narayan Gaur return readl_poll_timeout(base, reg, !(reg & mask), 481a5356aefSYogesh Narayan Gaur delay_us, timeout_us); 482a5356aefSYogesh Narayan Gaur } 483a5356aefSYogesh Narayan Gaur 484a5356aefSYogesh Narayan Gaur /* 485a5356aefSYogesh Narayan Gaur * If the slave device content being changed by Write/Erase, need to 486a5356aefSYogesh Narayan Gaur * invalidate the AHB buffer. This can be achieved by doing the reset 487a5356aefSYogesh Narayan Gaur * of controller after setting MCR0[SWRESET] bit. 488a5356aefSYogesh Narayan Gaur */ 489a5356aefSYogesh Narayan Gaur static inline void nxp_fspi_invalid(struct nxp_fspi *f) 490a5356aefSYogesh Narayan Gaur { 491a5356aefSYogesh Narayan Gaur u32 reg; 492a5356aefSYogesh Narayan Gaur int ret; 493a5356aefSYogesh Narayan Gaur 494a5356aefSYogesh Narayan Gaur reg = fspi_readl(f, f->iobase + FSPI_MCR0); 495a5356aefSYogesh Narayan Gaur fspi_writel(f, reg | FSPI_MCR0_SWRST, f->iobase + FSPI_MCR0); 496a5356aefSYogesh Narayan Gaur 497a5356aefSYogesh Narayan Gaur /* w1c register, wait unit clear */ 498a5356aefSYogesh Narayan Gaur ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0, 499a5356aefSYogesh Narayan Gaur FSPI_MCR0_SWRST, 0, POLL_TOUT, false); 500a5356aefSYogesh Narayan Gaur WARN_ON(ret); 501a5356aefSYogesh Narayan Gaur } 502a5356aefSYogesh Narayan Gaur 503a5356aefSYogesh Narayan Gaur static void nxp_fspi_prepare_lut(struct nxp_fspi *f, 504a5356aefSYogesh Narayan Gaur const struct spi_mem_op *op) 505a5356aefSYogesh Narayan Gaur { 506a5356aefSYogesh Narayan Gaur void __iomem *base = f->iobase; 507a5356aefSYogesh Narayan Gaur u32 lutval[4] = {}; 508a5356aefSYogesh Narayan Gaur int lutidx = 1, i; 509a5356aefSYogesh Narayan Gaur 510a5356aefSYogesh Narayan Gaur /* cmd */ 511a5356aefSYogesh Narayan Gaur lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth), 512a5356aefSYogesh Narayan Gaur op->cmd.opcode); 513a5356aefSYogesh Narayan Gaur 514a5356aefSYogesh Narayan Gaur /* addr bytes */ 515a5356aefSYogesh Narayan Gaur if (op->addr.nbytes) { 516a5356aefSYogesh Narayan Gaur lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_ADDR, 517a5356aefSYogesh Narayan Gaur LUT_PAD(op->addr.buswidth), 518a5356aefSYogesh Narayan Gaur op->addr.nbytes * 8); 519a5356aefSYogesh Narayan Gaur lutidx++; 520a5356aefSYogesh Narayan Gaur } 521a5356aefSYogesh Narayan Gaur 522a5356aefSYogesh Narayan Gaur /* dummy bytes, if needed */ 523a5356aefSYogesh Narayan Gaur if (op->dummy.nbytes) { 524a5356aefSYogesh Narayan Gaur lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY, 525a5356aefSYogesh Narayan Gaur /* 526a5356aefSYogesh Narayan Gaur * Due to FlexSPI controller limitation number of PAD for dummy 527a5356aefSYogesh Narayan Gaur * buswidth needs to be programmed as equal to data buswidth. 528a5356aefSYogesh Narayan Gaur */ 529a5356aefSYogesh Narayan Gaur LUT_PAD(op->data.buswidth), 530a5356aefSYogesh Narayan Gaur op->dummy.nbytes * 8 / 531a5356aefSYogesh Narayan Gaur op->dummy.buswidth); 532a5356aefSYogesh Narayan Gaur lutidx++; 533a5356aefSYogesh Narayan Gaur } 534a5356aefSYogesh Narayan Gaur 535a5356aefSYogesh Narayan Gaur /* read/write data bytes */ 536a5356aefSYogesh Narayan Gaur if (op->data.nbytes) { 537a5356aefSYogesh Narayan Gaur lutval[lutidx / 2] |= LUT_DEF(lutidx, 538a5356aefSYogesh Narayan Gaur op->data.dir == SPI_MEM_DATA_IN ? 539a5356aefSYogesh Narayan Gaur LUT_NXP_READ : LUT_NXP_WRITE, 540a5356aefSYogesh Narayan Gaur LUT_PAD(op->data.buswidth), 541a5356aefSYogesh Narayan Gaur 0); 542a5356aefSYogesh Narayan Gaur lutidx++; 543a5356aefSYogesh Narayan Gaur } 544a5356aefSYogesh Narayan Gaur 545a5356aefSYogesh Narayan Gaur /* stop condition. */ 546a5356aefSYogesh Narayan Gaur lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0); 547a5356aefSYogesh Narayan Gaur 548a5356aefSYogesh Narayan Gaur /* unlock LUT */ 549a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY); 550a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_LCKER_UNLOCK, f->iobase + FSPI_LCKCR); 551a5356aefSYogesh Narayan Gaur 552a5356aefSYogesh Narayan Gaur /* fill LUT */ 553a5356aefSYogesh Narayan Gaur for (i = 0; i < ARRAY_SIZE(lutval); i++) 554a5356aefSYogesh Narayan Gaur fspi_writel(f, lutval[i], base + FSPI_LUT_REG(i)); 555a5356aefSYogesh Narayan Gaur 556a5356aefSYogesh Narayan Gaur dev_dbg(f->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x]\n", 557a5356aefSYogesh Narayan Gaur op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3]); 558a5356aefSYogesh Narayan Gaur 559a5356aefSYogesh Narayan Gaur /* lock LUT */ 560a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY); 561a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_LCKER_LOCK, f->iobase + FSPI_LCKCR); 562a5356aefSYogesh Narayan Gaur } 563a5356aefSYogesh Narayan Gaur 564a5356aefSYogesh Narayan Gaur static int nxp_fspi_clk_prep_enable(struct nxp_fspi *f) 565a5356aefSYogesh Narayan Gaur { 566a5356aefSYogesh Narayan Gaur int ret; 567a5356aefSYogesh Narayan Gaur 56855ab8487Skuldip dwivedi if (is_acpi_node(f->dev->fwnode)) 56955ab8487Skuldip dwivedi return 0; 57055ab8487Skuldip dwivedi 571a5356aefSYogesh Narayan Gaur ret = clk_prepare_enable(f->clk_en); 572a5356aefSYogesh Narayan Gaur if (ret) 573a5356aefSYogesh Narayan Gaur return ret; 574a5356aefSYogesh Narayan Gaur 575a5356aefSYogesh Narayan Gaur ret = clk_prepare_enable(f->clk); 576a5356aefSYogesh Narayan Gaur if (ret) { 577a5356aefSYogesh Narayan Gaur clk_disable_unprepare(f->clk_en); 578a5356aefSYogesh Narayan Gaur return ret; 579a5356aefSYogesh Narayan Gaur } 580a5356aefSYogesh Narayan Gaur 581a5356aefSYogesh Narayan Gaur return 0; 582a5356aefSYogesh Narayan Gaur } 583a5356aefSYogesh Narayan Gaur 58455ab8487Skuldip dwivedi static int nxp_fspi_clk_disable_unprep(struct nxp_fspi *f) 585a5356aefSYogesh Narayan Gaur { 58655ab8487Skuldip dwivedi if (is_acpi_node(f->dev->fwnode)) 58755ab8487Skuldip dwivedi return 0; 58855ab8487Skuldip dwivedi 589a5356aefSYogesh Narayan Gaur clk_disable_unprepare(f->clk); 590a5356aefSYogesh Narayan Gaur clk_disable_unprepare(f->clk_en); 59155ab8487Skuldip dwivedi 59255ab8487Skuldip dwivedi return 0; 593a5356aefSYogesh Narayan Gaur } 594a5356aefSYogesh Narayan Gaur 595a5356aefSYogesh Narayan Gaur /* 596a5356aefSYogesh Narayan Gaur * In FlexSPI controller, flash access is based on value of FSPI_FLSHXXCR0 597a5356aefSYogesh Narayan Gaur * register and start base address of the slave device. 598a5356aefSYogesh Narayan Gaur * 599a5356aefSYogesh Narayan Gaur * (Higher address) 600a5356aefSYogesh Narayan Gaur * -------- <-- FLSHB2CR0 601a5356aefSYogesh Narayan Gaur * | B2 | 602a5356aefSYogesh Narayan Gaur * | | 603a5356aefSYogesh Narayan Gaur * B2 start address --> -------- <-- FLSHB1CR0 604a5356aefSYogesh Narayan Gaur * | B1 | 605a5356aefSYogesh Narayan Gaur * | | 606a5356aefSYogesh Narayan Gaur * B1 start address --> -------- <-- FLSHA2CR0 607a5356aefSYogesh Narayan Gaur * | A2 | 608a5356aefSYogesh Narayan Gaur * | | 609a5356aefSYogesh Narayan Gaur * A2 start address --> -------- <-- FLSHA1CR0 610a5356aefSYogesh Narayan Gaur * | A1 | 611a5356aefSYogesh Narayan Gaur * | | 612a5356aefSYogesh Narayan Gaur * A1 start address --> -------- (Lower address) 613a5356aefSYogesh Narayan Gaur * 614a5356aefSYogesh Narayan Gaur * 615a5356aefSYogesh Narayan Gaur * Start base address defines the starting address range for given CS and 616a5356aefSYogesh Narayan Gaur * FSPI_FLSHXXCR0 defines the size of the slave device connected at given CS. 617a5356aefSYogesh Narayan Gaur * 618a5356aefSYogesh Narayan Gaur * But, different targets are having different combinations of number of CS, 619a5356aefSYogesh Narayan Gaur * some targets only have single CS or two CS covering controller's full 620a5356aefSYogesh Narayan Gaur * memory mapped space area. 621a5356aefSYogesh Narayan Gaur * Thus, implementation is being done as independent of the size and number 622a5356aefSYogesh Narayan Gaur * of the connected slave device. 623a5356aefSYogesh Narayan Gaur * Assign controller memory mapped space size as the size to the connected 624a5356aefSYogesh Narayan Gaur * slave device. 625a5356aefSYogesh Narayan Gaur * Mark FLSHxxCR0 as zero initially and then assign value only to the selected 626a5356aefSYogesh Narayan Gaur * chip-select Flash configuration register. 627a5356aefSYogesh Narayan Gaur * 628a5356aefSYogesh Narayan Gaur * For e.g. to access CS2 (B1), FLSHB1CR0 register would be equal to the 629a5356aefSYogesh Narayan Gaur * memory mapped size of the controller. 630a5356aefSYogesh Narayan Gaur * Value for rest of the CS FLSHxxCR0 register would be zero. 631a5356aefSYogesh Narayan Gaur * 632a5356aefSYogesh Narayan Gaur */ 633a5356aefSYogesh Narayan Gaur static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi) 634a5356aefSYogesh Narayan Gaur { 635a5356aefSYogesh Narayan Gaur unsigned long rate = spi->max_speed_hz; 636a5356aefSYogesh Narayan Gaur int ret; 637a5356aefSYogesh Narayan Gaur uint64_t size_kb; 638a5356aefSYogesh Narayan Gaur 639a5356aefSYogesh Narayan Gaur /* 640a5356aefSYogesh Narayan Gaur * Return, if previously selected slave device is same as current 641a5356aefSYogesh Narayan Gaur * requested slave device. 642a5356aefSYogesh Narayan Gaur */ 643a5356aefSYogesh Narayan Gaur if (f->selected == spi->chip_select) 644a5356aefSYogesh Narayan Gaur return; 645a5356aefSYogesh Narayan Gaur 646a5356aefSYogesh Narayan Gaur /* Reset FLSHxxCR0 registers */ 647a5356aefSYogesh Narayan Gaur fspi_writel(f, 0, f->iobase + FSPI_FLSHA1CR0); 648a5356aefSYogesh Narayan Gaur fspi_writel(f, 0, f->iobase + FSPI_FLSHA2CR0); 649a5356aefSYogesh Narayan Gaur fspi_writel(f, 0, f->iobase + FSPI_FLSHB1CR0); 650a5356aefSYogesh Narayan Gaur fspi_writel(f, 0, f->iobase + FSPI_FLSHB2CR0); 651a5356aefSYogesh Narayan Gaur 652a5356aefSYogesh Narayan Gaur /* Assign controller memory mapped space as size, KBytes, of flash. */ 653a5356aefSYogesh Narayan Gaur size_kb = FSPI_FLSHXCR0_SZ(f->memmap_phy_size); 654a5356aefSYogesh Narayan Gaur 655a5356aefSYogesh Narayan Gaur fspi_writel(f, size_kb, f->iobase + FSPI_FLSHA1CR0 + 656a5356aefSYogesh Narayan Gaur 4 * spi->chip_select); 657a5356aefSYogesh Narayan Gaur 658a5356aefSYogesh Narayan Gaur dev_dbg(f->dev, "Slave device [CS:%x] selected\n", spi->chip_select); 659a5356aefSYogesh Narayan Gaur 660a5356aefSYogesh Narayan Gaur nxp_fspi_clk_disable_unprep(f); 661a5356aefSYogesh Narayan Gaur 662a5356aefSYogesh Narayan Gaur ret = clk_set_rate(f->clk, rate); 663a5356aefSYogesh Narayan Gaur if (ret) 664a5356aefSYogesh Narayan Gaur return; 665a5356aefSYogesh Narayan Gaur 666a5356aefSYogesh Narayan Gaur ret = nxp_fspi_clk_prep_enable(f); 667a5356aefSYogesh Narayan Gaur if (ret) 668a5356aefSYogesh Narayan Gaur return; 669a5356aefSYogesh Narayan Gaur 670a5356aefSYogesh Narayan Gaur f->selected = spi->chip_select; 671a5356aefSYogesh Narayan Gaur } 672a5356aefSYogesh Narayan Gaur 673d166a735SHan Xu static int nxp_fspi_read_ahb(struct nxp_fspi *f, const struct spi_mem_op *op) 674a5356aefSYogesh Narayan Gaur { 675d166a735SHan Xu u32 start = op->addr.val; 676a5356aefSYogesh Narayan Gaur u32 len = op->data.nbytes; 677a5356aefSYogesh Narayan Gaur 678d166a735SHan Xu /* if necessary, ioremap before AHB read */ 679d166a735SHan Xu if ((!f->ahb_addr) || start < f->memmap_start || 680d166a735SHan Xu start + len > f->memmap_start + f->memmap_len) { 681d166a735SHan Xu if (f->ahb_addr) 682d166a735SHan Xu iounmap(f->ahb_addr); 683d166a735SHan Xu 684d166a735SHan Xu f->memmap_start = start; 685d166a735SHan Xu f->memmap_len = len > NXP_FSPI_MIN_IOMAP ? 686d166a735SHan Xu len : NXP_FSPI_MIN_IOMAP; 687d166a735SHan Xu 688d166a735SHan Xu f->ahb_addr = ioremap_wc(f->memmap_phy + f->memmap_start, 689d166a735SHan Xu f->memmap_len); 690d166a735SHan Xu 691d166a735SHan Xu if (!f->ahb_addr) { 692d166a735SHan Xu dev_err(f->dev, "failed to alloc memory\n"); 693d166a735SHan Xu return -ENOMEM; 694d166a735SHan Xu } 695d166a735SHan Xu } 696d166a735SHan Xu 697a5356aefSYogesh Narayan Gaur /* Read out the data directly from the AHB buffer. */ 698d166a735SHan Xu memcpy_fromio(op->data.buf.in, 699d166a735SHan Xu f->ahb_addr + start - f->memmap_start, len); 700d166a735SHan Xu 701d166a735SHan Xu return 0; 702a5356aefSYogesh Narayan Gaur } 703a5356aefSYogesh Narayan Gaur 704a5356aefSYogesh Narayan Gaur static void nxp_fspi_fill_txfifo(struct nxp_fspi *f, 705a5356aefSYogesh Narayan Gaur const struct spi_mem_op *op) 706a5356aefSYogesh Narayan Gaur { 707a5356aefSYogesh Narayan Gaur void __iomem *base = f->iobase; 708a5356aefSYogesh Narayan Gaur int i, ret; 709a5356aefSYogesh Narayan Gaur u8 *buf = (u8 *) op->data.buf.out; 710a5356aefSYogesh Narayan Gaur 711a5356aefSYogesh Narayan Gaur /* clear the TX FIFO. */ 712a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_IPTXFCR_CLR, base + FSPI_IPTXFCR); 713a5356aefSYogesh Narayan Gaur 714a5356aefSYogesh Narayan Gaur /* 715a5356aefSYogesh Narayan Gaur * Default value of water mark level is 8 bytes, hence in single 716a5356aefSYogesh Narayan Gaur * write request controller can write max 8 bytes of data. 717a5356aefSYogesh Narayan Gaur */ 718a5356aefSYogesh Narayan Gaur 719a5356aefSYogesh Narayan Gaur for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 8); i += 8) { 720a5356aefSYogesh Narayan Gaur /* Wait for TXFIFO empty */ 721a5356aefSYogesh Narayan Gaur ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, 722a5356aefSYogesh Narayan Gaur FSPI_INTR_IPTXWE, 0, 723a5356aefSYogesh Narayan Gaur POLL_TOUT, true); 724a5356aefSYogesh Narayan Gaur WARN_ON(ret); 725a5356aefSYogesh Narayan Gaur 726a5356aefSYogesh Narayan Gaur fspi_writel(f, *(u32 *) (buf + i), base + FSPI_TFDR); 727a5356aefSYogesh Narayan Gaur fspi_writel(f, *(u32 *) (buf + i + 4), base + FSPI_TFDR + 4); 728a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR); 729a5356aefSYogesh Narayan Gaur } 730a5356aefSYogesh Narayan Gaur 731a5356aefSYogesh Narayan Gaur if (i < op->data.nbytes) { 732a5356aefSYogesh Narayan Gaur u32 data = 0; 733a5356aefSYogesh Narayan Gaur int j; 734a5356aefSYogesh Narayan Gaur /* Wait for TXFIFO empty */ 735a5356aefSYogesh Narayan Gaur ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, 736a5356aefSYogesh Narayan Gaur FSPI_INTR_IPTXWE, 0, 737a5356aefSYogesh Narayan Gaur POLL_TOUT, true); 738a5356aefSYogesh Narayan Gaur WARN_ON(ret); 739a5356aefSYogesh Narayan Gaur 740a5356aefSYogesh Narayan Gaur for (j = 0; j < ALIGN(op->data.nbytes - i, 4); j += 4) { 741a5356aefSYogesh Narayan Gaur memcpy(&data, buf + i + j, 4); 742a5356aefSYogesh Narayan Gaur fspi_writel(f, data, base + FSPI_TFDR + j); 743a5356aefSYogesh Narayan Gaur } 744a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR); 745a5356aefSYogesh Narayan Gaur } 746a5356aefSYogesh Narayan Gaur } 747a5356aefSYogesh Narayan Gaur 748a5356aefSYogesh Narayan Gaur static void nxp_fspi_read_rxfifo(struct nxp_fspi *f, 749a5356aefSYogesh Narayan Gaur const struct spi_mem_op *op) 750a5356aefSYogesh Narayan Gaur { 751a5356aefSYogesh Narayan Gaur void __iomem *base = f->iobase; 752a5356aefSYogesh Narayan Gaur int i, ret; 753a5356aefSYogesh Narayan Gaur int len = op->data.nbytes; 754a5356aefSYogesh Narayan Gaur u8 *buf = (u8 *) op->data.buf.in; 755a5356aefSYogesh Narayan Gaur 756a5356aefSYogesh Narayan Gaur /* 757a5356aefSYogesh Narayan Gaur * Default value of water mark level is 8 bytes, hence in single 758a5356aefSYogesh Narayan Gaur * read request controller can read max 8 bytes of data. 759a5356aefSYogesh Narayan Gaur */ 760a5356aefSYogesh Narayan Gaur for (i = 0; i < ALIGN_DOWN(len, 8); i += 8) { 761a5356aefSYogesh Narayan Gaur /* Wait for RXFIFO available */ 762a5356aefSYogesh Narayan Gaur ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, 763a5356aefSYogesh Narayan Gaur FSPI_INTR_IPRXWA, 0, 764a5356aefSYogesh Narayan Gaur POLL_TOUT, true); 765a5356aefSYogesh Narayan Gaur WARN_ON(ret); 766a5356aefSYogesh Narayan Gaur 767a5356aefSYogesh Narayan Gaur *(u32 *)(buf + i) = fspi_readl(f, base + FSPI_RFDR); 768a5356aefSYogesh Narayan Gaur *(u32 *)(buf + i + 4) = fspi_readl(f, base + FSPI_RFDR + 4); 769a5356aefSYogesh Narayan Gaur /* move the FIFO pointer */ 770a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR); 771a5356aefSYogesh Narayan Gaur } 772a5356aefSYogesh Narayan Gaur 773a5356aefSYogesh Narayan Gaur if (i < len) { 774a5356aefSYogesh Narayan Gaur u32 tmp; 775a5356aefSYogesh Narayan Gaur int size, j; 776a5356aefSYogesh Narayan Gaur 777a5356aefSYogesh Narayan Gaur buf = op->data.buf.in + i; 778a5356aefSYogesh Narayan Gaur /* Wait for RXFIFO available */ 779a5356aefSYogesh Narayan Gaur ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, 780a5356aefSYogesh Narayan Gaur FSPI_INTR_IPRXWA, 0, 781a5356aefSYogesh Narayan Gaur POLL_TOUT, true); 782a5356aefSYogesh Narayan Gaur WARN_ON(ret); 783a5356aefSYogesh Narayan Gaur 784a5356aefSYogesh Narayan Gaur len = op->data.nbytes - i; 785a5356aefSYogesh Narayan Gaur for (j = 0; j < op->data.nbytes - i; j += 4) { 786a5356aefSYogesh Narayan Gaur tmp = fspi_readl(f, base + FSPI_RFDR + j); 787a5356aefSYogesh Narayan Gaur size = min(len, 4); 788a5356aefSYogesh Narayan Gaur memcpy(buf + j, &tmp, size); 789a5356aefSYogesh Narayan Gaur len -= size; 790a5356aefSYogesh Narayan Gaur } 791a5356aefSYogesh Narayan Gaur } 792a5356aefSYogesh Narayan Gaur 793a5356aefSYogesh Narayan Gaur /* invalid the RXFIFO */ 794a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_IPRXFCR_CLR, base + FSPI_IPRXFCR); 795a5356aefSYogesh Narayan Gaur /* move the FIFO pointer */ 796a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR); 797a5356aefSYogesh Narayan Gaur } 798a5356aefSYogesh Narayan Gaur 799a5356aefSYogesh Narayan Gaur static int nxp_fspi_do_op(struct nxp_fspi *f, const struct spi_mem_op *op) 800a5356aefSYogesh Narayan Gaur { 801a5356aefSYogesh Narayan Gaur void __iomem *base = f->iobase; 802a5356aefSYogesh Narayan Gaur int seqnum = 0; 803a5356aefSYogesh Narayan Gaur int err = 0; 804a5356aefSYogesh Narayan Gaur u32 reg; 805a5356aefSYogesh Narayan Gaur 806a5356aefSYogesh Narayan Gaur reg = fspi_readl(f, base + FSPI_IPRXFCR); 807a5356aefSYogesh Narayan Gaur /* invalid RXFIFO first */ 808a5356aefSYogesh Narayan Gaur reg &= ~FSPI_IPRXFCR_DMA_EN; 809a5356aefSYogesh Narayan Gaur reg = reg | FSPI_IPRXFCR_CLR; 810a5356aefSYogesh Narayan Gaur fspi_writel(f, reg, base + FSPI_IPRXFCR); 811a5356aefSYogesh Narayan Gaur 812a5356aefSYogesh Narayan Gaur init_completion(&f->c); 813a5356aefSYogesh Narayan Gaur 814a5356aefSYogesh Narayan Gaur fspi_writel(f, op->addr.val, base + FSPI_IPCR0); 815a5356aefSYogesh Narayan Gaur /* 816a5356aefSYogesh Narayan Gaur * Always start the sequence at the same index since we update 817a5356aefSYogesh Narayan Gaur * the LUT at each exec_op() call. And also specify the DATA 818a5356aefSYogesh Narayan Gaur * length, since it's has not been specified in the LUT. 819a5356aefSYogesh Narayan Gaur */ 820a5356aefSYogesh Narayan Gaur fspi_writel(f, op->data.nbytes | 821a5356aefSYogesh Narayan Gaur (SEQID_LUT << FSPI_IPCR1_SEQID_SHIFT) | 822a5356aefSYogesh Narayan Gaur (seqnum << FSPI_IPCR1_SEQNUM_SHIFT), 823a5356aefSYogesh Narayan Gaur base + FSPI_IPCR1); 824a5356aefSYogesh Narayan Gaur 825a5356aefSYogesh Narayan Gaur /* Trigger the LUT now. */ 826a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_IPCMD_TRG, base + FSPI_IPCMD); 827a5356aefSYogesh Narayan Gaur 828a5356aefSYogesh Narayan Gaur /* Wait for the interrupt. */ 829a5356aefSYogesh Narayan Gaur if (!wait_for_completion_timeout(&f->c, msecs_to_jiffies(1000))) 830a5356aefSYogesh Narayan Gaur err = -ETIMEDOUT; 831a5356aefSYogesh Narayan Gaur 832a5356aefSYogesh Narayan Gaur /* Invoke IP data read, if request is of data read. */ 833a5356aefSYogesh Narayan Gaur if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN) 834a5356aefSYogesh Narayan Gaur nxp_fspi_read_rxfifo(f, op); 835a5356aefSYogesh Narayan Gaur 836a5356aefSYogesh Narayan Gaur return err; 837a5356aefSYogesh Narayan Gaur } 838a5356aefSYogesh Narayan Gaur 839a5356aefSYogesh Narayan Gaur static int nxp_fspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) 840a5356aefSYogesh Narayan Gaur { 841a5356aefSYogesh Narayan Gaur struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master); 842a5356aefSYogesh Narayan Gaur int err = 0; 843a5356aefSYogesh Narayan Gaur 844a5356aefSYogesh Narayan Gaur mutex_lock(&f->lock); 845a5356aefSYogesh Narayan Gaur 846a5356aefSYogesh Narayan Gaur /* Wait for controller being ready. */ 847a5356aefSYogesh Narayan Gaur err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0, 848a5356aefSYogesh Narayan Gaur FSPI_STS0_ARB_IDLE, 1, POLL_TOUT, true); 849a5356aefSYogesh Narayan Gaur WARN_ON(err); 850a5356aefSYogesh Narayan Gaur 851a5356aefSYogesh Narayan Gaur nxp_fspi_select_mem(f, mem->spi); 852a5356aefSYogesh Narayan Gaur 853a5356aefSYogesh Narayan Gaur nxp_fspi_prepare_lut(f, op); 854a5356aefSYogesh Narayan Gaur /* 855a5356aefSYogesh Narayan Gaur * If we have large chunks of data, we read them through the AHB bus 856a5356aefSYogesh Narayan Gaur * by accessing the mapped memory. In all other cases we use 857a5356aefSYogesh Narayan Gaur * IP commands to access the flash. 858a5356aefSYogesh Narayan Gaur */ 859a5356aefSYogesh Narayan Gaur if (op->data.nbytes > (f->devtype_data->rxfifo - 4) && 860a5356aefSYogesh Narayan Gaur op->data.dir == SPI_MEM_DATA_IN) { 861d166a735SHan Xu err = nxp_fspi_read_ahb(f, op); 862a5356aefSYogesh Narayan Gaur } else { 863a5356aefSYogesh Narayan Gaur if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) 864a5356aefSYogesh Narayan Gaur nxp_fspi_fill_txfifo(f, op); 865a5356aefSYogesh Narayan Gaur 866a5356aefSYogesh Narayan Gaur err = nxp_fspi_do_op(f, op); 867a5356aefSYogesh Narayan Gaur } 868a5356aefSYogesh Narayan Gaur 869a5356aefSYogesh Narayan Gaur /* Invalidate the data in the AHB buffer. */ 870a5356aefSYogesh Narayan Gaur nxp_fspi_invalid(f); 871a5356aefSYogesh Narayan Gaur 872a5356aefSYogesh Narayan Gaur mutex_unlock(&f->lock); 873a5356aefSYogesh Narayan Gaur 874a5356aefSYogesh Narayan Gaur return err; 875a5356aefSYogesh Narayan Gaur } 876a5356aefSYogesh Narayan Gaur 877a5356aefSYogesh Narayan Gaur static int nxp_fspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) 878a5356aefSYogesh Narayan Gaur { 879a5356aefSYogesh Narayan Gaur struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master); 880a5356aefSYogesh Narayan Gaur 881a5356aefSYogesh Narayan Gaur if (op->data.dir == SPI_MEM_DATA_OUT) { 882a5356aefSYogesh Narayan Gaur if (op->data.nbytes > f->devtype_data->txfifo) 883a5356aefSYogesh Narayan Gaur op->data.nbytes = f->devtype_data->txfifo; 884a5356aefSYogesh Narayan Gaur } else { 885a5356aefSYogesh Narayan Gaur if (op->data.nbytes > f->devtype_data->ahb_buf_size) 886a5356aefSYogesh Narayan Gaur op->data.nbytes = f->devtype_data->ahb_buf_size; 887a5356aefSYogesh Narayan Gaur else if (op->data.nbytes > (f->devtype_data->rxfifo - 4)) 888a5356aefSYogesh Narayan Gaur op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8); 889a5356aefSYogesh Narayan Gaur } 890a5356aefSYogesh Narayan Gaur 891a5356aefSYogesh Narayan Gaur return 0; 892a5356aefSYogesh Narayan Gaur } 893a5356aefSYogesh Narayan Gaur 894a5356aefSYogesh Narayan Gaur static int nxp_fspi_default_setup(struct nxp_fspi *f) 895a5356aefSYogesh Narayan Gaur { 896a5356aefSYogesh Narayan Gaur void __iomem *base = f->iobase; 897a5356aefSYogesh Narayan Gaur int ret, i; 898a5356aefSYogesh Narayan Gaur u32 reg; 899a5356aefSYogesh Narayan Gaur 900a5356aefSYogesh Narayan Gaur /* disable and unprepare clock to avoid glitch pass to controller */ 901a5356aefSYogesh Narayan Gaur nxp_fspi_clk_disable_unprep(f); 902a5356aefSYogesh Narayan Gaur 903a5356aefSYogesh Narayan Gaur /* the default frequency, we will change it later if necessary. */ 904a5356aefSYogesh Narayan Gaur ret = clk_set_rate(f->clk, 20000000); 905a5356aefSYogesh Narayan Gaur if (ret) 906a5356aefSYogesh Narayan Gaur return ret; 907a5356aefSYogesh Narayan Gaur 908a5356aefSYogesh Narayan Gaur ret = nxp_fspi_clk_prep_enable(f); 909a5356aefSYogesh Narayan Gaur if (ret) 910a5356aefSYogesh Narayan Gaur return ret; 911a5356aefSYogesh Narayan Gaur 912a5356aefSYogesh Narayan Gaur /* Reset the module */ 913a5356aefSYogesh Narayan Gaur /* w1c register, wait unit clear */ 914a5356aefSYogesh Narayan Gaur ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0, 915a5356aefSYogesh Narayan Gaur FSPI_MCR0_SWRST, 0, POLL_TOUT, false); 916a5356aefSYogesh Narayan Gaur WARN_ON(ret); 917a5356aefSYogesh Narayan Gaur 918a5356aefSYogesh Narayan Gaur /* Disable the module */ 919a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_MCR0_MDIS, base + FSPI_MCR0); 920a5356aefSYogesh Narayan Gaur 921a5356aefSYogesh Narayan Gaur /* Reset the DLL register to default value */ 922a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_DLLACR_OVRDEN, base + FSPI_DLLACR); 923a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_DLLBCR_OVRDEN, base + FSPI_DLLBCR); 924a5356aefSYogesh Narayan Gaur 925a5356aefSYogesh Narayan Gaur /* enable module */ 926b7461fa5SHan Xu fspi_writel(f, FSPI_MCR0_AHB_TIMEOUT(0xFF) | 927b7461fa5SHan Xu FSPI_MCR0_IP_TIMEOUT(0xFF) | (u32) FSPI_MCR0_OCTCOMB_EN, 928a5356aefSYogesh Narayan Gaur base + FSPI_MCR0); 929a5356aefSYogesh Narayan Gaur 930a5356aefSYogesh Narayan Gaur /* 931a5356aefSYogesh Narayan Gaur * Disable same device enable bit and configure all slave devices 932a5356aefSYogesh Narayan Gaur * independently. 933a5356aefSYogesh Narayan Gaur */ 934a5356aefSYogesh Narayan Gaur reg = fspi_readl(f, f->iobase + FSPI_MCR2); 935a5356aefSYogesh Narayan Gaur reg = reg & ~(FSPI_MCR2_SAMEDEVICEEN); 936a5356aefSYogesh Narayan Gaur fspi_writel(f, reg, base + FSPI_MCR2); 937a5356aefSYogesh Narayan Gaur 938a5356aefSYogesh Narayan Gaur /* AHB configuration for access buffer 0~7. */ 939a5356aefSYogesh Narayan Gaur for (i = 0; i < 7; i++) 940a5356aefSYogesh Narayan Gaur fspi_writel(f, 0, base + FSPI_AHBRX_BUF0CR0 + 4 * i); 941a5356aefSYogesh Narayan Gaur 942a5356aefSYogesh Narayan Gaur /* 943a5356aefSYogesh Narayan Gaur * Set ADATSZ with the maximum AHB buffer size to improve the read 944a5356aefSYogesh Narayan Gaur * performance. 945a5356aefSYogesh Narayan Gaur */ 946a5356aefSYogesh Narayan Gaur fspi_writel(f, (f->devtype_data->ahb_buf_size / 8 | 947a5356aefSYogesh Narayan Gaur FSPI_AHBRXBUF0CR7_PREF), base + FSPI_AHBRX_BUF7CR0); 948a5356aefSYogesh Narayan Gaur 949a5356aefSYogesh Narayan Gaur /* prefetch and no start address alignment limitation */ 950a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_AHBCR_PREF_EN | FSPI_AHBCR_RDADDROPT, 951a5356aefSYogesh Narayan Gaur base + FSPI_AHBCR); 952a5356aefSYogesh Narayan Gaur 953a5356aefSYogesh Narayan Gaur /* AHB Read - Set lut sequence ID for all CS. */ 954a5356aefSYogesh Narayan Gaur fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA1CR2); 955a5356aefSYogesh Narayan Gaur fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA2CR2); 956a5356aefSYogesh Narayan Gaur fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB1CR2); 957a5356aefSYogesh Narayan Gaur fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB2CR2); 958a5356aefSYogesh Narayan Gaur 959a5356aefSYogesh Narayan Gaur f->selected = -1; 960a5356aefSYogesh Narayan Gaur 961a5356aefSYogesh Narayan Gaur /* enable the interrupt */ 962a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_INTEN_IPCMDDONE, base + FSPI_INTEN); 963a5356aefSYogesh Narayan Gaur 964a5356aefSYogesh Narayan Gaur return 0; 965a5356aefSYogesh Narayan Gaur } 966a5356aefSYogesh Narayan Gaur 967a5356aefSYogesh Narayan Gaur static const char *nxp_fspi_get_name(struct spi_mem *mem) 968a5356aefSYogesh Narayan Gaur { 969a5356aefSYogesh Narayan Gaur struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master); 970a5356aefSYogesh Narayan Gaur struct device *dev = &mem->spi->dev; 971a5356aefSYogesh Narayan Gaur const char *name; 972a5356aefSYogesh Narayan Gaur 973a5356aefSYogesh Narayan Gaur // Set custom name derived from the platform_device of the controller. 974a5356aefSYogesh Narayan Gaur if (of_get_available_child_count(f->dev->of_node) == 1) 975a5356aefSYogesh Narayan Gaur return dev_name(f->dev); 976a5356aefSYogesh Narayan Gaur 977a5356aefSYogesh Narayan Gaur name = devm_kasprintf(dev, GFP_KERNEL, 978a5356aefSYogesh Narayan Gaur "%s-%d", dev_name(f->dev), 979a5356aefSYogesh Narayan Gaur mem->spi->chip_select); 980a5356aefSYogesh Narayan Gaur 981a5356aefSYogesh Narayan Gaur if (!name) { 982a5356aefSYogesh Narayan Gaur dev_err(dev, "failed to get memory for custom flash name\n"); 983a5356aefSYogesh Narayan Gaur return ERR_PTR(-ENOMEM); 984a5356aefSYogesh Narayan Gaur } 985a5356aefSYogesh Narayan Gaur 986a5356aefSYogesh Narayan Gaur return name; 987a5356aefSYogesh Narayan Gaur } 988a5356aefSYogesh Narayan Gaur 989a5356aefSYogesh Narayan Gaur static const struct spi_controller_mem_ops nxp_fspi_mem_ops = { 990a5356aefSYogesh Narayan Gaur .adjust_op_size = nxp_fspi_adjust_op_size, 991a5356aefSYogesh Narayan Gaur .supports_op = nxp_fspi_supports_op, 992a5356aefSYogesh Narayan Gaur .exec_op = nxp_fspi_exec_op, 993a5356aefSYogesh Narayan Gaur .get_name = nxp_fspi_get_name, 994a5356aefSYogesh Narayan Gaur }; 995a5356aefSYogesh Narayan Gaur 996a5356aefSYogesh Narayan Gaur static int nxp_fspi_probe(struct platform_device *pdev) 997a5356aefSYogesh Narayan Gaur { 998a5356aefSYogesh Narayan Gaur struct spi_controller *ctlr; 999a5356aefSYogesh Narayan Gaur struct device *dev = &pdev->dev; 1000a5356aefSYogesh Narayan Gaur struct device_node *np = dev->of_node; 1001a5356aefSYogesh Narayan Gaur struct resource *res; 1002a5356aefSYogesh Narayan Gaur struct nxp_fspi *f; 1003a5356aefSYogesh Narayan Gaur int ret; 100471d80563SRan Wang u32 reg; 1005a5356aefSYogesh Narayan Gaur 1006a5356aefSYogesh Narayan Gaur ctlr = spi_alloc_master(&pdev->dev, sizeof(*f)); 1007a5356aefSYogesh Narayan Gaur if (!ctlr) 1008a5356aefSYogesh Narayan Gaur return -ENOMEM; 1009a5356aefSYogesh Narayan Gaur 1010b3281794SYogesh Narayan Gaur ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL | 1011b3281794SYogesh Narayan Gaur SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL; 1012a5356aefSYogesh Narayan Gaur 1013a5356aefSYogesh Narayan Gaur f = spi_controller_get_devdata(ctlr); 1014a5356aefSYogesh Narayan Gaur f->dev = dev; 101555ab8487Skuldip dwivedi f->devtype_data = device_get_match_data(dev); 1016a5356aefSYogesh Narayan Gaur if (!f->devtype_data) { 1017a5356aefSYogesh Narayan Gaur ret = -ENODEV; 1018a5356aefSYogesh Narayan Gaur goto err_put_ctrl; 1019a5356aefSYogesh Narayan Gaur } 1020a5356aefSYogesh Narayan Gaur 1021a5356aefSYogesh Narayan Gaur platform_set_drvdata(pdev, f); 1022a5356aefSYogesh Narayan Gaur 1023a5356aefSYogesh Narayan Gaur /* find the resources - configuration register address space */ 102455ab8487Skuldip dwivedi if (is_acpi_node(f->dev->fwnode)) 102555ab8487Skuldip dwivedi res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 102655ab8487Skuldip dwivedi else 102755ab8487Skuldip dwivedi res = platform_get_resource_byname(pdev, 102855ab8487Skuldip dwivedi IORESOURCE_MEM, "fspi_base"); 102955ab8487Skuldip dwivedi 1030a5356aefSYogesh Narayan Gaur f->iobase = devm_ioremap_resource(dev, res); 1031a5356aefSYogesh Narayan Gaur if (IS_ERR(f->iobase)) { 1032a5356aefSYogesh Narayan Gaur ret = PTR_ERR(f->iobase); 1033a5356aefSYogesh Narayan Gaur goto err_put_ctrl; 1034a5356aefSYogesh Narayan Gaur } 1035a5356aefSYogesh Narayan Gaur 103671d80563SRan Wang /* Clear potential interrupts */ 103771d80563SRan Wang reg = fspi_readl(f, f->iobase + FSPI_INTR); 103871d80563SRan Wang if (reg) 103971d80563SRan Wang fspi_writel(f, reg, f->iobase + FSPI_INTR); 104071d80563SRan Wang 104171d80563SRan Wang 1042a5356aefSYogesh Narayan Gaur /* find the resources - controller memory mapped space */ 104355ab8487Skuldip dwivedi if (is_acpi_node(f->dev->fwnode)) 104455ab8487Skuldip dwivedi res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 104555ab8487Skuldip dwivedi else 104655ab8487Skuldip dwivedi res = platform_get_resource_byname(pdev, 104755ab8487Skuldip dwivedi IORESOURCE_MEM, "fspi_mmap"); 104855ab8487Skuldip dwivedi 10491a421ebaSDan Carpenter if (!res) { 10501a421ebaSDan Carpenter ret = -ENODEV; 1051a5356aefSYogesh Narayan Gaur goto err_put_ctrl; 1052a5356aefSYogesh Narayan Gaur } 1053a5356aefSYogesh Narayan Gaur 1054a5356aefSYogesh Narayan Gaur /* assign memory mapped starting address and mapped size. */ 1055a5356aefSYogesh Narayan Gaur f->memmap_phy = res->start; 1056a5356aefSYogesh Narayan Gaur f->memmap_phy_size = resource_size(res); 1057a5356aefSYogesh Narayan Gaur 1058a5356aefSYogesh Narayan Gaur /* find the clocks */ 105955ab8487Skuldip dwivedi if (dev_of_node(&pdev->dev)) { 1060a5356aefSYogesh Narayan Gaur f->clk_en = devm_clk_get(dev, "fspi_en"); 1061a5356aefSYogesh Narayan Gaur if (IS_ERR(f->clk_en)) { 1062a5356aefSYogesh Narayan Gaur ret = PTR_ERR(f->clk_en); 1063a5356aefSYogesh Narayan Gaur goto err_put_ctrl; 1064a5356aefSYogesh Narayan Gaur } 1065a5356aefSYogesh Narayan Gaur 1066a5356aefSYogesh Narayan Gaur f->clk = devm_clk_get(dev, "fspi"); 1067a5356aefSYogesh Narayan Gaur if (IS_ERR(f->clk)) { 1068a5356aefSYogesh Narayan Gaur ret = PTR_ERR(f->clk); 1069a5356aefSYogesh Narayan Gaur goto err_put_ctrl; 1070a5356aefSYogesh Narayan Gaur } 1071a5356aefSYogesh Narayan Gaur 1072a5356aefSYogesh Narayan Gaur ret = nxp_fspi_clk_prep_enable(f); 1073a5356aefSYogesh Narayan Gaur if (ret) { 1074a5356aefSYogesh Narayan Gaur dev_err(dev, "can not enable the clock\n"); 1075a5356aefSYogesh Narayan Gaur goto err_put_ctrl; 1076a5356aefSYogesh Narayan Gaur } 107755ab8487Skuldip dwivedi } 1078a5356aefSYogesh Narayan Gaur 1079a5356aefSYogesh Narayan Gaur /* find the irq */ 1080a5356aefSYogesh Narayan Gaur ret = platform_get_irq(pdev, 0); 10816b8ac10eSStephen Boyd if (ret < 0) 1082a5356aefSYogesh Narayan Gaur goto err_disable_clk; 1083a5356aefSYogesh Narayan Gaur 1084a5356aefSYogesh Narayan Gaur ret = devm_request_irq(dev, ret, 1085a5356aefSYogesh Narayan Gaur nxp_fspi_irq_handler, 0, pdev->name, f); 1086a5356aefSYogesh Narayan Gaur if (ret) { 1087a5356aefSYogesh Narayan Gaur dev_err(dev, "failed to request irq: %d\n", ret); 1088a5356aefSYogesh Narayan Gaur goto err_disable_clk; 1089a5356aefSYogesh Narayan Gaur } 1090a5356aefSYogesh Narayan Gaur 1091a5356aefSYogesh Narayan Gaur mutex_init(&f->lock); 1092a5356aefSYogesh Narayan Gaur 1093a5356aefSYogesh Narayan Gaur ctlr->bus_num = -1; 1094a5356aefSYogesh Narayan Gaur ctlr->num_chipselect = NXP_FSPI_MAX_CHIPSELECT; 1095a5356aefSYogesh Narayan Gaur ctlr->mem_ops = &nxp_fspi_mem_ops; 1096a5356aefSYogesh Narayan Gaur 1097a5356aefSYogesh Narayan Gaur nxp_fspi_default_setup(f); 1098a5356aefSYogesh Narayan Gaur 1099a5356aefSYogesh Narayan Gaur ctlr->dev.of_node = np; 1100a5356aefSYogesh Narayan Gaur 110169c23dbfSChuhong Yuan ret = devm_spi_register_controller(&pdev->dev, ctlr); 1102a5356aefSYogesh Narayan Gaur if (ret) 1103a5356aefSYogesh Narayan Gaur goto err_destroy_mutex; 1104a5356aefSYogesh Narayan Gaur 1105a5356aefSYogesh Narayan Gaur return 0; 1106a5356aefSYogesh Narayan Gaur 1107a5356aefSYogesh Narayan Gaur err_destroy_mutex: 1108a5356aefSYogesh Narayan Gaur mutex_destroy(&f->lock); 1109a5356aefSYogesh Narayan Gaur 1110a5356aefSYogesh Narayan Gaur err_disable_clk: 1111a5356aefSYogesh Narayan Gaur nxp_fspi_clk_disable_unprep(f); 1112a5356aefSYogesh Narayan Gaur 1113a5356aefSYogesh Narayan Gaur err_put_ctrl: 1114a5356aefSYogesh Narayan Gaur spi_controller_put(ctlr); 1115a5356aefSYogesh Narayan Gaur 1116a5356aefSYogesh Narayan Gaur dev_err(dev, "NXP FSPI probe failed\n"); 1117a5356aefSYogesh Narayan Gaur return ret; 1118a5356aefSYogesh Narayan Gaur } 1119a5356aefSYogesh Narayan Gaur 1120a5356aefSYogesh Narayan Gaur static int nxp_fspi_remove(struct platform_device *pdev) 1121a5356aefSYogesh Narayan Gaur { 1122a5356aefSYogesh Narayan Gaur struct nxp_fspi *f = platform_get_drvdata(pdev); 1123a5356aefSYogesh Narayan Gaur 1124a5356aefSYogesh Narayan Gaur /* disable the hardware */ 1125a5356aefSYogesh Narayan Gaur fspi_writel(f, FSPI_MCR0_MDIS, f->iobase + FSPI_MCR0); 1126a5356aefSYogesh Narayan Gaur 1127a5356aefSYogesh Narayan Gaur nxp_fspi_clk_disable_unprep(f); 1128a5356aefSYogesh Narayan Gaur 1129a5356aefSYogesh Narayan Gaur mutex_destroy(&f->lock); 1130a5356aefSYogesh Narayan Gaur 1131d166a735SHan Xu if (f->ahb_addr) 1132d166a735SHan Xu iounmap(f->ahb_addr); 1133d166a735SHan Xu 1134a5356aefSYogesh Narayan Gaur return 0; 1135a5356aefSYogesh Narayan Gaur } 1136a5356aefSYogesh Narayan Gaur 1137a5356aefSYogesh Narayan Gaur static int nxp_fspi_suspend(struct device *dev) 1138a5356aefSYogesh Narayan Gaur { 1139a5356aefSYogesh Narayan Gaur return 0; 1140a5356aefSYogesh Narayan Gaur } 1141a5356aefSYogesh Narayan Gaur 1142a5356aefSYogesh Narayan Gaur static int nxp_fspi_resume(struct device *dev) 1143a5356aefSYogesh Narayan Gaur { 1144a5356aefSYogesh Narayan Gaur struct nxp_fspi *f = dev_get_drvdata(dev); 1145a5356aefSYogesh Narayan Gaur 1146a5356aefSYogesh Narayan Gaur nxp_fspi_default_setup(f); 1147a5356aefSYogesh Narayan Gaur 1148a5356aefSYogesh Narayan Gaur return 0; 1149a5356aefSYogesh Narayan Gaur } 1150a5356aefSYogesh Narayan Gaur 1151a5356aefSYogesh Narayan Gaur static const struct of_device_id nxp_fspi_dt_ids[] = { 1152a5356aefSYogesh Narayan Gaur { .compatible = "nxp,lx2160a-fspi", .data = (void *)&lx2160a_data, }, 1153941be8a7SHan Xu { .compatible = "nxp,imx8mm-fspi", .data = (void *)&imx8mm_data, }, 1154941be8a7SHan Xu { .compatible = "nxp,imx8qxp-fspi", .data = (void *)&imx8qxp_data, }, 1155a5356aefSYogesh Narayan Gaur { /* sentinel */ } 1156a5356aefSYogesh Narayan Gaur }; 1157a5356aefSYogesh Narayan Gaur MODULE_DEVICE_TABLE(of, nxp_fspi_dt_ids); 1158a5356aefSYogesh Narayan Gaur 115955ab8487Skuldip dwivedi #ifdef CONFIG_ACPI 116055ab8487Skuldip dwivedi static const struct acpi_device_id nxp_fspi_acpi_ids[] = { 116155ab8487Skuldip dwivedi { "NXP0009", .driver_data = (kernel_ulong_t)&lx2160a_data, }, 116255ab8487Skuldip dwivedi {} 116355ab8487Skuldip dwivedi }; 116455ab8487Skuldip dwivedi MODULE_DEVICE_TABLE(acpi, nxp_fspi_acpi_ids); 116555ab8487Skuldip dwivedi #endif 116655ab8487Skuldip dwivedi 1167a5356aefSYogesh Narayan Gaur static const struct dev_pm_ops nxp_fspi_pm_ops = { 1168a5356aefSYogesh Narayan Gaur .suspend = nxp_fspi_suspend, 1169a5356aefSYogesh Narayan Gaur .resume = nxp_fspi_resume, 1170a5356aefSYogesh Narayan Gaur }; 1171a5356aefSYogesh Narayan Gaur 1172a5356aefSYogesh Narayan Gaur static struct platform_driver nxp_fspi_driver = { 1173a5356aefSYogesh Narayan Gaur .driver = { 1174a5356aefSYogesh Narayan Gaur .name = "nxp-fspi", 1175a5356aefSYogesh Narayan Gaur .of_match_table = nxp_fspi_dt_ids, 117655ab8487Skuldip dwivedi .acpi_match_table = ACPI_PTR(nxp_fspi_acpi_ids), 1177a5356aefSYogesh Narayan Gaur .pm = &nxp_fspi_pm_ops, 1178a5356aefSYogesh Narayan Gaur }, 1179a5356aefSYogesh Narayan Gaur .probe = nxp_fspi_probe, 1180a5356aefSYogesh Narayan Gaur .remove = nxp_fspi_remove, 1181a5356aefSYogesh Narayan Gaur }; 1182a5356aefSYogesh Narayan Gaur module_platform_driver(nxp_fspi_driver); 1183a5356aefSYogesh Narayan Gaur 1184a5356aefSYogesh Narayan Gaur MODULE_DESCRIPTION("NXP FSPI Controller Driver"); 1185a5356aefSYogesh Narayan Gaur MODULE_AUTHOR("NXP Semiconductor"); 1186a5356aefSYogesh Narayan Gaur MODULE_AUTHOR("Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>"); 1187ce6f0697SYogesh Narayan Gaur MODULE_AUTHOR("Boris Brezillon <bbrezillon@kernel.org>"); 1188a5356aefSYogesh Narayan Gaur MODULE_AUTHOR("Frieder Schrempf <frieder.schrempf@kontron.de>"); 1189ce6f0697SYogesh Narayan Gaur MODULE_LICENSE("GPL v2"); 1190