1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2018 Nuvoton Technology corporation. 3 4 #include <linux/kernel.h> 5 #include <linux/bitfield.h> 6 #include <linux/bitops.h> 7 #include <linux/clk.h> 8 #include <linux/interrupt.h> 9 #include <linux/io.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 #include <linux/spi/spi.h> 13 #include <linux/gpio.h> 14 #include <linux/of_gpio.h> 15 #include <linux/reset.h> 16 17 #include <asm/unaligned.h> 18 19 #include <linux/regmap.h> 20 #include <linux/mfd/syscon.h> 21 22 struct npcm_pspi { 23 struct completion xfer_done; 24 struct reset_control *reset; 25 struct spi_master *master; 26 unsigned int tx_bytes; 27 unsigned int rx_bytes; 28 void __iomem *base; 29 bool is_save_param; 30 u8 bits_per_word; 31 const u8 *tx_buf; 32 struct clk *clk; 33 u32 speed_hz; 34 u8 *rx_buf; 35 u16 mode; 36 u32 id; 37 }; 38 39 #define DRIVER_NAME "npcm-pspi" 40 41 #define NPCM_PSPI_DATA 0x00 42 #define NPCM_PSPI_CTL1 0x02 43 #define NPCM_PSPI_STAT 0x04 44 45 /* definitions for control and status register */ 46 #define NPCM_PSPI_CTL1_SPIEN BIT(0) 47 #define NPCM_PSPI_CTL1_MOD BIT(2) 48 #define NPCM_PSPI_CTL1_EIR BIT(5) 49 #define NPCM_PSPI_CTL1_EIW BIT(6) 50 #define NPCM_PSPI_CTL1_SCM BIT(7) 51 #define NPCM_PSPI_CTL1_SCIDL BIT(8) 52 #define NPCM_PSPI_CTL1_SCDV6_0 GENMASK(15, 9) 53 54 #define NPCM_PSPI_STAT_BSY BIT(0) 55 #define NPCM_PSPI_STAT_RBF BIT(1) 56 57 /* general definitions */ 58 #define NPCM_PSPI_TIMEOUT_MS 2000 59 #define NPCM_PSPI_MAX_CLK_DIVIDER 256 60 #define NPCM_PSPI_MIN_CLK_DIVIDER 4 61 #define NPCM_PSPI_DEFAULT_CLK 25000000 62 63 static inline unsigned int bytes_per_word(unsigned int bits) 64 { 65 return bits <= 8 ? 1 : 2; 66 } 67 68 static inline void npcm_pspi_irq_enable(struct npcm_pspi *priv, u16 mask) 69 { 70 u16 val; 71 72 val = ioread16(priv->base + NPCM_PSPI_CTL1); 73 val |= mask; 74 iowrite16(val, priv->base + NPCM_PSPI_CTL1); 75 } 76 77 static inline void npcm_pspi_irq_disable(struct npcm_pspi *priv, u16 mask) 78 { 79 u16 val; 80 81 val = ioread16(priv->base + NPCM_PSPI_CTL1); 82 val &= ~mask; 83 iowrite16(val, priv->base + NPCM_PSPI_CTL1); 84 } 85 86 static inline void npcm_pspi_enable(struct npcm_pspi *priv) 87 { 88 u16 val; 89 90 val = ioread16(priv->base + NPCM_PSPI_CTL1); 91 val |= NPCM_PSPI_CTL1_SPIEN; 92 iowrite16(val, priv->base + NPCM_PSPI_CTL1); 93 } 94 95 static inline void npcm_pspi_disable(struct npcm_pspi *priv) 96 { 97 u16 val; 98 99 val = ioread16(priv->base + NPCM_PSPI_CTL1); 100 val &= ~NPCM_PSPI_CTL1_SPIEN; 101 iowrite16(val, priv->base + NPCM_PSPI_CTL1); 102 } 103 104 static void npcm_pspi_set_mode(struct spi_device *spi) 105 { 106 struct npcm_pspi *priv = spi_master_get_devdata(spi->master); 107 u16 regtemp; 108 u16 mode_val; 109 110 switch (spi->mode & (SPI_CPOL | SPI_CPHA)) { 111 case SPI_MODE_0: 112 mode_val = 0; 113 break; 114 case SPI_MODE_1: 115 mode_val = NPCM_PSPI_CTL1_SCIDL; 116 break; 117 case SPI_MODE_2: 118 mode_val = NPCM_PSPI_CTL1_SCM; 119 break; 120 case SPI_MODE_3: 121 mode_val = NPCM_PSPI_CTL1_SCIDL | NPCM_PSPI_CTL1_SCM; 122 break; 123 } 124 125 regtemp = ioread16(priv->base + NPCM_PSPI_CTL1); 126 regtemp &= ~(NPCM_PSPI_CTL1_SCM | NPCM_PSPI_CTL1_SCIDL); 127 iowrite16(regtemp | mode_val, priv->base + NPCM_PSPI_CTL1); 128 } 129 130 static void npcm_pspi_set_transfer_size(struct npcm_pspi *priv, int size) 131 { 132 u16 regtemp; 133 134 regtemp = ioread16(NPCM_PSPI_CTL1 + priv->base); 135 136 switch (size) { 137 case 8: 138 regtemp &= ~NPCM_PSPI_CTL1_MOD; 139 break; 140 case 16: 141 regtemp |= NPCM_PSPI_CTL1_MOD; 142 break; 143 } 144 145 iowrite16(regtemp, NPCM_PSPI_CTL1 + priv->base); 146 } 147 148 static void npcm_pspi_set_baudrate(struct npcm_pspi *priv, unsigned int speed) 149 { 150 u32 ckdiv; 151 u16 regtemp; 152 153 /* the supported rates are numbers from 4 to 256. */ 154 ckdiv = DIV_ROUND_CLOSEST(clk_get_rate(priv->clk), (2 * speed)) - 1; 155 156 regtemp = ioread16(NPCM_PSPI_CTL1 + priv->base); 157 regtemp &= ~NPCM_PSPI_CTL1_SCDV6_0; 158 iowrite16(regtemp | (ckdiv << 9), NPCM_PSPI_CTL1 + priv->base); 159 } 160 161 static void npcm_pspi_setup_transfer(struct spi_device *spi, 162 struct spi_transfer *t) 163 { 164 struct npcm_pspi *priv = spi_master_get_devdata(spi->master); 165 166 priv->tx_buf = t->tx_buf; 167 priv->rx_buf = t->rx_buf; 168 priv->tx_bytes = t->len; 169 priv->rx_bytes = t->len; 170 171 if (!priv->is_save_param || priv->mode != spi->mode) { 172 npcm_pspi_set_mode(spi); 173 priv->mode = spi->mode; 174 } 175 176 /* 177 * If transfer is even length, and 8 bits per word transfer, 178 * then implement 16 bits-per-word transfer. 179 */ 180 if (priv->bits_per_word == 8 && !(t->len & 0x1)) 181 t->bits_per_word = 16; 182 183 if (!priv->is_save_param || priv->bits_per_word != t->bits_per_word) { 184 npcm_pspi_set_transfer_size(priv, t->bits_per_word); 185 priv->bits_per_word = t->bits_per_word; 186 } 187 188 if (!priv->is_save_param || priv->speed_hz != t->speed_hz) { 189 npcm_pspi_set_baudrate(priv, t->speed_hz); 190 priv->speed_hz = t->speed_hz; 191 } 192 193 if (!priv->is_save_param) 194 priv->is_save_param = true; 195 } 196 197 static void npcm_pspi_send(struct npcm_pspi *priv) 198 { 199 int wsize; 200 u16 val; 201 202 wsize = min(bytes_per_word(priv->bits_per_word), priv->tx_bytes); 203 priv->tx_bytes -= wsize; 204 205 if (!priv->tx_buf) 206 return; 207 208 switch (wsize) { 209 case 1: 210 val = *priv->tx_buf++; 211 iowrite8(val, NPCM_PSPI_DATA + priv->base); 212 break; 213 case 2: 214 val = *priv->tx_buf++; 215 val = *priv->tx_buf++ | (val << 8); 216 iowrite16(val, NPCM_PSPI_DATA + priv->base); 217 break; 218 default: 219 WARN_ON_ONCE(1); 220 return; 221 } 222 } 223 224 static void npcm_pspi_recv(struct npcm_pspi *priv) 225 { 226 int rsize; 227 u16 val; 228 229 rsize = min(bytes_per_word(priv->bits_per_word), priv->rx_bytes); 230 priv->rx_bytes -= rsize; 231 232 if (!priv->rx_buf) 233 return; 234 235 switch (rsize) { 236 case 1: 237 *priv->rx_buf++ = ioread8(priv->base + NPCM_PSPI_DATA); 238 break; 239 case 2: 240 val = ioread16(priv->base + NPCM_PSPI_DATA); 241 *priv->rx_buf++ = (val >> 8); 242 *priv->rx_buf++ = val & 0xff; 243 break; 244 default: 245 WARN_ON_ONCE(1); 246 return; 247 } 248 } 249 250 static int npcm_pspi_transfer_one(struct spi_master *master, 251 struct spi_device *spi, 252 struct spi_transfer *t) 253 { 254 struct npcm_pspi *priv = spi_master_get_devdata(master); 255 int status; 256 257 npcm_pspi_setup_transfer(spi, t); 258 reinit_completion(&priv->xfer_done); 259 npcm_pspi_enable(priv); 260 status = wait_for_completion_timeout(&priv->xfer_done, 261 msecs_to_jiffies 262 (NPCM_PSPI_TIMEOUT_MS)); 263 if (status == 0) { 264 npcm_pspi_disable(priv); 265 return -ETIMEDOUT; 266 } 267 268 return 0; 269 } 270 271 static int npcm_pspi_prepare_transfer_hardware(struct spi_master *master) 272 { 273 struct npcm_pspi *priv = spi_master_get_devdata(master); 274 275 npcm_pspi_irq_enable(priv, NPCM_PSPI_CTL1_EIR | NPCM_PSPI_CTL1_EIW); 276 277 return 0; 278 } 279 280 static int npcm_pspi_unprepare_transfer_hardware(struct spi_master *master) 281 { 282 struct npcm_pspi *priv = spi_master_get_devdata(master); 283 284 npcm_pspi_irq_disable(priv, NPCM_PSPI_CTL1_EIR | NPCM_PSPI_CTL1_EIW); 285 286 return 0; 287 } 288 289 static void npcm_pspi_reset_hw(struct npcm_pspi *priv) 290 { 291 reset_control_assert(priv->reset); 292 udelay(5); 293 reset_control_deassert(priv->reset); 294 } 295 296 static irqreturn_t npcm_pspi_handler(int irq, void *dev_id) 297 { 298 struct npcm_pspi *priv = dev_id; 299 u8 stat; 300 301 stat = ioread8(priv->base + NPCM_PSPI_STAT); 302 303 if (!priv->tx_buf && !priv->rx_buf) 304 return IRQ_NONE; 305 306 if (priv->tx_buf) { 307 if (stat & NPCM_PSPI_STAT_RBF) { 308 ioread8(NPCM_PSPI_DATA + priv->base); 309 if (priv->tx_bytes == 0) { 310 npcm_pspi_disable(priv); 311 complete(&priv->xfer_done); 312 return IRQ_HANDLED; 313 } 314 } 315 316 if ((stat & NPCM_PSPI_STAT_BSY) == 0) 317 if (priv->tx_bytes) 318 npcm_pspi_send(priv); 319 } 320 321 if (priv->rx_buf) { 322 if (stat & NPCM_PSPI_STAT_RBF) { 323 if (!priv->rx_bytes) 324 return IRQ_NONE; 325 326 npcm_pspi_recv(priv); 327 328 if (!priv->rx_bytes) { 329 npcm_pspi_disable(priv); 330 complete(&priv->xfer_done); 331 return IRQ_HANDLED; 332 } 333 } 334 335 if (((stat & NPCM_PSPI_STAT_BSY) == 0) && !priv->tx_buf) 336 iowrite8(0x0, NPCM_PSPI_DATA + priv->base); 337 } 338 339 return IRQ_HANDLED; 340 } 341 342 static int npcm_pspi_probe(struct platform_device *pdev) 343 { 344 struct npcm_pspi *priv; 345 struct spi_master *master; 346 unsigned long clk_hz; 347 struct device_node *np = pdev->dev.of_node; 348 int num_cs, i; 349 int csgpio; 350 int irq; 351 int ret; 352 353 num_cs = of_gpio_named_count(np, "cs-gpios"); 354 if (num_cs < 0) 355 return num_cs; 356 357 master = spi_alloc_master(&pdev->dev, sizeof(*priv)); 358 if (!master) 359 return -ENOMEM; 360 361 platform_set_drvdata(pdev, master); 362 363 priv = spi_master_get_devdata(master); 364 priv->master = master; 365 priv->is_save_param = false; 366 367 priv->base = devm_platform_ioremap_resource(pdev, 0); 368 if (IS_ERR(priv->base)) { 369 ret = PTR_ERR(priv->base); 370 goto out_master_put; 371 } 372 373 priv->clk = devm_clk_get(&pdev->dev, NULL); 374 if (IS_ERR(priv->clk)) { 375 dev_err(&pdev->dev, "failed to get clock\n"); 376 ret = PTR_ERR(priv->clk); 377 goto out_master_put; 378 } 379 380 ret = clk_prepare_enable(priv->clk); 381 if (ret) 382 goto out_master_put; 383 384 irq = platform_get_irq(pdev, 0); 385 if (irq < 0) { 386 ret = irq; 387 goto out_disable_clk; 388 } 389 390 priv->reset = devm_reset_control_get(&pdev->dev, NULL); 391 if (IS_ERR(priv->reset)) { 392 ret = PTR_ERR(priv->reset); 393 goto out_disable_clk; 394 } 395 396 /* reset SPI-HW block */ 397 npcm_pspi_reset_hw(priv); 398 399 ret = devm_request_irq(&pdev->dev, irq, npcm_pspi_handler, 0, 400 "npcm-pspi", priv); 401 if (ret) { 402 dev_err(&pdev->dev, "failed to request IRQ\n"); 403 goto out_disable_clk; 404 } 405 406 init_completion(&priv->xfer_done); 407 408 clk_hz = clk_get_rate(priv->clk); 409 410 master->max_speed_hz = DIV_ROUND_UP(clk_hz, NPCM_PSPI_MIN_CLK_DIVIDER); 411 master->min_speed_hz = DIV_ROUND_UP(clk_hz, NPCM_PSPI_MAX_CLK_DIVIDER); 412 master->mode_bits = SPI_CPHA | SPI_CPOL; 413 master->dev.of_node = pdev->dev.of_node; 414 master->bus_num = -1; 415 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); 416 master->transfer_one = npcm_pspi_transfer_one; 417 master->prepare_transfer_hardware = 418 npcm_pspi_prepare_transfer_hardware; 419 master->unprepare_transfer_hardware = 420 npcm_pspi_unprepare_transfer_hardware; 421 master->num_chipselect = num_cs; 422 423 for (i = 0; i < num_cs; i++) { 424 csgpio = of_get_named_gpio(np, "cs-gpios", i); 425 if (csgpio < 0) { 426 dev_err(&pdev->dev, "failed to get csgpio#%u\n", i); 427 goto out_disable_clk; 428 } 429 dev_dbg(&pdev->dev, "csgpio#%u = %d\n", i, csgpio); 430 ret = devm_gpio_request_one(&pdev->dev, csgpio, 431 GPIOF_OUT_INIT_HIGH, DRIVER_NAME); 432 if (ret < 0) { 433 dev_err(&pdev->dev, 434 "failed to configure csgpio#%u %d\n" 435 , i, csgpio); 436 goto out_disable_clk; 437 } 438 } 439 440 /* set to default clock rate */ 441 npcm_pspi_set_baudrate(priv, NPCM_PSPI_DEFAULT_CLK); 442 443 ret = devm_spi_register_master(&pdev->dev, master); 444 if (ret) 445 goto out_disable_clk; 446 447 pr_info("NPCM Peripheral SPI %d probed\n", master->bus_num); 448 449 return 0; 450 451 out_disable_clk: 452 clk_disable_unprepare(priv->clk); 453 454 out_master_put: 455 spi_master_put(master); 456 return ret; 457 } 458 459 static int npcm_pspi_remove(struct platform_device *pdev) 460 { 461 struct spi_master *master = platform_get_drvdata(pdev); 462 struct npcm_pspi *priv = spi_master_get_devdata(master); 463 464 npcm_pspi_reset_hw(priv); 465 clk_disable_unprepare(priv->clk); 466 467 return 0; 468 } 469 470 static const struct of_device_id npcm_pspi_match[] = { 471 { .compatible = "nuvoton,npcm750-pspi", .data = NULL }, 472 {} 473 }; 474 MODULE_DEVICE_TABLE(of, npcm_pspi_match); 475 476 static struct platform_driver npcm_pspi_driver = { 477 .driver = { 478 .name = DRIVER_NAME, 479 .of_match_table = npcm_pspi_match, 480 }, 481 .probe = npcm_pspi_probe, 482 .remove = npcm_pspi_remove, 483 }; 484 module_platform_driver(npcm_pspi_driver); 485 486 MODULE_DESCRIPTION("NPCM peripheral SPI Controller driver"); 487 MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>"); 488 MODULE_LICENSE("GPL v2"); 489 490