1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2018 Nuvoton Technology corporation. 3 4 #include <linux/kernel.h> 5 #include <linux/bitfield.h> 6 #include <linux/bitops.h> 7 #include <linux/clk.h> 8 #include <linux/interrupt.h> 9 #include <linux/io.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 #include <linux/spi/spi.h> 13 #include <linux/gpio.h> 14 #include <linux/of_gpio.h> 15 16 #include <asm/unaligned.h> 17 18 #include <linux/regmap.h> 19 #include <linux/mfd/syscon.h> 20 21 struct npcm_pspi { 22 struct completion xfer_done; 23 struct regmap *rst_regmap; 24 struct spi_master *master; 25 unsigned int tx_bytes; 26 unsigned int rx_bytes; 27 void __iomem *base; 28 bool is_save_param; 29 u8 bits_per_word; 30 const u8 *tx_buf; 31 struct clk *clk; 32 u32 speed_hz; 33 u8 *rx_buf; 34 u16 mode; 35 u32 id; 36 }; 37 38 #define DRIVER_NAME "npcm-pspi" 39 40 #define NPCM_PSPI_DATA 0x00 41 #define NPCM_PSPI_CTL1 0x02 42 #define NPCM_PSPI_STAT 0x04 43 44 /* definitions for control and status register */ 45 #define NPCM_PSPI_CTL1_SPIEN BIT(0) 46 #define NPCM_PSPI_CTL1_MOD BIT(2) 47 #define NPCM_PSPI_CTL1_EIR BIT(5) 48 #define NPCM_PSPI_CTL1_EIW BIT(6) 49 #define NPCM_PSPI_CTL1_SCM BIT(7) 50 #define NPCM_PSPI_CTL1_SCIDL BIT(8) 51 #define NPCM_PSPI_CTL1_SCDV6_0 GENMASK(15, 9) 52 53 #define NPCM_PSPI_STAT_BSY BIT(0) 54 #define NPCM_PSPI_STAT_RBF BIT(1) 55 56 /* general definitions */ 57 #define NPCM_PSPI_TIMEOUT_MS 2000 58 #define NPCM_PSPI_MAX_CLK_DIVIDER 256 59 #define NPCM_PSPI_MIN_CLK_DIVIDER 4 60 #define NPCM_PSPI_DEFAULT_CLK 25000000 61 62 /* reset register */ 63 #define NPCM7XX_IPSRST2_OFFSET 0x24 64 65 #define NPCM7XX_PSPI1_RESET BIT(22) 66 #define NPCM7XX_PSPI2_RESET BIT(23) 67 68 static inline unsigned int bytes_per_word(unsigned int bits) 69 { 70 return bits <= 8 ? 1 : 2; 71 } 72 73 static inline void npcm_pspi_irq_enable(struct npcm_pspi *priv, u16 mask) 74 { 75 u16 val; 76 77 val = ioread16(priv->base + NPCM_PSPI_CTL1); 78 val |= mask; 79 iowrite16(val, priv->base + NPCM_PSPI_CTL1); 80 } 81 82 static inline void npcm_pspi_irq_disable(struct npcm_pspi *priv, u16 mask) 83 { 84 u16 val; 85 86 val = ioread16(priv->base + NPCM_PSPI_CTL1); 87 val &= ~mask; 88 iowrite16(val, priv->base + NPCM_PSPI_CTL1); 89 } 90 91 static inline void npcm_pspi_enable(struct npcm_pspi *priv) 92 { 93 u16 val; 94 95 val = ioread16(priv->base + NPCM_PSPI_CTL1); 96 val |= NPCM_PSPI_CTL1_SPIEN; 97 iowrite16(val, priv->base + NPCM_PSPI_CTL1); 98 } 99 100 static inline void npcm_pspi_disable(struct npcm_pspi *priv) 101 { 102 u16 val; 103 104 val = ioread16(priv->base + NPCM_PSPI_CTL1); 105 val &= ~NPCM_PSPI_CTL1_SPIEN; 106 iowrite16(val, priv->base + NPCM_PSPI_CTL1); 107 } 108 109 static void npcm_pspi_set_mode(struct spi_device *spi) 110 { 111 struct npcm_pspi *priv = spi_master_get_devdata(spi->master); 112 u16 regtemp; 113 u16 mode_val; 114 115 switch (spi->mode & (SPI_CPOL | SPI_CPHA)) { 116 case SPI_MODE_0: 117 mode_val = 0; 118 break; 119 case SPI_MODE_1: 120 mode_val = NPCM_PSPI_CTL1_SCIDL; 121 break; 122 case SPI_MODE_2: 123 mode_val = NPCM_PSPI_CTL1_SCM; 124 break; 125 case SPI_MODE_3: 126 mode_val = NPCM_PSPI_CTL1_SCIDL | NPCM_PSPI_CTL1_SCM; 127 break; 128 } 129 130 regtemp = ioread16(priv->base + NPCM_PSPI_CTL1); 131 regtemp &= ~(NPCM_PSPI_CTL1_SCM | NPCM_PSPI_CTL1_SCIDL); 132 iowrite16(regtemp | mode_val, priv->base + NPCM_PSPI_CTL1); 133 } 134 135 static void npcm_pspi_set_transfer_size(struct npcm_pspi *priv, int size) 136 { 137 u16 regtemp; 138 139 regtemp = ioread16(NPCM_PSPI_CTL1 + priv->base); 140 141 switch (size) { 142 case 8: 143 regtemp &= ~NPCM_PSPI_CTL1_MOD; 144 break; 145 case 16: 146 regtemp |= NPCM_PSPI_CTL1_MOD; 147 break; 148 } 149 150 iowrite16(regtemp, NPCM_PSPI_CTL1 + priv->base); 151 } 152 153 static void npcm_pspi_set_baudrate(struct npcm_pspi *priv, unsigned int speed) 154 { 155 u32 ckdiv; 156 u16 regtemp; 157 158 /* the supported rates are numbers from 4 to 256. */ 159 ckdiv = DIV_ROUND_CLOSEST(clk_get_rate(priv->clk), (2 * speed)) - 1; 160 161 regtemp = ioread16(NPCM_PSPI_CTL1 + priv->base); 162 regtemp &= ~NPCM_PSPI_CTL1_SCDV6_0; 163 iowrite16(regtemp | (ckdiv << 9), NPCM_PSPI_CTL1 + priv->base); 164 } 165 166 static void npcm_pspi_setup_transfer(struct spi_device *spi, 167 struct spi_transfer *t) 168 { 169 struct npcm_pspi *priv = spi_master_get_devdata(spi->master); 170 171 priv->tx_buf = t->tx_buf; 172 priv->rx_buf = t->rx_buf; 173 priv->tx_bytes = t->len; 174 priv->rx_bytes = t->len; 175 176 if (!priv->is_save_param || priv->mode != spi->mode) { 177 npcm_pspi_set_mode(spi); 178 priv->mode = spi->mode; 179 } 180 181 if (!priv->is_save_param || priv->bits_per_word != t->bits_per_word) { 182 npcm_pspi_set_transfer_size(priv, t->bits_per_word); 183 priv->bits_per_word = t->bits_per_word; 184 } 185 186 if (!priv->is_save_param || priv->speed_hz != t->speed_hz) { 187 npcm_pspi_set_baudrate(priv, t->speed_hz); 188 priv->speed_hz = t->speed_hz; 189 } 190 191 if (!priv->is_save_param) 192 priv->is_save_param = true; 193 } 194 195 static void npcm_pspi_send(struct npcm_pspi *priv) 196 { 197 int wsize; 198 199 wsize = min(bytes_per_word(priv->bits_per_word), priv->tx_bytes); 200 priv->tx_bytes -= wsize; 201 202 if (!priv->tx_buf) 203 return; 204 205 switch (wsize) { 206 case 1: 207 iowrite8(*priv->tx_buf, NPCM_PSPI_DATA + priv->base); 208 break; 209 case 2: 210 iowrite16(*priv->tx_buf, NPCM_PSPI_DATA + priv->base); 211 break; 212 default: 213 WARN_ON_ONCE(1); 214 return; 215 } 216 217 priv->tx_buf += wsize; 218 } 219 220 static void npcm_pspi_recv(struct npcm_pspi *priv) 221 { 222 int rsize; 223 u16 val; 224 225 rsize = min(bytes_per_word(priv->bits_per_word), priv->rx_bytes); 226 priv->rx_bytes -= rsize; 227 228 if (!priv->rx_buf) 229 return; 230 231 switch (rsize) { 232 case 1: 233 val = ioread8(priv->base + NPCM_PSPI_DATA); 234 break; 235 case 2: 236 val = ioread16(priv->base + NPCM_PSPI_DATA); 237 break; 238 default: 239 WARN_ON_ONCE(1); 240 return; 241 } 242 243 *priv->rx_buf = val; 244 priv->rx_buf += rsize; 245 } 246 247 static int npcm_pspi_transfer_one(struct spi_master *master, 248 struct spi_device *spi, 249 struct spi_transfer *t) 250 { 251 struct npcm_pspi *priv = spi_master_get_devdata(master); 252 int status; 253 254 npcm_pspi_setup_transfer(spi, t); 255 reinit_completion(&priv->xfer_done); 256 npcm_pspi_enable(priv); 257 status = wait_for_completion_timeout(&priv->xfer_done, 258 msecs_to_jiffies 259 (NPCM_PSPI_TIMEOUT_MS)); 260 if (status == 0) { 261 npcm_pspi_disable(priv); 262 return -ETIMEDOUT; 263 } 264 265 return 0; 266 } 267 268 static int npcm_pspi_prepare_transfer_hardware(struct spi_master *master) 269 { 270 struct npcm_pspi *priv = spi_master_get_devdata(master); 271 272 npcm_pspi_irq_enable(priv, NPCM_PSPI_CTL1_EIR | NPCM_PSPI_CTL1_EIW); 273 274 return 0; 275 } 276 277 static int npcm_pspi_unprepare_transfer_hardware(struct spi_master *master) 278 { 279 struct npcm_pspi *priv = spi_master_get_devdata(master); 280 281 npcm_pspi_irq_disable(priv, NPCM_PSPI_CTL1_EIR | NPCM_PSPI_CTL1_EIW); 282 283 return 0; 284 } 285 286 static void npcm_pspi_reset_hw(struct npcm_pspi *priv) 287 { 288 regmap_write(priv->rst_regmap, NPCM7XX_IPSRST2_OFFSET, 289 NPCM7XX_PSPI1_RESET << priv->id); 290 regmap_write(priv->rst_regmap, NPCM7XX_IPSRST2_OFFSET, 0x0); 291 } 292 293 static irqreturn_t npcm_pspi_handler(int irq, void *dev_id) 294 { 295 struct npcm_pspi *priv = dev_id; 296 u8 stat; 297 298 stat = ioread8(priv->base + NPCM_PSPI_STAT); 299 300 if (!priv->tx_buf && !priv->rx_buf) 301 return IRQ_NONE; 302 303 if (priv->tx_buf) { 304 if (stat & NPCM_PSPI_STAT_RBF) { 305 ioread8(NPCM_PSPI_DATA + priv->base); 306 if (priv->tx_bytes == 0) { 307 npcm_pspi_disable(priv); 308 complete(&priv->xfer_done); 309 return IRQ_HANDLED; 310 } 311 } 312 313 if ((stat & NPCM_PSPI_STAT_BSY) == 0) 314 if (priv->tx_bytes) 315 npcm_pspi_send(priv); 316 } 317 318 if (priv->rx_buf) { 319 if (stat & NPCM_PSPI_STAT_RBF) { 320 if (!priv->rx_bytes) 321 return IRQ_NONE; 322 323 npcm_pspi_recv(priv); 324 325 if (!priv->rx_bytes) { 326 npcm_pspi_disable(priv); 327 complete(&priv->xfer_done); 328 return IRQ_HANDLED; 329 } 330 } 331 332 if (((stat & NPCM_PSPI_STAT_BSY) == 0) && !priv->tx_buf) 333 iowrite8(0x0, NPCM_PSPI_DATA + priv->base); 334 } 335 336 return IRQ_HANDLED; 337 } 338 339 static int npcm_pspi_probe(struct platform_device *pdev) 340 { 341 struct npcm_pspi *priv; 342 struct spi_master *master; 343 unsigned long clk_hz; 344 struct device_node *np = pdev->dev.of_node; 345 int num_cs, i; 346 int csgpio; 347 int irq; 348 int ret; 349 350 num_cs = of_gpio_named_count(np, "cs-gpios"); 351 if (num_cs < 0) 352 return num_cs; 353 354 pdev->id = of_alias_get_id(np, "spi"); 355 if (pdev->id < 0) 356 pdev->id = 0; 357 358 master = spi_alloc_master(&pdev->dev, sizeof(*priv)); 359 if (!master) 360 return -ENOMEM; 361 362 platform_set_drvdata(pdev, master); 363 364 priv = spi_master_get_devdata(master); 365 priv->master = master; 366 priv->is_save_param = false; 367 priv->id = pdev->id; 368 369 priv->base = devm_platform_ioremap_resource(pdev, 0); 370 if (IS_ERR(priv->base)) { 371 ret = PTR_ERR(priv->base); 372 goto out_master_put; 373 } 374 375 priv->clk = devm_clk_get(&pdev->dev, NULL); 376 if (IS_ERR(priv->clk)) { 377 dev_err(&pdev->dev, "failed to get clock\n"); 378 ret = PTR_ERR(priv->clk); 379 goto out_master_put; 380 } 381 382 ret = clk_prepare_enable(priv->clk); 383 if (ret) 384 goto out_master_put; 385 386 irq = platform_get_irq(pdev, 0); 387 if (irq < 0) { 388 ret = irq; 389 goto out_disable_clk; 390 } 391 392 priv->rst_regmap = 393 syscon_regmap_lookup_by_compatible("nuvoton,npcm750-rst"); 394 if (IS_ERR(priv->rst_regmap)) { 395 dev_err(&pdev->dev, "failed to find nuvoton,npcm750-rst\n"); 396 return PTR_ERR(priv->rst_regmap); 397 } 398 399 /* reset SPI-HW block */ 400 npcm_pspi_reset_hw(priv); 401 402 ret = devm_request_irq(&pdev->dev, irq, npcm_pspi_handler, 0, 403 "npcm-pspi", priv); 404 if (ret) { 405 dev_err(&pdev->dev, "failed to request IRQ\n"); 406 goto out_disable_clk; 407 } 408 409 init_completion(&priv->xfer_done); 410 411 clk_hz = clk_get_rate(priv->clk); 412 413 master->max_speed_hz = DIV_ROUND_UP(clk_hz, NPCM_PSPI_MIN_CLK_DIVIDER); 414 master->min_speed_hz = DIV_ROUND_UP(clk_hz, NPCM_PSPI_MAX_CLK_DIVIDER); 415 master->mode_bits = SPI_CPHA | SPI_CPOL; 416 master->dev.of_node = pdev->dev.of_node; 417 master->bus_num = pdev->id; 418 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); 419 master->transfer_one = npcm_pspi_transfer_one; 420 master->prepare_transfer_hardware = 421 npcm_pspi_prepare_transfer_hardware; 422 master->unprepare_transfer_hardware = 423 npcm_pspi_unprepare_transfer_hardware; 424 master->num_chipselect = num_cs; 425 426 for (i = 0; i < num_cs; i++) { 427 csgpio = of_get_named_gpio(np, "cs-gpios", i); 428 if (csgpio < 0) { 429 dev_err(&pdev->dev, "failed to get csgpio#%u\n", i); 430 goto out_disable_clk; 431 } 432 dev_dbg(&pdev->dev, "csgpio#%u = %d\n", i, csgpio); 433 ret = devm_gpio_request_one(&pdev->dev, csgpio, 434 GPIOF_OUT_INIT_HIGH, DRIVER_NAME); 435 if (ret < 0) { 436 dev_err(&pdev->dev, 437 "failed to configure csgpio#%u %d\n" 438 , i, csgpio); 439 goto out_disable_clk; 440 } 441 } 442 443 /* set to default clock rate */ 444 npcm_pspi_set_baudrate(priv, NPCM_PSPI_DEFAULT_CLK); 445 446 ret = devm_spi_register_master(&pdev->dev, master); 447 if (ret) 448 goto out_disable_clk; 449 450 pr_info("NPCM Peripheral SPI %d probed\n", pdev->id); 451 452 return 0; 453 454 out_disable_clk: 455 clk_disable_unprepare(priv->clk); 456 457 out_master_put: 458 spi_master_put(master); 459 return ret; 460 } 461 462 static int npcm_pspi_remove(struct platform_device *pdev) 463 { 464 struct spi_master *master = platform_get_drvdata(pdev); 465 struct npcm_pspi *priv = spi_master_get_devdata(master); 466 467 npcm_pspi_reset_hw(priv); 468 clk_disable_unprepare(priv->clk); 469 470 return 0; 471 } 472 473 static const struct of_device_id npcm_pspi_match[] = { 474 { .compatible = "nuvoton,npcm750-pspi", .data = NULL }, 475 {} 476 }; 477 MODULE_DEVICE_TABLE(of, npcm_pspi_match); 478 479 static struct platform_driver npcm_pspi_driver = { 480 .driver = { 481 .name = DRIVER_NAME, 482 .of_match_table = npcm_pspi_match, 483 }, 484 .probe = npcm_pspi_probe, 485 .remove = npcm_pspi_remove, 486 }; 487 module_platform_driver(npcm_pspi_driver); 488 489 MODULE_DESCRIPTION("NPCM peripheral SPI Controller driver"); 490 MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>"); 491 MODULE_LICENSE("GPL v2"); 492 493