xref: /openbmc/linux/drivers/spi/spi-mxs.c (revision b34e08d5) 
1 /*
2  * Freescale MXS SPI master driver
3  *
4  * Copyright 2012 DENX Software Engineering, GmbH.
5  * Copyright 2012 Freescale Semiconductor, Inc.
6  * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
7  *
8  * Rework and transition to new API by:
9  * Marek Vasut <marex@denx.de>
10  *
11  * Based on previous attempt by:
12  * Fabio Estevam <fabio.estevam@freescale.com>
13  *
14  * Based on code from U-Boot bootloader by:
15  * Marek Vasut <marex@denx.de>
16  *
17  * Based on spi-stmp.c, which is:
18  * Author: Dmitry Pervushin <dimka@embeddedalley.com>
19  *
20  * This program is free software; you can redistribute it and/or modify
21  * it under the terms of the GNU General Public License as published by
22  * the Free Software Foundation; either version 2 of the License, or
23  * (at your option) any later version.
24  *
25  * This program is distributed in the hope that it will be useful,
26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28  * GNU General Public License for more details.
29  */
30 
31 #include <linux/kernel.h>
32 #include <linux/ioport.h>
33 #include <linux/of.h>
34 #include <linux/of_device.h>
35 #include <linux/of_gpio.h>
36 #include <linux/platform_device.h>
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/dmaengine.h>
41 #include <linux/highmem.h>
42 #include <linux/clk.h>
43 #include <linux/err.h>
44 #include <linux/completion.h>
45 #include <linux/gpio.h>
46 #include <linux/regulator/consumer.h>
47 #include <linux/module.h>
48 #include <linux/stmp_device.h>
49 #include <linux/spi/spi.h>
50 #include <linux/spi/mxs-spi.h>
51 
52 #define DRIVER_NAME		"mxs-spi"
53 
54 /* Use 10S timeout for very long transfers, it should suffice. */
55 #define SSP_TIMEOUT		10000
56 
57 #define SG_MAXLEN		0xff00
58 
59 /*
60  * Flags for txrx functions.  More efficient that using an argument register for
61  * each one.
62  */
63 #define TXRX_WRITE		(1<<0)	/* This is a write */
64 #define TXRX_DEASSERT_CS	(1<<1)	/* De-assert CS at end of txrx */
65 
66 struct mxs_spi {
67 	struct mxs_ssp		ssp;
68 	struct completion	c;
69 	unsigned int		sck;	/* Rate requested (vs actual) */
70 };
71 
72 static int mxs_spi_setup_transfer(struct spi_device *dev,
73 				  const struct spi_transfer *t)
74 {
75 	struct mxs_spi *spi = spi_master_get_devdata(dev->master);
76 	struct mxs_ssp *ssp = &spi->ssp;
77 	const unsigned int hz = min(dev->max_speed_hz, t->speed_hz);
78 
79 	if (hz == 0) {
80 		dev_err(&dev->dev, "SPI clock rate of zero not allowed\n");
81 		return -EINVAL;
82 	}
83 
84 	if (hz != spi->sck) {
85 		mxs_ssp_set_clk_rate(ssp, hz);
86 		/*
87 		 * Save requested rate, hz, rather than the actual rate,
88 		 * ssp->clk_rate.  Otherwise we would set the rate every trasfer
89 		 * when the actual rate is not quite the same as requested rate.
90 		 */
91 		spi->sck = hz;
92 		/*
93 		 * Perhaps we should return an error if the actual clock is
94 		 * nowhere close to what was requested?
95 		 */
96 	}
97 
98 	writel(BM_SSP_CTRL0_LOCK_CS,
99 		ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
100 
101 	writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) |
102 	       BF_SSP_CTRL1_WORD_LENGTH(BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) |
103 	       ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
104 	       ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
105 	       ssp->base + HW_SSP_CTRL1(ssp));
106 
107 	writel(0x0, ssp->base + HW_SSP_CMD0);
108 	writel(0x0, ssp->base + HW_SSP_CMD1);
109 
110 	return 0;
111 }
112 
113 static u32 mxs_spi_cs_to_reg(unsigned cs)
114 {
115 	u32 select = 0;
116 
117 	/*
118 	 * i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
119 	 *
120 	 * The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
121 	 * in HW_SSP_CTRL0 register do have multiple usage, please refer to
122 	 * the datasheet for further details. In SPI mode, they are used to
123 	 * toggle the chip-select lines (nCS pins).
124 	 */
125 	if (cs & 1)
126 		select |= BM_SSP_CTRL0_WAIT_FOR_CMD;
127 	if (cs & 2)
128 		select |= BM_SSP_CTRL0_WAIT_FOR_IRQ;
129 
130 	return select;
131 }
132 
133 static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
134 {
135 	const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT);
136 	struct mxs_ssp *ssp = &spi->ssp;
137 	u32 reg;
138 
139 	do {
140 		reg = readl_relaxed(ssp->base + offset);
141 
142 		if (!set)
143 			reg = ~reg;
144 
145 		reg &= mask;
146 
147 		if (reg == mask)
148 			return 0;
149 	} while (time_before(jiffies, timeout));
150 
151 	return -ETIMEDOUT;
152 }
153 
154 static void mxs_ssp_dma_irq_callback(void *param)
155 {
156 	struct mxs_spi *spi = param;
157 	complete(&spi->c);
158 }
159 
160 static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
161 {
162 	struct mxs_ssp *ssp = dev_id;
163 	dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
164 		__func__, __LINE__,
165 		readl(ssp->base + HW_SSP_CTRL1(ssp)),
166 		readl(ssp->base + HW_SSP_STATUS(ssp)));
167 	return IRQ_HANDLED;
168 }
169 
170 static int mxs_spi_txrx_dma(struct mxs_spi *spi,
171 			    unsigned char *buf, int len,
172 			    unsigned int flags)
173 {
174 	struct mxs_ssp *ssp = &spi->ssp;
175 	struct dma_async_tx_descriptor *desc = NULL;
176 	const bool vmalloced_buf = is_vmalloc_addr(buf);
177 	const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN;
178 	const int sgs = DIV_ROUND_UP(len, desc_len);
179 	int sg_count;
180 	int min, ret;
181 	u32 ctrl0;
182 	struct page *vm_page;
183 	void *sg_buf;
184 	struct {
185 		u32			pio[4];
186 		struct scatterlist	sg;
187 	} *dma_xfer;
188 
189 	if (!len)
190 		return -EINVAL;
191 
192 	dma_xfer = kzalloc(sizeof(*dma_xfer) * sgs, GFP_KERNEL);
193 	if (!dma_xfer)
194 		return -ENOMEM;
195 
196 	reinit_completion(&spi->c);
197 
198 	/* Chip select was already programmed into CTRL0 */
199 	ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
200 	ctrl0 &= ~(BM_SSP_CTRL0_XFER_COUNT | BM_SSP_CTRL0_IGNORE_CRC |
201 		 BM_SSP_CTRL0_READ);
202 	ctrl0 |= BM_SSP_CTRL0_DATA_XFER;
203 
204 	if (!(flags & TXRX_WRITE))
205 		ctrl0 |= BM_SSP_CTRL0_READ;
206 
207 	/* Queue the DMA data transfer. */
208 	for (sg_count = 0; sg_count < sgs; sg_count++) {
209 		/* Prepare the transfer descriptor. */
210 		min = min(len, desc_len);
211 
212 		/*
213 		 * De-assert CS on last segment if flag is set (i.e., no more
214 		 * transfers will follow)
215 		 */
216 		if ((sg_count + 1 == sgs) && (flags & TXRX_DEASSERT_CS))
217 			ctrl0 |= BM_SSP_CTRL0_IGNORE_CRC;
218 
219 		if (ssp->devid == IMX23_SSP) {
220 			ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
221 			ctrl0 |= min;
222 		}
223 
224 		dma_xfer[sg_count].pio[0] = ctrl0;
225 		dma_xfer[sg_count].pio[3] = min;
226 
227 		if (vmalloced_buf) {
228 			vm_page = vmalloc_to_page(buf);
229 			if (!vm_page) {
230 				ret = -ENOMEM;
231 				goto err_vmalloc;
232 			}
233 			sg_buf = page_address(vm_page) +
234 				((size_t)buf & ~PAGE_MASK);
235 		} else {
236 			sg_buf = buf;
237 		}
238 
239 		sg_init_one(&dma_xfer[sg_count].sg, sg_buf, min);
240 		ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
241 			(flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
242 
243 		len -= min;
244 		buf += min;
245 
246 		/* Queue the PIO register write transfer. */
247 		desc = dmaengine_prep_slave_sg(ssp->dmach,
248 				(struct scatterlist *)dma_xfer[sg_count].pio,
249 				(ssp->devid == IMX23_SSP) ? 1 : 4,
250 				DMA_TRANS_NONE,
251 				sg_count ? DMA_PREP_INTERRUPT : 0);
252 		if (!desc) {
253 			dev_err(ssp->dev,
254 				"Failed to get PIO reg. write descriptor.\n");
255 			ret = -EINVAL;
256 			goto err_mapped;
257 		}
258 
259 		desc = dmaengine_prep_slave_sg(ssp->dmach,
260 				&dma_xfer[sg_count].sg, 1,
261 				(flags & TXRX_WRITE) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
262 				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
263 
264 		if (!desc) {
265 			dev_err(ssp->dev,
266 				"Failed to get DMA data write descriptor.\n");
267 			ret = -EINVAL;
268 			goto err_mapped;
269 		}
270 	}
271 
272 	/*
273 	 * The last descriptor must have this callback,
274 	 * to finish the DMA transaction.
275 	 */
276 	desc->callback = mxs_ssp_dma_irq_callback;
277 	desc->callback_param = spi;
278 
279 	/* Start the transfer. */
280 	dmaengine_submit(desc);
281 	dma_async_issue_pending(ssp->dmach);
282 
283 	ret = wait_for_completion_timeout(&spi->c,
284 				msecs_to_jiffies(SSP_TIMEOUT));
285 	if (!ret) {
286 		dev_err(ssp->dev, "DMA transfer timeout\n");
287 		ret = -ETIMEDOUT;
288 		dmaengine_terminate_all(ssp->dmach);
289 		goto err_vmalloc;
290 	}
291 
292 	ret = 0;
293 
294 err_vmalloc:
295 	while (--sg_count >= 0) {
296 err_mapped:
297 		dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
298 			(flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
299 	}
300 
301 	kfree(dma_xfer);
302 
303 	return ret;
304 }
305 
306 static int mxs_spi_txrx_pio(struct mxs_spi *spi,
307 			    unsigned char *buf, int len,
308 			    unsigned int flags)
309 {
310 	struct mxs_ssp *ssp = &spi->ssp;
311 
312 	writel(BM_SSP_CTRL0_IGNORE_CRC,
313 	       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
314 
315 	while (len--) {
316 		if (len == 0 && (flags & TXRX_DEASSERT_CS))
317 			writel(BM_SSP_CTRL0_IGNORE_CRC,
318 			       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
319 
320 		if (ssp->devid == IMX23_SSP) {
321 			writel(BM_SSP_CTRL0_XFER_COUNT,
322 				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
323 			writel(1,
324 				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
325 		} else {
326 			writel(1, ssp->base + HW_SSP_XFER_SIZE);
327 		}
328 
329 		if (flags & TXRX_WRITE)
330 			writel(BM_SSP_CTRL0_READ,
331 				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
332 		else
333 			writel(BM_SSP_CTRL0_READ,
334 				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
335 
336 		writel(BM_SSP_CTRL0_RUN,
337 				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
338 
339 		if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1))
340 			return -ETIMEDOUT;
341 
342 		if (flags & TXRX_WRITE)
343 			writel(*buf, ssp->base + HW_SSP_DATA(ssp));
344 
345 		writel(BM_SSP_CTRL0_DATA_XFER,
346 			     ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
347 
348 		if (!(flags & TXRX_WRITE)) {
349 			if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
350 						BM_SSP_STATUS_FIFO_EMPTY, 0))
351 				return -ETIMEDOUT;
352 
353 			*buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
354 		}
355 
356 		if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0))
357 			return -ETIMEDOUT;
358 
359 		buf++;
360 	}
361 
362 	if (len <= 0)
363 		return 0;
364 
365 	return -ETIMEDOUT;
366 }
367 
368 static int mxs_spi_transfer_one(struct spi_master *master,
369 				struct spi_message *m)
370 {
371 	struct mxs_spi *spi = spi_master_get_devdata(master);
372 	struct mxs_ssp *ssp = &spi->ssp;
373 	struct spi_transfer *t;
374 	unsigned int flag;
375 	int status = 0;
376 
377 	/* Program CS register bits here, it will be used for all transfers. */
378 	writel(BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ,
379 	       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
380 	writel(mxs_spi_cs_to_reg(m->spi->chip_select),
381 	       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
382 
383 	list_for_each_entry(t, &m->transfers, transfer_list) {
384 
385 		status = mxs_spi_setup_transfer(m->spi, t);
386 		if (status)
387 			break;
388 
389 		/* De-assert on last transfer, inverted by cs_change flag */
390 		flag = (&t->transfer_list == m->transfers.prev) ^ t->cs_change ?
391 		       TXRX_DEASSERT_CS : 0;
392 
393 		/*
394 		 * Small blocks can be transfered via PIO.
395 		 * Measured by empiric means:
396 		 *
397 		 * dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
398 		 *
399 		 * DMA only: 2.164808 seconds, 473.0KB/s
400 		 * Combined: 1.676276 seconds, 610.9KB/s
401 		 */
402 		if (t->len < 32) {
403 			writel(BM_SSP_CTRL1_DMA_ENABLE,
404 				ssp->base + HW_SSP_CTRL1(ssp) +
405 				STMP_OFFSET_REG_CLR);
406 
407 			if (t->tx_buf)
408 				status = mxs_spi_txrx_pio(spi,
409 						(void *)t->tx_buf,
410 						t->len, flag | TXRX_WRITE);
411 			if (t->rx_buf)
412 				status = mxs_spi_txrx_pio(spi,
413 						t->rx_buf, t->len,
414 						flag);
415 		} else {
416 			writel(BM_SSP_CTRL1_DMA_ENABLE,
417 				ssp->base + HW_SSP_CTRL1(ssp) +
418 				STMP_OFFSET_REG_SET);
419 
420 			if (t->tx_buf)
421 				status = mxs_spi_txrx_dma(spi,
422 						(void *)t->tx_buf, t->len,
423 						flag | TXRX_WRITE);
424 			if (t->rx_buf)
425 				status = mxs_spi_txrx_dma(spi,
426 						t->rx_buf, t->len,
427 						flag);
428 		}
429 
430 		if (status) {
431 			stmp_reset_block(ssp->base);
432 			break;
433 		}
434 
435 		m->actual_length += t->len;
436 	}
437 
438 	m->status = status;
439 	spi_finalize_current_message(master);
440 
441 	return status;
442 }
443 
444 static const struct of_device_id mxs_spi_dt_ids[] = {
445 	{ .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
446 	{ .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
447 	{ /* sentinel */ }
448 };
449 MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids);
450 
451 static int mxs_spi_probe(struct platform_device *pdev)
452 {
453 	const struct of_device_id *of_id =
454 			of_match_device(mxs_spi_dt_ids, &pdev->dev);
455 	struct device_node *np = pdev->dev.of_node;
456 	struct spi_master *master;
457 	struct mxs_spi *spi;
458 	struct mxs_ssp *ssp;
459 	struct resource *iores;
460 	struct clk *clk;
461 	void __iomem *base;
462 	int devid, clk_freq;
463 	int ret = 0, irq_err;
464 
465 	/*
466 	 * Default clock speed for the SPI core. 160MHz seems to
467 	 * work reasonably well with most SPI flashes, so use this
468 	 * as a default. Override with "clock-frequency" DT prop.
469 	 */
470 	const int clk_freq_default = 160000000;
471 
472 	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
473 	irq_err = platform_get_irq(pdev, 0);
474 	if (irq_err < 0)
475 		return irq_err;
476 
477 	base = devm_ioremap_resource(&pdev->dev, iores);
478 	if (IS_ERR(base))
479 		return PTR_ERR(base);
480 
481 	clk = devm_clk_get(&pdev->dev, NULL);
482 	if (IS_ERR(clk))
483 		return PTR_ERR(clk);
484 
485 	devid = (enum mxs_ssp_id) of_id->data;
486 	ret = of_property_read_u32(np, "clock-frequency",
487 				   &clk_freq);
488 	if (ret)
489 		clk_freq = clk_freq_default;
490 
491 	master = spi_alloc_master(&pdev->dev, sizeof(*spi));
492 	if (!master)
493 		return -ENOMEM;
494 
495 	master->transfer_one_message = mxs_spi_transfer_one;
496 	master->bits_per_word_mask = SPI_BPW_MASK(8);
497 	master->mode_bits = SPI_CPOL | SPI_CPHA;
498 	master->num_chipselect = 3;
499 	master->dev.of_node = np;
500 	master->flags = SPI_MASTER_HALF_DUPLEX;
501 
502 	spi = spi_master_get_devdata(master);
503 	ssp = &spi->ssp;
504 	ssp->dev = &pdev->dev;
505 	ssp->clk = clk;
506 	ssp->base = base;
507 	ssp->devid = devid;
508 
509 	init_completion(&spi->c);
510 
511 	ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
512 			       DRIVER_NAME, ssp);
513 	if (ret)
514 		goto out_master_free;
515 
516 	ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx");
517 	if (!ssp->dmach) {
518 		dev_err(ssp->dev, "Failed to request DMA\n");
519 		ret = -ENODEV;
520 		goto out_master_free;
521 	}
522 
523 	ret = clk_prepare_enable(ssp->clk);
524 	if (ret)
525 		goto out_dma_release;
526 
527 	clk_set_rate(ssp->clk, clk_freq);
528 
529 	ret = stmp_reset_block(ssp->base);
530 	if (ret)
531 		goto out_disable_clk;
532 
533 	platform_set_drvdata(pdev, master);
534 
535 	ret = devm_spi_register_master(&pdev->dev, master);
536 	if (ret) {
537 		dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
538 		goto out_disable_clk;
539 	}
540 
541 	return 0;
542 
543 out_disable_clk:
544 	clk_disable_unprepare(ssp->clk);
545 out_dma_release:
546 	dma_release_channel(ssp->dmach);
547 out_master_free:
548 	spi_master_put(master);
549 	return ret;
550 }
551 
552 static int mxs_spi_remove(struct platform_device *pdev)
553 {
554 	struct spi_master *master;
555 	struct mxs_spi *spi;
556 	struct mxs_ssp *ssp;
557 
558 	master = platform_get_drvdata(pdev);
559 	spi = spi_master_get_devdata(master);
560 	ssp = &spi->ssp;
561 
562 	clk_disable_unprepare(ssp->clk);
563 	dma_release_channel(ssp->dmach);
564 
565 	return 0;
566 }
567 
568 static struct platform_driver mxs_spi_driver = {
569 	.probe	= mxs_spi_probe,
570 	.remove	= mxs_spi_remove,
571 	.driver	= {
572 		.name	= DRIVER_NAME,
573 		.owner	= THIS_MODULE,
574 		.of_match_table = mxs_spi_dt_ids,
575 	},
576 };
577 
578 module_platform_driver(mxs_spi_driver);
579 
580 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
581 MODULE_DESCRIPTION("MXS SPI master driver");
582 MODULE_LICENSE("GPL");
583 MODULE_ALIAS("platform:mxs-spi");
584