1 /* 2 * Freescale MXS SPI master driver 3 * 4 * Copyright 2012 DENX Software Engineering, GmbH. 5 * Copyright 2012 Freescale Semiconductor, Inc. 6 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. 7 * 8 * Rework and transition to new API by: 9 * Marek Vasut <marex@denx.de> 10 * 11 * Based on previous attempt by: 12 * Fabio Estevam <fabio.estevam@freescale.com> 13 * 14 * Based on code from U-Boot bootloader by: 15 * Marek Vasut <marex@denx.de> 16 * 17 * Based on spi-stmp.c, which is: 18 * Author: Dmitry Pervushin <dimka@embeddedalley.com> 19 * 20 * This program is free software; you can redistribute it and/or modify 21 * it under the terms of the GNU General Public License as published by 22 * the Free Software Foundation; either version 2 of the License, or 23 * (at your option) any later version. 24 * 25 * This program is distributed in the hope that it will be useful, 26 * but WITHOUT ANY WARRANTY; without even the implied warranty of 27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 28 * GNU General Public License for more details. 29 */ 30 31 #include <linux/kernel.h> 32 #include <linux/ioport.h> 33 #include <linux/of.h> 34 #include <linux/of_device.h> 35 #include <linux/of_gpio.h> 36 #include <linux/platform_device.h> 37 #include <linux/delay.h> 38 #include <linux/interrupt.h> 39 #include <linux/dma-mapping.h> 40 #include <linux/dmaengine.h> 41 #include <linux/highmem.h> 42 #include <linux/clk.h> 43 #include <linux/err.h> 44 #include <linux/completion.h> 45 #include <linux/gpio.h> 46 #include <linux/regulator/consumer.h> 47 #include <linux/pm_runtime.h> 48 #include <linux/module.h> 49 #include <linux/stmp_device.h> 50 #include <linux/spi/spi.h> 51 #include <linux/spi/mxs-spi.h> 52 53 #define DRIVER_NAME "mxs-spi" 54 55 /* Use 10S timeout for very long transfers, it should suffice. */ 56 #define SSP_TIMEOUT 10000 57 58 #define SG_MAXLEN 0xff00 59 60 /* 61 * Flags for txrx functions. More efficient that using an argument register for 62 * each one. 63 */ 64 #define TXRX_WRITE (1<<0) /* This is a write */ 65 #define TXRX_DEASSERT_CS (1<<1) /* De-assert CS at end of txrx */ 66 67 struct mxs_spi { 68 struct mxs_ssp ssp; 69 struct completion c; 70 unsigned int sck; /* Rate requested (vs actual) */ 71 }; 72 73 static int mxs_spi_setup_transfer(struct spi_device *dev, 74 const struct spi_transfer *t) 75 { 76 struct mxs_spi *spi = spi_master_get_devdata(dev->master); 77 struct mxs_ssp *ssp = &spi->ssp; 78 const unsigned int hz = min(dev->max_speed_hz, t->speed_hz); 79 80 if (hz == 0) { 81 dev_err(&dev->dev, "SPI clock rate of zero not allowed\n"); 82 return -EINVAL; 83 } 84 85 if (hz != spi->sck) { 86 mxs_ssp_set_clk_rate(ssp, hz); 87 /* 88 * Save requested rate, hz, rather than the actual rate, 89 * ssp->clk_rate. Otherwise we would set the rate every transfer 90 * when the actual rate is not quite the same as requested rate. 91 */ 92 spi->sck = hz; 93 /* 94 * Perhaps we should return an error if the actual clock is 95 * nowhere close to what was requested? 96 */ 97 } 98 99 writel(BM_SSP_CTRL0_LOCK_CS, 100 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); 101 102 writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) | 103 BF_SSP_CTRL1_WORD_LENGTH(BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) | 104 ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) | 105 ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0), 106 ssp->base + HW_SSP_CTRL1(ssp)); 107 108 writel(0x0, ssp->base + HW_SSP_CMD0); 109 writel(0x0, ssp->base + HW_SSP_CMD1); 110 111 return 0; 112 } 113 114 static u32 mxs_spi_cs_to_reg(unsigned cs) 115 { 116 u32 select = 0; 117 118 /* 119 * i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0 120 * 121 * The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ 122 * in HW_SSP_CTRL0 register do have multiple usage, please refer to 123 * the datasheet for further details. In SPI mode, they are used to 124 * toggle the chip-select lines (nCS pins). 125 */ 126 if (cs & 1) 127 select |= BM_SSP_CTRL0_WAIT_FOR_CMD; 128 if (cs & 2) 129 select |= BM_SSP_CTRL0_WAIT_FOR_IRQ; 130 131 return select; 132 } 133 134 static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set) 135 { 136 const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT); 137 struct mxs_ssp *ssp = &spi->ssp; 138 u32 reg; 139 140 do { 141 reg = readl_relaxed(ssp->base + offset); 142 143 if (!set) 144 reg = ~reg; 145 146 reg &= mask; 147 148 if (reg == mask) 149 return 0; 150 } while (time_before(jiffies, timeout)); 151 152 return -ETIMEDOUT; 153 } 154 155 static void mxs_ssp_dma_irq_callback(void *param) 156 { 157 struct mxs_spi *spi = param; 158 159 complete(&spi->c); 160 } 161 162 static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id) 163 { 164 struct mxs_ssp *ssp = dev_id; 165 166 dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n", 167 __func__, __LINE__, 168 readl(ssp->base + HW_SSP_CTRL1(ssp)), 169 readl(ssp->base + HW_SSP_STATUS(ssp))); 170 return IRQ_HANDLED; 171 } 172 173 static int mxs_spi_txrx_dma(struct mxs_spi *spi, 174 unsigned char *buf, int len, 175 unsigned int flags) 176 { 177 struct mxs_ssp *ssp = &spi->ssp; 178 struct dma_async_tx_descriptor *desc = NULL; 179 const bool vmalloced_buf = is_vmalloc_addr(buf); 180 const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN; 181 const int sgs = DIV_ROUND_UP(len, desc_len); 182 int sg_count; 183 int min, ret; 184 u32 ctrl0; 185 struct page *vm_page; 186 struct { 187 u32 pio[4]; 188 struct scatterlist sg; 189 } *dma_xfer; 190 191 if (!len) 192 return -EINVAL; 193 194 dma_xfer = kcalloc(sgs, sizeof(*dma_xfer), GFP_KERNEL); 195 if (!dma_xfer) 196 return -ENOMEM; 197 198 reinit_completion(&spi->c); 199 200 /* Chip select was already programmed into CTRL0 */ 201 ctrl0 = readl(ssp->base + HW_SSP_CTRL0); 202 ctrl0 &= ~(BM_SSP_CTRL0_XFER_COUNT | BM_SSP_CTRL0_IGNORE_CRC | 203 BM_SSP_CTRL0_READ); 204 ctrl0 |= BM_SSP_CTRL0_DATA_XFER; 205 206 if (!(flags & TXRX_WRITE)) 207 ctrl0 |= BM_SSP_CTRL0_READ; 208 209 /* Queue the DMA data transfer. */ 210 for (sg_count = 0; sg_count < sgs; sg_count++) { 211 /* Prepare the transfer descriptor. */ 212 min = min(len, desc_len); 213 214 /* 215 * De-assert CS on last segment if flag is set (i.e., no more 216 * transfers will follow) 217 */ 218 if ((sg_count + 1 == sgs) && (flags & TXRX_DEASSERT_CS)) 219 ctrl0 |= BM_SSP_CTRL0_IGNORE_CRC; 220 221 if (ssp->devid == IMX23_SSP) { 222 ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT; 223 ctrl0 |= min; 224 } 225 226 dma_xfer[sg_count].pio[0] = ctrl0; 227 dma_xfer[sg_count].pio[3] = min; 228 229 if (vmalloced_buf) { 230 vm_page = vmalloc_to_page(buf); 231 if (!vm_page) { 232 ret = -ENOMEM; 233 goto err_vmalloc; 234 } 235 236 sg_init_table(&dma_xfer[sg_count].sg, 1); 237 sg_set_page(&dma_xfer[sg_count].sg, vm_page, 238 min, offset_in_page(buf)); 239 } else { 240 sg_init_one(&dma_xfer[sg_count].sg, buf, min); 241 } 242 243 ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1, 244 (flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); 245 246 len -= min; 247 buf += min; 248 249 /* Queue the PIO register write transfer. */ 250 desc = dmaengine_prep_slave_sg(ssp->dmach, 251 (struct scatterlist *)dma_xfer[sg_count].pio, 252 (ssp->devid == IMX23_SSP) ? 1 : 4, 253 DMA_TRANS_NONE, 254 sg_count ? DMA_PREP_INTERRUPT : 0); 255 if (!desc) { 256 dev_err(ssp->dev, 257 "Failed to get PIO reg. write descriptor.\n"); 258 ret = -EINVAL; 259 goto err_mapped; 260 } 261 262 desc = dmaengine_prep_slave_sg(ssp->dmach, 263 &dma_xfer[sg_count].sg, 1, 264 (flags & TXRX_WRITE) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, 265 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 266 267 if (!desc) { 268 dev_err(ssp->dev, 269 "Failed to get DMA data write descriptor.\n"); 270 ret = -EINVAL; 271 goto err_mapped; 272 } 273 } 274 275 /* 276 * The last descriptor must have this callback, 277 * to finish the DMA transaction. 278 */ 279 desc->callback = mxs_ssp_dma_irq_callback; 280 desc->callback_param = spi; 281 282 /* Start the transfer. */ 283 dmaengine_submit(desc); 284 dma_async_issue_pending(ssp->dmach); 285 286 if (!wait_for_completion_timeout(&spi->c, 287 msecs_to_jiffies(SSP_TIMEOUT))) { 288 dev_err(ssp->dev, "DMA transfer timeout\n"); 289 ret = -ETIMEDOUT; 290 dmaengine_terminate_all(ssp->dmach); 291 goto err_vmalloc; 292 } 293 294 ret = 0; 295 296 err_vmalloc: 297 while (--sg_count >= 0) { 298 err_mapped: 299 dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1, 300 (flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); 301 } 302 303 kfree(dma_xfer); 304 305 return ret; 306 } 307 308 static int mxs_spi_txrx_pio(struct mxs_spi *spi, 309 unsigned char *buf, int len, 310 unsigned int flags) 311 { 312 struct mxs_ssp *ssp = &spi->ssp; 313 314 writel(BM_SSP_CTRL0_IGNORE_CRC, 315 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); 316 317 while (len--) { 318 if (len == 0 && (flags & TXRX_DEASSERT_CS)) 319 writel(BM_SSP_CTRL0_IGNORE_CRC, 320 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); 321 322 if (ssp->devid == IMX23_SSP) { 323 writel(BM_SSP_CTRL0_XFER_COUNT, 324 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); 325 writel(1, 326 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); 327 } else { 328 writel(1, ssp->base + HW_SSP_XFER_SIZE); 329 } 330 331 if (flags & TXRX_WRITE) 332 writel(BM_SSP_CTRL0_READ, 333 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); 334 else 335 writel(BM_SSP_CTRL0_READ, 336 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); 337 338 writel(BM_SSP_CTRL0_RUN, 339 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); 340 341 if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1)) 342 return -ETIMEDOUT; 343 344 if (flags & TXRX_WRITE) 345 writel(*buf, ssp->base + HW_SSP_DATA(ssp)); 346 347 writel(BM_SSP_CTRL0_DATA_XFER, 348 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); 349 350 if (!(flags & TXRX_WRITE)) { 351 if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp), 352 BM_SSP_STATUS_FIFO_EMPTY, 0)) 353 return -ETIMEDOUT; 354 355 *buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff); 356 } 357 358 if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0)) 359 return -ETIMEDOUT; 360 361 buf++; 362 } 363 364 if (len <= 0) 365 return 0; 366 367 return -ETIMEDOUT; 368 } 369 370 static int mxs_spi_transfer_one(struct spi_master *master, 371 struct spi_message *m) 372 { 373 struct mxs_spi *spi = spi_master_get_devdata(master); 374 struct mxs_ssp *ssp = &spi->ssp; 375 struct spi_transfer *t; 376 unsigned int flag; 377 int status = 0; 378 379 /* Program CS register bits here, it will be used for all transfers. */ 380 writel(BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ, 381 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); 382 writel(mxs_spi_cs_to_reg(m->spi->chip_select), 383 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); 384 385 list_for_each_entry(t, &m->transfers, transfer_list) { 386 387 status = mxs_spi_setup_transfer(m->spi, t); 388 if (status) 389 break; 390 391 /* De-assert on last transfer, inverted by cs_change flag */ 392 flag = (&t->transfer_list == m->transfers.prev) ^ t->cs_change ? 393 TXRX_DEASSERT_CS : 0; 394 395 /* 396 * Small blocks can be transfered via PIO. 397 * Measured by empiric means: 398 * 399 * dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1 400 * 401 * DMA only: 2.164808 seconds, 473.0KB/s 402 * Combined: 1.676276 seconds, 610.9KB/s 403 */ 404 if (t->len < 32) { 405 writel(BM_SSP_CTRL1_DMA_ENABLE, 406 ssp->base + HW_SSP_CTRL1(ssp) + 407 STMP_OFFSET_REG_CLR); 408 409 if (t->tx_buf) 410 status = mxs_spi_txrx_pio(spi, 411 (void *)t->tx_buf, 412 t->len, flag | TXRX_WRITE); 413 if (t->rx_buf) 414 status = mxs_spi_txrx_pio(spi, 415 t->rx_buf, t->len, 416 flag); 417 } else { 418 writel(BM_SSP_CTRL1_DMA_ENABLE, 419 ssp->base + HW_SSP_CTRL1(ssp) + 420 STMP_OFFSET_REG_SET); 421 422 if (t->tx_buf) 423 status = mxs_spi_txrx_dma(spi, 424 (void *)t->tx_buf, t->len, 425 flag | TXRX_WRITE); 426 if (t->rx_buf) 427 status = mxs_spi_txrx_dma(spi, 428 t->rx_buf, t->len, 429 flag); 430 } 431 432 if (status) { 433 stmp_reset_block(ssp->base); 434 break; 435 } 436 437 m->actual_length += t->len; 438 } 439 440 m->status = status; 441 spi_finalize_current_message(master); 442 443 return status; 444 } 445 446 static int mxs_spi_runtime_suspend(struct device *dev) 447 { 448 struct spi_master *master = dev_get_drvdata(dev); 449 struct mxs_spi *spi = spi_master_get_devdata(master); 450 struct mxs_ssp *ssp = &spi->ssp; 451 int ret; 452 453 clk_disable_unprepare(ssp->clk); 454 455 ret = pinctrl_pm_select_idle_state(dev); 456 if (ret) { 457 int ret2 = clk_prepare_enable(ssp->clk); 458 459 if (ret2) 460 dev_warn(dev, "Failed to reenable clock after failing pinctrl request (pinctrl: %d, clk: %d)\n", 461 ret, ret2); 462 } 463 464 return ret; 465 } 466 467 static int mxs_spi_runtime_resume(struct device *dev) 468 { 469 struct spi_master *master = dev_get_drvdata(dev); 470 struct mxs_spi *spi = spi_master_get_devdata(master); 471 struct mxs_ssp *ssp = &spi->ssp; 472 int ret; 473 474 ret = pinctrl_pm_select_default_state(dev); 475 if (ret) 476 return ret; 477 478 ret = clk_prepare_enable(ssp->clk); 479 if (ret) 480 pinctrl_pm_select_idle_state(dev); 481 482 return ret; 483 } 484 485 static int __maybe_unused mxs_spi_suspend(struct device *dev) 486 { 487 struct spi_master *master = dev_get_drvdata(dev); 488 int ret; 489 490 ret = spi_master_suspend(master); 491 if (ret) 492 return ret; 493 494 if (!pm_runtime_suspended(dev)) 495 return mxs_spi_runtime_suspend(dev); 496 else 497 return 0; 498 } 499 500 static int __maybe_unused mxs_spi_resume(struct device *dev) 501 { 502 struct spi_master *master = dev_get_drvdata(dev); 503 int ret; 504 505 if (!pm_runtime_suspended(dev)) 506 ret = mxs_spi_runtime_resume(dev); 507 else 508 ret = 0; 509 if (ret) 510 return ret; 511 512 ret = spi_master_resume(master); 513 if (ret < 0 && !pm_runtime_suspended(dev)) 514 mxs_spi_runtime_suspend(dev); 515 516 return ret; 517 } 518 519 static const struct dev_pm_ops mxs_spi_pm = { 520 SET_RUNTIME_PM_OPS(mxs_spi_runtime_suspend, 521 mxs_spi_runtime_resume, NULL) 522 SET_SYSTEM_SLEEP_PM_OPS(mxs_spi_suspend, mxs_spi_resume) 523 }; 524 525 static const struct of_device_id mxs_spi_dt_ids[] = { 526 { .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, }, 527 { .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, }, 528 { /* sentinel */ } 529 }; 530 MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids); 531 532 static int mxs_spi_probe(struct platform_device *pdev) 533 { 534 const struct of_device_id *of_id = 535 of_match_device(mxs_spi_dt_ids, &pdev->dev); 536 struct device_node *np = pdev->dev.of_node; 537 struct spi_master *master; 538 struct mxs_spi *spi; 539 struct mxs_ssp *ssp; 540 struct resource *iores; 541 struct clk *clk; 542 void __iomem *base; 543 int devid, clk_freq; 544 int ret = 0, irq_err; 545 546 /* 547 * Default clock speed for the SPI core. 160MHz seems to 548 * work reasonably well with most SPI flashes, so use this 549 * as a default. Override with "clock-frequency" DT prop. 550 */ 551 const int clk_freq_default = 160000000; 552 553 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 554 irq_err = platform_get_irq(pdev, 0); 555 if (irq_err < 0) 556 return irq_err; 557 558 base = devm_ioremap_resource(&pdev->dev, iores); 559 if (IS_ERR(base)) 560 return PTR_ERR(base); 561 562 clk = devm_clk_get(&pdev->dev, NULL); 563 if (IS_ERR(clk)) 564 return PTR_ERR(clk); 565 566 devid = (enum mxs_ssp_id) of_id->data; 567 ret = of_property_read_u32(np, "clock-frequency", 568 &clk_freq); 569 if (ret) 570 clk_freq = clk_freq_default; 571 572 master = spi_alloc_master(&pdev->dev, sizeof(*spi)); 573 if (!master) 574 return -ENOMEM; 575 576 platform_set_drvdata(pdev, master); 577 578 master->transfer_one_message = mxs_spi_transfer_one; 579 master->bits_per_word_mask = SPI_BPW_MASK(8); 580 master->mode_bits = SPI_CPOL | SPI_CPHA; 581 master->num_chipselect = 3; 582 master->dev.of_node = np; 583 master->flags = SPI_MASTER_HALF_DUPLEX; 584 master->auto_runtime_pm = true; 585 586 spi = spi_master_get_devdata(master); 587 ssp = &spi->ssp; 588 ssp->dev = &pdev->dev; 589 ssp->clk = clk; 590 ssp->base = base; 591 ssp->devid = devid; 592 593 init_completion(&spi->c); 594 595 ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0, 596 dev_name(&pdev->dev), ssp); 597 if (ret) 598 goto out_master_free; 599 600 ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx"); 601 if (!ssp->dmach) { 602 dev_err(ssp->dev, "Failed to request DMA\n"); 603 ret = -ENODEV; 604 goto out_master_free; 605 } 606 607 pm_runtime_enable(ssp->dev); 608 if (!pm_runtime_enabled(ssp->dev)) { 609 ret = mxs_spi_runtime_resume(ssp->dev); 610 if (ret < 0) { 611 dev_err(ssp->dev, "runtime resume failed\n"); 612 goto out_dma_release; 613 } 614 } 615 616 ret = pm_runtime_get_sync(ssp->dev); 617 if (ret < 0) { 618 dev_err(ssp->dev, "runtime_get_sync failed\n"); 619 goto out_pm_runtime_disable; 620 } 621 622 clk_set_rate(ssp->clk, clk_freq); 623 624 ret = stmp_reset_block(ssp->base); 625 if (ret) 626 goto out_pm_runtime_put; 627 628 ret = devm_spi_register_master(&pdev->dev, master); 629 if (ret) { 630 dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret); 631 goto out_pm_runtime_put; 632 } 633 634 pm_runtime_put(ssp->dev); 635 636 return 0; 637 638 out_pm_runtime_put: 639 pm_runtime_put(ssp->dev); 640 out_pm_runtime_disable: 641 pm_runtime_disable(ssp->dev); 642 out_dma_release: 643 dma_release_channel(ssp->dmach); 644 out_master_free: 645 spi_master_put(master); 646 return ret; 647 } 648 649 static int mxs_spi_remove(struct platform_device *pdev) 650 { 651 struct spi_master *master; 652 struct mxs_spi *spi; 653 struct mxs_ssp *ssp; 654 655 master = platform_get_drvdata(pdev); 656 spi = spi_master_get_devdata(master); 657 ssp = &spi->ssp; 658 659 pm_runtime_disable(&pdev->dev); 660 if (!pm_runtime_status_suspended(&pdev->dev)) 661 mxs_spi_runtime_suspend(&pdev->dev); 662 663 dma_release_channel(ssp->dmach); 664 665 return 0; 666 } 667 668 static struct platform_driver mxs_spi_driver = { 669 .probe = mxs_spi_probe, 670 .remove = mxs_spi_remove, 671 .driver = { 672 .name = DRIVER_NAME, 673 .of_match_table = mxs_spi_dt_ids, 674 .pm = &mxs_spi_pm, 675 }, 676 }; 677 678 module_platform_driver(mxs_spi_driver); 679 680 MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); 681 MODULE_DESCRIPTION("MXS SPI master driver"); 682 MODULE_LICENSE("GPL"); 683 MODULE_ALIAS("platform:mxs-spi"); 684