1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Copyright (C) 2018 Macronix International Co., Ltd. 4 // 5 // Authors: 6 // Mason Yang <masonccyang@mxic.com.tw> 7 // zhengxunli <zhengxunli@mxic.com.tw> 8 // Boris Brezillon <boris.brezillon@bootlin.com> 9 // 10 11 #include <linux/clk.h> 12 #include <linux/io.h> 13 #include <linux/iopoll.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/spi/spi.h> 18 #include <linux/spi/spi-mem.h> 19 20 #define HC_CFG 0x0 21 #define HC_CFG_IF_CFG(x) ((x) << 27) 22 #define HC_CFG_DUAL_SLAVE BIT(31) 23 #define HC_CFG_INDIVIDUAL BIT(30) 24 #define HC_CFG_NIO(x) (((x) / 4) << 27) 25 #define HC_CFG_TYPE(s, t) ((t) << (23 + ((s) * 2))) 26 #define HC_CFG_TYPE_SPI_NOR 0 27 #define HC_CFG_TYPE_SPI_NAND 1 28 #define HC_CFG_TYPE_SPI_RAM 2 29 #define HC_CFG_TYPE_RAW_NAND 3 30 #define HC_CFG_SLV_ACT(x) ((x) << 21) 31 #define HC_CFG_CLK_PH_EN BIT(20) 32 #define HC_CFG_CLK_POL_INV BIT(19) 33 #define HC_CFG_BIG_ENDIAN BIT(18) 34 #define HC_CFG_DATA_PASS BIT(17) 35 #define HC_CFG_IDLE_SIO_LVL(x) ((x) << 16) 36 #define HC_CFG_MAN_START_EN BIT(3) 37 #define HC_CFG_MAN_START BIT(2) 38 #define HC_CFG_MAN_CS_EN BIT(1) 39 #define HC_CFG_MAN_CS_ASSERT BIT(0) 40 41 #define INT_STS 0x4 42 #define INT_STS_EN 0x8 43 #define INT_SIG_EN 0xc 44 #define INT_STS_ALL GENMASK(31, 0) 45 #define INT_RDY_PIN BIT(26) 46 #define INT_RDY_SR BIT(25) 47 #define INT_LNR_SUSP BIT(24) 48 #define INT_ECC_ERR BIT(17) 49 #define INT_CRC_ERR BIT(16) 50 #define INT_LWR_DIS BIT(12) 51 #define INT_LRD_DIS BIT(11) 52 #define INT_SDMA_INT BIT(10) 53 #define INT_DMA_FINISH BIT(9) 54 #define INT_RX_NOT_FULL BIT(3) 55 #define INT_RX_NOT_EMPTY BIT(2) 56 #define INT_TX_NOT_FULL BIT(1) 57 #define INT_TX_EMPTY BIT(0) 58 59 #define HC_EN 0x10 60 #define HC_EN_BIT BIT(0) 61 62 #define TXD(x) (0x14 + ((x) * 4)) 63 #define RXD 0x24 64 65 #define SS_CTRL(s) (0x30 + ((s) * 4)) 66 #define LRD_CFG 0x44 67 #define LWR_CFG 0x80 68 #define RWW_CFG 0x70 69 #define OP_READ BIT(23) 70 #define OP_DUMMY_CYC(x) ((x) << 17) 71 #define OP_ADDR_BYTES(x) ((x) << 14) 72 #define OP_CMD_BYTES(x) (((x) - 1) << 13) 73 #define OP_OCTA_CRC_EN BIT(12) 74 #define OP_DQS_EN BIT(11) 75 #define OP_ENHC_EN BIT(10) 76 #define OP_PREAMBLE_EN BIT(9) 77 #define OP_DATA_DDR BIT(8) 78 #define OP_DATA_BUSW(x) ((x) << 6) 79 #define OP_ADDR_DDR BIT(5) 80 #define OP_ADDR_BUSW(x) ((x) << 3) 81 #define OP_CMD_DDR BIT(2) 82 #define OP_CMD_BUSW(x) (x) 83 #define OP_BUSW_1 0 84 #define OP_BUSW_2 1 85 #define OP_BUSW_4 2 86 #define OP_BUSW_8 3 87 88 #define OCTA_CRC 0x38 89 #define OCTA_CRC_IN_EN(s) BIT(3 + ((s) * 16)) 90 #define OCTA_CRC_CHUNK(s, x) ((fls((x) / 32)) << (1 + ((s) * 16))) 91 #define OCTA_CRC_OUT_EN(s) BIT(0 + ((s) * 16)) 92 93 #define ONFI_DIN_CNT(s) (0x3c + (s)) 94 95 #define LRD_CTRL 0x48 96 #define RWW_CTRL 0x74 97 #define LWR_CTRL 0x84 98 #define LMODE_EN BIT(31) 99 #define LMODE_SLV_ACT(x) ((x) << 21) 100 #define LMODE_CMD1(x) ((x) << 8) 101 #define LMODE_CMD0(x) (x) 102 103 #define LRD_ADDR 0x4c 104 #define LWR_ADDR 0x88 105 #define LRD_RANGE 0x50 106 #define LWR_RANGE 0x8c 107 108 #define AXI_SLV_ADDR 0x54 109 110 #define DMAC_RD_CFG 0x58 111 #define DMAC_WR_CFG 0x94 112 #define DMAC_CFG_PERIPH_EN BIT(31) 113 #define DMAC_CFG_ALLFLUSH_EN BIT(30) 114 #define DMAC_CFG_LASTFLUSH_EN BIT(29) 115 #define DMAC_CFG_QE(x) (((x) + 1) << 16) 116 #define DMAC_CFG_BURST_LEN(x) (((x) + 1) << 12) 117 #define DMAC_CFG_BURST_SZ(x) ((x) << 8) 118 #define DMAC_CFG_DIR_READ BIT(1) 119 #define DMAC_CFG_START BIT(0) 120 121 #define DMAC_RD_CNT 0x5c 122 #define DMAC_WR_CNT 0x98 123 124 #define SDMA_ADDR 0x60 125 126 #define DMAM_CFG 0x64 127 #define DMAM_CFG_START BIT(31) 128 #define DMAM_CFG_CONT BIT(30) 129 #define DMAM_CFG_SDMA_GAP(x) (fls((x) / 8192) << 2) 130 #define DMAM_CFG_DIR_READ BIT(1) 131 #define DMAM_CFG_EN BIT(0) 132 133 #define DMAM_CNT 0x68 134 135 #define LNR_TIMER_TH 0x6c 136 137 #define RDM_CFG0 0x78 138 #define RDM_CFG0_POLY(x) (x) 139 140 #define RDM_CFG1 0x7c 141 #define RDM_CFG1_RDM_EN BIT(31) 142 #define RDM_CFG1_SEED(x) (x) 143 144 #define LWR_SUSP_CTRL 0x90 145 #define LWR_SUSP_CTRL_EN BIT(31) 146 147 #define DMAS_CTRL 0x9c 148 #define DMAS_CTRL_EN BIT(31) 149 #define DMAS_CTRL_DIR_READ BIT(30) 150 151 #define DATA_STROB 0xa0 152 #define DATA_STROB_EDO_EN BIT(2) 153 #define DATA_STROB_INV_POL BIT(1) 154 #define DATA_STROB_DELAY_2CYC BIT(0) 155 156 #define IDLY_CODE(x) (0xa4 + ((x) * 4)) 157 #define IDLY_CODE_VAL(x, v) ((v) << (((x) % 4) * 8)) 158 159 #define GPIO 0xc4 160 #define GPIO_PT(x) BIT(3 + ((x) * 16)) 161 #define GPIO_RESET(x) BIT(2 + ((x) * 16)) 162 #define GPIO_HOLDB(x) BIT(1 + ((x) * 16)) 163 #define GPIO_WPB(x) BIT((x) * 16) 164 165 #define HC_VER 0xd0 166 167 #define HW_TEST(x) (0xe0 + ((x) * 4)) 168 169 struct mxic_spi { 170 struct clk *ps_clk; 171 struct clk *send_clk; 172 struct clk *send_dly_clk; 173 void __iomem *regs; 174 u32 cur_speed_hz; 175 struct { 176 void __iomem *map; 177 dma_addr_t dma; 178 size_t size; 179 } linear; 180 }; 181 182 static int mxic_spi_clk_enable(struct mxic_spi *mxic) 183 { 184 int ret; 185 186 ret = clk_prepare_enable(mxic->send_clk); 187 if (ret) 188 return ret; 189 190 ret = clk_prepare_enable(mxic->send_dly_clk); 191 if (ret) 192 goto err_send_dly_clk; 193 194 return ret; 195 196 err_send_dly_clk: 197 clk_disable_unprepare(mxic->send_clk); 198 199 return ret; 200 } 201 202 static void mxic_spi_clk_disable(struct mxic_spi *mxic) 203 { 204 clk_disable_unprepare(mxic->send_clk); 205 clk_disable_unprepare(mxic->send_dly_clk); 206 } 207 208 static void mxic_spi_set_input_delay_dqs(struct mxic_spi *mxic, u8 idly_code) 209 { 210 writel(IDLY_CODE_VAL(0, idly_code) | 211 IDLY_CODE_VAL(1, idly_code) | 212 IDLY_CODE_VAL(2, idly_code) | 213 IDLY_CODE_VAL(3, idly_code), 214 mxic->regs + IDLY_CODE(0)); 215 writel(IDLY_CODE_VAL(4, idly_code) | 216 IDLY_CODE_VAL(5, idly_code) | 217 IDLY_CODE_VAL(6, idly_code) | 218 IDLY_CODE_VAL(7, idly_code), 219 mxic->regs + IDLY_CODE(1)); 220 } 221 222 static int mxic_spi_clk_setup(struct mxic_spi *mxic, unsigned long freq) 223 { 224 int ret; 225 226 ret = clk_set_rate(mxic->send_clk, freq); 227 if (ret) 228 return ret; 229 230 ret = clk_set_rate(mxic->send_dly_clk, freq); 231 if (ret) 232 return ret; 233 234 /* 235 * A constant delay range from 0x0 ~ 0x1F for input delay, 236 * the unit is 78 ps, the max input delay is 2.418 ns. 237 */ 238 mxic_spi_set_input_delay_dqs(mxic, 0xf); 239 240 /* 241 * Phase degree = 360 * freq * output-delay 242 * where output-delay is a constant value 1 ns in FPGA. 243 * 244 * Get Phase degree = 360 * freq * 1 ns 245 * = 360 * freq * 1 sec / 1000000000 246 * = 9 * freq / 25000000 247 */ 248 ret = clk_set_phase(mxic->send_dly_clk, 9 * freq / 25000000); 249 if (ret) 250 return ret; 251 252 return 0; 253 } 254 255 static int mxic_spi_set_freq(struct mxic_spi *mxic, unsigned long freq) 256 { 257 int ret; 258 259 if (mxic->cur_speed_hz == freq) 260 return 0; 261 262 mxic_spi_clk_disable(mxic); 263 ret = mxic_spi_clk_setup(mxic, freq); 264 if (ret) 265 return ret; 266 267 ret = mxic_spi_clk_enable(mxic); 268 if (ret) 269 return ret; 270 271 mxic->cur_speed_hz = freq; 272 273 return 0; 274 } 275 276 static void mxic_spi_hw_init(struct mxic_spi *mxic) 277 { 278 writel(0, mxic->regs + DATA_STROB); 279 writel(INT_STS_ALL, mxic->regs + INT_STS_EN); 280 writel(0, mxic->regs + HC_EN); 281 writel(0, mxic->regs + LRD_CFG); 282 writel(0, mxic->regs + LRD_CTRL); 283 writel(HC_CFG_NIO(1) | HC_CFG_TYPE(0, HC_CFG_TYPE_SPI_NOR) | 284 HC_CFG_SLV_ACT(0) | HC_CFG_MAN_CS_EN | HC_CFG_IDLE_SIO_LVL(1), 285 mxic->regs + HC_CFG); 286 } 287 288 static u32 mxic_spi_prep_hc_cfg(struct spi_device *spi, u32 flags) 289 { 290 int nio = 1; 291 292 if (spi->mode & (SPI_TX_OCTAL | SPI_RX_OCTAL)) 293 nio = 8; 294 else if (spi->mode & (SPI_TX_QUAD | SPI_RX_QUAD)) 295 nio = 4; 296 else if (spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL)) 297 nio = 2; 298 299 return flags | HC_CFG_NIO(nio) | 300 HC_CFG_TYPE(spi->chip_select, HC_CFG_TYPE_SPI_NOR) | 301 HC_CFG_SLV_ACT(spi->chip_select) | HC_CFG_IDLE_SIO_LVL(1); 302 } 303 304 static u32 mxic_spi_mem_prep_op_cfg(const struct spi_mem_op *op, 305 unsigned int data_len) 306 { 307 u32 cfg = OP_CMD_BYTES(op->cmd.nbytes) | 308 OP_CMD_BUSW(fls(op->cmd.buswidth) - 1) | 309 (op->cmd.dtr ? OP_CMD_DDR : 0); 310 311 if (op->addr.nbytes) 312 cfg |= OP_ADDR_BYTES(op->addr.nbytes) | 313 OP_ADDR_BUSW(fls(op->addr.buswidth) - 1) | 314 (op->addr.dtr ? OP_ADDR_DDR : 0); 315 316 if (op->dummy.nbytes) 317 cfg |= OP_DUMMY_CYC(op->dummy.nbytes); 318 319 /* Direct mapping data.nbytes field is not populated */ 320 if (data_len) { 321 cfg |= OP_DATA_BUSW(fls(op->data.buswidth) - 1) | 322 (op->data.dtr ? OP_DATA_DDR : 0); 323 if (op->data.dir == SPI_MEM_DATA_IN) { 324 cfg |= OP_READ; 325 if (op->data.dtr) 326 cfg |= OP_DQS_EN; 327 } 328 } 329 330 return cfg; 331 } 332 333 static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf, 334 void *rxbuf, unsigned int len) 335 { 336 unsigned int pos = 0; 337 338 while (pos < len) { 339 unsigned int nbytes = len - pos; 340 u32 data = 0xffffffff; 341 u32 sts; 342 int ret; 343 344 if (nbytes > 4) 345 nbytes = 4; 346 347 if (txbuf) 348 memcpy(&data, txbuf + pos, nbytes); 349 350 ret = readl_poll_timeout(mxic->regs + INT_STS, sts, 351 sts & INT_TX_EMPTY, 0, USEC_PER_SEC); 352 if (ret) 353 return ret; 354 355 writel(data, mxic->regs + TXD(nbytes % 4)); 356 357 ret = readl_poll_timeout(mxic->regs + INT_STS, sts, 358 sts & INT_TX_EMPTY, 0, USEC_PER_SEC); 359 if (ret) 360 return ret; 361 362 ret = readl_poll_timeout(mxic->regs + INT_STS, sts, 363 sts & INT_RX_NOT_EMPTY, 0, 364 USEC_PER_SEC); 365 if (ret) 366 return ret; 367 368 data = readl(mxic->regs + RXD); 369 if (rxbuf) { 370 data >>= (8 * (4 - nbytes)); 371 memcpy(rxbuf + pos, &data, nbytes); 372 } 373 WARN_ON(readl(mxic->regs + INT_STS) & INT_RX_NOT_EMPTY); 374 375 pos += nbytes; 376 } 377 378 return 0; 379 } 380 381 static ssize_t mxic_spi_mem_dirmap_read(struct spi_mem_dirmap_desc *desc, 382 u64 offs, size_t len, void *buf) 383 { 384 struct mxic_spi *mxic = spi_master_get_devdata(desc->mem->spi->master); 385 int ret; 386 u32 sts; 387 388 if (WARN_ON(offs + desc->info.offset + len > U32_MAX)) 389 return -EINVAL; 390 391 writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0), mxic->regs + HC_CFG); 392 393 writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len), 394 mxic->regs + LRD_CFG); 395 writel(desc->info.offset + offs, mxic->regs + LRD_ADDR); 396 len = min_t(size_t, len, mxic->linear.size); 397 writel(len, mxic->regs + LRD_RANGE); 398 writel(LMODE_CMD0(desc->info.op_tmpl.cmd.opcode) | 399 LMODE_SLV_ACT(desc->mem->spi->chip_select) | 400 LMODE_EN, 401 mxic->regs + LRD_CTRL); 402 403 memcpy_fromio(buf, mxic->linear.map, len); 404 405 writel(INT_LRD_DIS, mxic->regs + INT_STS); 406 writel(0, mxic->regs + LRD_CTRL); 407 408 ret = readl_poll_timeout(mxic->regs + INT_STS, sts, 409 sts & INT_LRD_DIS, 0, USEC_PER_SEC); 410 if (ret) 411 return ret; 412 413 return len; 414 } 415 416 static ssize_t mxic_spi_mem_dirmap_write(struct spi_mem_dirmap_desc *desc, 417 u64 offs, size_t len, 418 const void *buf) 419 { 420 struct mxic_spi *mxic = spi_master_get_devdata(desc->mem->spi->master); 421 u32 sts; 422 int ret; 423 424 if (WARN_ON(offs + desc->info.offset + len > U32_MAX)) 425 return -EINVAL; 426 427 writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0), mxic->regs + HC_CFG); 428 429 writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len), 430 mxic->regs + LWR_CFG); 431 writel(desc->info.offset + offs, mxic->regs + LWR_ADDR); 432 len = min_t(size_t, len, mxic->linear.size); 433 writel(len, mxic->regs + LWR_RANGE); 434 writel(LMODE_CMD0(desc->info.op_tmpl.cmd.opcode) | 435 LMODE_SLV_ACT(desc->mem->spi->chip_select) | 436 LMODE_EN, 437 mxic->regs + LWR_CTRL); 438 439 memcpy_toio(mxic->linear.map, buf, len); 440 441 writel(INT_LWR_DIS, mxic->regs + INT_STS); 442 writel(0, mxic->regs + LWR_CTRL); 443 444 ret = readl_poll_timeout(mxic->regs + INT_STS, sts, 445 sts & INT_LWR_DIS, 0, USEC_PER_SEC); 446 if (ret) 447 return ret; 448 449 return len; 450 } 451 452 static bool mxic_spi_mem_supports_op(struct spi_mem *mem, 453 const struct spi_mem_op *op) 454 { 455 if (op->data.buswidth > 8 || op->addr.buswidth > 8 || 456 op->dummy.buswidth > 8 || op->cmd.buswidth > 8) 457 return false; 458 459 if (op->data.nbytes && op->dummy.nbytes && 460 op->data.buswidth != op->dummy.buswidth) 461 return false; 462 463 if (op->addr.nbytes > 7) 464 return false; 465 466 return spi_mem_default_supports_op(mem, op); 467 } 468 469 static int mxic_spi_mem_dirmap_create(struct spi_mem_dirmap_desc *desc) 470 { 471 struct mxic_spi *mxic = spi_master_get_devdata(desc->mem->spi->master); 472 473 if (!mxic->linear.map) 474 return -EINVAL; 475 476 if (desc->info.offset + desc->info.length > U32_MAX) 477 return -EINVAL; 478 479 if (!mxic_spi_mem_supports_op(desc->mem, &desc->info.op_tmpl)) 480 return -EOPNOTSUPP; 481 482 return 0; 483 } 484 485 static int mxic_spi_mem_exec_op(struct spi_mem *mem, 486 const struct spi_mem_op *op) 487 { 488 struct mxic_spi *mxic = spi_master_get_devdata(mem->spi->master); 489 int i, ret; 490 u8 addr[8], cmd[2]; 491 492 ret = mxic_spi_set_freq(mxic, mem->spi->max_speed_hz); 493 if (ret) 494 return ret; 495 496 writel(mxic_spi_prep_hc_cfg(mem->spi, HC_CFG_MAN_CS_EN), 497 mxic->regs + HC_CFG); 498 499 writel(HC_EN_BIT, mxic->regs + HC_EN); 500 501 writel(mxic_spi_mem_prep_op_cfg(op, op->data.nbytes), 502 mxic->regs + SS_CTRL(mem->spi->chip_select)); 503 504 writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT, 505 mxic->regs + HC_CFG); 506 507 for (i = 0; i < op->cmd.nbytes; i++) 508 cmd[i] = op->cmd.opcode >> (8 * (op->cmd.nbytes - i - 1)); 509 510 ret = mxic_spi_data_xfer(mxic, cmd, NULL, op->cmd.nbytes); 511 if (ret) 512 goto out; 513 514 for (i = 0; i < op->addr.nbytes; i++) 515 addr[i] = op->addr.val >> (8 * (op->addr.nbytes - i - 1)); 516 517 ret = mxic_spi_data_xfer(mxic, addr, NULL, op->addr.nbytes); 518 if (ret) 519 goto out; 520 521 ret = mxic_spi_data_xfer(mxic, NULL, NULL, op->dummy.nbytes); 522 if (ret) 523 goto out; 524 525 ret = mxic_spi_data_xfer(mxic, 526 op->data.dir == SPI_MEM_DATA_OUT ? 527 op->data.buf.out : NULL, 528 op->data.dir == SPI_MEM_DATA_IN ? 529 op->data.buf.in : NULL, 530 op->data.nbytes); 531 532 out: 533 writel(readl(mxic->regs + HC_CFG) & ~HC_CFG_MAN_CS_ASSERT, 534 mxic->regs + HC_CFG); 535 writel(0, mxic->regs + HC_EN); 536 537 return ret; 538 } 539 540 static const struct spi_controller_mem_ops mxic_spi_mem_ops = { 541 .supports_op = mxic_spi_mem_supports_op, 542 .exec_op = mxic_spi_mem_exec_op, 543 .dirmap_create = mxic_spi_mem_dirmap_create, 544 .dirmap_read = mxic_spi_mem_dirmap_read, 545 .dirmap_write = mxic_spi_mem_dirmap_write, 546 }; 547 548 static const struct spi_controller_mem_caps mxic_spi_mem_caps = { 549 .dtr = true, 550 }; 551 552 static void mxic_spi_set_cs(struct spi_device *spi, bool lvl) 553 { 554 struct mxic_spi *mxic = spi_master_get_devdata(spi->master); 555 556 if (!lvl) { 557 writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_EN, 558 mxic->regs + HC_CFG); 559 writel(HC_EN_BIT, mxic->regs + HC_EN); 560 writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT, 561 mxic->regs + HC_CFG); 562 } else { 563 writel(readl(mxic->regs + HC_CFG) & ~HC_CFG_MAN_CS_ASSERT, 564 mxic->regs + HC_CFG); 565 writel(0, mxic->regs + HC_EN); 566 } 567 } 568 569 static int mxic_spi_transfer_one(struct spi_master *master, 570 struct spi_device *spi, 571 struct spi_transfer *t) 572 { 573 struct mxic_spi *mxic = spi_master_get_devdata(master); 574 unsigned int busw = OP_BUSW_1; 575 int ret; 576 577 if (t->rx_buf && t->tx_buf) { 578 if (((spi->mode & SPI_TX_QUAD) && 579 !(spi->mode & SPI_RX_QUAD)) || 580 ((spi->mode & SPI_TX_DUAL) && 581 !(spi->mode & SPI_RX_DUAL))) 582 return -ENOTSUPP; 583 } 584 585 ret = mxic_spi_set_freq(mxic, t->speed_hz); 586 if (ret) 587 return ret; 588 589 if (t->tx_buf) { 590 if (spi->mode & SPI_TX_QUAD) 591 busw = OP_BUSW_4; 592 else if (spi->mode & SPI_TX_DUAL) 593 busw = OP_BUSW_2; 594 } else if (t->rx_buf) { 595 if (spi->mode & SPI_RX_QUAD) 596 busw = OP_BUSW_4; 597 else if (spi->mode & SPI_RX_DUAL) 598 busw = OP_BUSW_2; 599 } 600 601 writel(OP_CMD_BYTES(1) | OP_CMD_BUSW(busw) | 602 OP_DATA_BUSW(busw) | (t->rx_buf ? OP_READ : 0), 603 mxic->regs + SS_CTRL(0)); 604 605 ret = mxic_spi_data_xfer(mxic, t->tx_buf, t->rx_buf, t->len); 606 if (ret) 607 return ret; 608 609 spi_finalize_current_transfer(master); 610 611 return 0; 612 } 613 614 static int __maybe_unused mxic_spi_runtime_suspend(struct device *dev) 615 { 616 struct spi_master *master = dev_get_drvdata(dev); 617 struct mxic_spi *mxic = spi_master_get_devdata(master); 618 619 mxic_spi_clk_disable(mxic); 620 clk_disable_unprepare(mxic->ps_clk); 621 622 return 0; 623 } 624 625 static int __maybe_unused mxic_spi_runtime_resume(struct device *dev) 626 { 627 struct spi_master *master = dev_get_drvdata(dev); 628 struct mxic_spi *mxic = spi_master_get_devdata(master); 629 int ret; 630 631 ret = clk_prepare_enable(mxic->ps_clk); 632 if (ret) { 633 dev_err(dev, "Cannot enable ps_clock.\n"); 634 return ret; 635 } 636 637 return mxic_spi_clk_enable(mxic); 638 } 639 640 static const struct dev_pm_ops mxic_spi_dev_pm_ops = { 641 SET_RUNTIME_PM_OPS(mxic_spi_runtime_suspend, 642 mxic_spi_runtime_resume, NULL) 643 }; 644 645 static int mxic_spi_probe(struct platform_device *pdev) 646 { 647 struct spi_master *master; 648 struct resource *res; 649 struct mxic_spi *mxic; 650 int ret; 651 652 master = devm_spi_alloc_master(&pdev->dev, sizeof(struct mxic_spi)); 653 if (!master) 654 return -ENOMEM; 655 656 platform_set_drvdata(pdev, master); 657 658 mxic = spi_master_get_devdata(master); 659 660 master->dev.of_node = pdev->dev.of_node; 661 662 mxic->ps_clk = devm_clk_get(&pdev->dev, "ps_clk"); 663 if (IS_ERR(mxic->ps_clk)) 664 return PTR_ERR(mxic->ps_clk); 665 666 mxic->send_clk = devm_clk_get(&pdev->dev, "send_clk"); 667 if (IS_ERR(mxic->send_clk)) 668 return PTR_ERR(mxic->send_clk); 669 670 mxic->send_dly_clk = devm_clk_get(&pdev->dev, "send_dly_clk"); 671 if (IS_ERR(mxic->send_dly_clk)) 672 return PTR_ERR(mxic->send_dly_clk); 673 674 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); 675 mxic->regs = devm_ioremap_resource(&pdev->dev, res); 676 if (IS_ERR(mxic->regs)) 677 return PTR_ERR(mxic->regs); 678 679 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dirmap"); 680 mxic->linear.map = devm_ioremap_resource(&pdev->dev, res); 681 if (!IS_ERR(mxic->linear.map)) { 682 mxic->linear.dma = res->start; 683 mxic->linear.size = resource_size(res); 684 } else { 685 mxic->linear.map = NULL; 686 } 687 688 pm_runtime_enable(&pdev->dev); 689 master->auto_runtime_pm = true; 690 691 master->num_chipselect = 1; 692 master->mem_ops = &mxic_spi_mem_ops; 693 master->mem_caps = &mxic_spi_mem_caps; 694 695 master->set_cs = mxic_spi_set_cs; 696 master->transfer_one = mxic_spi_transfer_one; 697 master->bits_per_word_mask = SPI_BPW_MASK(8); 698 master->mode_bits = SPI_CPOL | SPI_CPHA | 699 SPI_RX_DUAL | SPI_TX_DUAL | 700 SPI_RX_QUAD | SPI_TX_QUAD | 701 SPI_RX_OCTAL | SPI_TX_OCTAL; 702 703 mxic_spi_hw_init(mxic); 704 705 ret = spi_register_master(master); 706 if (ret) { 707 dev_err(&pdev->dev, "spi_register_master failed\n"); 708 pm_runtime_disable(&pdev->dev); 709 } 710 711 return ret; 712 } 713 714 static int mxic_spi_remove(struct platform_device *pdev) 715 { 716 struct spi_master *master = platform_get_drvdata(pdev); 717 718 pm_runtime_disable(&pdev->dev); 719 spi_unregister_master(master); 720 721 return 0; 722 } 723 724 static const struct of_device_id mxic_spi_of_ids[] = { 725 { .compatible = "mxicy,mx25f0a-spi", }, 726 { /* sentinel */ } 727 }; 728 MODULE_DEVICE_TABLE(of, mxic_spi_of_ids); 729 730 static struct platform_driver mxic_spi_driver = { 731 .probe = mxic_spi_probe, 732 .remove = mxic_spi_remove, 733 .driver = { 734 .name = "mxic-spi", 735 .of_match_table = mxic_spi_of_ids, 736 .pm = &mxic_spi_dev_pm_ops, 737 }, 738 }; 739 module_platform_driver(mxic_spi_driver); 740 741 MODULE_AUTHOR("Mason Yang <masonccyang@mxic.com.tw>"); 742 MODULE_DESCRIPTION("MX25F0A SPI controller driver"); 743 MODULE_LICENSE("GPL v2"); 744