1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Author: Leilk Liu <leilk.liu@mediatek.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/device.h> 9 #include <linux/err.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 #include <linux/ioport.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/platform_device.h> 17 #include <linux/platform_data/spi-mt65xx.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/spi/spi.h> 20 #include <linux/dma-mapping.h> 21 22 #define SPI_CFG0_REG 0x0000 23 #define SPI_CFG1_REG 0x0004 24 #define SPI_TX_SRC_REG 0x0008 25 #define SPI_RX_DST_REG 0x000c 26 #define SPI_TX_DATA_REG 0x0010 27 #define SPI_RX_DATA_REG 0x0014 28 #define SPI_CMD_REG 0x0018 29 #define SPI_STATUS0_REG 0x001c 30 #define SPI_PAD_SEL_REG 0x0024 31 #define SPI_CFG2_REG 0x0028 32 #define SPI_TX_SRC_REG_64 0x002c 33 #define SPI_RX_DST_REG_64 0x0030 34 #define SPI_CFG3_IPM_REG 0x0040 35 36 #define SPI_CFG0_SCK_HIGH_OFFSET 0 37 #define SPI_CFG0_SCK_LOW_OFFSET 8 38 #define SPI_CFG0_CS_HOLD_OFFSET 16 39 #define SPI_CFG0_CS_SETUP_OFFSET 24 40 #define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0 41 #define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16 42 43 #define SPI_CFG1_CS_IDLE_OFFSET 0 44 #define SPI_CFG1_PACKET_LOOP_OFFSET 8 45 #define SPI_CFG1_PACKET_LENGTH_OFFSET 16 46 #define SPI_CFG1_GET_TICK_DLY_OFFSET 29 47 #define SPI_CFG1_GET_TICK_DLY_OFFSET_V1 30 48 49 #define SPI_CFG1_GET_TICK_DLY_MASK 0xe0000000 50 #define SPI_CFG1_GET_TICK_DLY_MASK_V1 0xc0000000 51 52 #define SPI_CFG1_CS_IDLE_MASK 0xff 53 #define SPI_CFG1_PACKET_LOOP_MASK 0xff00 54 #define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000 55 #define SPI_CFG1_IPM_PACKET_LENGTH_MASK GENMASK(31, 16) 56 #define SPI_CFG2_SCK_HIGH_OFFSET 0 57 #define SPI_CFG2_SCK_LOW_OFFSET 16 58 59 #define SPI_CMD_ACT BIT(0) 60 #define SPI_CMD_RESUME BIT(1) 61 #define SPI_CMD_RST BIT(2) 62 #define SPI_CMD_PAUSE_EN BIT(4) 63 #define SPI_CMD_DEASSERT BIT(5) 64 #define SPI_CMD_SAMPLE_SEL BIT(6) 65 #define SPI_CMD_CS_POL BIT(7) 66 #define SPI_CMD_CPHA BIT(8) 67 #define SPI_CMD_CPOL BIT(9) 68 #define SPI_CMD_RX_DMA BIT(10) 69 #define SPI_CMD_TX_DMA BIT(11) 70 #define SPI_CMD_TXMSBF BIT(12) 71 #define SPI_CMD_RXMSBF BIT(13) 72 #define SPI_CMD_RX_ENDIAN BIT(14) 73 #define SPI_CMD_TX_ENDIAN BIT(15) 74 #define SPI_CMD_FINISH_IE BIT(16) 75 #define SPI_CMD_PAUSE_IE BIT(17) 76 #define SPI_CMD_IPM_NONIDLE_MODE BIT(19) 77 #define SPI_CMD_IPM_SPIM_LOOP BIT(21) 78 #define SPI_CMD_IPM_GET_TICKDLY_OFFSET 22 79 80 #define SPI_CMD_IPM_GET_TICKDLY_MASK GENMASK(24, 22) 81 #define SPI_CFG3_IPM_HALF_DUPLEX_DIR BIT(2) 82 #define SPI_CFG3_IPM_HALF_DUPLEX_EN BIT(3) 83 #define MT8173_SPI_MAX_PAD_SEL 3 84 85 #define MTK_SPI_PAUSE_INT_STATUS 0x2 86 87 #define MTK_SPI_IDLE 0 88 #define MTK_SPI_PAUSED 1 89 90 #define MTK_SPI_MAX_FIFO_SIZE 32U 91 #define MTK_SPI_PACKET_SIZE 1024 92 #define MTK_SPI_IPM_PACKET_SIZE SZ_64K 93 #define MTK_SPI_32BITS_MASK (0xffffffff) 94 95 #define DMA_ADDR_EXT_BITS (36) 96 #define DMA_ADDR_DEF_BITS (32) 97 98 struct mtk_spi_compatible { 99 bool need_pad_sel; 100 /* Must explicitly send dummy Tx bytes to do Rx only transfer */ 101 bool must_tx; 102 /* some IC design adjust cfg register to enhance time accuracy */ 103 bool enhance_timing; 104 /* some IC support DMA addr extension */ 105 bool dma_ext; 106 /* some IC no need unprepare SPI clk */ 107 bool no_need_unprepare; 108 /* IPM design adjust and extend register to support more features */ 109 bool ipm_design; 110 111 }; 112 113 struct mtk_spi { 114 void __iomem *base; 115 u32 state; 116 int pad_num; 117 u32 *pad_sel; 118 struct clk *parent_clk, *sel_clk, *spi_clk; 119 struct spi_transfer *cur_transfer; 120 u32 xfer_len; 121 u32 num_xfered; 122 struct scatterlist *tx_sgl, *rx_sgl; 123 u32 tx_sgl_len, rx_sgl_len; 124 const struct mtk_spi_compatible *dev_comp; 125 u32 spi_clk_hz; 126 }; 127 128 static const struct mtk_spi_compatible mtk_common_compat; 129 130 static const struct mtk_spi_compatible mt2712_compat = { 131 .must_tx = true, 132 }; 133 134 static const struct mtk_spi_compatible mtk_ipm_compat = { 135 .enhance_timing = true, 136 .dma_ext = true, 137 .ipm_design = true, 138 }; 139 140 static const struct mtk_spi_compatible mt6765_compat = { 141 .need_pad_sel = true, 142 .must_tx = true, 143 .enhance_timing = true, 144 .dma_ext = true, 145 }; 146 147 static const struct mtk_spi_compatible mt7622_compat = { 148 .must_tx = true, 149 .enhance_timing = true, 150 }; 151 152 static const struct mtk_spi_compatible mt8173_compat = { 153 .need_pad_sel = true, 154 .must_tx = true, 155 }; 156 157 static const struct mtk_spi_compatible mt8183_compat = { 158 .need_pad_sel = true, 159 .must_tx = true, 160 .enhance_timing = true, 161 }; 162 163 static const struct mtk_spi_compatible mt6893_compat = { 164 .need_pad_sel = true, 165 .must_tx = true, 166 .enhance_timing = true, 167 .dma_ext = true, 168 .no_need_unprepare = true, 169 }; 170 171 /* 172 * A piece of default chip info unless the platform 173 * supplies it. 174 */ 175 static const struct mtk_chip_config mtk_default_chip_info = { 176 .sample_sel = 0, 177 .tick_delay = 0, 178 }; 179 180 static const struct of_device_id mtk_spi_of_match[] = { 181 { .compatible = "mediatek,spi-ipm", 182 .data = (void *)&mtk_ipm_compat, 183 }, 184 { .compatible = "mediatek,mt2701-spi", 185 .data = (void *)&mtk_common_compat, 186 }, 187 { .compatible = "mediatek,mt2712-spi", 188 .data = (void *)&mt2712_compat, 189 }, 190 { .compatible = "mediatek,mt6589-spi", 191 .data = (void *)&mtk_common_compat, 192 }, 193 { .compatible = "mediatek,mt6765-spi", 194 .data = (void *)&mt6765_compat, 195 }, 196 { .compatible = "mediatek,mt7622-spi", 197 .data = (void *)&mt7622_compat, 198 }, 199 { .compatible = "mediatek,mt7629-spi", 200 .data = (void *)&mt7622_compat, 201 }, 202 { .compatible = "mediatek,mt8135-spi", 203 .data = (void *)&mtk_common_compat, 204 }, 205 { .compatible = "mediatek,mt8173-spi", 206 .data = (void *)&mt8173_compat, 207 }, 208 { .compatible = "mediatek,mt8183-spi", 209 .data = (void *)&mt8183_compat, 210 }, 211 { .compatible = "mediatek,mt8192-spi", 212 .data = (void *)&mt6765_compat, 213 }, 214 { .compatible = "mediatek,mt6893-spi", 215 .data = (void *)&mt6893_compat, 216 }, 217 {} 218 }; 219 MODULE_DEVICE_TABLE(of, mtk_spi_of_match); 220 221 static void mtk_spi_reset(struct mtk_spi *mdata) 222 { 223 u32 reg_val; 224 225 /* set the software reset bit in SPI_CMD_REG. */ 226 reg_val = readl(mdata->base + SPI_CMD_REG); 227 reg_val |= SPI_CMD_RST; 228 writel(reg_val, mdata->base + SPI_CMD_REG); 229 230 reg_val = readl(mdata->base + SPI_CMD_REG); 231 reg_val &= ~SPI_CMD_RST; 232 writel(reg_val, mdata->base + SPI_CMD_REG); 233 } 234 235 static int mtk_spi_set_hw_cs_timing(struct spi_device *spi) 236 { 237 struct mtk_spi *mdata = spi_master_get_devdata(spi->master); 238 struct spi_delay *cs_setup = &spi->cs_setup; 239 struct spi_delay *cs_hold = &spi->cs_hold; 240 struct spi_delay *cs_inactive = &spi->cs_inactive; 241 u32 setup, hold, inactive; 242 u32 reg_val; 243 int delay; 244 245 delay = spi_delay_to_ns(cs_setup, NULL); 246 if (delay < 0) 247 return delay; 248 setup = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000; 249 250 delay = spi_delay_to_ns(cs_hold, NULL); 251 if (delay < 0) 252 return delay; 253 hold = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000; 254 255 delay = spi_delay_to_ns(cs_inactive, NULL); 256 if (delay < 0) 257 return delay; 258 inactive = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000; 259 260 if (hold || setup) { 261 reg_val = readl(mdata->base + SPI_CFG0_REG); 262 if (mdata->dev_comp->enhance_timing) { 263 if (hold) { 264 hold = min_t(u32, hold, 0x10000); 265 reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_HOLD_OFFSET); 266 reg_val |= (((hold - 1) & 0xffff) 267 << SPI_ADJUST_CFG0_CS_HOLD_OFFSET); 268 } 269 if (setup) { 270 setup = min_t(u32, setup, 0x10000); 271 reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_SETUP_OFFSET); 272 reg_val |= (((setup - 1) & 0xffff) 273 << SPI_ADJUST_CFG0_CS_SETUP_OFFSET); 274 } 275 } else { 276 if (hold) { 277 hold = min_t(u32, hold, 0x100); 278 reg_val &= ~(0xff << SPI_CFG0_CS_HOLD_OFFSET); 279 reg_val |= (((hold - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET); 280 } 281 if (setup) { 282 setup = min_t(u32, setup, 0x100); 283 reg_val &= ~(0xff << SPI_CFG0_CS_SETUP_OFFSET); 284 reg_val |= (((setup - 1) & 0xff) 285 << SPI_CFG0_CS_SETUP_OFFSET); 286 } 287 } 288 writel(reg_val, mdata->base + SPI_CFG0_REG); 289 } 290 291 if (inactive) { 292 inactive = min_t(u32, inactive, 0x100); 293 reg_val = readl(mdata->base + SPI_CFG1_REG); 294 reg_val &= ~SPI_CFG1_CS_IDLE_MASK; 295 reg_val |= (((inactive - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET); 296 writel(reg_val, mdata->base + SPI_CFG1_REG); 297 } 298 299 return 0; 300 } 301 302 static int mtk_spi_hw_init(struct spi_master *master, 303 struct spi_device *spi) 304 { 305 u16 cpha, cpol; 306 u32 reg_val; 307 struct mtk_chip_config *chip_config = spi->controller_data; 308 struct mtk_spi *mdata = spi_master_get_devdata(master); 309 310 cpha = spi->mode & SPI_CPHA ? 1 : 0; 311 cpol = spi->mode & SPI_CPOL ? 1 : 0; 312 313 reg_val = readl(mdata->base + SPI_CMD_REG); 314 if (mdata->dev_comp->ipm_design) { 315 /* SPI transfer without idle time until packet length done */ 316 reg_val |= SPI_CMD_IPM_NONIDLE_MODE; 317 if (spi->mode & SPI_LOOP) 318 reg_val |= SPI_CMD_IPM_SPIM_LOOP; 319 else 320 reg_val &= ~SPI_CMD_IPM_SPIM_LOOP; 321 } 322 323 if (cpha) 324 reg_val |= SPI_CMD_CPHA; 325 else 326 reg_val &= ~SPI_CMD_CPHA; 327 if (cpol) 328 reg_val |= SPI_CMD_CPOL; 329 else 330 reg_val &= ~SPI_CMD_CPOL; 331 332 /* set the mlsbx and mlsbtx */ 333 if (spi->mode & SPI_LSB_FIRST) { 334 reg_val &= ~SPI_CMD_TXMSBF; 335 reg_val &= ~SPI_CMD_RXMSBF; 336 } else { 337 reg_val |= SPI_CMD_TXMSBF; 338 reg_val |= SPI_CMD_RXMSBF; 339 } 340 341 /* set the tx/rx endian */ 342 #ifdef __LITTLE_ENDIAN 343 reg_val &= ~SPI_CMD_TX_ENDIAN; 344 reg_val &= ~SPI_CMD_RX_ENDIAN; 345 #else 346 reg_val |= SPI_CMD_TX_ENDIAN; 347 reg_val |= SPI_CMD_RX_ENDIAN; 348 #endif 349 350 if (mdata->dev_comp->enhance_timing) { 351 /* set CS polarity */ 352 if (spi->mode & SPI_CS_HIGH) 353 reg_val |= SPI_CMD_CS_POL; 354 else 355 reg_val &= ~SPI_CMD_CS_POL; 356 357 if (chip_config->sample_sel) 358 reg_val |= SPI_CMD_SAMPLE_SEL; 359 else 360 reg_val &= ~SPI_CMD_SAMPLE_SEL; 361 } 362 363 /* set finish and pause interrupt always enable */ 364 reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE; 365 366 /* disable dma mode */ 367 reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA); 368 369 /* disable deassert mode */ 370 reg_val &= ~SPI_CMD_DEASSERT; 371 372 writel(reg_val, mdata->base + SPI_CMD_REG); 373 374 /* pad select */ 375 if (mdata->dev_comp->need_pad_sel) 376 writel(mdata->pad_sel[spi->chip_select], 377 mdata->base + SPI_PAD_SEL_REG); 378 379 /* tick delay */ 380 if (mdata->dev_comp->enhance_timing) { 381 if (mdata->dev_comp->ipm_design) { 382 reg_val = readl(mdata->base + SPI_CMD_REG); 383 reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK; 384 reg_val |= ((chip_config->tick_delay & 0x7) 385 << SPI_CMD_IPM_GET_TICKDLY_OFFSET); 386 writel(reg_val, mdata->base + SPI_CMD_REG); 387 } else { 388 reg_val = readl(mdata->base + SPI_CFG1_REG); 389 reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK; 390 reg_val |= ((chip_config->tick_delay & 0x7) 391 << SPI_CFG1_GET_TICK_DLY_OFFSET); 392 writel(reg_val, mdata->base + SPI_CFG1_REG); 393 } 394 } else { 395 reg_val = readl(mdata->base + SPI_CFG1_REG); 396 reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1; 397 reg_val |= ((chip_config->tick_delay & 0x3) 398 << SPI_CFG1_GET_TICK_DLY_OFFSET_V1); 399 writel(reg_val, mdata->base + SPI_CFG1_REG); 400 } 401 402 /* set hw cs timing */ 403 mtk_spi_set_hw_cs_timing(spi); 404 return 0; 405 } 406 407 static int mtk_spi_prepare_message(struct spi_master *master, 408 struct spi_message *msg) 409 { 410 return mtk_spi_hw_init(master, msg->spi); 411 } 412 413 static void mtk_spi_set_cs(struct spi_device *spi, bool enable) 414 { 415 u32 reg_val; 416 struct mtk_spi *mdata = spi_master_get_devdata(spi->master); 417 418 if (spi->mode & SPI_CS_HIGH) 419 enable = !enable; 420 421 reg_val = readl(mdata->base + SPI_CMD_REG); 422 if (!enable) { 423 reg_val |= SPI_CMD_PAUSE_EN; 424 writel(reg_val, mdata->base + SPI_CMD_REG); 425 } else { 426 reg_val &= ~SPI_CMD_PAUSE_EN; 427 writel(reg_val, mdata->base + SPI_CMD_REG); 428 mdata->state = MTK_SPI_IDLE; 429 mtk_spi_reset(mdata); 430 } 431 } 432 433 static void mtk_spi_prepare_transfer(struct spi_master *master, 434 u32 speed_hz) 435 { 436 u32 div, sck_time, reg_val; 437 struct mtk_spi *mdata = spi_master_get_devdata(master); 438 439 if (speed_hz < mdata->spi_clk_hz / 2) 440 div = DIV_ROUND_UP(mdata->spi_clk_hz, speed_hz); 441 else 442 div = 1; 443 444 sck_time = (div + 1) / 2; 445 446 if (mdata->dev_comp->enhance_timing) { 447 reg_val = readl(mdata->base + SPI_CFG2_REG); 448 reg_val &= ~(0xffff << SPI_CFG2_SCK_HIGH_OFFSET); 449 reg_val |= (((sck_time - 1) & 0xffff) 450 << SPI_CFG2_SCK_HIGH_OFFSET); 451 reg_val &= ~(0xffff << SPI_CFG2_SCK_LOW_OFFSET); 452 reg_val |= (((sck_time - 1) & 0xffff) 453 << SPI_CFG2_SCK_LOW_OFFSET); 454 writel(reg_val, mdata->base + SPI_CFG2_REG); 455 } else { 456 reg_val = readl(mdata->base + SPI_CFG0_REG); 457 reg_val &= ~(0xff << SPI_CFG0_SCK_HIGH_OFFSET); 458 reg_val |= (((sck_time - 1) & 0xff) 459 << SPI_CFG0_SCK_HIGH_OFFSET); 460 reg_val &= ~(0xff << SPI_CFG0_SCK_LOW_OFFSET); 461 reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET); 462 writel(reg_val, mdata->base + SPI_CFG0_REG); 463 } 464 } 465 466 static void mtk_spi_setup_packet(struct spi_master *master) 467 { 468 u32 packet_size, packet_loop, reg_val; 469 struct mtk_spi *mdata = spi_master_get_devdata(master); 470 471 if (mdata->dev_comp->ipm_design) 472 packet_size = min_t(u32, 473 mdata->xfer_len, 474 MTK_SPI_IPM_PACKET_SIZE); 475 else 476 packet_size = min_t(u32, 477 mdata->xfer_len, 478 MTK_SPI_PACKET_SIZE); 479 480 packet_loop = mdata->xfer_len / packet_size; 481 482 reg_val = readl(mdata->base + SPI_CFG1_REG); 483 if (mdata->dev_comp->ipm_design) 484 reg_val &= ~SPI_CFG1_IPM_PACKET_LENGTH_MASK; 485 else 486 reg_val &= ~SPI_CFG1_PACKET_LENGTH_MASK; 487 reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET; 488 reg_val &= ~SPI_CFG1_PACKET_LOOP_MASK; 489 reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET; 490 writel(reg_val, mdata->base + SPI_CFG1_REG); 491 } 492 493 static void mtk_spi_enable_transfer(struct spi_master *master) 494 { 495 u32 cmd; 496 struct mtk_spi *mdata = spi_master_get_devdata(master); 497 498 cmd = readl(mdata->base + SPI_CMD_REG); 499 if (mdata->state == MTK_SPI_IDLE) 500 cmd |= SPI_CMD_ACT; 501 else 502 cmd |= SPI_CMD_RESUME; 503 writel(cmd, mdata->base + SPI_CMD_REG); 504 } 505 506 static int mtk_spi_get_mult_delta(u32 xfer_len) 507 { 508 u32 mult_delta; 509 510 if (xfer_len > MTK_SPI_PACKET_SIZE) 511 mult_delta = xfer_len % MTK_SPI_PACKET_SIZE; 512 else 513 mult_delta = 0; 514 515 return mult_delta; 516 } 517 518 static void mtk_spi_update_mdata_len(struct spi_master *master) 519 { 520 int mult_delta; 521 struct mtk_spi *mdata = spi_master_get_devdata(master); 522 523 if (mdata->tx_sgl_len && mdata->rx_sgl_len) { 524 if (mdata->tx_sgl_len > mdata->rx_sgl_len) { 525 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len); 526 mdata->xfer_len = mdata->rx_sgl_len - mult_delta; 527 mdata->rx_sgl_len = mult_delta; 528 mdata->tx_sgl_len -= mdata->xfer_len; 529 } else { 530 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len); 531 mdata->xfer_len = mdata->tx_sgl_len - mult_delta; 532 mdata->tx_sgl_len = mult_delta; 533 mdata->rx_sgl_len -= mdata->xfer_len; 534 } 535 } else if (mdata->tx_sgl_len) { 536 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len); 537 mdata->xfer_len = mdata->tx_sgl_len - mult_delta; 538 mdata->tx_sgl_len = mult_delta; 539 } else if (mdata->rx_sgl_len) { 540 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len); 541 mdata->xfer_len = mdata->rx_sgl_len - mult_delta; 542 mdata->rx_sgl_len = mult_delta; 543 } 544 } 545 546 static void mtk_spi_setup_dma_addr(struct spi_master *master, 547 struct spi_transfer *xfer) 548 { 549 struct mtk_spi *mdata = spi_master_get_devdata(master); 550 551 if (mdata->tx_sgl) { 552 writel((u32)(xfer->tx_dma & MTK_SPI_32BITS_MASK), 553 mdata->base + SPI_TX_SRC_REG); 554 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 555 if (mdata->dev_comp->dma_ext) 556 writel((u32)(xfer->tx_dma >> 32), 557 mdata->base + SPI_TX_SRC_REG_64); 558 #endif 559 } 560 561 if (mdata->rx_sgl) { 562 writel((u32)(xfer->rx_dma & MTK_SPI_32BITS_MASK), 563 mdata->base + SPI_RX_DST_REG); 564 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 565 if (mdata->dev_comp->dma_ext) 566 writel((u32)(xfer->rx_dma >> 32), 567 mdata->base + SPI_RX_DST_REG_64); 568 #endif 569 } 570 } 571 572 static int mtk_spi_fifo_transfer(struct spi_master *master, 573 struct spi_device *spi, 574 struct spi_transfer *xfer) 575 { 576 int cnt, remainder; 577 u32 reg_val; 578 struct mtk_spi *mdata = spi_master_get_devdata(master); 579 580 mdata->cur_transfer = xfer; 581 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len); 582 mdata->num_xfered = 0; 583 mtk_spi_prepare_transfer(master, xfer->speed_hz); 584 mtk_spi_setup_packet(master); 585 586 if (xfer->tx_buf) { 587 cnt = xfer->len / 4; 588 iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt); 589 remainder = xfer->len % 4; 590 if (remainder > 0) { 591 reg_val = 0; 592 memcpy(®_val, xfer->tx_buf + (cnt * 4), remainder); 593 writel(reg_val, mdata->base + SPI_TX_DATA_REG); 594 } 595 } 596 597 mtk_spi_enable_transfer(master); 598 599 return 1; 600 } 601 602 static int mtk_spi_dma_transfer(struct spi_master *master, 603 struct spi_device *spi, 604 struct spi_transfer *xfer) 605 { 606 int cmd; 607 struct mtk_spi *mdata = spi_master_get_devdata(master); 608 609 mdata->tx_sgl = NULL; 610 mdata->rx_sgl = NULL; 611 mdata->tx_sgl_len = 0; 612 mdata->rx_sgl_len = 0; 613 mdata->cur_transfer = xfer; 614 mdata->num_xfered = 0; 615 616 mtk_spi_prepare_transfer(master, xfer->speed_hz); 617 618 cmd = readl(mdata->base + SPI_CMD_REG); 619 if (xfer->tx_buf) 620 cmd |= SPI_CMD_TX_DMA; 621 if (xfer->rx_buf) 622 cmd |= SPI_CMD_RX_DMA; 623 writel(cmd, mdata->base + SPI_CMD_REG); 624 625 if (xfer->tx_buf) 626 mdata->tx_sgl = xfer->tx_sg.sgl; 627 if (xfer->rx_buf) 628 mdata->rx_sgl = xfer->rx_sg.sgl; 629 630 if (mdata->tx_sgl) { 631 xfer->tx_dma = sg_dma_address(mdata->tx_sgl); 632 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl); 633 } 634 if (mdata->rx_sgl) { 635 xfer->rx_dma = sg_dma_address(mdata->rx_sgl); 636 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl); 637 } 638 639 mtk_spi_update_mdata_len(master); 640 mtk_spi_setup_packet(master); 641 mtk_spi_setup_dma_addr(master, xfer); 642 mtk_spi_enable_transfer(master); 643 644 return 1; 645 } 646 647 static int mtk_spi_transfer_one(struct spi_master *master, 648 struct spi_device *spi, 649 struct spi_transfer *xfer) 650 { 651 struct mtk_spi *mdata = spi_master_get_devdata(spi->master); 652 u32 reg_val = 0; 653 654 /* prepare xfer direction and duplex mode */ 655 if (mdata->dev_comp->ipm_design) { 656 if (!xfer->tx_buf || !xfer->rx_buf) { 657 reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN; 658 if (xfer->rx_buf) 659 reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR; 660 } 661 writel(reg_val, mdata->base + SPI_CFG3_IPM_REG); 662 } 663 664 if (master->can_dma(master, spi, xfer)) 665 return mtk_spi_dma_transfer(master, spi, xfer); 666 else 667 return mtk_spi_fifo_transfer(master, spi, xfer); 668 } 669 670 static bool mtk_spi_can_dma(struct spi_master *master, 671 struct spi_device *spi, 672 struct spi_transfer *xfer) 673 { 674 /* Buffers for DMA transactions must be 4-byte aligned */ 675 return (xfer->len > MTK_SPI_MAX_FIFO_SIZE && 676 (unsigned long)xfer->tx_buf % 4 == 0 && 677 (unsigned long)xfer->rx_buf % 4 == 0); 678 } 679 680 static int mtk_spi_setup(struct spi_device *spi) 681 { 682 struct mtk_spi *mdata = spi_master_get_devdata(spi->master); 683 684 if (!spi->controller_data) 685 spi->controller_data = (void *)&mtk_default_chip_info; 686 687 if (mdata->dev_comp->need_pad_sel && spi->cs_gpiod) 688 /* CS de-asserted, gpiolib will handle inversion */ 689 gpiod_direction_output(spi->cs_gpiod, 0); 690 691 return 0; 692 } 693 694 static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id) 695 { 696 u32 cmd, reg_val, cnt, remainder, len; 697 struct spi_master *master = dev_id; 698 struct mtk_spi *mdata = spi_master_get_devdata(master); 699 struct spi_transfer *trans = mdata->cur_transfer; 700 701 reg_val = readl(mdata->base + SPI_STATUS0_REG); 702 if (reg_val & MTK_SPI_PAUSE_INT_STATUS) 703 mdata->state = MTK_SPI_PAUSED; 704 else 705 mdata->state = MTK_SPI_IDLE; 706 707 if (!master->can_dma(master, NULL, trans)) { 708 if (trans->rx_buf) { 709 cnt = mdata->xfer_len / 4; 710 ioread32_rep(mdata->base + SPI_RX_DATA_REG, 711 trans->rx_buf + mdata->num_xfered, cnt); 712 remainder = mdata->xfer_len % 4; 713 if (remainder > 0) { 714 reg_val = readl(mdata->base + SPI_RX_DATA_REG); 715 memcpy(trans->rx_buf + 716 mdata->num_xfered + 717 (cnt * 4), 718 ®_val, 719 remainder); 720 } 721 } 722 723 mdata->num_xfered += mdata->xfer_len; 724 if (mdata->num_xfered == trans->len) { 725 spi_finalize_current_transfer(master); 726 return IRQ_HANDLED; 727 } 728 729 len = trans->len - mdata->num_xfered; 730 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, len); 731 mtk_spi_setup_packet(master); 732 733 cnt = mdata->xfer_len / 4; 734 iowrite32_rep(mdata->base + SPI_TX_DATA_REG, 735 trans->tx_buf + mdata->num_xfered, cnt); 736 737 remainder = mdata->xfer_len % 4; 738 if (remainder > 0) { 739 reg_val = 0; 740 memcpy(®_val, 741 trans->tx_buf + (cnt * 4) + mdata->num_xfered, 742 remainder); 743 writel(reg_val, mdata->base + SPI_TX_DATA_REG); 744 } 745 746 mtk_spi_enable_transfer(master); 747 748 return IRQ_HANDLED; 749 } 750 751 if (mdata->tx_sgl) 752 trans->tx_dma += mdata->xfer_len; 753 if (mdata->rx_sgl) 754 trans->rx_dma += mdata->xfer_len; 755 756 if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) { 757 mdata->tx_sgl = sg_next(mdata->tx_sgl); 758 if (mdata->tx_sgl) { 759 trans->tx_dma = sg_dma_address(mdata->tx_sgl); 760 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl); 761 } 762 } 763 if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) { 764 mdata->rx_sgl = sg_next(mdata->rx_sgl); 765 if (mdata->rx_sgl) { 766 trans->rx_dma = sg_dma_address(mdata->rx_sgl); 767 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl); 768 } 769 } 770 771 if (!mdata->tx_sgl && !mdata->rx_sgl) { 772 /* spi disable dma */ 773 cmd = readl(mdata->base + SPI_CMD_REG); 774 cmd &= ~SPI_CMD_TX_DMA; 775 cmd &= ~SPI_CMD_RX_DMA; 776 writel(cmd, mdata->base + SPI_CMD_REG); 777 778 spi_finalize_current_transfer(master); 779 return IRQ_HANDLED; 780 } 781 782 mtk_spi_update_mdata_len(master); 783 mtk_spi_setup_packet(master); 784 mtk_spi_setup_dma_addr(master, trans); 785 mtk_spi_enable_transfer(master); 786 787 return IRQ_HANDLED; 788 } 789 790 static int mtk_spi_probe(struct platform_device *pdev) 791 { 792 struct spi_master *master; 793 struct mtk_spi *mdata; 794 const struct of_device_id *of_id; 795 int i, irq, ret, addr_bits; 796 797 master = spi_alloc_master(&pdev->dev, sizeof(*mdata)); 798 if (!master) { 799 dev_err(&pdev->dev, "failed to alloc spi master\n"); 800 return -ENOMEM; 801 } 802 803 master->auto_runtime_pm = true; 804 master->dev.of_node = pdev->dev.of_node; 805 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; 806 807 master->set_cs = mtk_spi_set_cs; 808 master->prepare_message = mtk_spi_prepare_message; 809 master->transfer_one = mtk_spi_transfer_one; 810 master->can_dma = mtk_spi_can_dma; 811 master->setup = mtk_spi_setup; 812 master->set_cs_timing = mtk_spi_set_hw_cs_timing; 813 master->use_gpio_descriptors = true; 814 815 of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node); 816 if (!of_id) { 817 dev_err(&pdev->dev, "failed to probe of_node\n"); 818 ret = -EINVAL; 819 goto err_put_master; 820 } 821 822 mdata = spi_master_get_devdata(master); 823 mdata->dev_comp = of_id->data; 824 825 if (mdata->dev_comp->enhance_timing) 826 master->mode_bits |= SPI_CS_HIGH; 827 828 if (mdata->dev_comp->must_tx) 829 master->flags = SPI_MASTER_MUST_TX; 830 if (mdata->dev_comp->ipm_design) 831 master->mode_bits |= SPI_LOOP; 832 833 if (mdata->dev_comp->need_pad_sel) { 834 mdata->pad_num = of_property_count_u32_elems( 835 pdev->dev.of_node, 836 "mediatek,pad-select"); 837 if (mdata->pad_num < 0) { 838 dev_err(&pdev->dev, 839 "No 'mediatek,pad-select' property\n"); 840 ret = -EINVAL; 841 goto err_put_master; 842 } 843 844 mdata->pad_sel = devm_kmalloc_array(&pdev->dev, mdata->pad_num, 845 sizeof(u32), GFP_KERNEL); 846 if (!mdata->pad_sel) { 847 ret = -ENOMEM; 848 goto err_put_master; 849 } 850 851 for (i = 0; i < mdata->pad_num; i++) { 852 of_property_read_u32_index(pdev->dev.of_node, 853 "mediatek,pad-select", 854 i, &mdata->pad_sel[i]); 855 if (mdata->pad_sel[i] > MT8173_SPI_MAX_PAD_SEL) { 856 dev_err(&pdev->dev, "wrong pad-sel[%d]: %u\n", 857 i, mdata->pad_sel[i]); 858 ret = -EINVAL; 859 goto err_put_master; 860 } 861 } 862 } 863 864 platform_set_drvdata(pdev, master); 865 mdata->base = devm_platform_ioremap_resource(pdev, 0); 866 if (IS_ERR(mdata->base)) { 867 ret = PTR_ERR(mdata->base); 868 goto err_put_master; 869 } 870 871 irq = platform_get_irq(pdev, 0); 872 if (irq < 0) { 873 ret = irq; 874 goto err_put_master; 875 } 876 877 if (!pdev->dev.dma_mask) 878 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; 879 880 ret = devm_request_irq(&pdev->dev, irq, mtk_spi_interrupt, 881 IRQF_TRIGGER_NONE, dev_name(&pdev->dev), master); 882 if (ret) { 883 dev_err(&pdev->dev, "failed to register irq (%d)\n", ret); 884 goto err_put_master; 885 } 886 887 mdata->parent_clk = devm_clk_get(&pdev->dev, "parent-clk"); 888 if (IS_ERR(mdata->parent_clk)) { 889 ret = PTR_ERR(mdata->parent_clk); 890 dev_err(&pdev->dev, "failed to get parent-clk: %d\n", ret); 891 goto err_put_master; 892 } 893 894 mdata->sel_clk = devm_clk_get(&pdev->dev, "sel-clk"); 895 if (IS_ERR(mdata->sel_clk)) { 896 ret = PTR_ERR(mdata->sel_clk); 897 dev_err(&pdev->dev, "failed to get sel-clk: %d\n", ret); 898 goto err_put_master; 899 } 900 901 mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk"); 902 if (IS_ERR(mdata->spi_clk)) { 903 ret = PTR_ERR(mdata->spi_clk); 904 dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret); 905 goto err_put_master; 906 } 907 908 ret = clk_prepare_enable(mdata->spi_clk); 909 if (ret < 0) { 910 dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret); 911 goto err_put_master; 912 } 913 914 ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk); 915 if (ret < 0) { 916 dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret); 917 clk_disable_unprepare(mdata->spi_clk); 918 goto err_put_master; 919 } 920 921 mdata->spi_clk_hz = clk_get_rate(mdata->spi_clk); 922 923 if (mdata->dev_comp->no_need_unprepare) 924 clk_disable(mdata->spi_clk); 925 else 926 clk_disable_unprepare(mdata->spi_clk); 927 928 pm_runtime_enable(&pdev->dev); 929 930 if (mdata->dev_comp->need_pad_sel) { 931 if (mdata->pad_num != master->num_chipselect) { 932 dev_err(&pdev->dev, 933 "pad_num does not match num_chipselect(%d != %d)\n", 934 mdata->pad_num, master->num_chipselect); 935 ret = -EINVAL; 936 goto err_disable_runtime_pm; 937 } 938 939 if (!master->cs_gpiods && master->num_chipselect > 1) { 940 dev_err(&pdev->dev, 941 "cs_gpios not specified and num_chipselect > 1\n"); 942 ret = -EINVAL; 943 goto err_disable_runtime_pm; 944 } 945 } 946 947 if (mdata->dev_comp->dma_ext) 948 addr_bits = DMA_ADDR_EXT_BITS; 949 else 950 addr_bits = DMA_ADDR_DEF_BITS; 951 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(addr_bits)); 952 if (ret) 953 dev_notice(&pdev->dev, "SPI dma_set_mask(%d) failed, ret:%d\n", 954 addr_bits, ret); 955 956 ret = devm_spi_register_master(&pdev->dev, master); 957 if (ret) { 958 dev_err(&pdev->dev, "failed to register master (%d)\n", ret); 959 goto err_disable_runtime_pm; 960 } 961 962 return 0; 963 964 err_disable_runtime_pm: 965 pm_runtime_disable(&pdev->dev); 966 err_put_master: 967 spi_master_put(master); 968 969 return ret; 970 } 971 972 static int mtk_spi_remove(struct platform_device *pdev) 973 { 974 struct spi_master *master = platform_get_drvdata(pdev); 975 struct mtk_spi *mdata = spi_master_get_devdata(master); 976 977 pm_runtime_disable(&pdev->dev); 978 979 mtk_spi_reset(mdata); 980 981 if (mdata->dev_comp->no_need_unprepare) 982 clk_unprepare(mdata->spi_clk); 983 984 return 0; 985 } 986 987 #ifdef CONFIG_PM_SLEEP 988 static int mtk_spi_suspend(struct device *dev) 989 { 990 int ret; 991 struct spi_master *master = dev_get_drvdata(dev); 992 struct mtk_spi *mdata = spi_master_get_devdata(master); 993 994 ret = spi_master_suspend(master); 995 if (ret) 996 return ret; 997 998 if (!pm_runtime_suspended(dev)) 999 clk_disable_unprepare(mdata->spi_clk); 1000 1001 return ret; 1002 } 1003 1004 static int mtk_spi_resume(struct device *dev) 1005 { 1006 int ret; 1007 struct spi_master *master = dev_get_drvdata(dev); 1008 struct mtk_spi *mdata = spi_master_get_devdata(master); 1009 1010 if (!pm_runtime_suspended(dev)) { 1011 ret = clk_prepare_enable(mdata->spi_clk); 1012 if (ret < 0) { 1013 dev_err(dev, "failed to enable spi_clk (%d)\n", ret); 1014 return ret; 1015 } 1016 } 1017 1018 ret = spi_master_resume(master); 1019 if (ret < 0) 1020 clk_disable_unprepare(mdata->spi_clk); 1021 1022 return ret; 1023 } 1024 #endif /* CONFIG_PM_SLEEP */ 1025 1026 #ifdef CONFIG_PM 1027 static int mtk_spi_runtime_suspend(struct device *dev) 1028 { 1029 struct spi_master *master = dev_get_drvdata(dev); 1030 struct mtk_spi *mdata = spi_master_get_devdata(master); 1031 1032 if (mdata->dev_comp->no_need_unprepare) 1033 clk_disable(mdata->spi_clk); 1034 else 1035 clk_disable_unprepare(mdata->spi_clk); 1036 1037 return 0; 1038 } 1039 1040 static int mtk_spi_runtime_resume(struct device *dev) 1041 { 1042 struct spi_master *master = dev_get_drvdata(dev); 1043 struct mtk_spi *mdata = spi_master_get_devdata(master); 1044 int ret; 1045 1046 if (mdata->dev_comp->no_need_unprepare) 1047 ret = clk_enable(mdata->spi_clk); 1048 else 1049 ret = clk_prepare_enable(mdata->spi_clk); 1050 if (ret < 0) { 1051 dev_err(dev, "failed to enable spi_clk (%d)\n", ret); 1052 return ret; 1053 } 1054 1055 return 0; 1056 } 1057 #endif /* CONFIG_PM */ 1058 1059 static const struct dev_pm_ops mtk_spi_pm = { 1060 SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend, mtk_spi_resume) 1061 SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend, 1062 mtk_spi_runtime_resume, NULL) 1063 }; 1064 1065 static struct platform_driver mtk_spi_driver = { 1066 .driver = { 1067 .name = "mtk-spi", 1068 .pm = &mtk_spi_pm, 1069 .of_match_table = mtk_spi_of_match, 1070 }, 1071 .probe = mtk_spi_probe, 1072 .remove = mtk_spi_remove, 1073 }; 1074 1075 module_platform_driver(mtk_spi_driver); 1076 1077 MODULE_DESCRIPTION("MTK SPI Controller driver"); 1078 MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>"); 1079 MODULE_LICENSE("GPL v2"); 1080 MODULE_ALIAS("platform:mtk-spi"); 1081