1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Author: Leilk Liu <leilk.liu@mediatek.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/device.h> 9 #include <linux/err.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 #include <linux/ioport.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_gpio.h> 16 #include <linux/platform_device.h> 17 #include <linux/platform_data/spi-mt65xx.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/spi/spi.h> 20 #include <linux/dma-mapping.h> 21 22 #define SPI_CFG0_REG 0x0000 23 #define SPI_CFG1_REG 0x0004 24 #define SPI_TX_SRC_REG 0x0008 25 #define SPI_RX_DST_REG 0x000c 26 #define SPI_TX_DATA_REG 0x0010 27 #define SPI_RX_DATA_REG 0x0014 28 #define SPI_CMD_REG 0x0018 29 #define SPI_STATUS0_REG 0x001c 30 #define SPI_PAD_SEL_REG 0x0024 31 #define SPI_CFG2_REG 0x0028 32 #define SPI_TX_SRC_REG_64 0x002c 33 #define SPI_RX_DST_REG_64 0x0030 34 35 #define SPI_CFG0_SCK_HIGH_OFFSET 0 36 #define SPI_CFG0_SCK_LOW_OFFSET 8 37 #define SPI_CFG0_CS_HOLD_OFFSET 16 38 #define SPI_CFG0_CS_SETUP_OFFSET 24 39 #define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0 40 #define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16 41 42 #define SPI_CFG1_CS_IDLE_OFFSET 0 43 #define SPI_CFG1_PACKET_LOOP_OFFSET 8 44 #define SPI_CFG1_PACKET_LENGTH_OFFSET 16 45 #define SPI_CFG1_GET_TICK_DLY_OFFSET 30 46 47 #define SPI_CFG1_CS_IDLE_MASK 0xff 48 #define SPI_CFG1_PACKET_LOOP_MASK 0xff00 49 #define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000 50 #define SPI_CFG2_SCK_HIGH_OFFSET 0 51 #define SPI_CFG2_SCK_LOW_OFFSET 16 52 53 #define SPI_CMD_ACT BIT(0) 54 #define SPI_CMD_RESUME BIT(1) 55 #define SPI_CMD_RST BIT(2) 56 #define SPI_CMD_PAUSE_EN BIT(4) 57 #define SPI_CMD_DEASSERT BIT(5) 58 #define SPI_CMD_SAMPLE_SEL BIT(6) 59 #define SPI_CMD_CS_POL BIT(7) 60 #define SPI_CMD_CPHA BIT(8) 61 #define SPI_CMD_CPOL BIT(9) 62 #define SPI_CMD_RX_DMA BIT(10) 63 #define SPI_CMD_TX_DMA BIT(11) 64 #define SPI_CMD_TXMSBF BIT(12) 65 #define SPI_CMD_RXMSBF BIT(13) 66 #define SPI_CMD_RX_ENDIAN BIT(14) 67 #define SPI_CMD_TX_ENDIAN BIT(15) 68 #define SPI_CMD_FINISH_IE BIT(16) 69 #define SPI_CMD_PAUSE_IE BIT(17) 70 71 #define MT8173_SPI_MAX_PAD_SEL 3 72 73 #define MTK_SPI_PAUSE_INT_STATUS 0x2 74 75 #define MTK_SPI_IDLE 0 76 #define MTK_SPI_PAUSED 1 77 78 #define MTK_SPI_MAX_FIFO_SIZE 32U 79 #define MTK_SPI_PACKET_SIZE 1024 80 #define MTK_SPI_32BITS_MASK (0xffffffff) 81 82 #define DMA_ADDR_EXT_BITS (36) 83 #define DMA_ADDR_DEF_BITS (32) 84 85 struct mtk_spi_compatible { 86 bool need_pad_sel; 87 /* Must explicitly send dummy Tx bytes to do Rx only transfer */ 88 bool must_tx; 89 /* some IC design adjust cfg register to enhance time accuracy */ 90 bool enhance_timing; 91 /* some IC support DMA addr extension */ 92 bool dma_ext; 93 }; 94 95 struct mtk_spi { 96 void __iomem *base; 97 u32 state; 98 int pad_num; 99 u32 *pad_sel; 100 struct clk *parent_clk, *sel_clk, *spi_clk; 101 struct spi_transfer *cur_transfer; 102 u32 xfer_len; 103 u32 num_xfered; 104 struct scatterlist *tx_sgl, *rx_sgl; 105 u32 tx_sgl_len, rx_sgl_len; 106 const struct mtk_spi_compatible *dev_comp; 107 }; 108 109 static const struct mtk_spi_compatible mtk_common_compat; 110 111 static const struct mtk_spi_compatible mt2712_compat = { 112 .must_tx = true, 113 }; 114 115 static const struct mtk_spi_compatible mt6765_compat = { 116 .need_pad_sel = true, 117 .must_tx = true, 118 .enhance_timing = true, 119 .dma_ext = true, 120 }; 121 122 static const struct mtk_spi_compatible mt7622_compat = { 123 .must_tx = true, 124 .enhance_timing = true, 125 }; 126 127 static const struct mtk_spi_compatible mt8173_compat = { 128 .need_pad_sel = true, 129 .must_tx = true, 130 }; 131 132 static const struct mtk_spi_compatible mt8183_compat = { 133 .need_pad_sel = true, 134 .must_tx = true, 135 .enhance_timing = true, 136 }; 137 138 /* 139 * A piece of default chip info unless the platform 140 * supplies it. 141 */ 142 static const struct mtk_chip_config mtk_default_chip_info = { 143 .sample_sel = 0, 144 }; 145 146 static const struct of_device_id mtk_spi_of_match[] = { 147 { .compatible = "mediatek,mt2701-spi", 148 .data = (void *)&mtk_common_compat, 149 }, 150 { .compatible = "mediatek,mt2712-spi", 151 .data = (void *)&mt2712_compat, 152 }, 153 { .compatible = "mediatek,mt6589-spi", 154 .data = (void *)&mtk_common_compat, 155 }, 156 { .compatible = "mediatek,mt6765-spi", 157 .data = (void *)&mt6765_compat, 158 }, 159 { .compatible = "mediatek,mt7622-spi", 160 .data = (void *)&mt7622_compat, 161 }, 162 { .compatible = "mediatek,mt7629-spi", 163 .data = (void *)&mt7622_compat, 164 }, 165 { .compatible = "mediatek,mt8135-spi", 166 .data = (void *)&mtk_common_compat, 167 }, 168 { .compatible = "mediatek,mt8173-spi", 169 .data = (void *)&mt8173_compat, 170 }, 171 { .compatible = "mediatek,mt8183-spi", 172 .data = (void *)&mt8183_compat, 173 }, 174 { .compatible = "mediatek,mt8192-spi", 175 .data = (void *)&mt6765_compat, 176 }, 177 {} 178 }; 179 MODULE_DEVICE_TABLE(of, mtk_spi_of_match); 180 181 static void mtk_spi_reset(struct mtk_spi *mdata) 182 { 183 u32 reg_val; 184 185 /* set the software reset bit in SPI_CMD_REG. */ 186 reg_val = readl(mdata->base + SPI_CMD_REG); 187 reg_val |= SPI_CMD_RST; 188 writel(reg_val, mdata->base + SPI_CMD_REG); 189 190 reg_val = readl(mdata->base + SPI_CMD_REG); 191 reg_val &= ~SPI_CMD_RST; 192 writel(reg_val, mdata->base + SPI_CMD_REG); 193 } 194 195 static int mtk_spi_prepare_message(struct spi_master *master, 196 struct spi_message *msg) 197 { 198 u16 cpha, cpol; 199 u32 reg_val; 200 struct spi_device *spi = msg->spi; 201 struct mtk_chip_config *chip_config = spi->controller_data; 202 struct mtk_spi *mdata = spi_master_get_devdata(master); 203 204 cpha = spi->mode & SPI_CPHA ? 1 : 0; 205 cpol = spi->mode & SPI_CPOL ? 1 : 0; 206 207 reg_val = readl(mdata->base + SPI_CMD_REG); 208 if (cpha) 209 reg_val |= SPI_CMD_CPHA; 210 else 211 reg_val &= ~SPI_CMD_CPHA; 212 if (cpol) 213 reg_val |= SPI_CMD_CPOL; 214 else 215 reg_val &= ~SPI_CMD_CPOL; 216 217 /* set the mlsbx and mlsbtx */ 218 if (spi->mode & SPI_LSB_FIRST) { 219 reg_val &= ~SPI_CMD_TXMSBF; 220 reg_val &= ~SPI_CMD_RXMSBF; 221 } else { 222 reg_val |= SPI_CMD_TXMSBF; 223 reg_val |= SPI_CMD_RXMSBF; 224 } 225 226 /* set the tx/rx endian */ 227 #ifdef __LITTLE_ENDIAN 228 reg_val &= ~SPI_CMD_TX_ENDIAN; 229 reg_val &= ~SPI_CMD_RX_ENDIAN; 230 #else 231 reg_val |= SPI_CMD_TX_ENDIAN; 232 reg_val |= SPI_CMD_RX_ENDIAN; 233 #endif 234 235 if (mdata->dev_comp->enhance_timing) { 236 /* set CS polarity */ 237 if (spi->mode & SPI_CS_HIGH) 238 reg_val |= SPI_CMD_CS_POL; 239 else 240 reg_val &= ~SPI_CMD_CS_POL; 241 242 if (chip_config->sample_sel) 243 reg_val |= SPI_CMD_SAMPLE_SEL; 244 else 245 reg_val &= ~SPI_CMD_SAMPLE_SEL; 246 } 247 248 /* set finish and pause interrupt always enable */ 249 reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE; 250 251 /* disable dma mode */ 252 reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA); 253 254 /* disable deassert mode */ 255 reg_val &= ~SPI_CMD_DEASSERT; 256 257 writel(reg_val, mdata->base + SPI_CMD_REG); 258 259 /* pad select */ 260 if (mdata->dev_comp->need_pad_sel) 261 writel(mdata->pad_sel[spi->chip_select], 262 mdata->base + SPI_PAD_SEL_REG); 263 264 return 0; 265 } 266 267 static void mtk_spi_set_cs(struct spi_device *spi, bool enable) 268 { 269 u32 reg_val; 270 struct mtk_spi *mdata = spi_master_get_devdata(spi->master); 271 272 if (spi->mode & SPI_CS_HIGH) 273 enable = !enable; 274 275 reg_val = readl(mdata->base + SPI_CMD_REG); 276 if (!enable) { 277 reg_val |= SPI_CMD_PAUSE_EN; 278 writel(reg_val, mdata->base + SPI_CMD_REG); 279 } else { 280 reg_val &= ~SPI_CMD_PAUSE_EN; 281 writel(reg_val, mdata->base + SPI_CMD_REG); 282 mdata->state = MTK_SPI_IDLE; 283 mtk_spi_reset(mdata); 284 } 285 } 286 287 static void mtk_spi_prepare_transfer(struct spi_master *master, 288 struct spi_transfer *xfer) 289 { 290 u32 spi_clk_hz, div, sck_time, reg_val; 291 struct mtk_spi *mdata = spi_master_get_devdata(master); 292 293 spi_clk_hz = clk_get_rate(mdata->spi_clk); 294 if (xfer->speed_hz < spi_clk_hz / 2) 295 div = DIV_ROUND_UP(spi_clk_hz, xfer->speed_hz); 296 else 297 div = 1; 298 299 sck_time = (div + 1) / 2; 300 301 if (mdata->dev_comp->enhance_timing) { 302 reg_val = readl(mdata->base + SPI_CFG2_REG); 303 reg_val &= ~(0xffff << SPI_CFG2_SCK_HIGH_OFFSET); 304 reg_val |= (((sck_time - 1) & 0xffff) 305 << SPI_CFG2_SCK_HIGH_OFFSET); 306 reg_val &= ~(0xffff << SPI_CFG2_SCK_LOW_OFFSET); 307 reg_val |= (((sck_time - 1) & 0xffff) 308 << SPI_CFG2_SCK_LOW_OFFSET); 309 writel(reg_val, mdata->base + SPI_CFG2_REG); 310 } else { 311 reg_val = readl(mdata->base + SPI_CFG0_REG); 312 reg_val &= ~(0xff << SPI_CFG0_SCK_HIGH_OFFSET); 313 reg_val |= (((sck_time - 1) & 0xff) 314 << SPI_CFG0_SCK_HIGH_OFFSET); 315 reg_val &= ~(0xff << SPI_CFG0_SCK_LOW_OFFSET); 316 reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET); 317 writel(reg_val, mdata->base + SPI_CFG0_REG); 318 } 319 } 320 321 static void mtk_spi_setup_packet(struct spi_master *master) 322 { 323 u32 packet_size, packet_loop, reg_val; 324 struct mtk_spi *mdata = spi_master_get_devdata(master); 325 326 packet_size = min_t(u32, mdata->xfer_len, MTK_SPI_PACKET_SIZE); 327 packet_loop = mdata->xfer_len / packet_size; 328 329 reg_val = readl(mdata->base + SPI_CFG1_REG); 330 reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK); 331 reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET; 332 reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET; 333 writel(reg_val, mdata->base + SPI_CFG1_REG); 334 } 335 336 static void mtk_spi_enable_transfer(struct spi_master *master) 337 { 338 u32 cmd; 339 struct mtk_spi *mdata = spi_master_get_devdata(master); 340 341 cmd = readl(mdata->base + SPI_CMD_REG); 342 if (mdata->state == MTK_SPI_IDLE) 343 cmd |= SPI_CMD_ACT; 344 else 345 cmd |= SPI_CMD_RESUME; 346 writel(cmd, mdata->base + SPI_CMD_REG); 347 } 348 349 static int mtk_spi_get_mult_delta(u32 xfer_len) 350 { 351 u32 mult_delta; 352 353 if (xfer_len > MTK_SPI_PACKET_SIZE) 354 mult_delta = xfer_len % MTK_SPI_PACKET_SIZE; 355 else 356 mult_delta = 0; 357 358 return mult_delta; 359 } 360 361 static void mtk_spi_update_mdata_len(struct spi_master *master) 362 { 363 int mult_delta; 364 struct mtk_spi *mdata = spi_master_get_devdata(master); 365 366 if (mdata->tx_sgl_len && mdata->rx_sgl_len) { 367 if (mdata->tx_sgl_len > mdata->rx_sgl_len) { 368 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len); 369 mdata->xfer_len = mdata->rx_sgl_len - mult_delta; 370 mdata->rx_sgl_len = mult_delta; 371 mdata->tx_sgl_len -= mdata->xfer_len; 372 } else { 373 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len); 374 mdata->xfer_len = mdata->tx_sgl_len - mult_delta; 375 mdata->tx_sgl_len = mult_delta; 376 mdata->rx_sgl_len -= mdata->xfer_len; 377 } 378 } else if (mdata->tx_sgl_len) { 379 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len); 380 mdata->xfer_len = mdata->tx_sgl_len - mult_delta; 381 mdata->tx_sgl_len = mult_delta; 382 } else if (mdata->rx_sgl_len) { 383 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len); 384 mdata->xfer_len = mdata->rx_sgl_len - mult_delta; 385 mdata->rx_sgl_len = mult_delta; 386 } 387 } 388 389 static void mtk_spi_setup_dma_addr(struct spi_master *master, 390 struct spi_transfer *xfer) 391 { 392 struct mtk_spi *mdata = spi_master_get_devdata(master); 393 394 if (mdata->tx_sgl) { 395 writel((u32)(xfer->tx_dma & MTK_SPI_32BITS_MASK), 396 mdata->base + SPI_TX_SRC_REG); 397 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 398 if (mdata->dev_comp->dma_ext) 399 writel((u32)(xfer->tx_dma >> 32), 400 mdata->base + SPI_TX_SRC_REG_64); 401 #endif 402 } 403 404 if (mdata->rx_sgl) { 405 writel((u32)(xfer->rx_dma & MTK_SPI_32BITS_MASK), 406 mdata->base + SPI_RX_DST_REG); 407 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 408 if (mdata->dev_comp->dma_ext) 409 writel((u32)(xfer->rx_dma >> 32), 410 mdata->base + SPI_RX_DST_REG_64); 411 #endif 412 } 413 } 414 415 static int mtk_spi_fifo_transfer(struct spi_master *master, 416 struct spi_device *spi, 417 struct spi_transfer *xfer) 418 { 419 int cnt, remainder; 420 u32 reg_val; 421 struct mtk_spi *mdata = spi_master_get_devdata(master); 422 423 mdata->cur_transfer = xfer; 424 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len); 425 mdata->num_xfered = 0; 426 mtk_spi_prepare_transfer(master, xfer); 427 mtk_spi_setup_packet(master); 428 429 if (xfer->tx_buf) { 430 cnt = xfer->len / 4; 431 iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt); 432 remainder = xfer->len % 4; 433 if (remainder > 0) { 434 reg_val = 0; 435 memcpy(®_val, xfer->tx_buf + (cnt * 4), remainder); 436 writel(reg_val, mdata->base + SPI_TX_DATA_REG); 437 } 438 } 439 440 mtk_spi_enable_transfer(master); 441 442 return 1; 443 } 444 445 static int mtk_spi_dma_transfer(struct spi_master *master, 446 struct spi_device *spi, 447 struct spi_transfer *xfer) 448 { 449 int cmd; 450 struct mtk_spi *mdata = spi_master_get_devdata(master); 451 452 mdata->tx_sgl = NULL; 453 mdata->rx_sgl = NULL; 454 mdata->tx_sgl_len = 0; 455 mdata->rx_sgl_len = 0; 456 mdata->cur_transfer = xfer; 457 mdata->num_xfered = 0; 458 459 mtk_spi_prepare_transfer(master, xfer); 460 461 cmd = readl(mdata->base + SPI_CMD_REG); 462 if (xfer->tx_buf) 463 cmd |= SPI_CMD_TX_DMA; 464 if (xfer->rx_buf) 465 cmd |= SPI_CMD_RX_DMA; 466 writel(cmd, mdata->base + SPI_CMD_REG); 467 468 if (xfer->tx_buf) 469 mdata->tx_sgl = xfer->tx_sg.sgl; 470 if (xfer->rx_buf) 471 mdata->rx_sgl = xfer->rx_sg.sgl; 472 473 if (mdata->tx_sgl) { 474 xfer->tx_dma = sg_dma_address(mdata->tx_sgl); 475 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl); 476 } 477 if (mdata->rx_sgl) { 478 xfer->rx_dma = sg_dma_address(mdata->rx_sgl); 479 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl); 480 } 481 482 mtk_spi_update_mdata_len(master); 483 mtk_spi_setup_packet(master); 484 mtk_spi_setup_dma_addr(master, xfer); 485 mtk_spi_enable_transfer(master); 486 487 return 1; 488 } 489 490 static int mtk_spi_transfer_one(struct spi_master *master, 491 struct spi_device *spi, 492 struct spi_transfer *xfer) 493 { 494 if (master->can_dma(master, spi, xfer)) 495 return mtk_spi_dma_transfer(master, spi, xfer); 496 else 497 return mtk_spi_fifo_transfer(master, spi, xfer); 498 } 499 500 static bool mtk_spi_can_dma(struct spi_master *master, 501 struct spi_device *spi, 502 struct spi_transfer *xfer) 503 { 504 /* Buffers for DMA transactions must be 4-byte aligned */ 505 return (xfer->len > MTK_SPI_MAX_FIFO_SIZE && 506 (unsigned long)xfer->tx_buf % 4 == 0 && 507 (unsigned long)xfer->rx_buf % 4 == 0); 508 } 509 510 static int mtk_spi_set_hw_cs_timing(struct spi_device *spi, 511 struct spi_delay *setup, 512 struct spi_delay *hold, 513 struct spi_delay *inactive) 514 { 515 struct mtk_spi *mdata = spi_master_get_devdata(spi->master); 516 u16 setup_dly, hold_dly, inactive_dly; 517 u32 reg_val; 518 519 if ((setup && setup->unit != SPI_DELAY_UNIT_SCK) || 520 (hold && hold->unit != SPI_DELAY_UNIT_SCK) || 521 (inactive && inactive->unit != SPI_DELAY_UNIT_SCK)) { 522 dev_err(&spi->dev, 523 "Invalid delay unit, should be SPI_DELAY_UNIT_SCK\n"); 524 return -EINVAL; 525 } 526 527 setup_dly = setup ? setup->value : 1; 528 hold_dly = hold ? hold->value : 1; 529 inactive_dly = inactive ? inactive->value : 1; 530 531 reg_val = readl(mdata->base + SPI_CFG0_REG); 532 if (mdata->dev_comp->enhance_timing) { 533 reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_HOLD_OFFSET); 534 reg_val |= (((hold_dly - 1) & 0xffff) 535 << SPI_ADJUST_CFG0_CS_HOLD_OFFSET); 536 reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_SETUP_OFFSET); 537 reg_val |= (((setup_dly - 1) & 0xffff) 538 << SPI_ADJUST_CFG0_CS_SETUP_OFFSET); 539 } else { 540 reg_val &= ~(0xff << SPI_CFG0_CS_HOLD_OFFSET); 541 reg_val |= (((hold_dly - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET); 542 reg_val &= ~(0xff << SPI_CFG0_CS_SETUP_OFFSET); 543 reg_val |= (((setup_dly - 1) & 0xff) 544 << SPI_CFG0_CS_SETUP_OFFSET); 545 } 546 writel(reg_val, mdata->base + SPI_CFG0_REG); 547 548 reg_val = readl(mdata->base + SPI_CFG1_REG); 549 reg_val &= ~SPI_CFG1_CS_IDLE_MASK; 550 reg_val |= (((inactive_dly - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET); 551 writel(reg_val, mdata->base + SPI_CFG1_REG); 552 553 return 0; 554 } 555 556 static int mtk_spi_setup(struct spi_device *spi) 557 { 558 struct mtk_spi *mdata = spi_master_get_devdata(spi->master); 559 560 if (!spi->controller_data) 561 spi->controller_data = (void *)&mtk_default_chip_info; 562 563 if (mdata->dev_comp->need_pad_sel && gpio_is_valid(spi->cs_gpio)) 564 gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); 565 566 return 0; 567 } 568 569 static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id) 570 { 571 u32 cmd, reg_val, cnt, remainder, len; 572 struct spi_master *master = dev_id; 573 struct mtk_spi *mdata = spi_master_get_devdata(master); 574 struct spi_transfer *trans = mdata->cur_transfer; 575 576 reg_val = readl(mdata->base + SPI_STATUS0_REG); 577 if (reg_val & MTK_SPI_PAUSE_INT_STATUS) 578 mdata->state = MTK_SPI_PAUSED; 579 else 580 mdata->state = MTK_SPI_IDLE; 581 582 if (!master->can_dma(master, master->cur_msg->spi, trans)) { 583 if (trans->rx_buf) { 584 cnt = mdata->xfer_len / 4; 585 ioread32_rep(mdata->base + SPI_RX_DATA_REG, 586 trans->rx_buf + mdata->num_xfered, cnt); 587 remainder = mdata->xfer_len % 4; 588 if (remainder > 0) { 589 reg_val = readl(mdata->base + SPI_RX_DATA_REG); 590 memcpy(trans->rx_buf + 591 mdata->num_xfered + 592 (cnt * 4), 593 ®_val, 594 remainder); 595 } 596 } 597 598 mdata->num_xfered += mdata->xfer_len; 599 if (mdata->num_xfered == trans->len) { 600 spi_finalize_current_transfer(master); 601 return IRQ_HANDLED; 602 } 603 604 len = trans->len - mdata->num_xfered; 605 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, len); 606 mtk_spi_setup_packet(master); 607 608 cnt = mdata->xfer_len / 4; 609 iowrite32_rep(mdata->base + SPI_TX_DATA_REG, 610 trans->tx_buf + mdata->num_xfered, cnt); 611 612 remainder = mdata->xfer_len % 4; 613 if (remainder > 0) { 614 reg_val = 0; 615 memcpy(®_val, 616 trans->tx_buf + (cnt * 4) + mdata->num_xfered, 617 remainder); 618 writel(reg_val, mdata->base + SPI_TX_DATA_REG); 619 } 620 621 mtk_spi_enable_transfer(master); 622 623 return IRQ_HANDLED; 624 } 625 626 if (mdata->tx_sgl) 627 trans->tx_dma += mdata->xfer_len; 628 if (mdata->rx_sgl) 629 trans->rx_dma += mdata->xfer_len; 630 631 if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) { 632 mdata->tx_sgl = sg_next(mdata->tx_sgl); 633 if (mdata->tx_sgl) { 634 trans->tx_dma = sg_dma_address(mdata->tx_sgl); 635 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl); 636 } 637 } 638 if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) { 639 mdata->rx_sgl = sg_next(mdata->rx_sgl); 640 if (mdata->rx_sgl) { 641 trans->rx_dma = sg_dma_address(mdata->rx_sgl); 642 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl); 643 } 644 } 645 646 if (!mdata->tx_sgl && !mdata->rx_sgl) { 647 /* spi disable dma */ 648 cmd = readl(mdata->base + SPI_CMD_REG); 649 cmd &= ~SPI_CMD_TX_DMA; 650 cmd &= ~SPI_CMD_RX_DMA; 651 writel(cmd, mdata->base + SPI_CMD_REG); 652 653 spi_finalize_current_transfer(master); 654 return IRQ_HANDLED; 655 } 656 657 mtk_spi_update_mdata_len(master); 658 mtk_spi_setup_packet(master); 659 mtk_spi_setup_dma_addr(master, trans); 660 mtk_spi_enable_transfer(master); 661 662 return IRQ_HANDLED; 663 } 664 665 static int mtk_spi_probe(struct platform_device *pdev) 666 { 667 struct spi_master *master; 668 struct mtk_spi *mdata; 669 const struct of_device_id *of_id; 670 int i, irq, ret, addr_bits; 671 672 master = spi_alloc_master(&pdev->dev, sizeof(*mdata)); 673 if (!master) { 674 dev_err(&pdev->dev, "failed to alloc spi master\n"); 675 return -ENOMEM; 676 } 677 678 master->auto_runtime_pm = true; 679 master->dev.of_node = pdev->dev.of_node; 680 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; 681 682 master->set_cs = mtk_spi_set_cs; 683 master->prepare_message = mtk_spi_prepare_message; 684 master->transfer_one = mtk_spi_transfer_one; 685 master->can_dma = mtk_spi_can_dma; 686 master->setup = mtk_spi_setup; 687 master->set_cs_timing = mtk_spi_set_hw_cs_timing; 688 689 of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node); 690 if (!of_id) { 691 dev_err(&pdev->dev, "failed to probe of_node\n"); 692 ret = -EINVAL; 693 goto err_put_master; 694 } 695 696 mdata = spi_master_get_devdata(master); 697 mdata->dev_comp = of_id->data; 698 699 if (mdata->dev_comp->enhance_timing) 700 master->mode_bits |= SPI_CS_HIGH; 701 702 if (mdata->dev_comp->must_tx) 703 master->flags = SPI_MASTER_MUST_TX; 704 705 if (mdata->dev_comp->need_pad_sel) { 706 mdata->pad_num = of_property_count_u32_elems( 707 pdev->dev.of_node, 708 "mediatek,pad-select"); 709 if (mdata->pad_num < 0) { 710 dev_err(&pdev->dev, 711 "No 'mediatek,pad-select' property\n"); 712 ret = -EINVAL; 713 goto err_put_master; 714 } 715 716 mdata->pad_sel = devm_kmalloc_array(&pdev->dev, mdata->pad_num, 717 sizeof(u32), GFP_KERNEL); 718 if (!mdata->pad_sel) { 719 ret = -ENOMEM; 720 goto err_put_master; 721 } 722 723 for (i = 0; i < mdata->pad_num; i++) { 724 of_property_read_u32_index(pdev->dev.of_node, 725 "mediatek,pad-select", 726 i, &mdata->pad_sel[i]); 727 if (mdata->pad_sel[i] > MT8173_SPI_MAX_PAD_SEL) { 728 dev_err(&pdev->dev, "wrong pad-sel[%d]: %u\n", 729 i, mdata->pad_sel[i]); 730 ret = -EINVAL; 731 goto err_put_master; 732 } 733 } 734 } 735 736 platform_set_drvdata(pdev, master); 737 mdata->base = devm_platform_ioremap_resource(pdev, 0); 738 if (IS_ERR(mdata->base)) { 739 ret = PTR_ERR(mdata->base); 740 goto err_put_master; 741 } 742 743 irq = platform_get_irq(pdev, 0); 744 if (irq < 0) { 745 ret = irq; 746 goto err_put_master; 747 } 748 749 if (!pdev->dev.dma_mask) 750 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; 751 752 ret = devm_request_irq(&pdev->dev, irq, mtk_spi_interrupt, 753 IRQF_TRIGGER_NONE, dev_name(&pdev->dev), master); 754 if (ret) { 755 dev_err(&pdev->dev, "failed to register irq (%d)\n", ret); 756 goto err_put_master; 757 } 758 759 mdata->parent_clk = devm_clk_get(&pdev->dev, "parent-clk"); 760 if (IS_ERR(mdata->parent_clk)) { 761 ret = PTR_ERR(mdata->parent_clk); 762 dev_err(&pdev->dev, "failed to get parent-clk: %d\n", ret); 763 goto err_put_master; 764 } 765 766 mdata->sel_clk = devm_clk_get(&pdev->dev, "sel-clk"); 767 if (IS_ERR(mdata->sel_clk)) { 768 ret = PTR_ERR(mdata->sel_clk); 769 dev_err(&pdev->dev, "failed to get sel-clk: %d\n", ret); 770 goto err_put_master; 771 } 772 773 mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk"); 774 if (IS_ERR(mdata->spi_clk)) { 775 ret = PTR_ERR(mdata->spi_clk); 776 dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret); 777 goto err_put_master; 778 } 779 780 ret = clk_prepare_enable(mdata->spi_clk); 781 if (ret < 0) { 782 dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret); 783 goto err_put_master; 784 } 785 786 ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk); 787 if (ret < 0) { 788 dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret); 789 clk_disable_unprepare(mdata->spi_clk); 790 goto err_put_master; 791 } 792 793 clk_disable_unprepare(mdata->spi_clk); 794 795 pm_runtime_enable(&pdev->dev); 796 797 if (mdata->dev_comp->need_pad_sel) { 798 if (mdata->pad_num != master->num_chipselect) { 799 dev_err(&pdev->dev, 800 "pad_num does not match num_chipselect(%d != %d)\n", 801 mdata->pad_num, master->num_chipselect); 802 ret = -EINVAL; 803 goto err_disable_runtime_pm; 804 } 805 806 if (!master->cs_gpios && master->num_chipselect > 1) { 807 dev_err(&pdev->dev, 808 "cs_gpios not specified and num_chipselect > 1\n"); 809 ret = -EINVAL; 810 goto err_disable_runtime_pm; 811 } 812 813 if (master->cs_gpios) { 814 for (i = 0; i < master->num_chipselect; i++) { 815 ret = devm_gpio_request(&pdev->dev, 816 master->cs_gpios[i], 817 dev_name(&pdev->dev)); 818 if (ret) { 819 dev_err(&pdev->dev, 820 "can't get CS GPIO %i\n", i); 821 goto err_disable_runtime_pm; 822 } 823 } 824 } 825 } 826 827 if (mdata->dev_comp->dma_ext) 828 addr_bits = DMA_ADDR_EXT_BITS; 829 else 830 addr_bits = DMA_ADDR_DEF_BITS; 831 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(addr_bits)); 832 if (ret) 833 dev_notice(&pdev->dev, "SPI dma_set_mask(%d) failed, ret:%d\n", 834 addr_bits, ret); 835 836 ret = devm_spi_register_master(&pdev->dev, master); 837 if (ret) { 838 dev_err(&pdev->dev, "failed to register master (%d)\n", ret); 839 goto err_disable_runtime_pm; 840 } 841 842 return 0; 843 844 err_disable_runtime_pm: 845 pm_runtime_disable(&pdev->dev); 846 err_put_master: 847 spi_master_put(master); 848 849 return ret; 850 } 851 852 static int mtk_spi_remove(struct platform_device *pdev) 853 { 854 struct spi_master *master = platform_get_drvdata(pdev); 855 struct mtk_spi *mdata = spi_master_get_devdata(master); 856 857 pm_runtime_disable(&pdev->dev); 858 859 mtk_spi_reset(mdata); 860 861 return 0; 862 } 863 864 #ifdef CONFIG_PM_SLEEP 865 static int mtk_spi_suspend(struct device *dev) 866 { 867 int ret; 868 struct spi_master *master = dev_get_drvdata(dev); 869 struct mtk_spi *mdata = spi_master_get_devdata(master); 870 871 ret = spi_master_suspend(master); 872 if (ret) 873 return ret; 874 875 if (!pm_runtime_suspended(dev)) 876 clk_disable_unprepare(mdata->spi_clk); 877 878 return ret; 879 } 880 881 static int mtk_spi_resume(struct device *dev) 882 { 883 int ret; 884 struct spi_master *master = dev_get_drvdata(dev); 885 struct mtk_spi *mdata = spi_master_get_devdata(master); 886 887 if (!pm_runtime_suspended(dev)) { 888 ret = clk_prepare_enable(mdata->spi_clk); 889 if (ret < 0) { 890 dev_err(dev, "failed to enable spi_clk (%d)\n", ret); 891 return ret; 892 } 893 } 894 895 ret = spi_master_resume(master); 896 if (ret < 0) 897 clk_disable_unprepare(mdata->spi_clk); 898 899 return ret; 900 } 901 #endif /* CONFIG_PM_SLEEP */ 902 903 #ifdef CONFIG_PM 904 static int mtk_spi_runtime_suspend(struct device *dev) 905 { 906 struct spi_master *master = dev_get_drvdata(dev); 907 struct mtk_spi *mdata = spi_master_get_devdata(master); 908 909 clk_disable_unprepare(mdata->spi_clk); 910 911 return 0; 912 } 913 914 static int mtk_spi_runtime_resume(struct device *dev) 915 { 916 struct spi_master *master = dev_get_drvdata(dev); 917 struct mtk_spi *mdata = spi_master_get_devdata(master); 918 int ret; 919 920 ret = clk_prepare_enable(mdata->spi_clk); 921 if (ret < 0) { 922 dev_err(dev, "failed to enable spi_clk (%d)\n", ret); 923 return ret; 924 } 925 926 return 0; 927 } 928 #endif /* CONFIG_PM */ 929 930 static const struct dev_pm_ops mtk_spi_pm = { 931 SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend, mtk_spi_resume) 932 SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend, 933 mtk_spi_runtime_resume, NULL) 934 }; 935 936 static struct platform_driver mtk_spi_driver = { 937 .driver = { 938 .name = "mtk-spi", 939 .pm = &mtk_spi_pm, 940 .of_match_table = mtk_spi_of_match, 941 }, 942 .probe = mtk_spi_probe, 943 .remove = mtk_spi_remove, 944 }; 945 946 module_platform_driver(mtk_spi_driver); 947 948 MODULE_DESCRIPTION("MTK SPI Controller driver"); 949 MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>"); 950 MODULE_LICENSE("GPL v2"); 951 MODULE_ALIAS("platform:mtk-spi"); 952