1 /* 2 * Copyright (c) 2015 MediaTek Inc. 3 * Author: Leilk Liu <leilk.liu@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/device.h> 17 #include <linux/err.h> 18 #include <linux/interrupt.h> 19 #include <linux/io.h> 20 #include <linux/ioport.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/platform_device.h> 24 #include <linux/platform_data/spi-mt65xx.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/spi/spi.h> 27 28 #define SPI_CFG0_REG 0x0000 29 #define SPI_CFG1_REG 0x0004 30 #define SPI_TX_SRC_REG 0x0008 31 #define SPI_RX_DST_REG 0x000c 32 #define SPI_TX_DATA_REG 0x0010 33 #define SPI_RX_DATA_REG 0x0014 34 #define SPI_CMD_REG 0x0018 35 #define SPI_STATUS0_REG 0x001c 36 #define SPI_PAD_SEL_REG 0x0024 37 38 #define SPI_CFG0_SCK_HIGH_OFFSET 0 39 #define SPI_CFG0_SCK_LOW_OFFSET 8 40 #define SPI_CFG0_CS_HOLD_OFFSET 16 41 #define SPI_CFG0_CS_SETUP_OFFSET 24 42 43 #define SPI_CFG1_CS_IDLE_OFFSET 0 44 #define SPI_CFG1_PACKET_LOOP_OFFSET 8 45 #define SPI_CFG1_PACKET_LENGTH_OFFSET 16 46 #define SPI_CFG1_GET_TICK_DLY_OFFSET 30 47 48 #define SPI_CFG1_CS_IDLE_MASK 0xff 49 #define SPI_CFG1_PACKET_LOOP_MASK 0xff00 50 #define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000 51 52 #define SPI_CMD_ACT BIT(0) 53 #define SPI_CMD_RESUME BIT(1) 54 #define SPI_CMD_RST BIT(2) 55 #define SPI_CMD_PAUSE_EN BIT(4) 56 #define SPI_CMD_DEASSERT BIT(5) 57 #define SPI_CMD_CPHA BIT(8) 58 #define SPI_CMD_CPOL BIT(9) 59 #define SPI_CMD_RX_DMA BIT(10) 60 #define SPI_CMD_TX_DMA BIT(11) 61 #define SPI_CMD_TXMSBF BIT(12) 62 #define SPI_CMD_RXMSBF BIT(13) 63 #define SPI_CMD_RX_ENDIAN BIT(14) 64 #define SPI_CMD_TX_ENDIAN BIT(15) 65 #define SPI_CMD_FINISH_IE BIT(16) 66 #define SPI_CMD_PAUSE_IE BIT(17) 67 68 #define MT8173_SPI_MAX_PAD_SEL 3 69 70 #define MTK_SPI_PAUSE_INT_STATUS 0x2 71 72 #define MTK_SPI_IDLE 0 73 #define MTK_SPI_PAUSED 1 74 75 #define MTK_SPI_MAX_FIFO_SIZE 32 76 #define MTK_SPI_PACKET_SIZE 1024 77 78 struct mtk_spi_compatible { 79 bool need_pad_sel; 80 /* Must explicitly send dummy Tx bytes to do Rx only transfer */ 81 bool must_tx; 82 }; 83 84 struct mtk_spi { 85 void __iomem *base; 86 u32 state; 87 u32 pad_sel; 88 struct clk *spi_clk, *parent_clk; 89 struct spi_transfer *cur_transfer; 90 u32 xfer_len; 91 struct scatterlist *tx_sgl, *rx_sgl; 92 u32 tx_sgl_len, rx_sgl_len; 93 const struct mtk_spi_compatible *dev_comp; 94 }; 95 96 static const struct mtk_spi_compatible mt6589_compat; 97 static const struct mtk_spi_compatible mt8135_compat; 98 static const struct mtk_spi_compatible mt8173_compat = { 99 .need_pad_sel = true, 100 .must_tx = true, 101 }; 102 103 /* 104 * A piece of default chip info unless the platform 105 * supplies it. 106 */ 107 static const struct mtk_chip_config mtk_default_chip_info = { 108 .rx_mlsb = 1, 109 .tx_mlsb = 1, 110 }; 111 112 static const struct of_device_id mtk_spi_of_match[] = { 113 { .compatible = "mediatek,mt6589-spi", .data = (void *)&mt6589_compat }, 114 { .compatible = "mediatek,mt8135-spi", .data = (void *)&mt8135_compat }, 115 { .compatible = "mediatek,mt8173-spi", .data = (void *)&mt8173_compat }, 116 {} 117 }; 118 MODULE_DEVICE_TABLE(of, mtk_spi_of_match); 119 120 static void mtk_spi_reset(struct mtk_spi *mdata) 121 { 122 u32 reg_val; 123 124 /* set the software reset bit in SPI_CMD_REG. */ 125 reg_val = readl(mdata->base + SPI_CMD_REG); 126 reg_val |= SPI_CMD_RST; 127 writel(reg_val, mdata->base + SPI_CMD_REG); 128 129 reg_val = readl(mdata->base + SPI_CMD_REG); 130 reg_val &= ~SPI_CMD_RST; 131 writel(reg_val, mdata->base + SPI_CMD_REG); 132 } 133 134 static void mtk_spi_config(struct mtk_spi *mdata, 135 struct mtk_chip_config *chip_config) 136 { 137 u32 reg_val; 138 139 reg_val = readl(mdata->base + SPI_CMD_REG); 140 141 /* set the mlsbx and mlsbtx */ 142 if (chip_config->tx_mlsb) 143 reg_val |= SPI_CMD_TXMSBF; 144 else 145 reg_val &= ~SPI_CMD_TXMSBF; 146 if (chip_config->rx_mlsb) 147 reg_val |= SPI_CMD_RXMSBF; 148 else 149 reg_val &= ~SPI_CMD_RXMSBF; 150 151 /* set the tx/rx endian */ 152 #ifdef __LITTLE_ENDIAN 153 reg_val &= ~SPI_CMD_TX_ENDIAN; 154 reg_val &= ~SPI_CMD_RX_ENDIAN; 155 #else 156 reg_val |= SPI_CMD_TX_ENDIAN; 157 reg_val |= SPI_CMD_RX_ENDIAN; 158 #endif 159 160 /* set finish and pause interrupt always enable */ 161 reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE; 162 163 /* disable dma mode */ 164 reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA); 165 166 /* disable deassert mode */ 167 reg_val &= ~SPI_CMD_DEASSERT; 168 169 writel(reg_val, mdata->base + SPI_CMD_REG); 170 171 /* pad select */ 172 if (mdata->dev_comp->need_pad_sel) 173 writel(mdata->pad_sel, mdata->base + SPI_PAD_SEL_REG); 174 } 175 176 static int mtk_spi_prepare_hardware(struct spi_master *master) 177 { 178 struct spi_transfer *trans; 179 struct mtk_spi *mdata = spi_master_get_devdata(master); 180 struct spi_message *msg = master->cur_msg; 181 182 trans = list_first_entry(&msg->transfers, struct spi_transfer, 183 transfer_list); 184 if (!trans->cs_change) { 185 mdata->state = MTK_SPI_IDLE; 186 mtk_spi_reset(mdata); 187 } 188 189 return 0; 190 } 191 192 static int mtk_spi_prepare_message(struct spi_master *master, 193 struct spi_message *msg) 194 { 195 u32 reg_val; 196 u8 cpha, cpol; 197 struct mtk_chip_config *chip_config; 198 struct spi_device *spi = msg->spi; 199 struct mtk_spi *mdata = spi_master_get_devdata(master); 200 201 cpha = spi->mode & SPI_CPHA ? 1 : 0; 202 cpol = spi->mode & SPI_CPOL ? 1 : 0; 203 204 reg_val = readl(mdata->base + SPI_CMD_REG); 205 if (cpha) 206 reg_val |= SPI_CMD_CPHA; 207 else 208 reg_val &= ~SPI_CMD_CPHA; 209 if (cpol) 210 reg_val |= SPI_CMD_CPOL; 211 else 212 reg_val &= ~SPI_CMD_CPOL; 213 writel(reg_val, mdata->base + SPI_CMD_REG); 214 215 chip_config = spi->controller_data; 216 if (!chip_config) { 217 chip_config = (void *)&mtk_default_chip_info; 218 spi->controller_data = chip_config; 219 } 220 mtk_spi_config(mdata, chip_config); 221 222 return 0; 223 } 224 225 static void mtk_spi_set_cs(struct spi_device *spi, bool enable) 226 { 227 u32 reg_val; 228 struct mtk_spi *mdata = spi_master_get_devdata(spi->master); 229 230 reg_val = readl(mdata->base + SPI_CMD_REG); 231 if (!enable) 232 reg_val |= SPI_CMD_PAUSE_EN; 233 else 234 reg_val &= ~SPI_CMD_PAUSE_EN; 235 writel(reg_val, mdata->base + SPI_CMD_REG); 236 } 237 238 static void mtk_spi_prepare_transfer(struct spi_master *master, 239 struct spi_transfer *xfer) 240 { 241 u32 spi_clk_hz, div, sck_time, cs_time, reg_val = 0; 242 struct mtk_spi *mdata = spi_master_get_devdata(master); 243 244 spi_clk_hz = clk_get_rate(mdata->spi_clk); 245 if (xfer->speed_hz < spi_clk_hz / 2) 246 div = DIV_ROUND_UP(spi_clk_hz, xfer->speed_hz); 247 else 248 div = 1; 249 250 sck_time = (div + 1) / 2; 251 cs_time = sck_time * 2; 252 253 reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_HIGH_OFFSET); 254 reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET); 255 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET); 256 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET); 257 writel(reg_val, mdata->base + SPI_CFG0_REG); 258 259 reg_val = readl(mdata->base + SPI_CFG1_REG); 260 reg_val &= ~SPI_CFG1_CS_IDLE_MASK; 261 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET); 262 writel(reg_val, mdata->base + SPI_CFG1_REG); 263 } 264 265 static void mtk_spi_setup_packet(struct spi_master *master) 266 { 267 u32 packet_size, packet_loop, reg_val; 268 struct mtk_spi *mdata = spi_master_get_devdata(master); 269 270 packet_size = min_t(u32, mdata->xfer_len, MTK_SPI_PACKET_SIZE); 271 packet_loop = mdata->xfer_len / packet_size; 272 273 reg_val = readl(mdata->base + SPI_CFG1_REG); 274 reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK); 275 reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET; 276 reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET; 277 writel(reg_val, mdata->base + SPI_CFG1_REG); 278 } 279 280 static void mtk_spi_enable_transfer(struct spi_master *master) 281 { 282 u32 cmd; 283 struct mtk_spi *mdata = spi_master_get_devdata(master); 284 285 cmd = readl(mdata->base + SPI_CMD_REG); 286 if (mdata->state == MTK_SPI_IDLE) 287 cmd |= SPI_CMD_ACT; 288 else 289 cmd |= SPI_CMD_RESUME; 290 writel(cmd, mdata->base + SPI_CMD_REG); 291 } 292 293 static int mtk_spi_get_mult_delta(u32 xfer_len) 294 { 295 u32 mult_delta; 296 297 if (xfer_len > MTK_SPI_PACKET_SIZE) 298 mult_delta = xfer_len % MTK_SPI_PACKET_SIZE; 299 else 300 mult_delta = 0; 301 302 return mult_delta; 303 } 304 305 static void mtk_spi_update_mdata_len(struct spi_master *master) 306 { 307 int mult_delta; 308 struct mtk_spi *mdata = spi_master_get_devdata(master); 309 310 if (mdata->tx_sgl_len && mdata->rx_sgl_len) { 311 if (mdata->tx_sgl_len > mdata->rx_sgl_len) { 312 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len); 313 mdata->xfer_len = mdata->rx_sgl_len - mult_delta; 314 mdata->rx_sgl_len = mult_delta; 315 mdata->tx_sgl_len -= mdata->xfer_len; 316 } else { 317 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len); 318 mdata->xfer_len = mdata->tx_sgl_len - mult_delta; 319 mdata->tx_sgl_len = mult_delta; 320 mdata->rx_sgl_len -= mdata->xfer_len; 321 } 322 } else if (mdata->tx_sgl_len) { 323 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len); 324 mdata->xfer_len = mdata->tx_sgl_len - mult_delta; 325 mdata->tx_sgl_len = mult_delta; 326 } else if (mdata->rx_sgl_len) { 327 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len); 328 mdata->xfer_len = mdata->rx_sgl_len - mult_delta; 329 mdata->rx_sgl_len = mult_delta; 330 } 331 } 332 333 static void mtk_spi_setup_dma_addr(struct spi_master *master, 334 struct spi_transfer *xfer) 335 { 336 struct mtk_spi *mdata = spi_master_get_devdata(master); 337 338 if (mdata->tx_sgl) 339 writel(xfer->tx_dma, mdata->base + SPI_TX_SRC_REG); 340 if (mdata->rx_sgl) 341 writel(xfer->rx_dma, mdata->base + SPI_RX_DST_REG); 342 } 343 344 static int mtk_spi_fifo_transfer(struct spi_master *master, 345 struct spi_device *spi, 346 struct spi_transfer *xfer) 347 { 348 int cnt; 349 struct mtk_spi *mdata = spi_master_get_devdata(master); 350 351 mdata->cur_transfer = xfer; 352 mdata->xfer_len = xfer->len; 353 mtk_spi_prepare_transfer(master, xfer); 354 mtk_spi_setup_packet(master); 355 356 if (xfer->len % 4) 357 cnt = xfer->len / 4 + 1; 358 else 359 cnt = xfer->len / 4; 360 iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt); 361 362 mtk_spi_enable_transfer(master); 363 364 return 1; 365 } 366 367 static int mtk_spi_dma_transfer(struct spi_master *master, 368 struct spi_device *spi, 369 struct spi_transfer *xfer) 370 { 371 int cmd; 372 struct mtk_spi *mdata = spi_master_get_devdata(master); 373 374 mdata->tx_sgl = NULL; 375 mdata->rx_sgl = NULL; 376 mdata->tx_sgl_len = 0; 377 mdata->rx_sgl_len = 0; 378 mdata->cur_transfer = xfer; 379 380 mtk_spi_prepare_transfer(master, xfer); 381 382 cmd = readl(mdata->base + SPI_CMD_REG); 383 if (xfer->tx_buf) 384 cmd |= SPI_CMD_TX_DMA; 385 if (xfer->rx_buf) 386 cmd |= SPI_CMD_RX_DMA; 387 writel(cmd, mdata->base + SPI_CMD_REG); 388 389 if (xfer->tx_buf) 390 mdata->tx_sgl = xfer->tx_sg.sgl; 391 if (xfer->rx_buf) 392 mdata->rx_sgl = xfer->rx_sg.sgl; 393 394 if (mdata->tx_sgl) { 395 xfer->tx_dma = sg_dma_address(mdata->tx_sgl); 396 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl); 397 } 398 if (mdata->rx_sgl) { 399 xfer->rx_dma = sg_dma_address(mdata->rx_sgl); 400 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl); 401 } 402 403 mtk_spi_update_mdata_len(master); 404 mtk_spi_setup_packet(master); 405 mtk_spi_setup_dma_addr(master, xfer); 406 mtk_spi_enable_transfer(master); 407 408 return 1; 409 } 410 411 static int mtk_spi_transfer_one(struct spi_master *master, 412 struct spi_device *spi, 413 struct spi_transfer *xfer) 414 { 415 if (master->can_dma(master, spi, xfer)) 416 return mtk_spi_dma_transfer(master, spi, xfer); 417 else 418 return mtk_spi_fifo_transfer(master, spi, xfer); 419 } 420 421 static bool mtk_spi_can_dma(struct spi_master *master, 422 struct spi_device *spi, 423 struct spi_transfer *xfer) 424 { 425 return xfer->len > MTK_SPI_MAX_FIFO_SIZE; 426 } 427 428 static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id) 429 { 430 u32 cmd, reg_val, cnt; 431 struct spi_master *master = dev_id; 432 struct mtk_spi *mdata = spi_master_get_devdata(master); 433 struct spi_transfer *trans = mdata->cur_transfer; 434 435 reg_val = readl(mdata->base + SPI_STATUS0_REG); 436 if (reg_val & MTK_SPI_PAUSE_INT_STATUS) 437 mdata->state = MTK_SPI_PAUSED; 438 else 439 mdata->state = MTK_SPI_IDLE; 440 441 if (!master->can_dma(master, master->cur_msg->spi, trans)) { 442 if (trans->rx_buf) { 443 if (mdata->xfer_len % 4) 444 cnt = mdata->xfer_len / 4 + 1; 445 else 446 cnt = mdata->xfer_len / 4; 447 ioread32_rep(mdata->base + SPI_RX_DATA_REG, 448 trans->rx_buf, cnt); 449 } 450 spi_finalize_current_transfer(master); 451 return IRQ_HANDLED; 452 } 453 454 if (mdata->tx_sgl) 455 trans->tx_dma += mdata->xfer_len; 456 if (mdata->rx_sgl) 457 trans->rx_dma += mdata->xfer_len; 458 459 if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) { 460 mdata->tx_sgl = sg_next(mdata->tx_sgl); 461 if (mdata->tx_sgl) { 462 trans->tx_dma = sg_dma_address(mdata->tx_sgl); 463 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl); 464 } 465 } 466 if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) { 467 mdata->rx_sgl = sg_next(mdata->rx_sgl); 468 if (mdata->rx_sgl) { 469 trans->rx_dma = sg_dma_address(mdata->rx_sgl); 470 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl); 471 } 472 } 473 474 if (!mdata->tx_sgl && !mdata->rx_sgl) { 475 /* spi disable dma */ 476 cmd = readl(mdata->base + SPI_CMD_REG); 477 cmd &= ~SPI_CMD_TX_DMA; 478 cmd &= ~SPI_CMD_RX_DMA; 479 writel(cmd, mdata->base + SPI_CMD_REG); 480 481 spi_finalize_current_transfer(master); 482 return IRQ_HANDLED; 483 } 484 485 mtk_spi_update_mdata_len(master); 486 mtk_spi_setup_packet(master); 487 mtk_spi_setup_dma_addr(master, trans); 488 mtk_spi_enable_transfer(master); 489 490 return IRQ_HANDLED; 491 } 492 493 static int mtk_spi_probe(struct platform_device *pdev) 494 { 495 struct spi_master *master; 496 struct mtk_spi *mdata; 497 const struct of_device_id *of_id; 498 struct resource *res; 499 int irq, ret; 500 501 master = spi_alloc_master(&pdev->dev, sizeof(*mdata)); 502 if (!master) { 503 dev_err(&pdev->dev, "failed to alloc spi master\n"); 504 return -ENOMEM; 505 } 506 507 master->auto_runtime_pm = true; 508 master->dev.of_node = pdev->dev.of_node; 509 master->mode_bits = SPI_CPOL | SPI_CPHA; 510 511 master->set_cs = mtk_spi_set_cs; 512 master->prepare_transfer_hardware = mtk_spi_prepare_hardware; 513 master->prepare_message = mtk_spi_prepare_message; 514 master->transfer_one = mtk_spi_transfer_one; 515 master->can_dma = mtk_spi_can_dma; 516 517 of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node); 518 if (!of_id) { 519 dev_err(&pdev->dev, "failed to probe of_node\n"); 520 ret = -EINVAL; 521 goto err_put_master; 522 } 523 524 mdata = spi_master_get_devdata(master); 525 mdata->dev_comp = of_id->data; 526 if (mdata->dev_comp->must_tx) 527 master->flags = SPI_MASTER_MUST_TX; 528 529 if (mdata->dev_comp->need_pad_sel) { 530 ret = of_property_read_u32(pdev->dev.of_node, 531 "mediatek,pad-select", 532 &mdata->pad_sel); 533 if (ret) { 534 dev_err(&pdev->dev, "failed to read pad select: %d\n", 535 ret); 536 goto err_put_master; 537 } 538 539 if (mdata->pad_sel > MT8173_SPI_MAX_PAD_SEL) { 540 dev_err(&pdev->dev, "wrong pad-select: %u\n", 541 mdata->pad_sel); 542 ret = -EINVAL; 543 goto err_put_master; 544 } 545 } 546 547 platform_set_drvdata(pdev, master); 548 549 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 550 if (!res) { 551 ret = -ENODEV; 552 dev_err(&pdev->dev, "failed to determine base address\n"); 553 goto err_put_master; 554 } 555 556 mdata->base = devm_ioremap_resource(&pdev->dev, res); 557 if (IS_ERR(mdata->base)) { 558 ret = PTR_ERR(mdata->base); 559 goto err_put_master; 560 } 561 562 irq = platform_get_irq(pdev, 0); 563 if (irq < 0) { 564 dev_err(&pdev->dev, "failed to get irq (%d)\n", irq); 565 ret = irq; 566 goto err_put_master; 567 } 568 569 if (!pdev->dev.dma_mask) 570 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; 571 572 ret = devm_request_irq(&pdev->dev, irq, mtk_spi_interrupt, 573 IRQF_TRIGGER_NONE, dev_name(&pdev->dev), master); 574 if (ret) { 575 dev_err(&pdev->dev, "failed to register irq (%d)\n", ret); 576 goto err_put_master; 577 } 578 579 mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk"); 580 if (IS_ERR(mdata->spi_clk)) { 581 ret = PTR_ERR(mdata->spi_clk); 582 dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret); 583 goto err_put_master; 584 } 585 586 mdata->parent_clk = devm_clk_get(&pdev->dev, "parent-clk"); 587 if (IS_ERR(mdata->parent_clk)) { 588 ret = PTR_ERR(mdata->parent_clk); 589 dev_err(&pdev->dev, "failed to get parent-clk: %d\n", ret); 590 goto err_put_master; 591 } 592 593 ret = clk_prepare_enable(mdata->spi_clk); 594 if (ret < 0) { 595 dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret); 596 goto err_put_master; 597 } 598 599 ret = clk_set_parent(mdata->spi_clk, mdata->parent_clk); 600 if (ret < 0) { 601 dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret); 602 goto err_disable_clk; 603 } 604 605 clk_disable_unprepare(mdata->spi_clk); 606 607 pm_runtime_enable(&pdev->dev); 608 609 ret = devm_spi_register_master(&pdev->dev, master); 610 if (ret) { 611 dev_err(&pdev->dev, "failed to register master (%d)\n", ret); 612 goto err_put_master; 613 } 614 615 return 0; 616 617 err_disable_clk: 618 clk_disable_unprepare(mdata->spi_clk); 619 err_put_master: 620 spi_master_put(master); 621 622 return ret; 623 } 624 625 static int mtk_spi_remove(struct platform_device *pdev) 626 { 627 struct spi_master *master = platform_get_drvdata(pdev); 628 struct mtk_spi *mdata = spi_master_get_devdata(master); 629 630 pm_runtime_disable(&pdev->dev); 631 632 mtk_spi_reset(mdata); 633 clk_disable_unprepare(mdata->spi_clk); 634 spi_master_put(master); 635 636 return 0; 637 } 638 639 #ifdef CONFIG_PM_SLEEP 640 static int mtk_spi_suspend(struct device *dev) 641 { 642 int ret; 643 struct spi_master *master = dev_get_drvdata(dev); 644 struct mtk_spi *mdata = spi_master_get_devdata(master); 645 646 ret = spi_master_suspend(master); 647 if (ret) 648 return ret; 649 650 if (!pm_runtime_suspended(dev)) 651 clk_disable_unprepare(mdata->spi_clk); 652 653 return ret; 654 } 655 656 static int mtk_spi_resume(struct device *dev) 657 { 658 int ret; 659 struct spi_master *master = dev_get_drvdata(dev); 660 struct mtk_spi *mdata = spi_master_get_devdata(master); 661 662 if (!pm_runtime_suspended(dev)) { 663 ret = clk_prepare_enable(mdata->spi_clk); 664 if (ret < 0) { 665 dev_err(dev, "failed to enable spi_clk (%d)\n", ret); 666 return ret; 667 } 668 } 669 670 ret = spi_master_resume(master); 671 if (ret < 0) 672 clk_disable_unprepare(mdata->spi_clk); 673 674 return ret; 675 } 676 #endif /* CONFIG_PM_SLEEP */ 677 678 #ifdef CONFIG_PM 679 static int mtk_spi_runtime_suspend(struct device *dev) 680 { 681 struct spi_master *master = dev_get_drvdata(dev); 682 struct mtk_spi *mdata = spi_master_get_devdata(master); 683 684 clk_disable_unprepare(mdata->spi_clk); 685 686 return 0; 687 } 688 689 static int mtk_spi_runtime_resume(struct device *dev) 690 { 691 struct spi_master *master = dev_get_drvdata(dev); 692 struct mtk_spi *mdata = spi_master_get_devdata(master); 693 int ret; 694 695 ret = clk_prepare_enable(mdata->spi_clk); 696 if (ret < 0) { 697 dev_err(dev, "failed to enable spi_clk (%d)\n", ret); 698 return ret; 699 } 700 701 return 0; 702 } 703 #endif /* CONFIG_PM */ 704 705 static const struct dev_pm_ops mtk_spi_pm = { 706 SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend, mtk_spi_resume) 707 SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend, 708 mtk_spi_runtime_resume, NULL) 709 }; 710 711 static struct platform_driver mtk_spi_driver = { 712 .driver = { 713 .name = "mtk-spi", 714 .pm = &mtk_spi_pm, 715 .of_match_table = mtk_spi_of_match, 716 }, 717 .probe = mtk_spi_probe, 718 .remove = mtk_spi_remove, 719 }; 720 721 module_platform_driver(mtk_spi_driver); 722 723 MODULE_DESCRIPTION("MTK SPI Controller driver"); 724 MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>"); 725 MODULE_LICENSE("GPL v2"); 726 MODULE_ALIAS("platform:mtk-spi"); 727