1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * MPC52xx SPI bus driver. 4 * 5 * Copyright (C) 2008 Secret Lab Technologies Ltd. 6 * 7 * This is the driver for the MPC5200's dedicated SPI controller. 8 * 9 * Note: this driver does not support the MPC5200 PSC in SPI mode. For 10 * that driver see drivers/spi/mpc52xx_psc_spi.c 11 */ 12 13 #include <linux/module.h> 14 #include <linux/errno.h> 15 #include <linux/of_platform.h> 16 #include <linux/interrupt.h> 17 #include <linux/delay.h> 18 #include <linux/spi/spi.h> 19 #include <linux/io.h> 20 #include <linux/of_gpio.h> 21 #include <linux/slab.h> 22 #include <asm/time.h> 23 #include <asm/mpc52xx.h> 24 25 MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>"); 26 MODULE_DESCRIPTION("MPC52xx SPI (non-PSC) Driver"); 27 MODULE_LICENSE("GPL"); 28 29 /* Register offsets */ 30 #define SPI_CTRL1 0x00 31 #define SPI_CTRL1_SPIE (1 << 7) 32 #define SPI_CTRL1_SPE (1 << 6) 33 #define SPI_CTRL1_MSTR (1 << 4) 34 #define SPI_CTRL1_CPOL (1 << 3) 35 #define SPI_CTRL1_CPHA (1 << 2) 36 #define SPI_CTRL1_SSOE (1 << 1) 37 #define SPI_CTRL1_LSBFE (1 << 0) 38 39 #define SPI_CTRL2 0x01 40 #define SPI_BRR 0x04 41 42 #define SPI_STATUS 0x05 43 #define SPI_STATUS_SPIF (1 << 7) 44 #define SPI_STATUS_WCOL (1 << 6) 45 #define SPI_STATUS_MODF (1 << 4) 46 47 #define SPI_DATA 0x09 48 #define SPI_PORTDATA 0x0d 49 #define SPI_DATADIR 0x10 50 51 /* FSM state return values */ 52 #define FSM_STOP 0 /* Nothing more for the state machine to */ 53 /* do. If something interesting happens */ 54 /* then an IRQ will be received */ 55 #define FSM_POLL 1 /* need to poll for completion, an IRQ is */ 56 /* not expected */ 57 #define FSM_CONTINUE 2 /* Keep iterating the state machine */ 58 59 /* Driver internal data */ 60 struct mpc52xx_spi { 61 struct spi_master *master; 62 void __iomem *regs; 63 int irq0; /* MODF irq */ 64 int irq1; /* SPIF irq */ 65 unsigned int ipb_freq; 66 67 /* Statistics; not used now, but will be reintroduced for debugfs */ 68 int msg_count; 69 int wcol_count; 70 int wcol_ticks; 71 u32 wcol_tx_timestamp; 72 int modf_count; 73 int byte_count; 74 75 struct list_head queue; /* queue of pending messages */ 76 spinlock_t lock; 77 struct work_struct work; 78 79 /* Details of current transfer (length, and buffer pointers) */ 80 struct spi_message *message; /* current message */ 81 struct spi_transfer *transfer; /* current transfer */ 82 int (*state)(int irq, struct mpc52xx_spi *ms, u8 status, u8 data); 83 int len; 84 int timestamp; 85 u8 *rx_buf; 86 const u8 *tx_buf; 87 int cs_change; 88 int gpio_cs_count; 89 unsigned int *gpio_cs; 90 }; 91 92 /* 93 * CS control function 94 */ 95 static void mpc52xx_spi_chipsel(struct mpc52xx_spi *ms, int value) 96 { 97 int cs; 98 99 if (ms->gpio_cs_count > 0) { 100 cs = ms->message->spi->chip_select; 101 gpio_set_value(ms->gpio_cs[cs], value ? 0 : 1); 102 } else 103 out_8(ms->regs + SPI_PORTDATA, value ? 0 : 0x08); 104 } 105 106 /* 107 * Start a new transfer. This is called both by the idle state 108 * for the first transfer in a message, and by the wait state when the 109 * previous transfer in a message is complete. 110 */ 111 static void mpc52xx_spi_start_transfer(struct mpc52xx_spi *ms) 112 { 113 ms->rx_buf = ms->transfer->rx_buf; 114 ms->tx_buf = ms->transfer->tx_buf; 115 ms->len = ms->transfer->len; 116 117 /* Activate the chip select */ 118 if (ms->cs_change) 119 mpc52xx_spi_chipsel(ms, 1); 120 ms->cs_change = ms->transfer->cs_change; 121 122 /* Write out the first byte */ 123 ms->wcol_tx_timestamp = get_tbl(); 124 if (ms->tx_buf) 125 out_8(ms->regs + SPI_DATA, *ms->tx_buf++); 126 else 127 out_8(ms->regs + SPI_DATA, 0); 128 } 129 130 /* Forward declaration of state handlers */ 131 static int mpc52xx_spi_fsmstate_transfer(int irq, struct mpc52xx_spi *ms, 132 u8 status, u8 data); 133 static int mpc52xx_spi_fsmstate_wait(int irq, struct mpc52xx_spi *ms, 134 u8 status, u8 data); 135 136 /* 137 * IDLE state 138 * 139 * No transfers are in progress; if another transfer is pending then retrieve 140 * it and kick it off. Otherwise, stop processing the state machine 141 */ 142 static int 143 mpc52xx_spi_fsmstate_idle(int irq, struct mpc52xx_spi *ms, u8 status, u8 data) 144 { 145 struct spi_device *spi; 146 int spr, sppr; 147 u8 ctrl1; 148 149 if (status && (irq != NO_IRQ)) 150 dev_err(&ms->master->dev, "spurious irq, status=0x%.2x\n", 151 status); 152 153 /* Check if there is another transfer waiting. */ 154 if (list_empty(&ms->queue)) 155 return FSM_STOP; 156 157 /* get the head of the queue */ 158 ms->message = list_first_entry(&ms->queue, struct spi_message, queue); 159 list_del_init(&ms->message->queue); 160 161 /* Setup the controller parameters */ 162 ctrl1 = SPI_CTRL1_SPIE | SPI_CTRL1_SPE | SPI_CTRL1_MSTR; 163 spi = ms->message->spi; 164 if (spi->mode & SPI_CPHA) 165 ctrl1 |= SPI_CTRL1_CPHA; 166 if (spi->mode & SPI_CPOL) 167 ctrl1 |= SPI_CTRL1_CPOL; 168 if (spi->mode & SPI_LSB_FIRST) 169 ctrl1 |= SPI_CTRL1_LSBFE; 170 out_8(ms->regs + SPI_CTRL1, ctrl1); 171 172 /* Setup the controller speed */ 173 /* minimum divider is '2'. Also, add '1' to force rounding the 174 * divider up. */ 175 sppr = ((ms->ipb_freq / ms->message->spi->max_speed_hz) + 1) >> 1; 176 spr = 0; 177 if (sppr < 1) 178 sppr = 1; 179 while (((sppr - 1) & ~0x7) != 0) { 180 sppr = (sppr + 1) >> 1; /* add '1' to force rounding up */ 181 spr++; 182 } 183 sppr--; /* sppr quantity in register is offset by 1 */ 184 if (spr > 7) { 185 /* Don't overrun limits of SPI baudrate register */ 186 spr = 7; 187 sppr = 7; 188 } 189 out_8(ms->regs + SPI_BRR, sppr << 4 | spr); /* Set speed */ 190 191 ms->cs_change = 1; 192 ms->transfer = container_of(ms->message->transfers.next, 193 struct spi_transfer, transfer_list); 194 195 mpc52xx_spi_start_transfer(ms); 196 ms->state = mpc52xx_spi_fsmstate_transfer; 197 198 return FSM_CONTINUE; 199 } 200 201 /* 202 * TRANSFER state 203 * 204 * In the middle of a transfer. If the SPI core has completed processing 205 * a byte, then read out the received data and write out the next byte 206 * (unless this transfer is finished; in which case go on to the wait 207 * state) 208 */ 209 static int mpc52xx_spi_fsmstate_transfer(int irq, struct mpc52xx_spi *ms, 210 u8 status, u8 data) 211 { 212 if (!status) 213 return ms->irq0 ? FSM_STOP : FSM_POLL; 214 215 if (status & SPI_STATUS_WCOL) { 216 /* The SPI controller is stoopid. At slower speeds, it may 217 * raise the SPIF flag before the state machine is actually 218 * finished, which causes a collision (internal to the state 219 * machine only). The manual recommends inserting a delay 220 * between receiving the interrupt and sending the next byte, 221 * but it can also be worked around simply by retrying the 222 * transfer which is what we do here. */ 223 ms->wcol_count++; 224 ms->wcol_ticks += get_tbl() - ms->wcol_tx_timestamp; 225 ms->wcol_tx_timestamp = get_tbl(); 226 data = 0; 227 if (ms->tx_buf) 228 data = *(ms->tx_buf - 1); 229 out_8(ms->regs + SPI_DATA, data); /* try again */ 230 return FSM_CONTINUE; 231 } else if (status & SPI_STATUS_MODF) { 232 ms->modf_count++; 233 dev_err(&ms->master->dev, "mode fault\n"); 234 mpc52xx_spi_chipsel(ms, 0); 235 ms->message->status = -EIO; 236 if (ms->message->complete) 237 ms->message->complete(ms->message->context); 238 ms->state = mpc52xx_spi_fsmstate_idle; 239 return FSM_CONTINUE; 240 } 241 242 /* Read data out of the spi device */ 243 ms->byte_count++; 244 if (ms->rx_buf) 245 *ms->rx_buf++ = data; 246 247 /* Is the transfer complete? */ 248 ms->len--; 249 if (ms->len == 0) { 250 ms->timestamp = get_tbl(); 251 ms->timestamp += ms->transfer->delay_usecs * tb_ticks_per_usec; 252 ms->state = mpc52xx_spi_fsmstate_wait; 253 return FSM_CONTINUE; 254 } 255 256 /* Write out the next byte */ 257 ms->wcol_tx_timestamp = get_tbl(); 258 if (ms->tx_buf) 259 out_8(ms->regs + SPI_DATA, *ms->tx_buf++); 260 else 261 out_8(ms->regs + SPI_DATA, 0); 262 263 return FSM_CONTINUE; 264 } 265 266 /* 267 * WAIT state 268 * 269 * A transfer has completed; need to wait for the delay period to complete 270 * before starting the next transfer 271 */ 272 static int 273 mpc52xx_spi_fsmstate_wait(int irq, struct mpc52xx_spi *ms, u8 status, u8 data) 274 { 275 if (status && irq) 276 dev_err(&ms->master->dev, "spurious irq, status=0x%.2x\n", 277 status); 278 279 if (((int)get_tbl()) - ms->timestamp < 0) 280 return FSM_POLL; 281 282 ms->message->actual_length += ms->transfer->len; 283 284 /* Check if there is another transfer in this message. If there 285 * aren't then deactivate CS, notify sender, and drop back to idle 286 * to start the next message. */ 287 if (ms->transfer->transfer_list.next == &ms->message->transfers) { 288 ms->msg_count++; 289 mpc52xx_spi_chipsel(ms, 0); 290 ms->message->status = 0; 291 if (ms->message->complete) 292 ms->message->complete(ms->message->context); 293 ms->state = mpc52xx_spi_fsmstate_idle; 294 return FSM_CONTINUE; 295 } 296 297 /* There is another transfer; kick it off */ 298 299 if (ms->cs_change) 300 mpc52xx_spi_chipsel(ms, 0); 301 302 ms->transfer = container_of(ms->transfer->transfer_list.next, 303 struct spi_transfer, transfer_list); 304 mpc52xx_spi_start_transfer(ms); 305 ms->state = mpc52xx_spi_fsmstate_transfer; 306 return FSM_CONTINUE; 307 } 308 309 /** 310 * mpc52xx_spi_fsm_process - Finite State Machine iteration function 311 * @irq: irq number that triggered the FSM or 0 for polling 312 * @ms: pointer to mpc52xx_spi driver data 313 */ 314 static void mpc52xx_spi_fsm_process(int irq, struct mpc52xx_spi *ms) 315 { 316 int rc = FSM_CONTINUE; 317 u8 status, data; 318 319 while (rc == FSM_CONTINUE) { 320 /* Interrupt cleared by read of STATUS followed by 321 * read of DATA registers */ 322 status = in_8(ms->regs + SPI_STATUS); 323 data = in_8(ms->regs + SPI_DATA); 324 rc = ms->state(irq, ms, status, data); 325 } 326 327 if (rc == FSM_POLL) 328 schedule_work(&ms->work); 329 } 330 331 /** 332 * mpc52xx_spi_irq - IRQ handler 333 */ 334 static irqreturn_t mpc52xx_spi_irq(int irq, void *_ms) 335 { 336 struct mpc52xx_spi *ms = _ms; 337 spin_lock(&ms->lock); 338 mpc52xx_spi_fsm_process(irq, ms); 339 spin_unlock(&ms->lock); 340 return IRQ_HANDLED; 341 } 342 343 /** 344 * mpc52xx_spi_wq - Workqueue function for polling the state machine 345 */ 346 static void mpc52xx_spi_wq(struct work_struct *work) 347 { 348 struct mpc52xx_spi *ms = container_of(work, struct mpc52xx_spi, work); 349 unsigned long flags; 350 351 spin_lock_irqsave(&ms->lock, flags); 352 mpc52xx_spi_fsm_process(0, ms); 353 spin_unlock_irqrestore(&ms->lock, flags); 354 } 355 356 /* 357 * spi_master ops 358 */ 359 360 static int mpc52xx_spi_transfer(struct spi_device *spi, struct spi_message *m) 361 { 362 struct mpc52xx_spi *ms = spi_master_get_devdata(spi->master); 363 unsigned long flags; 364 365 m->actual_length = 0; 366 m->status = -EINPROGRESS; 367 368 spin_lock_irqsave(&ms->lock, flags); 369 list_add_tail(&m->queue, &ms->queue); 370 spin_unlock_irqrestore(&ms->lock, flags); 371 schedule_work(&ms->work); 372 373 return 0; 374 } 375 376 /* 377 * OF Platform Bus Binding 378 */ 379 static int mpc52xx_spi_probe(struct platform_device *op) 380 { 381 struct spi_master *master; 382 struct mpc52xx_spi *ms; 383 void __iomem *regs; 384 u8 ctrl1; 385 int rc, i = 0; 386 int gpio_cs; 387 388 /* MMIO registers */ 389 dev_dbg(&op->dev, "probing mpc5200 SPI device\n"); 390 regs = of_iomap(op->dev.of_node, 0); 391 if (!regs) 392 return -ENODEV; 393 394 /* initialize the device */ 395 ctrl1 = SPI_CTRL1_SPIE | SPI_CTRL1_SPE | SPI_CTRL1_MSTR; 396 out_8(regs + SPI_CTRL1, ctrl1); 397 out_8(regs + SPI_CTRL2, 0x0); 398 out_8(regs + SPI_DATADIR, 0xe); /* Set output pins */ 399 out_8(regs + SPI_PORTDATA, 0x8); /* Deassert /SS signal */ 400 401 /* Clear the status register and re-read it to check for a MODF 402 * failure. This driver cannot currently handle multiple masters 403 * on the SPI bus. This fault will also occur if the SPI signals 404 * are not connected to any pins (port_config setting) */ 405 in_8(regs + SPI_STATUS); 406 out_8(regs + SPI_CTRL1, ctrl1); 407 408 in_8(regs + SPI_DATA); 409 if (in_8(regs + SPI_STATUS) & SPI_STATUS_MODF) { 410 dev_err(&op->dev, "mode fault; is port_config correct?\n"); 411 rc = -EIO; 412 goto err_init; 413 } 414 415 dev_dbg(&op->dev, "allocating spi_master struct\n"); 416 master = spi_alloc_master(&op->dev, sizeof *ms); 417 if (!master) { 418 rc = -ENOMEM; 419 goto err_alloc; 420 } 421 422 master->transfer = mpc52xx_spi_transfer; 423 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; 424 master->bits_per_word_mask = SPI_BPW_MASK(8); 425 master->dev.of_node = op->dev.of_node; 426 427 platform_set_drvdata(op, master); 428 429 ms = spi_master_get_devdata(master); 430 ms->master = master; 431 ms->regs = regs; 432 ms->irq0 = irq_of_parse_and_map(op->dev.of_node, 0); 433 ms->irq1 = irq_of_parse_and_map(op->dev.of_node, 1); 434 ms->state = mpc52xx_spi_fsmstate_idle; 435 ms->ipb_freq = mpc5xxx_get_bus_frequency(op->dev.of_node); 436 ms->gpio_cs_count = of_gpio_count(op->dev.of_node); 437 if (ms->gpio_cs_count > 0) { 438 master->num_chipselect = ms->gpio_cs_count; 439 ms->gpio_cs = kmalloc_array(ms->gpio_cs_count, 440 sizeof(*ms->gpio_cs), 441 GFP_KERNEL); 442 if (!ms->gpio_cs) { 443 rc = -ENOMEM; 444 goto err_alloc_gpio; 445 } 446 447 for (i = 0; i < ms->gpio_cs_count; i++) { 448 gpio_cs = of_get_gpio(op->dev.of_node, i); 449 if (!gpio_is_valid(gpio_cs)) { 450 dev_err(&op->dev, 451 "could not parse the gpio field in oftree\n"); 452 rc = -ENODEV; 453 goto err_gpio; 454 } 455 456 rc = gpio_request(gpio_cs, dev_name(&op->dev)); 457 if (rc) { 458 dev_err(&op->dev, 459 "can't request spi cs gpio #%d on gpio line %d\n", 460 i, gpio_cs); 461 goto err_gpio; 462 } 463 464 gpio_direction_output(gpio_cs, 1); 465 ms->gpio_cs[i] = gpio_cs; 466 } 467 } 468 469 spin_lock_init(&ms->lock); 470 INIT_LIST_HEAD(&ms->queue); 471 INIT_WORK(&ms->work, mpc52xx_spi_wq); 472 473 /* Decide if interrupts can be used */ 474 if (ms->irq0 && ms->irq1) { 475 rc = request_irq(ms->irq0, mpc52xx_spi_irq, 0, 476 "mpc5200-spi-modf", ms); 477 rc |= request_irq(ms->irq1, mpc52xx_spi_irq, 0, 478 "mpc5200-spi-spif", ms); 479 if (rc) { 480 free_irq(ms->irq0, ms); 481 free_irq(ms->irq1, ms); 482 ms->irq0 = ms->irq1 = 0; 483 } 484 } else { 485 /* operate in polled mode */ 486 ms->irq0 = ms->irq1 = 0; 487 } 488 489 if (!ms->irq0) 490 dev_info(&op->dev, "using polled mode\n"); 491 492 dev_dbg(&op->dev, "registering spi_master struct\n"); 493 rc = spi_register_master(master); 494 if (rc) 495 goto err_register; 496 497 dev_info(&ms->master->dev, "registered MPC5200 SPI bus\n"); 498 499 return rc; 500 501 err_register: 502 dev_err(&ms->master->dev, "initialization failed\n"); 503 err_gpio: 504 while (i-- > 0) 505 gpio_free(ms->gpio_cs[i]); 506 507 kfree(ms->gpio_cs); 508 err_alloc_gpio: 509 spi_master_put(master); 510 err_alloc: 511 err_init: 512 iounmap(regs); 513 return rc; 514 } 515 516 static int mpc52xx_spi_remove(struct platform_device *op) 517 { 518 struct spi_master *master = spi_master_get(platform_get_drvdata(op)); 519 struct mpc52xx_spi *ms = spi_master_get_devdata(master); 520 int i; 521 522 free_irq(ms->irq0, ms); 523 free_irq(ms->irq1, ms); 524 525 for (i = 0; i < ms->gpio_cs_count; i++) 526 gpio_free(ms->gpio_cs[i]); 527 528 kfree(ms->gpio_cs); 529 spi_unregister_master(master); 530 iounmap(ms->regs); 531 spi_master_put(master); 532 533 return 0; 534 } 535 536 static const struct of_device_id mpc52xx_spi_match[] = { 537 { .compatible = "fsl,mpc5200-spi", }, 538 {} 539 }; 540 MODULE_DEVICE_TABLE(of, mpc52xx_spi_match); 541 542 static struct platform_driver mpc52xx_spi_of_driver = { 543 .driver = { 544 .name = "mpc52xx-spi", 545 .of_match_table = mpc52xx_spi_match, 546 }, 547 .probe = mpc52xx_spi_probe, 548 .remove = mpc52xx_spi_remove, 549 }; 550 module_platform_driver(mpc52xx_spi_of_driver); 551