1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * MPC52xx SPI bus driver. 4 * 5 * Copyright (C) 2008 Secret Lab Technologies Ltd. 6 * 7 * This is the driver for the MPC5200's dedicated SPI controller. 8 * 9 * Note: this driver does not support the MPC5200 PSC in SPI mode. For 10 * that driver see drivers/spi/mpc52xx_psc_spi.c 11 */ 12 13 #include <linux/module.h> 14 #include <linux/errno.h> 15 #include <linux/of_platform.h> 16 #include <linux/interrupt.h> 17 #include <linux/delay.h> 18 #include <linux/spi/spi.h> 19 #include <linux/io.h> 20 #include <linux/of_gpio.h> 21 #include <linux/slab.h> 22 #include <linux/of_address.h> 23 #include <linux/of_irq.h> 24 25 #include <asm/time.h> 26 #include <asm/mpc52xx.h> 27 28 MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>"); 29 MODULE_DESCRIPTION("MPC52xx SPI (non-PSC) Driver"); 30 MODULE_LICENSE("GPL"); 31 32 /* Register offsets */ 33 #define SPI_CTRL1 0x00 34 #define SPI_CTRL1_SPIE (1 << 7) 35 #define SPI_CTRL1_SPE (1 << 6) 36 #define SPI_CTRL1_MSTR (1 << 4) 37 #define SPI_CTRL1_CPOL (1 << 3) 38 #define SPI_CTRL1_CPHA (1 << 2) 39 #define SPI_CTRL1_SSOE (1 << 1) 40 #define SPI_CTRL1_LSBFE (1 << 0) 41 42 #define SPI_CTRL2 0x01 43 #define SPI_BRR 0x04 44 45 #define SPI_STATUS 0x05 46 #define SPI_STATUS_SPIF (1 << 7) 47 #define SPI_STATUS_WCOL (1 << 6) 48 #define SPI_STATUS_MODF (1 << 4) 49 50 #define SPI_DATA 0x09 51 #define SPI_PORTDATA 0x0d 52 #define SPI_DATADIR 0x10 53 54 /* FSM state return values */ 55 #define FSM_STOP 0 /* Nothing more for the state machine to */ 56 /* do. If something interesting happens */ 57 /* then an IRQ will be received */ 58 #define FSM_POLL 1 /* need to poll for completion, an IRQ is */ 59 /* not expected */ 60 #define FSM_CONTINUE 2 /* Keep iterating the state machine */ 61 62 /* Driver internal data */ 63 struct mpc52xx_spi { 64 struct spi_master *master; 65 void __iomem *regs; 66 int irq0; /* MODF irq */ 67 int irq1; /* SPIF irq */ 68 unsigned int ipb_freq; 69 70 /* Statistics; not used now, but will be reintroduced for debugfs */ 71 int msg_count; 72 int wcol_count; 73 int wcol_ticks; 74 u32 wcol_tx_timestamp; 75 int modf_count; 76 int byte_count; 77 78 struct list_head queue; /* queue of pending messages */ 79 spinlock_t lock; 80 struct work_struct work; 81 82 /* Details of current transfer (length, and buffer pointers) */ 83 struct spi_message *message; /* current message */ 84 struct spi_transfer *transfer; /* current transfer */ 85 int (*state)(int irq, struct mpc52xx_spi *ms, u8 status, u8 data); 86 int len; 87 int timestamp; 88 u8 *rx_buf; 89 const u8 *tx_buf; 90 int cs_change; 91 int gpio_cs_count; 92 unsigned int *gpio_cs; 93 }; 94 95 /* 96 * CS control function 97 */ 98 static void mpc52xx_spi_chipsel(struct mpc52xx_spi *ms, int value) 99 { 100 int cs; 101 102 if (ms->gpio_cs_count > 0) { 103 cs = ms->message->spi->chip_select; 104 gpio_set_value(ms->gpio_cs[cs], value ? 0 : 1); 105 } else 106 out_8(ms->regs + SPI_PORTDATA, value ? 0 : 0x08); 107 } 108 109 /* 110 * Start a new transfer. This is called both by the idle state 111 * for the first transfer in a message, and by the wait state when the 112 * previous transfer in a message is complete. 113 */ 114 static void mpc52xx_spi_start_transfer(struct mpc52xx_spi *ms) 115 { 116 ms->rx_buf = ms->transfer->rx_buf; 117 ms->tx_buf = ms->transfer->tx_buf; 118 ms->len = ms->transfer->len; 119 120 /* Activate the chip select */ 121 if (ms->cs_change) 122 mpc52xx_spi_chipsel(ms, 1); 123 ms->cs_change = ms->transfer->cs_change; 124 125 /* Write out the first byte */ 126 ms->wcol_tx_timestamp = mftb(); 127 if (ms->tx_buf) 128 out_8(ms->regs + SPI_DATA, *ms->tx_buf++); 129 else 130 out_8(ms->regs + SPI_DATA, 0); 131 } 132 133 /* Forward declaration of state handlers */ 134 static int mpc52xx_spi_fsmstate_transfer(int irq, struct mpc52xx_spi *ms, 135 u8 status, u8 data); 136 static int mpc52xx_spi_fsmstate_wait(int irq, struct mpc52xx_spi *ms, 137 u8 status, u8 data); 138 139 /* 140 * IDLE state 141 * 142 * No transfers are in progress; if another transfer is pending then retrieve 143 * it and kick it off. Otherwise, stop processing the state machine 144 */ 145 static int 146 mpc52xx_spi_fsmstate_idle(int irq, struct mpc52xx_spi *ms, u8 status, u8 data) 147 { 148 struct spi_device *spi; 149 int spr, sppr; 150 u8 ctrl1; 151 152 if (status && (irq != NO_IRQ)) 153 dev_err(&ms->master->dev, "spurious irq, status=0x%.2x\n", 154 status); 155 156 /* Check if there is another transfer waiting. */ 157 if (list_empty(&ms->queue)) 158 return FSM_STOP; 159 160 /* get the head of the queue */ 161 ms->message = list_first_entry(&ms->queue, struct spi_message, queue); 162 list_del_init(&ms->message->queue); 163 164 /* Setup the controller parameters */ 165 ctrl1 = SPI_CTRL1_SPIE | SPI_CTRL1_SPE | SPI_CTRL1_MSTR; 166 spi = ms->message->spi; 167 if (spi->mode & SPI_CPHA) 168 ctrl1 |= SPI_CTRL1_CPHA; 169 if (spi->mode & SPI_CPOL) 170 ctrl1 |= SPI_CTRL1_CPOL; 171 if (spi->mode & SPI_LSB_FIRST) 172 ctrl1 |= SPI_CTRL1_LSBFE; 173 out_8(ms->regs + SPI_CTRL1, ctrl1); 174 175 /* Setup the controller speed */ 176 /* minimum divider is '2'. Also, add '1' to force rounding the 177 * divider up. */ 178 sppr = ((ms->ipb_freq / ms->message->spi->max_speed_hz) + 1) >> 1; 179 spr = 0; 180 if (sppr < 1) 181 sppr = 1; 182 while (((sppr - 1) & ~0x7) != 0) { 183 sppr = (sppr + 1) >> 1; /* add '1' to force rounding up */ 184 spr++; 185 } 186 sppr--; /* sppr quantity in register is offset by 1 */ 187 if (spr > 7) { 188 /* Don't overrun limits of SPI baudrate register */ 189 spr = 7; 190 sppr = 7; 191 } 192 out_8(ms->regs + SPI_BRR, sppr << 4 | spr); /* Set speed */ 193 194 ms->cs_change = 1; 195 ms->transfer = container_of(ms->message->transfers.next, 196 struct spi_transfer, transfer_list); 197 198 mpc52xx_spi_start_transfer(ms); 199 ms->state = mpc52xx_spi_fsmstate_transfer; 200 201 return FSM_CONTINUE; 202 } 203 204 /* 205 * TRANSFER state 206 * 207 * In the middle of a transfer. If the SPI core has completed processing 208 * a byte, then read out the received data and write out the next byte 209 * (unless this transfer is finished; in which case go on to the wait 210 * state) 211 */ 212 static int mpc52xx_spi_fsmstate_transfer(int irq, struct mpc52xx_spi *ms, 213 u8 status, u8 data) 214 { 215 if (!status) 216 return ms->irq0 ? FSM_STOP : FSM_POLL; 217 218 if (status & SPI_STATUS_WCOL) { 219 /* The SPI controller is stoopid. At slower speeds, it may 220 * raise the SPIF flag before the state machine is actually 221 * finished, which causes a collision (internal to the state 222 * machine only). The manual recommends inserting a delay 223 * between receiving the interrupt and sending the next byte, 224 * but it can also be worked around simply by retrying the 225 * transfer which is what we do here. */ 226 ms->wcol_count++; 227 ms->wcol_ticks += mftb() - ms->wcol_tx_timestamp; 228 ms->wcol_tx_timestamp = mftb(); 229 data = 0; 230 if (ms->tx_buf) 231 data = *(ms->tx_buf - 1); 232 out_8(ms->regs + SPI_DATA, data); /* try again */ 233 return FSM_CONTINUE; 234 } else if (status & SPI_STATUS_MODF) { 235 ms->modf_count++; 236 dev_err(&ms->master->dev, "mode fault\n"); 237 mpc52xx_spi_chipsel(ms, 0); 238 ms->message->status = -EIO; 239 if (ms->message->complete) 240 ms->message->complete(ms->message->context); 241 ms->state = mpc52xx_spi_fsmstate_idle; 242 return FSM_CONTINUE; 243 } 244 245 /* Read data out of the spi device */ 246 ms->byte_count++; 247 if (ms->rx_buf) 248 *ms->rx_buf++ = data; 249 250 /* Is the transfer complete? */ 251 ms->len--; 252 if (ms->len == 0) { 253 ms->timestamp = mftb(); 254 if (ms->transfer->delay.unit == SPI_DELAY_UNIT_USECS) 255 ms->timestamp += ms->transfer->delay.value * 256 tb_ticks_per_usec; 257 ms->state = mpc52xx_spi_fsmstate_wait; 258 return FSM_CONTINUE; 259 } 260 261 /* Write out the next byte */ 262 ms->wcol_tx_timestamp = mftb(); 263 if (ms->tx_buf) 264 out_8(ms->regs + SPI_DATA, *ms->tx_buf++); 265 else 266 out_8(ms->regs + SPI_DATA, 0); 267 268 return FSM_CONTINUE; 269 } 270 271 /* 272 * WAIT state 273 * 274 * A transfer has completed; need to wait for the delay period to complete 275 * before starting the next transfer 276 */ 277 static int 278 mpc52xx_spi_fsmstate_wait(int irq, struct mpc52xx_spi *ms, u8 status, u8 data) 279 { 280 if (status && irq) 281 dev_err(&ms->master->dev, "spurious irq, status=0x%.2x\n", 282 status); 283 284 if (((int)mftb()) - ms->timestamp < 0) 285 return FSM_POLL; 286 287 ms->message->actual_length += ms->transfer->len; 288 289 /* Check if there is another transfer in this message. If there 290 * aren't then deactivate CS, notify sender, and drop back to idle 291 * to start the next message. */ 292 if (ms->transfer->transfer_list.next == &ms->message->transfers) { 293 ms->msg_count++; 294 mpc52xx_spi_chipsel(ms, 0); 295 ms->message->status = 0; 296 if (ms->message->complete) 297 ms->message->complete(ms->message->context); 298 ms->state = mpc52xx_spi_fsmstate_idle; 299 return FSM_CONTINUE; 300 } 301 302 /* There is another transfer; kick it off */ 303 304 if (ms->cs_change) 305 mpc52xx_spi_chipsel(ms, 0); 306 307 ms->transfer = container_of(ms->transfer->transfer_list.next, 308 struct spi_transfer, transfer_list); 309 mpc52xx_spi_start_transfer(ms); 310 ms->state = mpc52xx_spi_fsmstate_transfer; 311 return FSM_CONTINUE; 312 } 313 314 /** 315 * mpc52xx_spi_fsm_process - Finite State Machine iteration function 316 * @irq: irq number that triggered the FSM or 0 for polling 317 * @ms: pointer to mpc52xx_spi driver data 318 */ 319 static void mpc52xx_spi_fsm_process(int irq, struct mpc52xx_spi *ms) 320 { 321 int rc = FSM_CONTINUE; 322 u8 status, data; 323 324 while (rc == FSM_CONTINUE) { 325 /* Interrupt cleared by read of STATUS followed by 326 * read of DATA registers */ 327 status = in_8(ms->regs + SPI_STATUS); 328 data = in_8(ms->regs + SPI_DATA); 329 rc = ms->state(irq, ms, status, data); 330 } 331 332 if (rc == FSM_POLL) 333 schedule_work(&ms->work); 334 } 335 336 /** 337 * mpc52xx_spi_irq - IRQ handler 338 */ 339 static irqreturn_t mpc52xx_spi_irq(int irq, void *_ms) 340 { 341 struct mpc52xx_spi *ms = _ms; 342 spin_lock(&ms->lock); 343 mpc52xx_spi_fsm_process(irq, ms); 344 spin_unlock(&ms->lock); 345 return IRQ_HANDLED; 346 } 347 348 /** 349 * mpc52xx_spi_wq - Workqueue function for polling the state machine 350 */ 351 static void mpc52xx_spi_wq(struct work_struct *work) 352 { 353 struct mpc52xx_spi *ms = container_of(work, struct mpc52xx_spi, work); 354 unsigned long flags; 355 356 spin_lock_irqsave(&ms->lock, flags); 357 mpc52xx_spi_fsm_process(0, ms); 358 spin_unlock_irqrestore(&ms->lock, flags); 359 } 360 361 /* 362 * spi_master ops 363 */ 364 365 static int mpc52xx_spi_transfer(struct spi_device *spi, struct spi_message *m) 366 { 367 struct mpc52xx_spi *ms = spi_master_get_devdata(spi->master); 368 unsigned long flags; 369 370 m->actual_length = 0; 371 m->status = -EINPROGRESS; 372 373 spin_lock_irqsave(&ms->lock, flags); 374 list_add_tail(&m->queue, &ms->queue); 375 spin_unlock_irqrestore(&ms->lock, flags); 376 schedule_work(&ms->work); 377 378 return 0; 379 } 380 381 /* 382 * OF Platform Bus Binding 383 */ 384 static int mpc52xx_spi_probe(struct platform_device *op) 385 { 386 struct spi_master *master; 387 struct mpc52xx_spi *ms; 388 void __iomem *regs; 389 u8 ctrl1; 390 int rc, i = 0; 391 int gpio_cs; 392 393 /* MMIO registers */ 394 dev_dbg(&op->dev, "probing mpc5200 SPI device\n"); 395 regs = of_iomap(op->dev.of_node, 0); 396 if (!regs) 397 return -ENODEV; 398 399 /* initialize the device */ 400 ctrl1 = SPI_CTRL1_SPIE | SPI_CTRL1_SPE | SPI_CTRL1_MSTR; 401 out_8(regs + SPI_CTRL1, ctrl1); 402 out_8(regs + SPI_CTRL2, 0x0); 403 out_8(regs + SPI_DATADIR, 0xe); /* Set output pins */ 404 out_8(regs + SPI_PORTDATA, 0x8); /* Deassert /SS signal */ 405 406 /* Clear the status register and re-read it to check for a MODF 407 * failure. This driver cannot currently handle multiple masters 408 * on the SPI bus. This fault will also occur if the SPI signals 409 * are not connected to any pins (port_config setting) */ 410 in_8(regs + SPI_STATUS); 411 out_8(regs + SPI_CTRL1, ctrl1); 412 413 in_8(regs + SPI_DATA); 414 if (in_8(regs + SPI_STATUS) & SPI_STATUS_MODF) { 415 dev_err(&op->dev, "mode fault; is port_config correct?\n"); 416 rc = -EIO; 417 goto err_init; 418 } 419 420 dev_dbg(&op->dev, "allocating spi_master struct\n"); 421 master = spi_alloc_master(&op->dev, sizeof(*ms)); 422 if (!master) { 423 rc = -ENOMEM; 424 goto err_alloc; 425 } 426 427 master->transfer = mpc52xx_spi_transfer; 428 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; 429 master->bits_per_word_mask = SPI_BPW_MASK(8); 430 master->dev.of_node = op->dev.of_node; 431 432 platform_set_drvdata(op, master); 433 434 ms = spi_master_get_devdata(master); 435 ms->master = master; 436 ms->regs = regs; 437 ms->irq0 = irq_of_parse_and_map(op->dev.of_node, 0); 438 ms->irq1 = irq_of_parse_and_map(op->dev.of_node, 1); 439 ms->state = mpc52xx_spi_fsmstate_idle; 440 ms->ipb_freq = mpc5xxx_get_bus_frequency(op->dev.of_node); 441 ms->gpio_cs_count = of_gpio_count(op->dev.of_node); 442 if (ms->gpio_cs_count > 0) { 443 master->num_chipselect = ms->gpio_cs_count; 444 ms->gpio_cs = kmalloc_array(ms->gpio_cs_count, 445 sizeof(*ms->gpio_cs), 446 GFP_KERNEL); 447 if (!ms->gpio_cs) { 448 rc = -ENOMEM; 449 goto err_alloc_gpio; 450 } 451 452 for (i = 0; i < ms->gpio_cs_count; i++) { 453 gpio_cs = of_get_gpio(op->dev.of_node, i); 454 if (!gpio_is_valid(gpio_cs)) { 455 dev_err(&op->dev, 456 "could not parse the gpio field in oftree\n"); 457 rc = -ENODEV; 458 goto err_gpio; 459 } 460 461 rc = gpio_request(gpio_cs, dev_name(&op->dev)); 462 if (rc) { 463 dev_err(&op->dev, 464 "can't request spi cs gpio #%d on gpio line %d\n", 465 i, gpio_cs); 466 goto err_gpio; 467 } 468 469 gpio_direction_output(gpio_cs, 1); 470 ms->gpio_cs[i] = gpio_cs; 471 } 472 } 473 474 spin_lock_init(&ms->lock); 475 INIT_LIST_HEAD(&ms->queue); 476 INIT_WORK(&ms->work, mpc52xx_spi_wq); 477 478 /* Decide if interrupts can be used */ 479 if (ms->irq0 && ms->irq1) { 480 rc = request_irq(ms->irq0, mpc52xx_spi_irq, 0, 481 "mpc5200-spi-modf", ms); 482 rc |= request_irq(ms->irq1, mpc52xx_spi_irq, 0, 483 "mpc5200-spi-spif", ms); 484 if (rc) { 485 free_irq(ms->irq0, ms); 486 free_irq(ms->irq1, ms); 487 ms->irq0 = ms->irq1 = 0; 488 } 489 } else { 490 /* operate in polled mode */ 491 ms->irq0 = ms->irq1 = 0; 492 } 493 494 if (!ms->irq0) 495 dev_info(&op->dev, "using polled mode\n"); 496 497 dev_dbg(&op->dev, "registering spi_master struct\n"); 498 rc = spi_register_master(master); 499 if (rc) 500 goto err_register; 501 502 dev_info(&ms->master->dev, "registered MPC5200 SPI bus\n"); 503 504 return rc; 505 506 err_register: 507 dev_err(&ms->master->dev, "initialization failed\n"); 508 err_gpio: 509 while (i-- > 0) 510 gpio_free(ms->gpio_cs[i]); 511 512 kfree(ms->gpio_cs); 513 err_alloc_gpio: 514 spi_master_put(master); 515 err_alloc: 516 err_init: 517 iounmap(regs); 518 return rc; 519 } 520 521 static int mpc52xx_spi_remove(struct platform_device *op) 522 { 523 struct spi_master *master = spi_master_get(platform_get_drvdata(op)); 524 struct mpc52xx_spi *ms = spi_master_get_devdata(master); 525 int i; 526 527 free_irq(ms->irq0, ms); 528 free_irq(ms->irq1, ms); 529 530 for (i = 0; i < ms->gpio_cs_count; i++) 531 gpio_free(ms->gpio_cs[i]); 532 533 kfree(ms->gpio_cs); 534 spi_unregister_master(master); 535 iounmap(ms->regs); 536 spi_master_put(master); 537 538 return 0; 539 } 540 541 static const struct of_device_id mpc52xx_spi_match[] = { 542 { .compatible = "fsl,mpc5200-spi", }, 543 {} 544 }; 545 MODULE_DEVICE_TABLE(of, mpc52xx_spi_match); 546 547 static struct platform_driver mpc52xx_spi_of_driver = { 548 .driver = { 549 .name = "mpc52xx-spi", 550 .of_match_table = mpc52xx_spi_match, 551 }, 552 .probe = mpc52xx_spi_probe, 553 .remove = mpc52xx_spi_remove, 554 }; 555 module_platform_driver(mpc52xx_spi_of_driver); 556