xref: /openbmc/linux/drivers/spi/spi-mpc52xx.c (revision 02b30248) 
155716d26SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2ca632f55SGrant Likely /*
3ca632f55SGrant Likely  * MPC52xx SPI bus driver.
4ca632f55SGrant Likely  *
5ca632f55SGrant Likely  * Copyright (C) 2008 Secret Lab Technologies Ltd.
6ca632f55SGrant Likely  *
7ca632f55SGrant Likely  * This is the driver for the MPC5200's dedicated SPI controller.
8ca632f55SGrant Likely  *
9ca632f55SGrant Likely  * Note: this driver does not support the MPC5200 PSC in SPI mode.  For
10ca632f55SGrant Likely  * that driver see drivers/spi/mpc52xx_psc_spi.c
11ca632f55SGrant Likely  */
12ca632f55SGrant Likely 
13ca632f55SGrant Likely #include <linux/module.h>
14ca632f55SGrant Likely #include <linux/errno.h>
15ca632f55SGrant Likely #include <linux/of_platform.h>
16ca632f55SGrant Likely #include <linux/interrupt.h>
17ca632f55SGrant Likely #include <linux/delay.h>
18ca632f55SGrant Likely #include <linux/spi/spi.h>
19ca632f55SGrant Likely #include <linux/io.h>
20ca632f55SGrant Likely #include <linux/of_gpio.h>
21ca632f55SGrant Likely #include <linux/slab.h>
22*02b30248SChristophe Leroy #include <linux/of_address.h>
23*02b30248SChristophe Leroy #include <linux/of_irq.h>
24*02b30248SChristophe Leroy 
25ca632f55SGrant Likely #include <asm/time.h>
26ca632f55SGrant Likely #include <asm/mpc52xx.h>
27ca632f55SGrant Likely 
28ca632f55SGrant Likely MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
29ca632f55SGrant Likely MODULE_DESCRIPTION("MPC52xx SPI (non-PSC) Driver");
30ca632f55SGrant Likely MODULE_LICENSE("GPL");
31ca632f55SGrant Likely 
32ca632f55SGrant Likely /* Register offsets */
33ca632f55SGrant Likely #define SPI_CTRL1	0x00
34ca632f55SGrant Likely #define SPI_CTRL1_SPIE		(1 << 7)
35ca632f55SGrant Likely #define SPI_CTRL1_SPE		(1 << 6)
36ca632f55SGrant Likely #define SPI_CTRL1_MSTR		(1 << 4)
37ca632f55SGrant Likely #define SPI_CTRL1_CPOL		(1 << 3)
38ca632f55SGrant Likely #define SPI_CTRL1_CPHA		(1 << 2)
39ca632f55SGrant Likely #define SPI_CTRL1_SSOE		(1 << 1)
40ca632f55SGrant Likely #define SPI_CTRL1_LSBFE		(1 << 0)
41ca632f55SGrant Likely 
42ca632f55SGrant Likely #define SPI_CTRL2	0x01
43ca632f55SGrant Likely #define SPI_BRR		0x04
44ca632f55SGrant Likely 
45ca632f55SGrant Likely #define SPI_STATUS	0x05
46ca632f55SGrant Likely #define SPI_STATUS_SPIF		(1 << 7)
47ca632f55SGrant Likely #define SPI_STATUS_WCOL		(1 << 6)
48ca632f55SGrant Likely #define SPI_STATUS_MODF		(1 << 4)
49ca632f55SGrant Likely 
50ca632f55SGrant Likely #define SPI_DATA	0x09
51ca632f55SGrant Likely #define SPI_PORTDATA	0x0d
52ca632f55SGrant Likely #define SPI_DATADIR	0x10
53ca632f55SGrant Likely 
54ca632f55SGrant Likely /* FSM state return values */
55ca632f55SGrant Likely #define FSM_STOP	0	/* Nothing more for the state machine to */
56ca632f55SGrant Likely 				/* do.  If something interesting happens */
57ca632f55SGrant Likely 				/* then an IRQ will be received */
58ca632f55SGrant Likely #define FSM_POLL	1	/* need to poll for completion, an IRQ is */
59ca632f55SGrant Likely 				/* not expected */
60ca632f55SGrant Likely #define FSM_CONTINUE	2	/* Keep iterating the state machine */
61ca632f55SGrant Likely 
62ca632f55SGrant Likely /* Driver internal data */
63ca632f55SGrant Likely struct mpc52xx_spi {
64ca632f55SGrant Likely 	struct spi_master *master;
65ca632f55SGrant Likely 	void __iomem *regs;
66ca632f55SGrant Likely 	int irq0;	/* MODF irq */
67ca632f55SGrant Likely 	int irq1;	/* SPIF irq */
68ca632f55SGrant Likely 	unsigned int ipb_freq;
69ca632f55SGrant Likely 
70ca632f55SGrant Likely 	/* Statistics; not used now, but will be reintroduced for debugfs */
71ca632f55SGrant Likely 	int msg_count;
72ca632f55SGrant Likely 	int wcol_count;
73ca632f55SGrant Likely 	int wcol_ticks;
74ca632f55SGrant Likely 	u32 wcol_tx_timestamp;
75ca632f55SGrant Likely 	int modf_count;
76ca632f55SGrant Likely 	int byte_count;
77ca632f55SGrant Likely 
78ca632f55SGrant Likely 	struct list_head queue;		/* queue of pending messages */
79ca632f55SGrant Likely 	spinlock_t lock;
80ca632f55SGrant Likely 	struct work_struct work;
81ca632f55SGrant Likely 
82ca632f55SGrant Likely 	/* Details of current transfer (length, and buffer pointers) */
83ca632f55SGrant Likely 	struct spi_message *message;	/* current message */
84ca632f55SGrant Likely 	struct spi_transfer *transfer;	/* current transfer */
85ca632f55SGrant Likely 	int (*state)(int irq, struct mpc52xx_spi *ms, u8 status, u8 data);
86ca632f55SGrant Likely 	int len;
87ca632f55SGrant Likely 	int timestamp;
88ca632f55SGrant Likely 	u8 *rx_buf;
89ca632f55SGrant Likely 	const u8 *tx_buf;
90ca632f55SGrant Likely 	int cs_change;
91ca632f55SGrant Likely 	int gpio_cs_count;
92ca632f55SGrant Likely 	unsigned int *gpio_cs;
93ca632f55SGrant Likely };
94ca632f55SGrant Likely 
95ca632f55SGrant Likely /*
96ca632f55SGrant Likely  * CS control function
97ca632f55SGrant Likely  */
98ca632f55SGrant Likely static void mpc52xx_spi_chipsel(struct mpc52xx_spi *ms, int value)
99ca632f55SGrant Likely {
100ca632f55SGrant Likely 	int cs;
101ca632f55SGrant Likely 
102ca632f55SGrant Likely 	if (ms->gpio_cs_count > 0) {
103ca632f55SGrant Likely 		cs = ms->message->spi->chip_select;
104ca632f55SGrant Likely 		gpio_set_value(ms->gpio_cs[cs], value ? 0 : 1);
105ca632f55SGrant Likely 	} else
106ca632f55SGrant Likely 		out_8(ms->regs + SPI_PORTDATA, value ? 0 : 0x08);
107ca632f55SGrant Likely }
108ca632f55SGrant Likely 
109ca632f55SGrant Likely /*
110ca632f55SGrant Likely  * Start a new transfer.  This is called both by the idle state
111ca632f55SGrant Likely  * for the first transfer in a message, and by the wait state when the
112ca632f55SGrant Likely  * previous transfer in a message is complete.
113ca632f55SGrant Likely  */
114ca632f55SGrant Likely static void mpc52xx_spi_start_transfer(struct mpc52xx_spi *ms)
115ca632f55SGrant Likely {
116ca632f55SGrant Likely 	ms->rx_buf = ms->transfer->rx_buf;
117ca632f55SGrant Likely 	ms->tx_buf = ms->transfer->tx_buf;
118ca632f55SGrant Likely 	ms->len = ms->transfer->len;
119ca632f55SGrant Likely 
120ca632f55SGrant Likely 	/* Activate the chip select */
121ca632f55SGrant Likely 	if (ms->cs_change)
122ca632f55SGrant Likely 		mpc52xx_spi_chipsel(ms, 1);
123ca632f55SGrant Likely 	ms->cs_change = ms->transfer->cs_change;
124ca632f55SGrant Likely 
125ca632f55SGrant Likely 	/* Write out the first byte */
126e1065611SChristophe Leroy 	ms->wcol_tx_timestamp = mftb();
127ca632f55SGrant Likely 	if (ms->tx_buf)
128ca632f55SGrant Likely 		out_8(ms->regs + SPI_DATA, *ms->tx_buf++);
129ca632f55SGrant Likely 	else
130ca632f55SGrant Likely 		out_8(ms->regs + SPI_DATA, 0);
131ca632f55SGrant Likely }
132ca632f55SGrant Likely 
133ca632f55SGrant Likely /* Forward declaration of state handlers */
134ca632f55SGrant Likely static int mpc52xx_spi_fsmstate_transfer(int irq, struct mpc52xx_spi *ms,
135ca632f55SGrant Likely 					 u8 status, u8 data);
136ca632f55SGrant Likely static int mpc52xx_spi_fsmstate_wait(int irq, struct mpc52xx_spi *ms,
137ca632f55SGrant Likely 				     u8 status, u8 data);
138ca632f55SGrant Likely 
139ca632f55SGrant Likely /*
140ca632f55SGrant Likely  * IDLE state
141ca632f55SGrant Likely  *
142ca632f55SGrant Likely  * No transfers are in progress; if another transfer is pending then retrieve
143ca632f55SGrant Likely  * it and kick it off.  Otherwise, stop processing the state machine
144ca632f55SGrant Likely  */
145ca632f55SGrant Likely static int
146ca632f55SGrant Likely mpc52xx_spi_fsmstate_idle(int irq, struct mpc52xx_spi *ms, u8 status, u8 data)
147ca632f55SGrant Likely {
148ca632f55SGrant Likely 	struct spi_device *spi;
149ca632f55SGrant Likely 	int spr, sppr;
150ca632f55SGrant Likely 	u8 ctrl1;
151ca632f55SGrant Likely 
152ca632f55SGrant Likely 	if (status && (irq != NO_IRQ))
153ca632f55SGrant Likely 		dev_err(&ms->master->dev, "spurious irq, status=0x%.2x\n",
154ca632f55SGrant Likely 			status);
155ca632f55SGrant Likely 
156ca632f55SGrant Likely 	/* Check if there is another transfer waiting. */
157ca632f55SGrant Likely 	if (list_empty(&ms->queue))
158ca632f55SGrant Likely 		return FSM_STOP;
159ca632f55SGrant Likely 
160ca632f55SGrant Likely 	/* get the head of the queue */
161ca632f55SGrant Likely 	ms->message = list_first_entry(&ms->queue, struct spi_message, queue);
162ca632f55SGrant Likely 	list_del_init(&ms->message->queue);
163ca632f55SGrant Likely 
164ca632f55SGrant Likely 	/* Setup the controller parameters */
165ca632f55SGrant Likely 	ctrl1 = SPI_CTRL1_SPIE | SPI_CTRL1_SPE | SPI_CTRL1_MSTR;
166ca632f55SGrant Likely 	spi = ms->message->spi;
167ca632f55SGrant Likely 	if (spi->mode & SPI_CPHA)
168ca632f55SGrant Likely 		ctrl1 |= SPI_CTRL1_CPHA;
169ca632f55SGrant Likely 	if (spi->mode & SPI_CPOL)
170ca632f55SGrant Likely 		ctrl1 |= SPI_CTRL1_CPOL;
171ca632f55SGrant Likely 	if (spi->mode & SPI_LSB_FIRST)
172ca632f55SGrant Likely 		ctrl1 |= SPI_CTRL1_LSBFE;
173ca632f55SGrant Likely 	out_8(ms->regs + SPI_CTRL1, ctrl1);
174ca632f55SGrant Likely 
175ca632f55SGrant Likely 	/* Setup the controller speed */
176ca632f55SGrant Likely 	/* minimum divider is '2'.  Also, add '1' to force rounding the
177ca632f55SGrant Likely 	 * divider up. */
178ca632f55SGrant Likely 	sppr = ((ms->ipb_freq / ms->message->spi->max_speed_hz) + 1) >> 1;
179ca632f55SGrant Likely 	spr = 0;
180ca632f55SGrant Likely 	if (sppr < 1)
181ca632f55SGrant Likely 		sppr = 1;
182ca632f55SGrant Likely 	while (((sppr - 1) & ~0x7) != 0) {
183ca632f55SGrant Likely 		sppr = (sppr + 1) >> 1; /* add '1' to force rounding up */
184ca632f55SGrant Likely 		spr++;
185ca632f55SGrant Likely 	}
186ca632f55SGrant Likely 	sppr--;		/* sppr quantity in register is offset by 1 */
187ca632f55SGrant Likely 	if (spr > 7) {
188ca632f55SGrant Likely 		/* Don't overrun limits of SPI baudrate register */
189ca632f55SGrant Likely 		spr = 7;
190ca632f55SGrant Likely 		sppr = 7;
191ca632f55SGrant Likely 	}
192ca632f55SGrant Likely 	out_8(ms->regs + SPI_BRR, sppr << 4 | spr); /* Set speed */
193ca632f55SGrant Likely 
194ca632f55SGrant Likely 	ms->cs_change = 1;
195ca632f55SGrant Likely 	ms->transfer = container_of(ms->message->transfers.next,
196ca632f55SGrant Likely 				    struct spi_transfer, transfer_list);
197ca632f55SGrant Likely 
198ca632f55SGrant Likely 	mpc52xx_spi_start_transfer(ms);
199ca632f55SGrant Likely 	ms->state = mpc52xx_spi_fsmstate_transfer;
200ca632f55SGrant Likely 
201ca632f55SGrant Likely 	return FSM_CONTINUE;
202ca632f55SGrant Likely }
203ca632f55SGrant Likely 
204ca632f55SGrant Likely /*
205ca632f55SGrant Likely  * TRANSFER state
206ca632f55SGrant Likely  *
207ca632f55SGrant Likely  * In the middle of a transfer.  If the SPI core has completed processing
208ca632f55SGrant Likely  * a byte, then read out the received data and write out the next byte
209ca632f55SGrant Likely  * (unless this transfer is finished; in which case go on to the wait
210ca632f55SGrant Likely  * state)
211ca632f55SGrant Likely  */
212ca632f55SGrant Likely static int mpc52xx_spi_fsmstate_transfer(int irq, struct mpc52xx_spi *ms,
213ca632f55SGrant Likely 					 u8 status, u8 data)
214ca632f55SGrant Likely {
215ca632f55SGrant Likely 	if (!status)
216ca632f55SGrant Likely 		return ms->irq0 ? FSM_STOP : FSM_POLL;
217ca632f55SGrant Likely 
218ca632f55SGrant Likely 	if (status & SPI_STATUS_WCOL) {
219ca632f55SGrant Likely 		/* The SPI controller is stoopid.  At slower speeds, it may
220ca632f55SGrant Likely 		 * raise the SPIF flag before the state machine is actually
221ca632f55SGrant Likely 		 * finished, which causes a collision (internal to the state
222ca632f55SGrant Likely 		 * machine only).  The manual recommends inserting a delay
223ca632f55SGrant Likely 		 * between receiving the interrupt and sending the next byte,
224ca632f55SGrant Likely 		 * but it can also be worked around simply by retrying the
225ca632f55SGrant Likely 		 * transfer which is what we do here. */
226ca632f55SGrant Likely 		ms->wcol_count++;
227e1065611SChristophe Leroy 		ms->wcol_ticks += mftb() - ms->wcol_tx_timestamp;
228e1065611SChristophe Leroy 		ms->wcol_tx_timestamp = mftb();
229ca632f55SGrant Likely 		data = 0;
230ca632f55SGrant Likely 		if (ms->tx_buf)
231ca632f55SGrant Likely 			data = *(ms->tx_buf - 1);
232ca632f55SGrant Likely 		out_8(ms->regs + SPI_DATA, data); /* try again */
233ca632f55SGrant Likely 		return FSM_CONTINUE;
234ca632f55SGrant Likely 	} else if (status & SPI_STATUS_MODF) {
235ca632f55SGrant Likely 		ms->modf_count++;
236ca632f55SGrant Likely 		dev_err(&ms->master->dev, "mode fault\n");
237ca632f55SGrant Likely 		mpc52xx_spi_chipsel(ms, 0);
238ca632f55SGrant Likely 		ms->message->status = -EIO;
2390a6d3879SAxel Lin 		if (ms->message->complete)
240ca632f55SGrant Likely 			ms->message->complete(ms->message->context);
241ca632f55SGrant Likely 		ms->state = mpc52xx_spi_fsmstate_idle;
242ca632f55SGrant Likely 		return FSM_CONTINUE;
243ca632f55SGrant Likely 	}
244ca632f55SGrant Likely 
245ca632f55SGrant Likely 	/* Read data out of the spi device */
246ca632f55SGrant Likely 	ms->byte_count++;
247ca632f55SGrant Likely 	if (ms->rx_buf)
248ca632f55SGrant Likely 		*ms->rx_buf++ = data;
249ca632f55SGrant Likely 
250ca632f55SGrant Likely 	/* Is the transfer complete? */
251ca632f55SGrant Likely 	ms->len--;
252ca632f55SGrant Likely 	if (ms->len == 0) {
253e1065611SChristophe Leroy 		ms->timestamp = mftb();
254258ea99fSSergiu Cuciurean 		if (ms->transfer->delay.unit == SPI_DELAY_UNIT_USECS)
255258ea99fSSergiu Cuciurean 			ms->timestamp += ms->transfer->delay.value *
256258ea99fSSergiu Cuciurean 					 tb_ticks_per_usec;
257ca632f55SGrant Likely 		ms->state = mpc52xx_spi_fsmstate_wait;
258ca632f55SGrant Likely 		return FSM_CONTINUE;
259ca632f55SGrant Likely 	}
260ca632f55SGrant Likely 
261ca632f55SGrant Likely 	/* Write out the next byte */
262e1065611SChristophe Leroy 	ms->wcol_tx_timestamp = mftb();
263ca632f55SGrant Likely 	if (ms->tx_buf)
264ca632f55SGrant Likely 		out_8(ms->regs + SPI_DATA, *ms->tx_buf++);
265ca632f55SGrant Likely 	else
266ca632f55SGrant Likely 		out_8(ms->regs + SPI_DATA, 0);
267ca632f55SGrant Likely 
268ca632f55SGrant Likely 	return FSM_CONTINUE;
269ca632f55SGrant Likely }
270ca632f55SGrant Likely 
271ca632f55SGrant Likely /*
272ca632f55SGrant Likely  * WAIT state
273ca632f55SGrant Likely  *
274ca632f55SGrant Likely  * A transfer has completed; need to wait for the delay period to complete
275ca632f55SGrant Likely  * before starting the next transfer
276ca632f55SGrant Likely  */
277ca632f55SGrant Likely static int
278ca632f55SGrant Likely mpc52xx_spi_fsmstate_wait(int irq, struct mpc52xx_spi *ms, u8 status, u8 data)
279ca632f55SGrant Likely {
280ca632f55SGrant Likely 	if (status && irq)
281ca632f55SGrant Likely 		dev_err(&ms->master->dev, "spurious irq, status=0x%.2x\n",
282ca632f55SGrant Likely 			status);
283ca632f55SGrant Likely 
284e1065611SChristophe Leroy 	if (((int)mftb()) - ms->timestamp < 0)
285ca632f55SGrant Likely 		return FSM_POLL;
286ca632f55SGrant Likely 
287ca632f55SGrant Likely 	ms->message->actual_length += ms->transfer->len;
288ca632f55SGrant Likely 
289ca632f55SGrant Likely 	/* Check if there is another transfer in this message.  If there
290ca632f55SGrant Likely 	 * aren't then deactivate CS, notify sender, and drop back to idle
291ca632f55SGrant Likely 	 * to start the next message. */
292ca632f55SGrant Likely 	if (ms->transfer->transfer_list.next == &ms->message->transfers) {
293ca632f55SGrant Likely 		ms->msg_count++;
294ca632f55SGrant Likely 		mpc52xx_spi_chipsel(ms, 0);
295ca632f55SGrant Likely 		ms->message->status = 0;
2960a6d3879SAxel Lin 		if (ms->message->complete)
297ca632f55SGrant Likely 			ms->message->complete(ms->message->context);
298ca632f55SGrant Likely 		ms->state = mpc52xx_spi_fsmstate_idle;
299ca632f55SGrant Likely 		return FSM_CONTINUE;
300ca632f55SGrant Likely 	}
301ca632f55SGrant Likely 
302ca632f55SGrant Likely 	/* There is another transfer; kick it off */
303ca632f55SGrant Likely 
304ca632f55SGrant Likely 	if (ms->cs_change)
305ca632f55SGrant Likely 		mpc52xx_spi_chipsel(ms, 0);
306ca632f55SGrant Likely 
307ca632f55SGrant Likely 	ms->transfer = container_of(ms->transfer->transfer_list.next,
308ca632f55SGrant Likely 				    struct spi_transfer, transfer_list);
309ca632f55SGrant Likely 	mpc52xx_spi_start_transfer(ms);
310ca632f55SGrant Likely 	ms->state = mpc52xx_spi_fsmstate_transfer;
311ca632f55SGrant Likely 	return FSM_CONTINUE;
312ca632f55SGrant Likely }
313ca632f55SGrant Likely 
314ca632f55SGrant Likely /**
315ca632f55SGrant Likely  * mpc52xx_spi_fsm_process - Finite State Machine iteration function
316ca632f55SGrant Likely  * @irq: irq number that triggered the FSM or 0 for polling
317ca632f55SGrant Likely  * @ms: pointer to mpc52xx_spi driver data
318ca632f55SGrant Likely  */
319ca632f55SGrant Likely static void mpc52xx_spi_fsm_process(int irq, struct mpc52xx_spi *ms)
320ca632f55SGrant Likely {
321ca632f55SGrant Likely 	int rc = FSM_CONTINUE;
322ca632f55SGrant Likely 	u8 status, data;
323ca632f55SGrant Likely 
324ca632f55SGrant Likely 	while (rc == FSM_CONTINUE) {
325ca632f55SGrant Likely 		/* Interrupt cleared by read of STATUS followed by
326ca632f55SGrant Likely 		 * read of DATA registers */
327ca632f55SGrant Likely 		status = in_8(ms->regs + SPI_STATUS);
328ca632f55SGrant Likely 		data = in_8(ms->regs + SPI_DATA);
329ca632f55SGrant Likely 		rc = ms->state(irq, ms, status, data);
330ca632f55SGrant Likely 	}
331ca632f55SGrant Likely 
332ca632f55SGrant Likely 	if (rc == FSM_POLL)
333ca632f55SGrant Likely 		schedule_work(&ms->work);
334ca632f55SGrant Likely }
335ca632f55SGrant Likely 
336ca632f55SGrant Likely /**
337ca632f55SGrant Likely  * mpc52xx_spi_irq - IRQ handler
338ca632f55SGrant Likely  */
339ca632f55SGrant Likely static irqreturn_t mpc52xx_spi_irq(int irq, void *_ms)
340ca632f55SGrant Likely {
341ca632f55SGrant Likely 	struct mpc52xx_spi *ms = _ms;
342ca632f55SGrant Likely 	spin_lock(&ms->lock);
343ca632f55SGrant Likely 	mpc52xx_spi_fsm_process(irq, ms);
344ca632f55SGrant Likely 	spin_unlock(&ms->lock);
345ca632f55SGrant Likely 	return IRQ_HANDLED;
346ca632f55SGrant Likely }
347ca632f55SGrant Likely 
348ca632f55SGrant Likely /**
349ca632f55SGrant Likely  * mpc52xx_spi_wq - Workqueue function for polling the state machine
350ca632f55SGrant Likely  */
351ca632f55SGrant Likely static void mpc52xx_spi_wq(struct work_struct *work)
352ca632f55SGrant Likely {
353ca632f55SGrant Likely 	struct mpc52xx_spi *ms = container_of(work, struct mpc52xx_spi, work);
354ca632f55SGrant Likely 	unsigned long flags;
355ca632f55SGrant Likely 
356ca632f55SGrant Likely 	spin_lock_irqsave(&ms->lock, flags);
357ca632f55SGrant Likely 	mpc52xx_spi_fsm_process(0, ms);
358ca632f55SGrant Likely 	spin_unlock_irqrestore(&ms->lock, flags);
359ca632f55SGrant Likely }
360ca632f55SGrant Likely 
361ca632f55SGrant Likely /*
362ca632f55SGrant Likely  * spi_master ops
363ca632f55SGrant Likely  */
364ca632f55SGrant Likely 
365ca632f55SGrant Likely static int mpc52xx_spi_transfer(struct spi_device *spi, struct spi_message *m)
366ca632f55SGrant Likely {
367ca632f55SGrant Likely 	struct mpc52xx_spi *ms = spi_master_get_devdata(spi->master);
368ca632f55SGrant Likely 	unsigned long flags;
369ca632f55SGrant Likely 
370ca632f55SGrant Likely 	m->actual_length = 0;
371ca632f55SGrant Likely 	m->status = -EINPROGRESS;
372ca632f55SGrant Likely 
373ca632f55SGrant Likely 	spin_lock_irqsave(&ms->lock, flags);
374ca632f55SGrant Likely 	list_add_tail(&m->queue, &ms->queue);
375ca632f55SGrant Likely 	spin_unlock_irqrestore(&ms->lock, flags);
376ca632f55SGrant Likely 	schedule_work(&ms->work);
377ca632f55SGrant Likely 
378ca632f55SGrant Likely 	return 0;
379ca632f55SGrant Likely }
380ca632f55SGrant Likely 
381ca632f55SGrant Likely /*
382ca632f55SGrant Likely  * OF Platform Bus Binding
383ca632f55SGrant Likely  */
384fd4a319bSGrant Likely static int mpc52xx_spi_probe(struct platform_device *op)
385ca632f55SGrant Likely {
386ca632f55SGrant Likely 	struct spi_master *master;
387ca632f55SGrant Likely 	struct mpc52xx_spi *ms;
388ca632f55SGrant Likely 	void __iomem *regs;
389ca632f55SGrant Likely 	u8 ctrl1;
390ca632f55SGrant Likely 	int rc, i = 0;
391ca632f55SGrant Likely 	int gpio_cs;
392ca632f55SGrant Likely 
393ca632f55SGrant Likely 	/* MMIO registers */
394ca632f55SGrant Likely 	dev_dbg(&op->dev, "probing mpc5200 SPI device\n");
395ca632f55SGrant Likely 	regs = of_iomap(op->dev.of_node, 0);
396ca632f55SGrant Likely 	if (!regs)
397ca632f55SGrant Likely 		return -ENODEV;
398ca632f55SGrant Likely 
399ca632f55SGrant Likely 	/* initialize the device */
400ca632f55SGrant Likely 	ctrl1 = SPI_CTRL1_SPIE | SPI_CTRL1_SPE | SPI_CTRL1_MSTR;
401ca632f55SGrant Likely 	out_8(regs + SPI_CTRL1, ctrl1);
402ca632f55SGrant Likely 	out_8(regs + SPI_CTRL2, 0x0);
403ca632f55SGrant Likely 	out_8(regs + SPI_DATADIR, 0xe);	/* Set output pins */
404ca632f55SGrant Likely 	out_8(regs + SPI_PORTDATA, 0x8);	/* Deassert /SS signal */
405ca632f55SGrant Likely 
406ca632f55SGrant Likely 	/* Clear the status register and re-read it to check for a MODF
407ca632f55SGrant Likely 	 * failure.  This driver cannot currently handle multiple masters
408ca632f55SGrant Likely 	 * on the SPI bus.  This fault will also occur if the SPI signals
409ca632f55SGrant Likely 	 * are not connected to any pins (port_config setting) */
410ca632f55SGrant Likely 	in_8(regs + SPI_STATUS);
411ca632f55SGrant Likely 	out_8(regs + SPI_CTRL1, ctrl1);
412ca632f55SGrant Likely 
413ca632f55SGrant Likely 	in_8(regs + SPI_DATA);
414ca632f55SGrant Likely 	if (in_8(regs + SPI_STATUS) & SPI_STATUS_MODF) {
415ca632f55SGrant Likely 		dev_err(&op->dev, "mode fault; is port_config correct?\n");
416ca632f55SGrant Likely 		rc = -EIO;
417ca632f55SGrant Likely 		goto err_init;
418ca632f55SGrant Likely 	}
419ca632f55SGrant Likely 
420ca632f55SGrant Likely 	dev_dbg(&op->dev, "allocating spi_master struct\n");
421ac7357acSZhiqi Song 	master = spi_alloc_master(&op->dev, sizeof(*ms));
422ca632f55SGrant Likely 	if (!master) {
423ca632f55SGrant Likely 		rc = -ENOMEM;
424ca632f55SGrant Likely 		goto err_alloc;
425ca632f55SGrant Likely 	}
426ca632f55SGrant Likely 
427ca632f55SGrant Likely 	master->transfer = mpc52xx_spi_transfer;
428ca632f55SGrant Likely 	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
4295c5989ccSAxel Lin 	master->bits_per_word_mask = SPI_BPW_MASK(8);
430ca632f55SGrant Likely 	master->dev.of_node = op->dev.of_node;
431ca632f55SGrant Likely 
43224b5a82cSJingoo Han 	platform_set_drvdata(op, master);
433ca632f55SGrant Likely 
434ca632f55SGrant Likely 	ms = spi_master_get_devdata(master);
435ca632f55SGrant Likely 	ms->master = master;
436ca632f55SGrant Likely 	ms->regs = regs;
437ca632f55SGrant Likely 	ms->irq0 = irq_of_parse_and_map(op->dev.of_node, 0);
438ca632f55SGrant Likely 	ms->irq1 = irq_of_parse_and_map(op->dev.of_node, 1);
439ca632f55SGrant Likely 	ms->state = mpc52xx_spi_fsmstate_idle;
440ca632f55SGrant Likely 	ms->ipb_freq = mpc5xxx_get_bus_frequency(op->dev.of_node);
441ca632f55SGrant Likely 	ms->gpio_cs_count = of_gpio_count(op->dev.of_node);
442ca632f55SGrant Likely 	if (ms->gpio_cs_count > 0) {
443ca632f55SGrant Likely 		master->num_chipselect = ms->gpio_cs_count;
4448b6c8955SMarkus Elfring 		ms->gpio_cs = kmalloc_array(ms->gpio_cs_count,
4458b6c8955SMarkus Elfring 					    sizeof(*ms->gpio_cs),
446ca632f55SGrant Likely 					    GFP_KERNEL);
447ca632f55SGrant Likely 		if (!ms->gpio_cs) {
448ca632f55SGrant Likely 			rc = -ENOMEM;
449866c0f25SGuenter Roeck 			goto err_alloc_gpio;
450ca632f55SGrant Likely 		}
451ca632f55SGrant Likely 
452ca632f55SGrant Likely 		for (i = 0; i < ms->gpio_cs_count; i++) {
453ca632f55SGrant Likely 			gpio_cs = of_get_gpio(op->dev.of_node, i);
4540a090d65SArvind Yadav 			if (!gpio_is_valid(gpio_cs)) {
455ca632f55SGrant Likely 				dev_err(&op->dev,
4569c4f0440SMarkus Elfring 					"could not parse the gpio field in oftree\n");
457ca632f55SGrant Likely 				rc = -ENODEV;
458ca632f55SGrant Likely 				goto err_gpio;
459ca632f55SGrant Likely 			}
460ca632f55SGrant Likely 
461ca632f55SGrant Likely 			rc = gpio_request(gpio_cs, dev_name(&op->dev));
462ca632f55SGrant Likely 			if (rc) {
463ca632f55SGrant Likely 				dev_err(&op->dev,
4649c4f0440SMarkus Elfring 					"can't request spi cs gpio #%d on gpio line %d\n",
4659c4f0440SMarkus Elfring 					i, gpio_cs);
466ca632f55SGrant Likely 				goto err_gpio;
467ca632f55SGrant Likely 			}
468ca632f55SGrant Likely 
469ca632f55SGrant Likely 			gpio_direction_output(gpio_cs, 1);
470ca632f55SGrant Likely 			ms->gpio_cs[i] = gpio_cs;
471ca632f55SGrant Likely 		}
472ca632f55SGrant Likely 	}
473ca632f55SGrant Likely 
474ca632f55SGrant Likely 	spin_lock_init(&ms->lock);
475ca632f55SGrant Likely 	INIT_LIST_HEAD(&ms->queue);
476ca632f55SGrant Likely 	INIT_WORK(&ms->work, mpc52xx_spi_wq);
477ca632f55SGrant Likely 
478ca632f55SGrant Likely 	/* Decide if interrupts can be used */
479ca632f55SGrant Likely 	if (ms->irq0 && ms->irq1) {
480ca632f55SGrant Likely 		rc = request_irq(ms->irq0, mpc52xx_spi_irq, 0,
481ca632f55SGrant Likely 				  "mpc5200-spi-modf", ms);
482ca632f55SGrant Likely 		rc |= request_irq(ms->irq1, mpc52xx_spi_irq, 0,
483ca632f55SGrant Likely 				  "mpc5200-spi-spif", ms);
484ca632f55SGrant Likely 		if (rc) {
485ca632f55SGrant Likely 			free_irq(ms->irq0, ms);
486ca632f55SGrant Likely 			free_irq(ms->irq1, ms);
487ca632f55SGrant Likely 			ms->irq0 = ms->irq1 = 0;
488ca632f55SGrant Likely 		}
489ca632f55SGrant Likely 	} else {
490ca632f55SGrant Likely 		/* operate in polled mode */
491ca632f55SGrant Likely 		ms->irq0 = ms->irq1 = 0;
492ca632f55SGrant Likely 	}
493ca632f55SGrant Likely 
494ca632f55SGrant Likely 	if (!ms->irq0)
495ca632f55SGrant Likely 		dev_info(&op->dev, "using polled mode\n");
496ca632f55SGrant Likely 
497ca632f55SGrant Likely 	dev_dbg(&op->dev, "registering spi_master struct\n");
498ca632f55SGrant Likely 	rc = spi_register_master(master);
499ca632f55SGrant Likely 	if (rc)
500ca632f55SGrant Likely 		goto err_register;
501ca632f55SGrant Likely 
502ca632f55SGrant Likely 	dev_info(&ms->master->dev, "registered MPC5200 SPI bus\n");
503ca632f55SGrant Likely 
504ca632f55SGrant Likely 	return rc;
505ca632f55SGrant Likely 
506ca632f55SGrant Likely  err_register:
507ca632f55SGrant Likely 	dev_err(&ms->master->dev, "initialization failed\n");
508ca632f55SGrant Likely  err_gpio:
509ca632f55SGrant Likely 	while (i-- > 0)
510ca632f55SGrant Likely 		gpio_free(ms->gpio_cs[i]);
511ca632f55SGrant Likely 
512ca632f55SGrant Likely 	kfree(ms->gpio_cs);
513866c0f25SGuenter Roeck  err_alloc_gpio:
514866c0f25SGuenter Roeck 	spi_master_put(master);
515ca632f55SGrant Likely  err_alloc:
516ca632f55SGrant Likely  err_init:
517ca632f55SGrant Likely 	iounmap(regs);
518ca632f55SGrant Likely 	return rc;
519ca632f55SGrant Likely }
520ca632f55SGrant Likely 
521fd4a319bSGrant Likely static int mpc52xx_spi_remove(struct platform_device *op)
522ca632f55SGrant Likely {
52324b5a82cSJingoo Han 	struct spi_master *master = spi_master_get(platform_get_drvdata(op));
524ca632f55SGrant Likely 	struct mpc52xx_spi *ms = spi_master_get_devdata(master);
525ca632f55SGrant Likely 	int i;
526ca632f55SGrant Likely 
527ca632f55SGrant Likely 	free_irq(ms->irq0, ms);
528ca632f55SGrant Likely 	free_irq(ms->irq1, ms);
529ca632f55SGrant Likely 
530ca632f55SGrant Likely 	for (i = 0; i < ms->gpio_cs_count; i++)
531ca632f55SGrant Likely 		gpio_free(ms->gpio_cs[i]);
532ca632f55SGrant Likely 
533ca632f55SGrant Likely 	kfree(ms->gpio_cs);
534ca632f55SGrant Likely 	spi_unregister_master(master);
535ca632f55SGrant Likely 	iounmap(ms->regs);
536f95e1028SGuenter Roeck 	spi_master_put(master);
537ca632f55SGrant Likely 
538ca632f55SGrant Likely 	return 0;
539ca632f55SGrant Likely }
540ca632f55SGrant Likely 
541fd4a319bSGrant Likely static const struct of_device_id mpc52xx_spi_match[] = {
542ca632f55SGrant Likely 	{ .compatible = "fsl,mpc5200-spi", },
543ca632f55SGrant Likely 	{}
544ca632f55SGrant Likely };
545ca632f55SGrant Likely MODULE_DEVICE_TABLE(of, mpc52xx_spi_match);
546ca632f55SGrant Likely 
547ca632f55SGrant Likely static struct platform_driver mpc52xx_spi_of_driver = {
548ca632f55SGrant Likely 	.driver = {
549ca632f55SGrant Likely 		.name = "mpc52xx-spi",
550ca632f55SGrant Likely 		.of_match_table = mpc52xx_spi_match,
551ca632f55SGrant Likely 	},
552ca632f55SGrant Likely 	.probe = mpc52xx_spi_probe,
553fd4a319bSGrant Likely 	.remove = mpc52xx_spi_remove,
554ca632f55SGrant Likely };
555940ab889SGrant Likely module_platform_driver(mpc52xx_spi_of_driver);
556