155716d26SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2ca632f55SGrant Likely /*
3ca632f55SGrant Likely * MPC52xx SPI bus driver.
4ca632f55SGrant Likely *
5ca632f55SGrant Likely * Copyright (C) 2008 Secret Lab Technologies Ltd.
6ca632f55SGrant Likely *
7ca632f55SGrant Likely * This is the driver for the MPC5200's dedicated SPI controller.
8ca632f55SGrant Likely *
9ca632f55SGrant Likely * Note: this driver does not support the MPC5200 PSC in SPI mode. For
10ca632f55SGrant Likely * that driver see drivers/spi/mpc52xx_psc_spi.c
11ca632f55SGrant Likely */
12ca632f55SGrant Likely
13ca632f55SGrant Likely #include <linux/module.h>
142f3a896bSDmitry Torokhov #include <linux/err.h>
15ca632f55SGrant Likely #include <linux/errno.h>
16ca632f55SGrant Likely #include <linux/of_platform.h>
17ca632f55SGrant Likely #include <linux/interrupt.h>
18ca632f55SGrant Likely #include <linux/delay.h>
19a0c4b120SAndy Shevchenko #include <linux/gpio/consumer.h>
20ca632f55SGrant Likely #include <linux/spi/spi.h>
21ca632f55SGrant Likely #include <linux/io.h>
22ca632f55SGrant Likely #include <linux/slab.h>
2302b30248SChristophe Leroy #include <linux/of_address.h>
2402b30248SChristophe Leroy #include <linux/of_irq.h>
2502b30248SChristophe Leroy
26ca632f55SGrant Likely #include <asm/time.h>
27ca632f55SGrant Likely #include <asm/mpc52xx.h>
28ca632f55SGrant Likely
29ca632f55SGrant Likely MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
30ca632f55SGrant Likely MODULE_DESCRIPTION("MPC52xx SPI (non-PSC) Driver");
31ca632f55SGrant Likely MODULE_LICENSE("GPL");
32ca632f55SGrant Likely
33ca632f55SGrant Likely /* Register offsets */
34ca632f55SGrant Likely #define SPI_CTRL1 0x00
35ca632f55SGrant Likely #define SPI_CTRL1_SPIE (1 << 7)
36ca632f55SGrant Likely #define SPI_CTRL1_SPE (1 << 6)
37ca632f55SGrant Likely #define SPI_CTRL1_MSTR (1 << 4)
38ca632f55SGrant Likely #define SPI_CTRL1_CPOL (1 << 3)
39ca632f55SGrant Likely #define SPI_CTRL1_CPHA (1 << 2)
40ca632f55SGrant Likely #define SPI_CTRL1_SSOE (1 << 1)
41ca632f55SGrant Likely #define SPI_CTRL1_LSBFE (1 << 0)
42ca632f55SGrant Likely
43ca632f55SGrant Likely #define SPI_CTRL2 0x01
44ca632f55SGrant Likely #define SPI_BRR 0x04
45ca632f55SGrant Likely
46ca632f55SGrant Likely #define SPI_STATUS 0x05
47ca632f55SGrant Likely #define SPI_STATUS_SPIF (1 << 7)
48ca632f55SGrant Likely #define SPI_STATUS_WCOL (1 << 6)
49ca632f55SGrant Likely #define SPI_STATUS_MODF (1 << 4)
50ca632f55SGrant Likely
51ca632f55SGrant Likely #define SPI_DATA 0x09
52ca632f55SGrant Likely #define SPI_PORTDATA 0x0d
53ca632f55SGrant Likely #define SPI_DATADIR 0x10
54ca632f55SGrant Likely
55ca632f55SGrant Likely /* FSM state return values */
56ca632f55SGrant Likely #define FSM_STOP 0 /* Nothing more for the state machine to */
57ca632f55SGrant Likely /* do. If something interesting happens */
58ca632f55SGrant Likely /* then an IRQ will be received */
59ca632f55SGrant Likely #define FSM_POLL 1 /* need to poll for completion, an IRQ is */
60ca632f55SGrant Likely /* not expected */
61ca632f55SGrant Likely #define FSM_CONTINUE 2 /* Keep iterating the state machine */
62ca632f55SGrant Likely
63ca632f55SGrant Likely /* Driver internal data */
64ca632f55SGrant Likely struct mpc52xx_spi {
65ca632f55SGrant Likely struct spi_master *master;
66ca632f55SGrant Likely void __iomem *regs;
67ca632f55SGrant Likely int irq0; /* MODF irq */
68ca632f55SGrant Likely int irq1; /* SPIF irq */
69ca632f55SGrant Likely unsigned int ipb_freq;
70ca632f55SGrant Likely
71ca632f55SGrant Likely /* Statistics; not used now, but will be reintroduced for debugfs */
72ca632f55SGrant Likely int msg_count;
73ca632f55SGrant Likely int wcol_count;
74ca632f55SGrant Likely int wcol_ticks;
75ca632f55SGrant Likely u32 wcol_tx_timestamp;
76ca632f55SGrant Likely int modf_count;
77ca632f55SGrant Likely int byte_count;
78ca632f55SGrant Likely
79ca632f55SGrant Likely struct list_head queue; /* queue of pending messages */
80ca632f55SGrant Likely spinlock_t lock;
81ca632f55SGrant Likely struct work_struct work;
82ca632f55SGrant Likely
83ca632f55SGrant Likely /* Details of current transfer (length, and buffer pointers) */
84ca632f55SGrant Likely struct spi_message *message; /* current message */
85ca632f55SGrant Likely struct spi_transfer *transfer; /* current transfer */
86ca632f55SGrant Likely int (*state)(int irq, struct mpc52xx_spi *ms, u8 status, u8 data);
87ca632f55SGrant Likely int len;
88ca632f55SGrant Likely int timestamp;
89ca632f55SGrant Likely u8 *rx_buf;
90ca632f55SGrant Likely const u8 *tx_buf;
91ca632f55SGrant Likely int cs_change;
92ca632f55SGrant Likely int gpio_cs_count;
932f3a896bSDmitry Torokhov struct gpio_desc **gpio_cs;
94ca632f55SGrant Likely };
95ca632f55SGrant Likely
96ca632f55SGrant Likely /*
97ca632f55SGrant Likely * CS control function
98ca632f55SGrant Likely */
mpc52xx_spi_chipsel(struct mpc52xx_spi * ms,int value)99ca632f55SGrant Likely static void mpc52xx_spi_chipsel(struct mpc52xx_spi *ms, int value)
100ca632f55SGrant Likely {
101ca632f55SGrant Likely int cs;
102ca632f55SGrant Likely
103ca632f55SGrant Likely if (ms->gpio_cs_count > 0) {
104*9e264f3fSAmit Kumar Mahapatra via Alsa-devel cs = spi_get_chipselect(ms->message->spi, 0);
1052f3a896bSDmitry Torokhov gpiod_set_value(ms->gpio_cs[cs], value);
1062f3a896bSDmitry Torokhov } else {
107ca632f55SGrant Likely out_8(ms->regs + SPI_PORTDATA, value ? 0 : 0x08);
108ca632f55SGrant Likely }
1092f3a896bSDmitry Torokhov }
110ca632f55SGrant Likely
111ca632f55SGrant Likely /*
112ca632f55SGrant Likely * Start a new transfer. This is called both by the idle state
113ca632f55SGrant Likely * for the first transfer in a message, and by the wait state when the
114ca632f55SGrant Likely * previous transfer in a message is complete.
115ca632f55SGrant Likely */
mpc52xx_spi_start_transfer(struct mpc52xx_spi * ms)116ca632f55SGrant Likely static void mpc52xx_spi_start_transfer(struct mpc52xx_spi *ms)
117ca632f55SGrant Likely {
118ca632f55SGrant Likely ms->rx_buf = ms->transfer->rx_buf;
119ca632f55SGrant Likely ms->tx_buf = ms->transfer->tx_buf;
120ca632f55SGrant Likely ms->len = ms->transfer->len;
121ca632f55SGrant Likely
122ca632f55SGrant Likely /* Activate the chip select */
123ca632f55SGrant Likely if (ms->cs_change)
124ca632f55SGrant Likely mpc52xx_spi_chipsel(ms, 1);
125ca632f55SGrant Likely ms->cs_change = ms->transfer->cs_change;
126ca632f55SGrant Likely
127ca632f55SGrant Likely /* Write out the first byte */
128e1065611SChristophe Leroy ms->wcol_tx_timestamp = mftb();
129ca632f55SGrant Likely if (ms->tx_buf)
130ca632f55SGrant Likely out_8(ms->regs + SPI_DATA, *ms->tx_buf++);
131ca632f55SGrant Likely else
132ca632f55SGrant Likely out_8(ms->regs + SPI_DATA, 0);
133ca632f55SGrant Likely }
134ca632f55SGrant Likely
135ca632f55SGrant Likely /* Forward declaration of state handlers */
136ca632f55SGrant Likely static int mpc52xx_spi_fsmstate_transfer(int irq, struct mpc52xx_spi *ms,
137ca632f55SGrant Likely u8 status, u8 data);
138ca632f55SGrant Likely static int mpc52xx_spi_fsmstate_wait(int irq, struct mpc52xx_spi *ms,
139ca632f55SGrant Likely u8 status, u8 data);
140ca632f55SGrant Likely
141ca632f55SGrant Likely /*
142ca632f55SGrant Likely * IDLE state
143ca632f55SGrant Likely *
144ca632f55SGrant Likely * No transfers are in progress; if another transfer is pending then retrieve
145ca632f55SGrant Likely * it and kick it off. Otherwise, stop processing the state machine
146ca632f55SGrant Likely */
147ca632f55SGrant Likely static int
mpc52xx_spi_fsmstate_idle(int irq,struct mpc52xx_spi * ms,u8 status,u8 data)148ca632f55SGrant Likely mpc52xx_spi_fsmstate_idle(int irq, struct mpc52xx_spi *ms, u8 status, u8 data)
149ca632f55SGrant Likely {
150ca632f55SGrant Likely struct spi_device *spi;
151ca632f55SGrant Likely int spr, sppr;
152ca632f55SGrant Likely u8 ctrl1;
153ca632f55SGrant Likely
154b25fe93fSChristophe Leroy if (status && irq)
155ca632f55SGrant Likely dev_err(&ms->master->dev, "spurious irq, status=0x%.2x\n",
156ca632f55SGrant Likely status);
157ca632f55SGrant Likely
158ca632f55SGrant Likely /* Check if there is another transfer waiting. */
159ca632f55SGrant Likely if (list_empty(&ms->queue))
160ca632f55SGrant Likely return FSM_STOP;
161ca632f55SGrant Likely
162ca632f55SGrant Likely /* get the head of the queue */
163ca632f55SGrant Likely ms->message = list_first_entry(&ms->queue, struct spi_message, queue);
164ca632f55SGrant Likely list_del_init(&ms->message->queue);
165ca632f55SGrant Likely
166ca632f55SGrant Likely /* Setup the controller parameters */
167ca632f55SGrant Likely ctrl1 = SPI_CTRL1_SPIE | SPI_CTRL1_SPE | SPI_CTRL1_MSTR;
168ca632f55SGrant Likely spi = ms->message->spi;
169ca632f55SGrant Likely if (spi->mode & SPI_CPHA)
170ca632f55SGrant Likely ctrl1 |= SPI_CTRL1_CPHA;
171ca632f55SGrant Likely if (spi->mode & SPI_CPOL)
172ca632f55SGrant Likely ctrl1 |= SPI_CTRL1_CPOL;
173ca632f55SGrant Likely if (spi->mode & SPI_LSB_FIRST)
174ca632f55SGrant Likely ctrl1 |= SPI_CTRL1_LSBFE;
175ca632f55SGrant Likely out_8(ms->regs + SPI_CTRL1, ctrl1);
176ca632f55SGrant Likely
177ca632f55SGrant Likely /* Setup the controller speed */
178ca632f55SGrant Likely /* minimum divider is '2'. Also, add '1' to force rounding the
179ca632f55SGrant Likely * divider up. */
180ca632f55SGrant Likely sppr = ((ms->ipb_freq / ms->message->spi->max_speed_hz) + 1) >> 1;
181ca632f55SGrant Likely spr = 0;
182ca632f55SGrant Likely if (sppr < 1)
183ca632f55SGrant Likely sppr = 1;
184ca632f55SGrant Likely while (((sppr - 1) & ~0x7) != 0) {
185ca632f55SGrant Likely sppr = (sppr + 1) >> 1; /* add '1' to force rounding up */
186ca632f55SGrant Likely spr++;
187ca632f55SGrant Likely }
188ca632f55SGrant Likely sppr--; /* sppr quantity in register is offset by 1 */
189ca632f55SGrant Likely if (spr > 7) {
190ca632f55SGrant Likely /* Don't overrun limits of SPI baudrate register */
191ca632f55SGrant Likely spr = 7;
192ca632f55SGrant Likely sppr = 7;
193ca632f55SGrant Likely }
194ca632f55SGrant Likely out_8(ms->regs + SPI_BRR, sppr << 4 | spr); /* Set speed */
195ca632f55SGrant Likely
196ca632f55SGrant Likely ms->cs_change = 1;
197ca632f55SGrant Likely ms->transfer = container_of(ms->message->transfers.next,
198ca632f55SGrant Likely struct spi_transfer, transfer_list);
199ca632f55SGrant Likely
200ca632f55SGrant Likely mpc52xx_spi_start_transfer(ms);
201ca632f55SGrant Likely ms->state = mpc52xx_spi_fsmstate_transfer;
202ca632f55SGrant Likely
203ca632f55SGrant Likely return FSM_CONTINUE;
204ca632f55SGrant Likely }
205ca632f55SGrant Likely
206ca632f55SGrant Likely /*
207ca632f55SGrant Likely * TRANSFER state
208ca632f55SGrant Likely *
209ca632f55SGrant Likely * In the middle of a transfer. If the SPI core has completed processing
210ca632f55SGrant Likely * a byte, then read out the received data and write out the next byte
211ca632f55SGrant Likely * (unless this transfer is finished; in which case go on to the wait
212ca632f55SGrant Likely * state)
213ca632f55SGrant Likely */
mpc52xx_spi_fsmstate_transfer(int irq,struct mpc52xx_spi * ms,u8 status,u8 data)214ca632f55SGrant Likely static int mpc52xx_spi_fsmstate_transfer(int irq, struct mpc52xx_spi *ms,
215ca632f55SGrant Likely u8 status, u8 data)
216ca632f55SGrant Likely {
217ca632f55SGrant Likely if (!status)
218ca632f55SGrant Likely return ms->irq0 ? FSM_STOP : FSM_POLL;
219ca632f55SGrant Likely
220ca632f55SGrant Likely if (status & SPI_STATUS_WCOL) {
221ca632f55SGrant Likely /* The SPI controller is stoopid. At slower speeds, it may
222ca632f55SGrant Likely * raise the SPIF flag before the state machine is actually
223ca632f55SGrant Likely * finished, which causes a collision (internal to the state
224ca632f55SGrant Likely * machine only). The manual recommends inserting a delay
225ca632f55SGrant Likely * between receiving the interrupt and sending the next byte,
226ca632f55SGrant Likely * but it can also be worked around simply by retrying the
227ca632f55SGrant Likely * transfer which is what we do here. */
228ca632f55SGrant Likely ms->wcol_count++;
229e1065611SChristophe Leroy ms->wcol_ticks += mftb() - ms->wcol_tx_timestamp;
230e1065611SChristophe Leroy ms->wcol_tx_timestamp = mftb();
231ca632f55SGrant Likely data = 0;
232ca632f55SGrant Likely if (ms->tx_buf)
233ca632f55SGrant Likely data = *(ms->tx_buf - 1);
234ca632f55SGrant Likely out_8(ms->regs + SPI_DATA, data); /* try again */
235ca632f55SGrant Likely return FSM_CONTINUE;
236ca632f55SGrant Likely } else if (status & SPI_STATUS_MODF) {
237ca632f55SGrant Likely ms->modf_count++;
238ca632f55SGrant Likely dev_err(&ms->master->dev, "mode fault\n");
239ca632f55SGrant Likely mpc52xx_spi_chipsel(ms, 0);
240ca632f55SGrant Likely ms->message->status = -EIO;
2410a6d3879SAxel Lin if (ms->message->complete)
242ca632f55SGrant Likely ms->message->complete(ms->message->context);
243ca632f55SGrant Likely ms->state = mpc52xx_spi_fsmstate_idle;
244ca632f55SGrant Likely return FSM_CONTINUE;
245ca632f55SGrant Likely }
246ca632f55SGrant Likely
247ca632f55SGrant Likely /* Read data out of the spi device */
248ca632f55SGrant Likely ms->byte_count++;
249ca632f55SGrant Likely if (ms->rx_buf)
250ca632f55SGrant Likely *ms->rx_buf++ = data;
251ca632f55SGrant Likely
252ca632f55SGrant Likely /* Is the transfer complete? */
253ca632f55SGrant Likely ms->len--;
254ca632f55SGrant Likely if (ms->len == 0) {
255e1065611SChristophe Leroy ms->timestamp = mftb();
256258ea99fSSergiu Cuciurean if (ms->transfer->delay.unit == SPI_DELAY_UNIT_USECS)
257258ea99fSSergiu Cuciurean ms->timestamp += ms->transfer->delay.value *
258258ea99fSSergiu Cuciurean tb_ticks_per_usec;
259ca632f55SGrant Likely ms->state = mpc52xx_spi_fsmstate_wait;
260ca632f55SGrant Likely return FSM_CONTINUE;
261ca632f55SGrant Likely }
262ca632f55SGrant Likely
263ca632f55SGrant Likely /* Write out the next byte */
264e1065611SChristophe Leroy ms->wcol_tx_timestamp = mftb();
265ca632f55SGrant Likely if (ms->tx_buf)
266ca632f55SGrant Likely out_8(ms->regs + SPI_DATA, *ms->tx_buf++);
267ca632f55SGrant Likely else
268ca632f55SGrant Likely out_8(ms->regs + SPI_DATA, 0);
269ca632f55SGrant Likely
270ca632f55SGrant Likely return FSM_CONTINUE;
271ca632f55SGrant Likely }
272ca632f55SGrant Likely
273ca632f55SGrant Likely /*
274ca632f55SGrant Likely * WAIT state
275ca632f55SGrant Likely *
276ca632f55SGrant Likely * A transfer has completed; need to wait for the delay period to complete
277ca632f55SGrant Likely * before starting the next transfer
278ca632f55SGrant Likely */
279ca632f55SGrant Likely static int
mpc52xx_spi_fsmstate_wait(int irq,struct mpc52xx_spi * ms,u8 status,u8 data)280ca632f55SGrant Likely mpc52xx_spi_fsmstate_wait(int irq, struct mpc52xx_spi *ms, u8 status, u8 data)
281ca632f55SGrant Likely {
282ca632f55SGrant Likely if (status && irq)
283ca632f55SGrant Likely dev_err(&ms->master->dev, "spurious irq, status=0x%.2x\n",
284ca632f55SGrant Likely status);
285ca632f55SGrant Likely
286e1065611SChristophe Leroy if (((int)mftb()) - ms->timestamp < 0)
287ca632f55SGrant Likely return FSM_POLL;
288ca632f55SGrant Likely
289ca632f55SGrant Likely ms->message->actual_length += ms->transfer->len;
290ca632f55SGrant Likely
291ca632f55SGrant Likely /* Check if there is another transfer in this message. If there
292ca632f55SGrant Likely * aren't then deactivate CS, notify sender, and drop back to idle
293ca632f55SGrant Likely * to start the next message. */
294ca632f55SGrant Likely if (ms->transfer->transfer_list.next == &ms->message->transfers) {
295ca632f55SGrant Likely ms->msg_count++;
296ca632f55SGrant Likely mpc52xx_spi_chipsel(ms, 0);
297ca632f55SGrant Likely ms->message->status = 0;
2980a6d3879SAxel Lin if (ms->message->complete)
299ca632f55SGrant Likely ms->message->complete(ms->message->context);
300ca632f55SGrant Likely ms->state = mpc52xx_spi_fsmstate_idle;
301ca632f55SGrant Likely return FSM_CONTINUE;
302ca632f55SGrant Likely }
303ca632f55SGrant Likely
304ca632f55SGrant Likely /* There is another transfer; kick it off */
305ca632f55SGrant Likely
306ca632f55SGrant Likely if (ms->cs_change)
307ca632f55SGrant Likely mpc52xx_spi_chipsel(ms, 0);
308ca632f55SGrant Likely
309ca632f55SGrant Likely ms->transfer = container_of(ms->transfer->transfer_list.next,
310ca632f55SGrant Likely struct spi_transfer, transfer_list);
311ca632f55SGrant Likely mpc52xx_spi_start_transfer(ms);
312ca632f55SGrant Likely ms->state = mpc52xx_spi_fsmstate_transfer;
313ca632f55SGrant Likely return FSM_CONTINUE;
314ca632f55SGrant Likely }
315ca632f55SGrant Likely
316ca632f55SGrant Likely /**
317ca632f55SGrant Likely * mpc52xx_spi_fsm_process - Finite State Machine iteration function
318ca632f55SGrant Likely * @irq: irq number that triggered the FSM or 0 for polling
319ca632f55SGrant Likely * @ms: pointer to mpc52xx_spi driver data
320ca632f55SGrant Likely */
mpc52xx_spi_fsm_process(int irq,struct mpc52xx_spi * ms)321ca632f55SGrant Likely static void mpc52xx_spi_fsm_process(int irq, struct mpc52xx_spi *ms)
322ca632f55SGrant Likely {
323ca632f55SGrant Likely int rc = FSM_CONTINUE;
324ca632f55SGrant Likely u8 status, data;
325ca632f55SGrant Likely
326ca632f55SGrant Likely while (rc == FSM_CONTINUE) {
327ca632f55SGrant Likely /* Interrupt cleared by read of STATUS followed by
328ca632f55SGrant Likely * read of DATA registers */
329ca632f55SGrant Likely status = in_8(ms->regs + SPI_STATUS);
330ca632f55SGrant Likely data = in_8(ms->regs + SPI_DATA);
331ca632f55SGrant Likely rc = ms->state(irq, ms, status, data);
332ca632f55SGrant Likely }
333ca632f55SGrant Likely
334ca632f55SGrant Likely if (rc == FSM_POLL)
335ca632f55SGrant Likely schedule_work(&ms->work);
336ca632f55SGrant Likely }
337ca632f55SGrant Likely
338ca632f55SGrant Likely /**
339ca632f55SGrant Likely * mpc52xx_spi_irq - IRQ handler
340ca632f55SGrant Likely */
mpc52xx_spi_irq(int irq,void * _ms)341ca632f55SGrant Likely static irqreturn_t mpc52xx_spi_irq(int irq, void *_ms)
342ca632f55SGrant Likely {
343ca632f55SGrant Likely struct mpc52xx_spi *ms = _ms;
344ca632f55SGrant Likely spin_lock(&ms->lock);
345ca632f55SGrant Likely mpc52xx_spi_fsm_process(irq, ms);
346ca632f55SGrant Likely spin_unlock(&ms->lock);
347ca632f55SGrant Likely return IRQ_HANDLED;
348ca632f55SGrant Likely }
349ca632f55SGrant Likely
350ca632f55SGrant Likely /**
351ca632f55SGrant Likely * mpc52xx_spi_wq - Workqueue function for polling the state machine
352ca632f55SGrant Likely */
mpc52xx_spi_wq(struct work_struct * work)353ca632f55SGrant Likely static void mpc52xx_spi_wq(struct work_struct *work)
354ca632f55SGrant Likely {
355ca632f55SGrant Likely struct mpc52xx_spi *ms = container_of(work, struct mpc52xx_spi, work);
356ca632f55SGrant Likely unsigned long flags;
357ca632f55SGrant Likely
358ca632f55SGrant Likely spin_lock_irqsave(&ms->lock, flags);
359ca632f55SGrant Likely mpc52xx_spi_fsm_process(0, ms);
360ca632f55SGrant Likely spin_unlock_irqrestore(&ms->lock, flags);
361ca632f55SGrant Likely }
362ca632f55SGrant Likely
363ca632f55SGrant Likely /*
364ca632f55SGrant Likely * spi_master ops
365ca632f55SGrant Likely */
366ca632f55SGrant Likely
mpc52xx_spi_transfer(struct spi_device * spi,struct spi_message * m)367ca632f55SGrant Likely static int mpc52xx_spi_transfer(struct spi_device *spi, struct spi_message *m)
368ca632f55SGrant Likely {
369ca632f55SGrant Likely struct mpc52xx_spi *ms = spi_master_get_devdata(spi->master);
370ca632f55SGrant Likely unsigned long flags;
371ca632f55SGrant Likely
372ca632f55SGrant Likely m->actual_length = 0;
373ca632f55SGrant Likely m->status = -EINPROGRESS;
374ca632f55SGrant Likely
375ca632f55SGrant Likely spin_lock_irqsave(&ms->lock, flags);
376ca632f55SGrant Likely list_add_tail(&m->queue, &ms->queue);
377ca632f55SGrant Likely spin_unlock_irqrestore(&ms->lock, flags);
378ca632f55SGrant Likely schedule_work(&ms->work);
379ca632f55SGrant Likely
380ca632f55SGrant Likely return 0;
381ca632f55SGrant Likely }
382ca632f55SGrant Likely
383ca632f55SGrant Likely /*
384ca632f55SGrant Likely * OF Platform Bus Binding
385ca632f55SGrant Likely */
mpc52xx_spi_probe(struct platform_device * op)386fd4a319bSGrant Likely static int mpc52xx_spi_probe(struct platform_device *op)
387ca632f55SGrant Likely {
388ca632f55SGrant Likely struct spi_master *master;
389ca632f55SGrant Likely struct mpc52xx_spi *ms;
3902f3a896bSDmitry Torokhov struct gpio_desc *gpio_cs;
391ca632f55SGrant Likely void __iomem *regs;
392ca632f55SGrant Likely u8 ctrl1;
393ca632f55SGrant Likely int rc, i = 0;
394ca632f55SGrant Likely
395ca632f55SGrant Likely /* MMIO registers */
396ca632f55SGrant Likely dev_dbg(&op->dev, "probing mpc5200 SPI device\n");
397ca632f55SGrant Likely regs = of_iomap(op->dev.of_node, 0);
398ca632f55SGrant Likely if (!regs)
399ca632f55SGrant Likely return -ENODEV;
400ca632f55SGrant Likely
401ca632f55SGrant Likely /* initialize the device */
402ca632f55SGrant Likely ctrl1 = SPI_CTRL1_SPIE | SPI_CTRL1_SPE | SPI_CTRL1_MSTR;
403ca632f55SGrant Likely out_8(regs + SPI_CTRL1, ctrl1);
404ca632f55SGrant Likely out_8(regs + SPI_CTRL2, 0x0);
405ca632f55SGrant Likely out_8(regs + SPI_DATADIR, 0xe); /* Set output pins */
406ca632f55SGrant Likely out_8(regs + SPI_PORTDATA, 0x8); /* Deassert /SS signal */
407ca632f55SGrant Likely
408ca632f55SGrant Likely /* Clear the status register and re-read it to check for a MODF
409ca632f55SGrant Likely * failure. This driver cannot currently handle multiple masters
410ca632f55SGrant Likely * on the SPI bus. This fault will also occur if the SPI signals
411ca632f55SGrant Likely * are not connected to any pins (port_config setting) */
412ca632f55SGrant Likely in_8(regs + SPI_STATUS);
413ca632f55SGrant Likely out_8(regs + SPI_CTRL1, ctrl1);
414ca632f55SGrant Likely
415ca632f55SGrant Likely in_8(regs + SPI_DATA);
416ca632f55SGrant Likely if (in_8(regs + SPI_STATUS) & SPI_STATUS_MODF) {
417ca632f55SGrant Likely dev_err(&op->dev, "mode fault; is port_config correct?\n");
418ca632f55SGrant Likely rc = -EIO;
419ca632f55SGrant Likely goto err_init;
420ca632f55SGrant Likely }
421ca632f55SGrant Likely
422ca632f55SGrant Likely dev_dbg(&op->dev, "allocating spi_master struct\n");
423ac7357acSZhiqi Song master = spi_alloc_master(&op->dev, sizeof(*ms));
424ca632f55SGrant Likely if (!master) {
425ca632f55SGrant Likely rc = -ENOMEM;
426ca632f55SGrant Likely goto err_alloc;
427ca632f55SGrant Likely }
428ca632f55SGrant Likely
429ca632f55SGrant Likely master->transfer = mpc52xx_spi_transfer;
430ca632f55SGrant Likely master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
4315c5989ccSAxel Lin master->bits_per_word_mask = SPI_BPW_MASK(8);
432ca632f55SGrant Likely master->dev.of_node = op->dev.of_node;
433ca632f55SGrant Likely
43424b5a82cSJingoo Han platform_set_drvdata(op, master);
435ca632f55SGrant Likely
436ca632f55SGrant Likely ms = spi_master_get_devdata(master);
437ca632f55SGrant Likely ms->master = master;
438ca632f55SGrant Likely ms->regs = regs;
439ca632f55SGrant Likely ms->irq0 = irq_of_parse_and_map(op->dev.of_node, 0);
440ca632f55SGrant Likely ms->irq1 = irq_of_parse_and_map(op->dev.of_node, 1);
441ca632f55SGrant Likely ms->state = mpc52xx_spi_fsmstate_idle;
442de06fba6SAndy Shevchenko ms->ipb_freq = mpc5xxx_get_bus_frequency(&op->dev);
443a0c4b120SAndy Shevchenko ms->gpio_cs_count = gpiod_count(&op->dev, NULL);
444ca632f55SGrant Likely if (ms->gpio_cs_count > 0) {
445ca632f55SGrant Likely master->num_chipselect = ms->gpio_cs_count;
4468b6c8955SMarkus Elfring ms->gpio_cs = kmalloc_array(ms->gpio_cs_count,
4478b6c8955SMarkus Elfring sizeof(*ms->gpio_cs),
448ca632f55SGrant Likely GFP_KERNEL);
449ca632f55SGrant Likely if (!ms->gpio_cs) {
450ca632f55SGrant Likely rc = -ENOMEM;
451866c0f25SGuenter Roeck goto err_alloc_gpio;
452ca632f55SGrant Likely }
453ca632f55SGrant Likely
454ca632f55SGrant Likely for (i = 0; i < ms->gpio_cs_count; i++) {
4552f3a896bSDmitry Torokhov gpio_cs = gpiod_get_index(&op->dev,
4562f3a896bSDmitry Torokhov NULL, i, GPIOD_OUT_LOW);
4572f3a896bSDmitry Torokhov rc = PTR_ERR_OR_ZERO(gpio_cs);
458ca632f55SGrant Likely if (rc) {
459ca632f55SGrant Likely dev_err(&op->dev,
4602f3a896bSDmitry Torokhov "failed to get spi cs gpio #%d: %d\n",
4612f3a896bSDmitry Torokhov i, rc);
462ca632f55SGrant Likely goto err_gpio;
463ca632f55SGrant Likely }
464ca632f55SGrant Likely
465ca632f55SGrant Likely ms->gpio_cs[i] = gpio_cs;
466ca632f55SGrant Likely }
467ca632f55SGrant Likely }
468ca632f55SGrant Likely
469ca632f55SGrant Likely spin_lock_init(&ms->lock);
470ca632f55SGrant Likely INIT_LIST_HEAD(&ms->queue);
471ca632f55SGrant Likely INIT_WORK(&ms->work, mpc52xx_spi_wq);
472ca632f55SGrant Likely
473ca632f55SGrant Likely /* Decide if interrupts can be used */
474ca632f55SGrant Likely if (ms->irq0 && ms->irq1) {
475ca632f55SGrant Likely rc = request_irq(ms->irq0, mpc52xx_spi_irq, 0,
476ca632f55SGrant Likely "mpc5200-spi-modf", ms);
477ca632f55SGrant Likely rc |= request_irq(ms->irq1, mpc52xx_spi_irq, 0,
478ca632f55SGrant Likely "mpc5200-spi-spif", ms);
479ca632f55SGrant Likely if (rc) {
480ca632f55SGrant Likely free_irq(ms->irq0, ms);
481ca632f55SGrant Likely free_irq(ms->irq1, ms);
482ca632f55SGrant Likely ms->irq0 = ms->irq1 = 0;
483ca632f55SGrant Likely }
484ca632f55SGrant Likely } else {
485ca632f55SGrant Likely /* operate in polled mode */
486ca632f55SGrant Likely ms->irq0 = ms->irq1 = 0;
487ca632f55SGrant Likely }
488ca632f55SGrant Likely
489ca632f55SGrant Likely if (!ms->irq0)
490ca632f55SGrant Likely dev_info(&op->dev, "using polled mode\n");
491ca632f55SGrant Likely
492ca632f55SGrant Likely dev_dbg(&op->dev, "registering spi_master struct\n");
493ca632f55SGrant Likely rc = spi_register_master(master);
494ca632f55SGrant Likely if (rc)
495ca632f55SGrant Likely goto err_register;
496ca632f55SGrant Likely
497ca632f55SGrant Likely dev_info(&ms->master->dev, "registered MPC5200 SPI bus\n");
498ca632f55SGrant Likely
499ca632f55SGrant Likely return rc;
500ca632f55SGrant Likely
501ca632f55SGrant Likely err_register:
502ca632f55SGrant Likely dev_err(&ms->master->dev, "initialization failed\n");
503ca632f55SGrant Likely err_gpio:
504ca632f55SGrant Likely while (i-- > 0)
5052f3a896bSDmitry Torokhov gpiod_put(ms->gpio_cs[i]);
506ca632f55SGrant Likely
507ca632f55SGrant Likely kfree(ms->gpio_cs);
508866c0f25SGuenter Roeck err_alloc_gpio:
509866c0f25SGuenter Roeck spi_master_put(master);
510ca632f55SGrant Likely err_alloc:
511ca632f55SGrant Likely err_init:
512ca632f55SGrant Likely iounmap(regs);
513ca632f55SGrant Likely return rc;
514ca632f55SGrant Likely }
515ca632f55SGrant Likely
mpc52xx_spi_remove(struct platform_device * op)5163fa689a8SUwe Kleine-König static void mpc52xx_spi_remove(struct platform_device *op)
517ca632f55SGrant Likely {
51824b5a82cSJingoo Han struct spi_master *master = spi_master_get(platform_get_drvdata(op));
519ca632f55SGrant Likely struct mpc52xx_spi *ms = spi_master_get_devdata(master);
520ca632f55SGrant Likely int i;
521ca632f55SGrant Likely
522ca632f55SGrant Likely free_irq(ms->irq0, ms);
523ca632f55SGrant Likely free_irq(ms->irq1, ms);
524ca632f55SGrant Likely
525ca632f55SGrant Likely for (i = 0; i < ms->gpio_cs_count; i++)
5262f3a896bSDmitry Torokhov gpiod_put(ms->gpio_cs[i]);
527ca632f55SGrant Likely
528ca632f55SGrant Likely kfree(ms->gpio_cs);
529ca632f55SGrant Likely spi_unregister_master(master);
530ca632f55SGrant Likely iounmap(ms->regs);
531f95e1028SGuenter Roeck spi_master_put(master);
532ca632f55SGrant Likely }
533ca632f55SGrant Likely
534fd4a319bSGrant Likely static const struct of_device_id mpc52xx_spi_match[] = {
535ca632f55SGrant Likely { .compatible = "fsl,mpc5200-spi", },
536ca632f55SGrant Likely {}
537ca632f55SGrant Likely };
538ca632f55SGrant Likely MODULE_DEVICE_TABLE(of, mpc52xx_spi_match);
539ca632f55SGrant Likely
540ca632f55SGrant Likely static struct platform_driver mpc52xx_spi_of_driver = {
541ca632f55SGrant Likely .driver = {
542ca632f55SGrant Likely .name = "mpc52xx-spi",
543ca632f55SGrant Likely .of_match_table = mpc52xx_spi_match,
544ca632f55SGrant Likely },
545ca632f55SGrant Likely .probe = mpc52xx_spi_probe,
5463fa689a8SUwe Kleine-König .remove_new = mpc52xx_spi_remove,
547ca632f55SGrant Likely };
548940ab889SGrant Likely module_platform_driver(mpc52xx_spi_of_driver);
549