1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * MPC512x PSC in SPI mode driver. 4 * 5 * Copyright (C) 2007,2008 Freescale Semiconductor Inc. 6 * Original port from 52xx driver: 7 * Hongjun Chen <hong-jun.chen@freescale.com> 8 * 9 * Fork of mpc52xx_psc_spi.c: 10 * Copyright (C) 2006 TOPTICA Photonics AG., Dragos Carp 11 */ 12 13 #include <linux/module.h> 14 #include <linux/kernel.h> 15 #include <linux/errno.h> 16 #include <linux/interrupt.h> 17 #include <linux/completion.h> 18 #include <linux/io.h> 19 #include <linux/platform_device.h> 20 #include <linux/property.h> 21 #include <linux/delay.h> 22 #include <linux/clk.h> 23 #include <linux/spi/spi.h> 24 #include <asm/mpc52xx_psc.h> 25 26 enum { 27 TYPE_MPC5121, 28 TYPE_MPC5125, 29 }; 30 31 /* 32 * This macro abstracts the differences in the PSC register layout between 33 * MPC5121 (which uses a struct mpc52xx_psc) and MPC5125 (using mpc5125_psc). 34 */ 35 #define psc_addr(mps, regname) ({ \ 36 void *__ret = NULL; \ 37 switch (mps->type) { \ 38 case TYPE_MPC5121: { \ 39 struct mpc52xx_psc __iomem *psc = mps->psc; \ 40 __ret = &psc->regname; \ 41 }; \ 42 break; \ 43 case TYPE_MPC5125: { \ 44 struct mpc5125_psc __iomem *psc = mps->psc; \ 45 __ret = &psc->regname; \ 46 }; \ 47 break; \ 48 } \ 49 __ret; }) 50 51 struct mpc512x_psc_spi { 52 /* driver internal data */ 53 int type; 54 void __iomem *psc; 55 struct mpc512x_psc_fifo __iomem *fifo; 56 int irq; 57 u8 bits_per_word; 58 u32 mclk_rate; 59 60 struct completion txisrdone; 61 }; 62 63 /* controller state */ 64 struct mpc512x_psc_spi_cs { 65 int bits_per_word; 66 int speed_hz; 67 }; 68 69 /* set clock freq, clock ramp, bits per work 70 * if t is NULL then reset the values to the default values 71 */ 72 static int mpc512x_psc_spi_transfer_setup(struct spi_device *spi, 73 struct spi_transfer *t) 74 { 75 struct mpc512x_psc_spi_cs *cs = spi->controller_state; 76 77 cs->speed_hz = (t && t->speed_hz) 78 ? t->speed_hz : spi->max_speed_hz; 79 cs->bits_per_word = (t && t->bits_per_word) 80 ? t->bits_per_word : spi->bits_per_word; 81 cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8; 82 return 0; 83 } 84 85 static void mpc512x_psc_spi_activate_cs(struct spi_device *spi) 86 { 87 struct mpc512x_psc_spi_cs *cs = spi->controller_state; 88 struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master); 89 u32 sicr; 90 u32 ccr; 91 int speed; 92 u16 bclkdiv; 93 94 sicr = in_be32(psc_addr(mps, sicr)); 95 96 /* Set clock phase and polarity */ 97 if (spi->mode & SPI_CPHA) 98 sicr |= 0x00001000; 99 else 100 sicr &= ~0x00001000; 101 102 if (spi->mode & SPI_CPOL) 103 sicr |= 0x00002000; 104 else 105 sicr &= ~0x00002000; 106 107 if (spi->mode & SPI_LSB_FIRST) 108 sicr |= 0x10000000; 109 else 110 sicr &= ~0x10000000; 111 out_be32(psc_addr(mps, sicr), sicr); 112 113 ccr = in_be32(psc_addr(mps, ccr)); 114 ccr &= 0xFF000000; 115 speed = cs->speed_hz; 116 if (!speed) 117 speed = 1000000; /* default 1MHz */ 118 bclkdiv = (mps->mclk_rate / speed) - 1; 119 120 ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8)); 121 out_be32(psc_addr(mps, ccr), ccr); 122 mps->bits_per_word = cs->bits_per_word; 123 124 if (spi_get_csgpiod(spi, 0)) { 125 /* gpiolib will deal with the inversion */ 126 gpiod_set_value(spi_get_csgpiod(spi, 0), 1); 127 } 128 } 129 130 static void mpc512x_psc_spi_deactivate_cs(struct spi_device *spi) 131 { 132 if (spi_get_csgpiod(spi, 0)) { 133 /* gpiolib will deal with the inversion */ 134 gpiod_set_value(spi_get_csgpiod(spi, 0), 0); 135 } 136 } 137 138 /* extract and scale size field in txsz or rxsz */ 139 #define MPC512x_PSC_FIFO_SZ(sz) ((sz & 0x7ff) << 2); 140 141 #define EOFBYTE 1 142 143 static int mpc512x_psc_spi_transfer_rxtx(struct spi_device *spi, 144 struct spi_transfer *t) 145 { 146 struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master); 147 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo; 148 size_t tx_len = t->len; 149 size_t rx_len = t->len; 150 u8 *tx_buf = (u8 *)t->tx_buf; 151 u8 *rx_buf = (u8 *)t->rx_buf; 152 153 if (!tx_buf && !rx_buf && t->len) 154 return -EINVAL; 155 156 while (rx_len || tx_len) { 157 size_t txcount; 158 u8 data; 159 size_t fifosz; 160 size_t rxcount; 161 int rxtries; 162 163 /* 164 * send the TX bytes in as large a chunk as possible 165 * but neither exceed the TX nor the RX FIFOs 166 */ 167 fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->txsz)); 168 txcount = min(fifosz, tx_len); 169 fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->rxsz)); 170 fifosz -= in_be32(&fifo->rxcnt) + 1; 171 txcount = min(fifosz, txcount); 172 if (txcount) { 173 174 /* fill the TX FIFO */ 175 while (txcount-- > 0) { 176 data = tx_buf ? *tx_buf++ : 0; 177 if (tx_len == EOFBYTE && t->cs_change) 178 setbits32(&fifo->txcmd, 179 MPC512x_PSC_FIFO_EOF); 180 out_8(&fifo->txdata_8, data); 181 tx_len--; 182 } 183 184 /* have the ISR trigger when the TX FIFO is empty */ 185 reinit_completion(&mps->txisrdone); 186 out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY); 187 out_be32(&fifo->tximr, MPC512x_PSC_FIFO_EMPTY); 188 wait_for_completion(&mps->txisrdone); 189 } 190 191 /* 192 * consume as much RX data as the FIFO holds, while we 193 * iterate over the transfer's TX data length 194 * 195 * only insist in draining all the remaining RX bytes 196 * when the TX bytes were exhausted (that's at the very 197 * end of this transfer, not when still iterating over 198 * the transfer's chunks) 199 */ 200 rxtries = 50; 201 do { 202 203 /* 204 * grab whatever was in the FIFO when we started 205 * looking, don't bother fetching what was added to 206 * the FIFO while we read from it -- we'll return 207 * here eventually and prefer sending out remaining 208 * TX data 209 */ 210 fifosz = in_be32(&fifo->rxcnt); 211 rxcount = min(fifosz, rx_len); 212 while (rxcount-- > 0) { 213 data = in_8(&fifo->rxdata_8); 214 if (rx_buf) 215 *rx_buf++ = data; 216 rx_len--; 217 } 218 219 /* 220 * come back later if there still is TX data to send, 221 * bail out of the RX drain loop if all of the TX data 222 * was sent and all of the RX data was received (i.e. 223 * when the transmission has completed) 224 */ 225 if (tx_len) 226 break; 227 if (!rx_len) 228 break; 229 230 /* 231 * TX data transmission has completed while RX data 232 * is still pending -- that's a transient situation 233 * which depends on wire speed and specific 234 * hardware implementation details (buffering) yet 235 * should resolve very quickly 236 * 237 * just yield for a moment to not hog the CPU for 238 * too long when running SPI at low speed 239 * 240 * the timeout range is rather arbitrary and tries 241 * to balance throughput against system load; the 242 * chosen values result in a minimal timeout of 50 243 * times 10us and thus work at speeds as low as 244 * some 20kbps, while the maximum timeout at the 245 * transfer's end could be 5ms _if_ nothing else 246 * ticks in the system _and_ RX data still wasn't 247 * received, which only occurs in situations that 248 * are exceptional; removing the unpredictability 249 * of the timeout either decreases throughput 250 * (longer timeouts), or puts more load on the 251 * system (fixed short timeouts) or requires the 252 * use of a timeout API instead of a counter and an 253 * unknown inner delay 254 */ 255 usleep_range(10, 100); 256 257 } while (--rxtries > 0); 258 if (!tx_len && rx_len && !rxtries) { 259 /* 260 * not enough RX bytes even after several retries 261 * and the resulting rather long timeout? 262 */ 263 rxcount = in_be32(&fifo->rxcnt); 264 dev_warn(&spi->dev, 265 "short xfer, missing %zd RX bytes, FIFO level %zd\n", 266 rx_len, rxcount); 267 } 268 269 /* 270 * drain and drop RX data which "should not be there" in 271 * the first place, for undisturbed transmission this turns 272 * into a NOP (except for the FIFO level fetch) 273 */ 274 if (!tx_len && !rx_len) { 275 while (in_be32(&fifo->rxcnt)) 276 in_8(&fifo->rxdata_8); 277 } 278 279 } 280 return 0; 281 } 282 283 static int mpc512x_psc_spi_msg_xfer(struct spi_master *master, 284 struct spi_message *m) 285 { 286 struct spi_device *spi; 287 unsigned cs_change; 288 int status; 289 struct spi_transfer *t; 290 291 spi = m->spi; 292 cs_change = 1; 293 status = 0; 294 list_for_each_entry(t, &m->transfers, transfer_list) { 295 status = mpc512x_psc_spi_transfer_setup(spi, t); 296 if (status < 0) 297 break; 298 299 if (cs_change) 300 mpc512x_psc_spi_activate_cs(spi); 301 cs_change = t->cs_change; 302 303 status = mpc512x_psc_spi_transfer_rxtx(spi, t); 304 if (status) 305 break; 306 m->actual_length += t->len; 307 308 spi_transfer_delay_exec(t); 309 310 if (cs_change) 311 mpc512x_psc_spi_deactivate_cs(spi); 312 } 313 314 m->status = status; 315 if (m->complete) 316 m->complete(m->context); 317 318 if (status || !cs_change) 319 mpc512x_psc_spi_deactivate_cs(spi); 320 321 mpc512x_psc_spi_transfer_setup(spi, NULL); 322 323 spi_finalize_current_message(master); 324 return status; 325 } 326 327 static int mpc512x_psc_spi_prep_xfer_hw(struct spi_master *master) 328 { 329 struct mpc512x_psc_spi *mps = spi_master_get_devdata(master); 330 331 dev_dbg(&master->dev, "%s()\n", __func__); 332 333 /* Zero MR2 */ 334 in_8(psc_addr(mps, mr2)); 335 out_8(psc_addr(mps, mr2), 0x0); 336 337 /* enable transmitter/receiver */ 338 out_8(psc_addr(mps, command), MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE); 339 340 return 0; 341 } 342 343 static int mpc512x_psc_spi_unprep_xfer_hw(struct spi_master *master) 344 { 345 struct mpc512x_psc_spi *mps = spi_master_get_devdata(master); 346 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo; 347 348 dev_dbg(&master->dev, "%s()\n", __func__); 349 350 /* disable transmitter/receiver and fifo interrupt */ 351 out_8(psc_addr(mps, command), MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE); 352 out_be32(&fifo->tximr, 0); 353 354 return 0; 355 } 356 357 static int mpc512x_psc_spi_setup(struct spi_device *spi) 358 { 359 struct mpc512x_psc_spi_cs *cs = spi->controller_state; 360 361 if (spi->bits_per_word % 8) 362 return -EINVAL; 363 364 if (!cs) { 365 cs = kzalloc(sizeof(*cs), GFP_KERNEL); 366 if (!cs) 367 return -ENOMEM; 368 369 spi->controller_state = cs; 370 } 371 372 cs->bits_per_word = spi->bits_per_word; 373 cs->speed_hz = spi->max_speed_hz; 374 375 return 0; 376 } 377 378 static void mpc512x_psc_spi_cleanup(struct spi_device *spi) 379 { 380 kfree(spi->controller_state); 381 } 382 383 static int mpc512x_psc_spi_port_config(struct spi_master *master, 384 struct mpc512x_psc_spi *mps) 385 { 386 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo; 387 u32 sicr; 388 u32 ccr; 389 int speed; 390 u16 bclkdiv; 391 392 /* Reset the PSC into a known state */ 393 out_8(psc_addr(mps, command), MPC52xx_PSC_RST_RX); 394 out_8(psc_addr(mps, command), MPC52xx_PSC_RST_TX); 395 out_8(psc_addr(mps, command), MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE); 396 397 /* Disable psc interrupts all useful interrupts are in fifo */ 398 out_be16(psc_addr(mps, isr_imr.imr), 0); 399 400 /* Disable fifo interrupts, will be enabled later */ 401 out_be32(&fifo->tximr, 0); 402 out_be32(&fifo->rximr, 0); 403 404 /* Setup fifo slice address and size */ 405 /*out_be32(&fifo->txsz, 0x0fe00004);*/ 406 /*out_be32(&fifo->rxsz, 0x0ff00004);*/ 407 408 sicr = 0x01000000 | /* SIM = 0001 -- 8 bit */ 409 0x00800000 | /* GenClk = 1 -- internal clk */ 410 0x00008000 | /* SPI = 1 */ 411 0x00004000 | /* MSTR = 1 -- SPI master */ 412 0x00000800; /* UseEOF = 1 -- SS low until EOF */ 413 414 out_be32(psc_addr(mps, sicr), sicr); 415 416 ccr = in_be32(psc_addr(mps, ccr)); 417 ccr &= 0xFF000000; 418 speed = 1000000; /* default 1MHz */ 419 bclkdiv = (mps->mclk_rate / speed) - 1; 420 ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8)); 421 out_be32(psc_addr(mps, ccr), ccr); 422 423 /* Set 2ms DTL delay */ 424 out_8(psc_addr(mps, ctur), 0x00); 425 out_8(psc_addr(mps, ctlr), 0x82); 426 427 /* we don't use the alarms */ 428 out_be32(&fifo->rxalarm, 0xfff); 429 out_be32(&fifo->txalarm, 0); 430 431 /* Enable FIFO slices for Rx/Tx */ 432 out_be32(&fifo->rxcmd, 433 MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA); 434 out_be32(&fifo->txcmd, 435 MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA); 436 437 mps->bits_per_word = 8; 438 439 return 0; 440 } 441 442 static irqreturn_t mpc512x_psc_spi_isr(int irq, void *dev_id) 443 { 444 struct mpc512x_psc_spi *mps = (struct mpc512x_psc_spi *)dev_id; 445 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo; 446 447 /* clear interrupt and wake up the rx/tx routine */ 448 if (in_be32(&fifo->txisr) & 449 in_be32(&fifo->tximr) & MPC512x_PSC_FIFO_EMPTY) { 450 out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY); 451 out_be32(&fifo->tximr, 0); 452 complete(&mps->txisrdone); 453 return IRQ_HANDLED; 454 } 455 return IRQ_NONE; 456 } 457 458 static int mpc512x_psc_spi_of_probe(struct platform_device *pdev) 459 { 460 struct device *dev = &pdev->dev; 461 struct mpc512x_psc_spi *mps; 462 struct spi_master *master; 463 int ret; 464 void *tempp; 465 struct clk *clk; 466 467 master = devm_spi_alloc_master(dev, sizeof(*mps)); 468 if (master == NULL) 469 return -ENOMEM; 470 471 dev_set_drvdata(dev, master); 472 mps = spi_master_get_devdata(master); 473 mps->type = (int)device_get_match_data(dev); 474 475 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; 476 master->setup = mpc512x_psc_spi_setup; 477 master->prepare_transfer_hardware = mpc512x_psc_spi_prep_xfer_hw; 478 master->transfer_one_message = mpc512x_psc_spi_msg_xfer; 479 master->unprepare_transfer_hardware = mpc512x_psc_spi_unprep_xfer_hw; 480 master->use_gpio_descriptors = true; 481 master->cleanup = mpc512x_psc_spi_cleanup; 482 483 device_set_node(&master->dev, dev_fwnode(dev)); 484 485 tempp = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); 486 if (IS_ERR(tempp)) 487 return dev_err_probe(dev, PTR_ERR(tempp), "could not ioremap I/O port range\n"); 488 mps->psc = tempp; 489 mps->fifo = 490 (struct mpc512x_psc_fifo *)(tempp + sizeof(struct mpc52xx_psc)); 491 492 mps->irq = platform_get_irq(pdev, 0); 493 if (mps->irq < 0) 494 return mps->irq; 495 496 ret = devm_request_irq(dev, mps->irq, mpc512x_psc_spi_isr, IRQF_SHARED, 497 "mpc512x-psc-spi", mps); 498 if (ret) 499 return ret; 500 init_completion(&mps->txisrdone); 501 502 clk = devm_clk_get_enabled(dev, "mclk"); 503 if (IS_ERR(clk)) 504 return PTR_ERR(clk); 505 506 mps->mclk_rate = clk_get_rate(clk); 507 508 clk = devm_clk_get_enabled(dev, "ipg"); 509 if (IS_ERR(clk)) 510 return PTR_ERR(clk); 511 512 ret = mpc512x_psc_spi_port_config(master, mps); 513 if (ret < 0) 514 return ret; 515 516 return devm_spi_register_master(dev, master); 517 } 518 519 static const struct of_device_id mpc512x_psc_spi_of_match[] = { 520 { .compatible = "fsl,mpc5121-psc-spi", .data = (void *)TYPE_MPC5121 }, 521 { .compatible = "fsl,mpc5125-psc-spi", .data = (void *)TYPE_MPC5125 }, 522 {}, 523 }; 524 525 MODULE_DEVICE_TABLE(of, mpc512x_psc_spi_of_match); 526 527 static struct platform_driver mpc512x_psc_spi_of_driver = { 528 .probe = mpc512x_psc_spi_of_probe, 529 .driver = { 530 .name = "mpc512x-psc-spi", 531 .of_match_table = mpc512x_psc_spi_of_match, 532 }, 533 }; 534 module_platform_driver(mpc512x_psc_spi_of_driver); 535 536 MODULE_AUTHOR("John Rigby"); 537 MODULE_DESCRIPTION("MPC512x PSC SPI Driver"); 538 MODULE_LICENSE("GPL"); 539