1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * MPC512x PSC in SPI mode driver. 4 * 5 * Copyright (C) 2007,2008 Freescale Semiconductor Inc. 6 * Original port from 52xx driver: 7 * Hongjun Chen <hong-jun.chen@freescale.com> 8 * 9 * Fork of mpc52xx_psc_spi.c: 10 * Copyright (C) 2006 TOPTICA Photonics AG., Dragos Carp 11 */ 12 13 #include <linux/module.h> 14 #include <linux/kernel.h> 15 #include <linux/errno.h> 16 #include <linux/interrupt.h> 17 #include <linux/of_address.h> 18 #include <linux/of_irq.h> 19 #include <linux/of_platform.h> 20 #include <linux/completion.h> 21 #include <linux/io.h> 22 #include <linux/delay.h> 23 #include <linux/clk.h> 24 #include <linux/spi/spi.h> 25 #include <linux/fsl_devices.h> 26 #include <asm/mpc52xx_psc.h> 27 28 enum { 29 TYPE_MPC5121, 30 TYPE_MPC5125, 31 }; 32 33 /* 34 * This macro abstracts the differences in the PSC register layout between 35 * MPC5121 (which uses a struct mpc52xx_psc) and MPC5125 (using mpc5125_psc). 36 */ 37 #define psc_addr(mps, regname) ({ \ 38 void *__ret = NULL; \ 39 switch (mps->type) { \ 40 case TYPE_MPC5121: { \ 41 struct mpc52xx_psc __iomem *psc = mps->psc; \ 42 __ret = &psc->regname; \ 43 }; \ 44 break; \ 45 case TYPE_MPC5125: { \ 46 struct mpc5125_psc __iomem *psc = mps->psc; \ 47 __ret = &psc->regname; \ 48 }; \ 49 break; \ 50 } \ 51 __ret; }) 52 53 struct mpc512x_psc_spi { 54 void (*cs_control)(struct spi_device *spi, bool on); 55 56 /* driver internal data */ 57 int type; 58 void __iomem *psc; 59 struct mpc512x_psc_fifo __iomem *fifo; 60 unsigned int irq; 61 u8 bits_per_word; 62 struct clk *clk_mclk; 63 struct clk *clk_ipg; 64 u32 mclk_rate; 65 66 struct completion txisrdone; 67 }; 68 69 /* controller state */ 70 struct mpc512x_psc_spi_cs { 71 int bits_per_word; 72 int speed_hz; 73 }; 74 75 /* set clock freq, clock ramp, bits per work 76 * if t is NULL then reset the values to the default values 77 */ 78 static int mpc512x_psc_spi_transfer_setup(struct spi_device *spi, 79 struct spi_transfer *t) 80 { 81 struct mpc512x_psc_spi_cs *cs = spi->controller_state; 82 83 cs->speed_hz = (t && t->speed_hz) 84 ? t->speed_hz : spi->max_speed_hz; 85 cs->bits_per_word = (t && t->bits_per_word) 86 ? t->bits_per_word : spi->bits_per_word; 87 cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8; 88 return 0; 89 } 90 91 static void mpc512x_psc_spi_activate_cs(struct spi_device *spi) 92 { 93 struct mpc512x_psc_spi_cs *cs = spi->controller_state; 94 struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master); 95 u32 sicr; 96 u32 ccr; 97 int speed; 98 u16 bclkdiv; 99 100 sicr = in_be32(psc_addr(mps, sicr)); 101 102 /* Set clock phase and polarity */ 103 if (spi->mode & SPI_CPHA) 104 sicr |= 0x00001000; 105 else 106 sicr &= ~0x00001000; 107 108 if (spi->mode & SPI_CPOL) 109 sicr |= 0x00002000; 110 else 111 sicr &= ~0x00002000; 112 113 if (spi->mode & SPI_LSB_FIRST) 114 sicr |= 0x10000000; 115 else 116 sicr &= ~0x10000000; 117 out_be32(psc_addr(mps, sicr), sicr); 118 119 ccr = in_be32(psc_addr(mps, ccr)); 120 ccr &= 0xFF000000; 121 speed = cs->speed_hz; 122 if (!speed) 123 speed = 1000000; /* default 1MHz */ 124 bclkdiv = (mps->mclk_rate / speed) - 1; 125 126 ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8)); 127 out_be32(psc_addr(mps, ccr), ccr); 128 mps->bits_per_word = cs->bits_per_word; 129 130 if (spi->cs_gpiod) { 131 if (mps->cs_control) 132 /* boardfile override */ 133 mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 1 : 0); 134 else 135 /* gpiolib will deal with the inversion */ 136 gpiod_set_value(spi->cs_gpiod, 1); 137 } 138 } 139 140 static void mpc512x_psc_spi_deactivate_cs(struct spi_device *spi) 141 { 142 struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master); 143 144 if (spi->cs_gpiod) { 145 if (mps->cs_control) 146 /* boardfile override */ 147 mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 0 : 1); 148 else 149 /* gpiolib will deal with the inversion */ 150 gpiod_set_value(spi->cs_gpiod, 0); 151 } 152 } 153 154 /* extract and scale size field in txsz or rxsz */ 155 #define MPC512x_PSC_FIFO_SZ(sz) ((sz & 0x7ff) << 2); 156 157 #define EOFBYTE 1 158 159 static int mpc512x_psc_spi_transfer_rxtx(struct spi_device *spi, 160 struct spi_transfer *t) 161 { 162 struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master); 163 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo; 164 size_t tx_len = t->len; 165 size_t rx_len = t->len; 166 u8 *tx_buf = (u8 *)t->tx_buf; 167 u8 *rx_buf = (u8 *)t->rx_buf; 168 169 if (!tx_buf && !rx_buf && t->len) 170 return -EINVAL; 171 172 while (rx_len || tx_len) { 173 size_t txcount; 174 u8 data; 175 size_t fifosz; 176 size_t rxcount; 177 int rxtries; 178 179 /* 180 * send the TX bytes in as large a chunk as possible 181 * but neither exceed the TX nor the RX FIFOs 182 */ 183 fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->txsz)); 184 txcount = min(fifosz, tx_len); 185 fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->rxsz)); 186 fifosz -= in_be32(&fifo->rxcnt) + 1; 187 txcount = min(fifosz, txcount); 188 if (txcount) { 189 190 /* fill the TX FIFO */ 191 while (txcount-- > 0) { 192 data = tx_buf ? *tx_buf++ : 0; 193 if (tx_len == EOFBYTE && t->cs_change) 194 setbits32(&fifo->txcmd, 195 MPC512x_PSC_FIFO_EOF); 196 out_8(&fifo->txdata_8, data); 197 tx_len--; 198 } 199 200 /* have the ISR trigger when the TX FIFO is empty */ 201 reinit_completion(&mps->txisrdone); 202 out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY); 203 out_be32(&fifo->tximr, MPC512x_PSC_FIFO_EMPTY); 204 wait_for_completion(&mps->txisrdone); 205 } 206 207 /* 208 * consume as much RX data as the FIFO holds, while we 209 * iterate over the transfer's TX data length 210 * 211 * only insist in draining all the remaining RX bytes 212 * when the TX bytes were exhausted (that's at the very 213 * end of this transfer, not when still iterating over 214 * the transfer's chunks) 215 */ 216 rxtries = 50; 217 do { 218 219 /* 220 * grab whatever was in the FIFO when we started 221 * looking, don't bother fetching what was added to 222 * the FIFO while we read from it -- we'll return 223 * here eventually and prefer sending out remaining 224 * TX data 225 */ 226 fifosz = in_be32(&fifo->rxcnt); 227 rxcount = min(fifosz, rx_len); 228 while (rxcount-- > 0) { 229 data = in_8(&fifo->rxdata_8); 230 if (rx_buf) 231 *rx_buf++ = data; 232 rx_len--; 233 } 234 235 /* 236 * come back later if there still is TX data to send, 237 * bail out of the RX drain loop if all of the TX data 238 * was sent and all of the RX data was received (i.e. 239 * when the transmission has completed) 240 */ 241 if (tx_len) 242 break; 243 if (!rx_len) 244 break; 245 246 /* 247 * TX data transmission has completed while RX data 248 * is still pending -- that's a transient situation 249 * which depends on wire speed and specific 250 * hardware implementation details (buffering) yet 251 * should resolve very quickly 252 * 253 * just yield for a moment to not hog the CPU for 254 * too long when running SPI at low speed 255 * 256 * the timeout range is rather arbitrary and tries 257 * to balance throughput against system load; the 258 * chosen values result in a minimal timeout of 50 259 * times 10us and thus work at speeds as low as 260 * some 20kbps, while the maximum timeout at the 261 * transfer's end could be 5ms _if_ nothing else 262 * ticks in the system _and_ RX data still wasn't 263 * received, which only occurs in situations that 264 * are exceptional; removing the unpredictability 265 * of the timeout either decreases throughput 266 * (longer timeouts), or puts more load on the 267 * system (fixed short timeouts) or requires the 268 * use of a timeout API instead of a counter and an 269 * unknown inner delay 270 */ 271 usleep_range(10, 100); 272 273 } while (--rxtries > 0); 274 if (!tx_len && rx_len && !rxtries) { 275 /* 276 * not enough RX bytes even after several retries 277 * and the resulting rather long timeout? 278 */ 279 rxcount = in_be32(&fifo->rxcnt); 280 dev_warn(&spi->dev, 281 "short xfer, missing %zd RX bytes, FIFO level %zd\n", 282 rx_len, rxcount); 283 } 284 285 /* 286 * drain and drop RX data which "should not be there" in 287 * the first place, for undisturbed transmission this turns 288 * into a NOP (except for the FIFO level fetch) 289 */ 290 if (!tx_len && !rx_len) { 291 while (in_be32(&fifo->rxcnt)) 292 in_8(&fifo->rxdata_8); 293 } 294 295 } 296 return 0; 297 } 298 299 static int mpc512x_psc_spi_msg_xfer(struct spi_master *master, 300 struct spi_message *m) 301 { 302 struct spi_device *spi; 303 unsigned cs_change; 304 int status; 305 struct spi_transfer *t; 306 307 spi = m->spi; 308 cs_change = 1; 309 status = 0; 310 list_for_each_entry(t, &m->transfers, transfer_list) { 311 status = mpc512x_psc_spi_transfer_setup(spi, t); 312 if (status < 0) 313 break; 314 315 if (cs_change) 316 mpc512x_psc_spi_activate_cs(spi); 317 cs_change = t->cs_change; 318 319 status = mpc512x_psc_spi_transfer_rxtx(spi, t); 320 if (status) 321 break; 322 m->actual_length += t->len; 323 324 spi_transfer_delay_exec(t); 325 326 if (cs_change) 327 mpc512x_psc_spi_deactivate_cs(spi); 328 } 329 330 m->status = status; 331 if (m->complete) 332 m->complete(m->context); 333 334 if (status || !cs_change) 335 mpc512x_psc_spi_deactivate_cs(spi); 336 337 mpc512x_psc_spi_transfer_setup(spi, NULL); 338 339 spi_finalize_current_message(master); 340 return status; 341 } 342 343 static int mpc512x_psc_spi_prep_xfer_hw(struct spi_master *master) 344 { 345 struct mpc512x_psc_spi *mps = spi_master_get_devdata(master); 346 347 dev_dbg(&master->dev, "%s()\n", __func__); 348 349 /* Zero MR2 */ 350 in_8(psc_addr(mps, mr2)); 351 out_8(psc_addr(mps, mr2), 0x0); 352 353 /* enable transmitter/receiver */ 354 out_8(psc_addr(mps, command), MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE); 355 356 return 0; 357 } 358 359 static int mpc512x_psc_spi_unprep_xfer_hw(struct spi_master *master) 360 { 361 struct mpc512x_psc_spi *mps = spi_master_get_devdata(master); 362 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo; 363 364 dev_dbg(&master->dev, "%s()\n", __func__); 365 366 /* disable transmitter/receiver and fifo interrupt */ 367 out_8(psc_addr(mps, command), MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE); 368 out_be32(&fifo->tximr, 0); 369 370 return 0; 371 } 372 373 static int mpc512x_psc_spi_setup(struct spi_device *spi) 374 { 375 struct mpc512x_psc_spi_cs *cs = spi->controller_state; 376 377 if (spi->bits_per_word % 8) 378 return -EINVAL; 379 380 if (!cs) { 381 cs = kzalloc(sizeof(*cs), GFP_KERNEL); 382 if (!cs) 383 return -ENOMEM; 384 385 spi->controller_state = cs; 386 } 387 388 cs->bits_per_word = spi->bits_per_word; 389 cs->speed_hz = spi->max_speed_hz; 390 391 return 0; 392 } 393 394 static void mpc512x_psc_spi_cleanup(struct spi_device *spi) 395 { 396 kfree(spi->controller_state); 397 } 398 399 static int mpc512x_psc_spi_port_config(struct spi_master *master, 400 struct mpc512x_psc_spi *mps) 401 { 402 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo; 403 u32 sicr; 404 u32 ccr; 405 int speed; 406 u16 bclkdiv; 407 408 /* Reset the PSC into a known state */ 409 out_8(psc_addr(mps, command), MPC52xx_PSC_RST_RX); 410 out_8(psc_addr(mps, command), MPC52xx_PSC_RST_TX); 411 out_8(psc_addr(mps, command), MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE); 412 413 /* Disable psc interrupts all useful interrupts are in fifo */ 414 out_be16(psc_addr(mps, isr_imr.imr), 0); 415 416 /* Disable fifo interrupts, will be enabled later */ 417 out_be32(&fifo->tximr, 0); 418 out_be32(&fifo->rximr, 0); 419 420 /* Setup fifo slice address and size */ 421 /*out_be32(&fifo->txsz, 0x0fe00004);*/ 422 /*out_be32(&fifo->rxsz, 0x0ff00004);*/ 423 424 sicr = 0x01000000 | /* SIM = 0001 -- 8 bit */ 425 0x00800000 | /* GenClk = 1 -- internal clk */ 426 0x00008000 | /* SPI = 1 */ 427 0x00004000 | /* MSTR = 1 -- SPI master */ 428 0x00000800; /* UseEOF = 1 -- SS low until EOF */ 429 430 out_be32(psc_addr(mps, sicr), sicr); 431 432 ccr = in_be32(psc_addr(mps, ccr)); 433 ccr &= 0xFF000000; 434 speed = 1000000; /* default 1MHz */ 435 bclkdiv = (mps->mclk_rate / speed) - 1; 436 ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8)); 437 out_be32(psc_addr(mps, ccr), ccr); 438 439 /* Set 2ms DTL delay */ 440 out_8(psc_addr(mps, ctur), 0x00); 441 out_8(psc_addr(mps, ctlr), 0x82); 442 443 /* we don't use the alarms */ 444 out_be32(&fifo->rxalarm, 0xfff); 445 out_be32(&fifo->txalarm, 0); 446 447 /* Enable FIFO slices for Rx/Tx */ 448 out_be32(&fifo->rxcmd, 449 MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA); 450 out_be32(&fifo->txcmd, 451 MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA); 452 453 mps->bits_per_word = 8; 454 455 return 0; 456 } 457 458 static irqreturn_t mpc512x_psc_spi_isr(int irq, void *dev_id) 459 { 460 struct mpc512x_psc_spi *mps = (struct mpc512x_psc_spi *)dev_id; 461 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo; 462 463 /* clear interrupt and wake up the rx/tx routine */ 464 if (in_be32(&fifo->txisr) & 465 in_be32(&fifo->tximr) & MPC512x_PSC_FIFO_EMPTY) { 466 out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY); 467 out_be32(&fifo->tximr, 0); 468 complete(&mps->txisrdone); 469 return IRQ_HANDLED; 470 } 471 return IRQ_NONE; 472 } 473 474 static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr, 475 u32 size, unsigned int irq) 476 { 477 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); 478 struct mpc512x_psc_spi *mps; 479 struct spi_master *master; 480 int ret; 481 void *tempp; 482 struct clk *clk; 483 484 master = spi_alloc_master(dev, sizeof(*mps)); 485 if (master == NULL) 486 return -ENOMEM; 487 488 dev_set_drvdata(dev, master); 489 mps = spi_master_get_devdata(master); 490 mps->type = (int)of_device_get_match_data(dev); 491 mps->irq = irq; 492 493 if (pdata) { 494 mps->cs_control = pdata->cs_control; 495 master->bus_num = pdata->bus_num; 496 master->num_chipselect = pdata->max_chipselect; 497 } 498 499 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; 500 master->setup = mpc512x_psc_spi_setup; 501 master->prepare_transfer_hardware = mpc512x_psc_spi_prep_xfer_hw; 502 master->transfer_one_message = mpc512x_psc_spi_msg_xfer; 503 master->unprepare_transfer_hardware = mpc512x_psc_spi_unprep_xfer_hw; 504 master->use_gpio_descriptors = true; 505 master->cleanup = mpc512x_psc_spi_cleanup; 506 master->dev.of_node = dev->of_node; 507 508 tempp = devm_ioremap(dev, regaddr, size); 509 if (!tempp) { 510 dev_err(dev, "could not ioremap I/O port range\n"); 511 ret = -EFAULT; 512 goto free_master; 513 } 514 mps->psc = tempp; 515 mps->fifo = 516 (struct mpc512x_psc_fifo *)(tempp + sizeof(struct mpc52xx_psc)); 517 ret = devm_request_irq(dev, mps->irq, mpc512x_psc_spi_isr, IRQF_SHARED, 518 "mpc512x-psc-spi", mps); 519 if (ret) 520 goto free_master; 521 init_completion(&mps->txisrdone); 522 523 clk = devm_clk_get(dev, "mclk"); 524 if (IS_ERR(clk)) { 525 ret = PTR_ERR(clk); 526 goto free_master; 527 } 528 ret = clk_prepare_enable(clk); 529 if (ret) 530 goto free_master; 531 mps->clk_mclk = clk; 532 mps->mclk_rate = clk_get_rate(clk); 533 534 clk = devm_clk_get(dev, "ipg"); 535 if (IS_ERR(clk)) { 536 ret = PTR_ERR(clk); 537 goto free_mclk_clock; 538 } 539 ret = clk_prepare_enable(clk); 540 if (ret) 541 goto free_mclk_clock; 542 mps->clk_ipg = clk; 543 544 ret = mpc512x_psc_spi_port_config(master, mps); 545 if (ret < 0) 546 goto free_ipg_clock; 547 548 ret = devm_spi_register_master(dev, master); 549 if (ret < 0) 550 goto free_ipg_clock; 551 552 return ret; 553 554 free_ipg_clock: 555 clk_disable_unprepare(mps->clk_ipg); 556 free_mclk_clock: 557 clk_disable_unprepare(mps->clk_mclk); 558 free_master: 559 spi_master_put(master); 560 561 return ret; 562 } 563 564 static int mpc512x_psc_spi_do_remove(struct device *dev) 565 { 566 struct spi_master *master = dev_get_drvdata(dev); 567 struct mpc512x_psc_spi *mps = spi_master_get_devdata(master); 568 569 clk_disable_unprepare(mps->clk_mclk); 570 clk_disable_unprepare(mps->clk_ipg); 571 572 return 0; 573 } 574 575 static int mpc512x_psc_spi_of_probe(struct platform_device *op) 576 { 577 const u32 *regaddr_p; 578 u64 regaddr64, size64; 579 580 regaddr_p = of_get_address(op->dev.of_node, 0, &size64, NULL); 581 if (!regaddr_p) { 582 dev_err(&op->dev, "Invalid PSC address\n"); 583 return -EINVAL; 584 } 585 regaddr64 = of_translate_address(op->dev.of_node, regaddr_p); 586 587 return mpc512x_psc_spi_do_probe(&op->dev, (u32) regaddr64, (u32) size64, 588 irq_of_parse_and_map(op->dev.of_node, 0)); 589 } 590 591 static int mpc512x_psc_spi_of_remove(struct platform_device *op) 592 { 593 return mpc512x_psc_spi_do_remove(&op->dev); 594 } 595 596 static const struct of_device_id mpc512x_psc_spi_of_match[] = { 597 { .compatible = "fsl,mpc5121-psc-spi", .data = (void *)TYPE_MPC5121 }, 598 { .compatible = "fsl,mpc5125-psc-spi", .data = (void *)TYPE_MPC5125 }, 599 {}, 600 }; 601 602 MODULE_DEVICE_TABLE(of, mpc512x_psc_spi_of_match); 603 604 static struct platform_driver mpc512x_psc_spi_of_driver = { 605 .probe = mpc512x_psc_spi_of_probe, 606 .remove = mpc512x_psc_spi_of_remove, 607 .driver = { 608 .name = "mpc512x-psc-spi", 609 .of_match_table = mpc512x_psc_spi_of_match, 610 }, 611 }; 612 module_platform_driver(mpc512x_psc_spi_of_driver); 613 614 MODULE_AUTHOR("John Rigby"); 615 MODULE_DESCRIPTION("MPC512x PSC SPI Driver"); 616 MODULE_LICENSE("GPL"); 617