1 // SPDX-License-Identifier: (GPL-2.0) 2 /* 3 * Microchip CoreSPI SPI controller driver 4 * 5 * Copyright (c) 2018-2022 Microchip Technology Inc. and its subsidiaries 6 * 7 * Author: Daire McNamara <daire.mcnamara@microchip.com> 8 * Author: Conor Dooley <conor.dooley@microchip.com> 9 * 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/err.h> 15 #include <linux/init.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/platform_device.h> 21 #include <linux/spi/spi.h> 22 23 #define MAX_LEN (0xffff) 24 #define MAX_CS (8) 25 #define DEFAULT_FRAMESIZE (8) 26 #define FIFO_DEPTH (32) 27 #define CLK_GEN_MODE1_MAX (255) 28 #define CLK_GEN_MODE0_MAX (15) 29 #define CLK_GEN_MIN (0) 30 #define MODE_X_MASK_SHIFT (24) 31 32 #define CONTROL_ENABLE BIT(0) 33 #define CONTROL_MASTER BIT(1) 34 #define CONTROL_RX_DATA_INT BIT(4) 35 #define CONTROL_TX_DATA_INT BIT(5) 36 #define CONTROL_RX_OVER_INT BIT(6) 37 #define CONTROL_TX_UNDER_INT BIT(7) 38 #define CONTROL_SPO BIT(24) 39 #define CONTROL_SPH BIT(25) 40 #define CONTROL_SPS BIT(26) 41 #define CONTROL_FRAMEURUN BIT(27) 42 #define CONTROL_CLKMODE BIT(28) 43 #define CONTROL_BIGFIFO BIT(29) 44 #define CONTROL_OENOFF BIT(30) 45 #define CONTROL_RESET BIT(31) 46 47 #define CONTROL_MODE_MASK GENMASK(3, 2) 48 #define MOTOROLA_MODE (0) 49 #define CONTROL_FRAMECNT_MASK GENMASK(23, 8) 50 #define CONTROL_FRAMECNT_SHIFT (8) 51 52 #define STATUS_ACTIVE BIT(14) 53 #define STATUS_SSEL BIT(13) 54 #define STATUS_FRAMESTART BIT(12) 55 #define STATUS_TXFIFO_EMPTY_NEXT_READ BIT(11) 56 #define STATUS_TXFIFO_EMPTY BIT(10) 57 #define STATUS_TXFIFO_FULL_NEXT_WRITE BIT(9) 58 #define STATUS_TXFIFO_FULL BIT(8) 59 #define STATUS_RXFIFO_EMPTY_NEXT_READ BIT(7) 60 #define STATUS_RXFIFO_EMPTY BIT(6) 61 #define STATUS_RXFIFO_FULL_NEXT_WRITE BIT(5) 62 #define STATUS_RXFIFO_FULL BIT(4) 63 #define STATUS_TX_UNDERRUN BIT(3) 64 #define STATUS_RX_OVERFLOW BIT(2) 65 #define STATUS_RXDAT_RXED BIT(1) 66 #define STATUS_TXDAT_SENT BIT(0) 67 68 #define INT_TXDONE BIT(0) 69 #define INT_RXRDY BIT(1) 70 #define INT_RX_CHANNEL_OVERFLOW BIT(2) 71 #define INT_TX_CHANNEL_UNDERRUN BIT(3) 72 73 #define INT_ENABLE_MASK (CONTROL_RX_DATA_INT | CONTROL_TX_DATA_INT | \ 74 CONTROL_RX_OVER_INT | CONTROL_TX_UNDER_INT) 75 76 #define REG_CONTROL (0x00) 77 #define REG_FRAME_SIZE (0x04) 78 #define REG_STATUS (0x08) 79 #define REG_INT_CLEAR (0x0c) 80 #define REG_RX_DATA (0x10) 81 #define REG_TX_DATA (0x14) 82 #define REG_CLK_GEN (0x18) 83 #define REG_SLAVE_SELECT (0x1c) 84 #define SSEL_MASK GENMASK(7, 0) 85 #define SSEL_DIRECT BIT(8) 86 #define SSELOUT_SHIFT 9 87 #define SSELOUT BIT(SSELOUT_SHIFT) 88 #define REG_MIS (0x20) 89 #define REG_RIS (0x24) 90 #define REG_CONTROL2 (0x28) 91 #define REG_COMMAND (0x2c) 92 #define REG_PKTSIZE (0x30) 93 #define REG_CMD_SIZE (0x34) 94 #define REG_HWSTATUS (0x38) 95 #define REG_STAT8 (0x3c) 96 #define REG_CTRL2 (0x48) 97 #define REG_FRAMESUP (0x50) 98 99 struct mchp_corespi { 100 void __iomem *regs; 101 struct clk *clk; 102 const u8 *tx_buf; 103 u8 *rx_buf; 104 u32 clk_gen; /* divider for spi output clock generated by the controller */ 105 u32 clk_mode; 106 int irq; 107 int tx_len; 108 int rx_len; 109 int pending; 110 }; 111 112 static inline u32 mchp_corespi_read(struct mchp_corespi *spi, unsigned int reg) 113 { 114 return readl(spi->regs + reg); 115 } 116 117 static inline void mchp_corespi_write(struct mchp_corespi *spi, unsigned int reg, u32 val) 118 { 119 writel(val, spi->regs + reg); 120 } 121 122 static inline void mchp_corespi_enable(struct mchp_corespi *spi) 123 { 124 u32 control = mchp_corespi_read(spi, REG_CONTROL); 125 126 control |= CONTROL_ENABLE; 127 128 mchp_corespi_write(spi, REG_CONTROL, control); 129 } 130 131 static inline void mchp_corespi_disable(struct mchp_corespi *spi) 132 { 133 u32 control = mchp_corespi_read(spi, REG_CONTROL); 134 135 control &= ~CONTROL_ENABLE; 136 137 mchp_corespi_write(spi, REG_CONTROL, control); 138 } 139 140 static inline void mchp_corespi_read_fifo(struct mchp_corespi *spi) 141 { 142 u8 data; 143 int fifo_max, i = 0; 144 145 fifo_max = min(spi->rx_len, FIFO_DEPTH); 146 147 while ((i < fifo_max) && !(mchp_corespi_read(spi, REG_STATUS) & STATUS_RXFIFO_EMPTY)) { 148 data = mchp_corespi_read(spi, REG_RX_DATA); 149 150 if (spi->rx_buf) 151 *spi->rx_buf++ = data; 152 i++; 153 } 154 spi->rx_len -= i; 155 spi->pending -= i; 156 } 157 158 static void mchp_corespi_enable_ints(struct mchp_corespi *spi) 159 { 160 u32 control, mask = INT_ENABLE_MASK; 161 162 mchp_corespi_disable(spi); 163 164 control = mchp_corespi_read(spi, REG_CONTROL); 165 166 control |= mask; 167 mchp_corespi_write(spi, REG_CONTROL, control); 168 169 control |= CONTROL_ENABLE; 170 mchp_corespi_write(spi, REG_CONTROL, control); 171 } 172 173 static void mchp_corespi_disable_ints(struct mchp_corespi *spi) 174 { 175 u32 control, mask = INT_ENABLE_MASK; 176 177 mchp_corespi_disable(spi); 178 179 control = mchp_corespi_read(spi, REG_CONTROL); 180 control &= ~mask; 181 mchp_corespi_write(spi, REG_CONTROL, control); 182 183 control |= CONTROL_ENABLE; 184 mchp_corespi_write(spi, REG_CONTROL, control); 185 } 186 187 static inline void mchp_corespi_set_xfer_size(struct mchp_corespi *spi, int len) 188 { 189 u32 control; 190 u16 lenpart; 191 192 /* 193 * Disable the SPI controller. Writes to transfer length have 194 * no effect when the controller is enabled. 195 */ 196 mchp_corespi_disable(spi); 197 198 /* 199 * The lower 16 bits of the frame count are stored in the control reg 200 * for legacy reasons, but the upper 16 written to a different register: 201 * FRAMESUP. While both the upper and lower bits can be *READ* from the 202 * FRAMESUP register, writing to the lower 16 bits is a NOP 203 */ 204 lenpart = len & 0xffff; 205 206 control = mchp_corespi_read(spi, REG_CONTROL); 207 control &= ~CONTROL_FRAMECNT_MASK; 208 control |= lenpart << CONTROL_FRAMECNT_SHIFT; 209 mchp_corespi_write(spi, REG_CONTROL, control); 210 211 lenpart = len & 0xffff0000; 212 mchp_corespi_write(spi, REG_FRAMESUP, lenpart); 213 214 control |= CONTROL_ENABLE; 215 mchp_corespi_write(spi, REG_CONTROL, control); 216 } 217 218 static inline void mchp_corespi_write_fifo(struct mchp_corespi *spi) 219 { 220 u8 byte; 221 int fifo_max, i = 0; 222 223 fifo_max = min(spi->tx_len, FIFO_DEPTH); 224 mchp_corespi_set_xfer_size(spi, fifo_max); 225 226 while ((i < fifo_max) && !(mchp_corespi_read(spi, REG_STATUS) & STATUS_TXFIFO_FULL)) { 227 byte = spi->tx_buf ? *spi->tx_buf++ : 0xaa; 228 mchp_corespi_write(spi, REG_TX_DATA, byte); 229 i++; 230 } 231 232 spi->tx_len -= i; 233 spi->pending += i; 234 } 235 236 static inline void mchp_corespi_set_framesize(struct mchp_corespi *spi, int bt) 237 { 238 u32 control; 239 240 /* 241 * Disable the SPI controller. Writes to the frame size have 242 * no effect when the controller is enabled. 243 */ 244 mchp_corespi_disable(spi); 245 246 mchp_corespi_write(spi, REG_FRAME_SIZE, bt); 247 248 control = mchp_corespi_read(spi, REG_CONTROL); 249 control |= CONTROL_ENABLE; 250 mchp_corespi_write(spi, REG_CONTROL, control); 251 } 252 253 static void mchp_corespi_set_cs(struct spi_device *spi, bool disable) 254 { 255 u32 reg; 256 struct mchp_corespi *corespi = spi_master_get_devdata(spi->master); 257 258 reg = mchp_corespi_read(corespi, REG_SLAVE_SELECT); 259 reg &= ~BIT(spi->chip_select); 260 reg |= !disable << spi->chip_select; 261 262 mchp_corespi_write(corespi, REG_SLAVE_SELECT, reg); 263 } 264 265 static int mchp_corespi_setup(struct spi_device *spi) 266 { 267 struct mchp_corespi *corespi = spi_master_get_devdata(spi->master); 268 u32 reg; 269 270 /* 271 * Active high slaves need to be specifically set to their inactive 272 * states during probe by adding them to the "control group" & thus 273 * driving their select line low. 274 */ 275 if (spi->mode & SPI_CS_HIGH) { 276 reg = mchp_corespi_read(corespi, REG_SLAVE_SELECT); 277 reg |= BIT(spi->chip_select); 278 mchp_corespi_write(corespi, REG_SLAVE_SELECT, reg); 279 } 280 return 0; 281 } 282 283 static void mchp_corespi_init(struct spi_master *master, struct mchp_corespi *spi) 284 { 285 unsigned long clk_hz; 286 u32 control = mchp_corespi_read(spi, REG_CONTROL); 287 288 control |= CONTROL_MASTER; 289 290 control &= ~CONTROL_MODE_MASK; 291 control |= MOTOROLA_MODE; 292 293 mchp_corespi_set_framesize(spi, DEFAULT_FRAMESIZE); 294 295 /* max. possible spi clock rate is the apb clock rate */ 296 clk_hz = clk_get_rate(spi->clk); 297 master->max_speed_hz = clk_hz; 298 299 /* 300 * The controller must be configured so that it doesn't remove Chip 301 * Select until the entire message has been transferred, even if at 302 * some points TX FIFO becomes empty. 303 * 304 * BIGFIFO mode is also enabled, which sets the fifo depth to 32 frames 305 * for the 8 bit transfers that this driver uses. 306 */ 307 control = mchp_corespi_read(spi, REG_CONTROL); 308 control |= CONTROL_SPS | CONTROL_BIGFIFO; 309 310 mchp_corespi_write(spi, REG_CONTROL, control); 311 312 mchp_corespi_enable_ints(spi); 313 314 /* 315 * It is required to enable direct mode, otherwise control over the chip 316 * select is relinquished to the hardware. SSELOUT is enabled too so we 317 * can deal with active high slaves. 318 */ 319 mchp_corespi_write(spi, REG_SLAVE_SELECT, SSELOUT | SSEL_DIRECT); 320 321 control = mchp_corespi_read(spi, REG_CONTROL); 322 323 control &= ~CONTROL_RESET; 324 control |= CONTROL_ENABLE; 325 326 mchp_corespi_write(spi, REG_CONTROL, control); 327 } 328 329 static inline void mchp_corespi_set_clk_gen(struct mchp_corespi *spi) 330 { 331 u32 control; 332 333 mchp_corespi_disable(spi); 334 335 control = mchp_corespi_read(spi, REG_CONTROL); 336 if (spi->clk_mode) 337 control |= CONTROL_CLKMODE; 338 else 339 control &= ~CONTROL_CLKMODE; 340 341 mchp_corespi_write(spi, REG_CLK_GEN, spi->clk_gen); 342 mchp_corespi_write(spi, REG_CONTROL, control); 343 mchp_corespi_write(spi, REG_CONTROL, control | CONTROL_ENABLE); 344 } 345 346 static inline void mchp_corespi_set_mode(struct mchp_corespi *spi, unsigned int mode) 347 { 348 u32 control, mode_val; 349 350 switch (mode & SPI_MODE_X_MASK) { 351 case SPI_MODE_0: 352 mode_val = 0; 353 break; 354 case SPI_MODE_1: 355 mode_val = CONTROL_SPH; 356 break; 357 case SPI_MODE_2: 358 mode_val = CONTROL_SPO; 359 break; 360 case SPI_MODE_3: 361 mode_val = CONTROL_SPH | CONTROL_SPO; 362 break; 363 } 364 365 /* 366 * Disable the SPI controller. Writes to the frame size have 367 * no effect when the controller is enabled. 368 */ 369 mchp_corespi_disable(spi); 370 371 control = mchp_corespi_read(spi, REG_CONTROL); 372 control &= ~(SPI_MODE_X_MASK << MODE_X_MASK_SHIFT); 373 control |= mode_val; 374 375 mchp_corespi_write(spi, REG_CONTROL, control); 376 377 control |= CONTROL_ENABLE; 378 mchp_corespi_write(spi, REG_CONTROL, control); 379 } 380 381 static irqreturn_t mchp_corespi_interrupt(int irq, void *dev_id) 382 { 383 struct spi_master *master = dev_id; 384 struct mchp_corespi *spi = spi_master_get_devdata(master); 385 u32 intfield = mchp_corespi_read(spi, REG_MIS) & 0xf; 386 bool finalise = false; 387 388 /* Interrupt line may be shared and not for us at all */ 389 if (intfield == 0) 390 return IRQ_NONE; 391 392 if (intfield & INT_TXDONE) { 393 mchp_corespi_write(spi, REG_INT_CLEAR, INT_TXDONE); 394 395 if (spi->rx_len) 396 mchp_corespi_read_fifo(spi); 397 398 if (spi->tx_len) 399 mchp_corespi_write_fifo(spi); 400 401 if (!spi->rx_len) 402 finalise = true; 403 } 404 405 if (intfield & INT_RXRDY) 406 mchp_corespi_write(spi, REG_INT_CLEAR, INT_RXRDY); 407 408 if (intfield & INT_RX_CHANNEL_OVERFLOW) { 409 mchp_corespi_write(spi, REG_INT_CLEAR, INT_RX_CHANNEL_OVERFLOW); 410 finalise = true; 411 dev_err(&master->dev, 412 "%s: RX OVERFLOW: rxlen: %d, txlen: %d\n", __func__, 413 spi->rx_len, spi->tx_len); 414 } 415 416 if (intfield & INT_TX_CHANNEL_UNDERRUN) { 417 mchp_corespi_write(spi, REG_INT_CLEAR, INT_TX_CHANNEL_UNDERRUN); 418 finalise = true; 419 dev_err(&master->dev, 420 "%s: TX UNDERFLOW: rxlen: %d, txlen: %d\n", __func__, 421 spi->rx_len, spi->tx_len); 422 } 423 424 if (finalise) 425 spi_finalize_current_transfer(master); 426 427 return IRQ_HANDLED; 428 } 429 430 static int mchp_corespi_calculate_clkgen(struct mchp_corespi *spi, 431 unsigned long target_hz) 432 { 433 unsigned long clk_hz, spi_hz, clk_gen; 434 435 clk_hz = clk_get_rate(spi->clk); 436 if (!clk_hz) 437 return -EINVAL; 438 spi_hz = min(target_hz, clk_hz); 439 440 /* 441 * There are two possible clock modes for the controller generated 442 * clock's division ratio: 443 * CLK_MODE = 0: 1 / (2^(CLK_GEN + 1)) where CLK_GEN = 0 to 15. 444 * CLK_MODE = 1: 1 / (2 * CLK_GEN + 1) where CLK_GEN = 0 to 255. 445 * First try mode 1, fall back to 0 and if we have tried both modes and 446 * we /still/ can't get a good setting, we then throw the toys out of 447 * the pram and give up 448 * clk_gen is the register name for the clock divider on MPFS. 449 */ 450 clk_gen = DIV_ROUND_UP(clk_hz, 2 * spi_hz) - 1; 451 if (clk_gen > CLK_GEN_MODE1_MAX || clk_gen <= CLK_GEN_MIN) { 452 clk_gen = DIV_ROUND_UP(clk_hz, spi_hz); 453 clk_gen = fls(clk_gen) - 1; 454 455 if (clk_gen > CLK_GEN_MODE0_MAX) 456 return -EINVAL; 457 458 spi->clk_mode = 0; 459 } else { 460 spi->clk_mode = 1; 461 } 462 463 spi->clk_gen = clk_gen; 464 return 0; 465 } 466 467 static int mchp_corespi_transfer_one(struct spi_master *master, 468 struct spi_device *spi_dev, 469 struct spi_transfer *xfer) 470 { 471 struct mchp_corespi *spi = spi_master_get_devdata(master); 472 int ret; 473 474 ret = mchp_corespi_calculate_clkgen(spi, (unsigned long)xfer->speed_hz); 475 if (ret) { 476 dev_err(&master->dev, "failed to set clk_gen for target %u Hz\n", xfer->speed_hz); 477 return ret; 478 } 479 480 mchp_corespi_set_clk_gen(spi); 481 482 spi->tx_buf = xfer->tx_buf; 483 spi->rx_buf = xfer->rx_buf; 484 spi->tx_len = xfer->len; 485 spi->rx_len = xfer->len; 486 spi->pending = 0; 487 488 mchp_corespi_set_xfer_size(spi, (spi->tx_len > FIFO_DEPTH) 489 ? FIFO_DEPTH : spi->tx_len); 490 491 if (spi->tx_len) 492 mchp_corespi_write_fifo(spi); 493 return 1; 494 } 495 496 static int mchp_corespi_prepare_message(struct spi_master *master, 497 struct spi_message *msg) 498 { 499 struct spi_device *spi_dev = msg->spi; 500 struct mchp_corespi *spi = spi_master_get_devdata(master); 501 502 mchp_corespi_set_framesize(spi, DEFAULT_FRAMESIZE); 503 mchp_corespi_set_mode(spi, spi_dev->mode); 504 505 return 0; 506 } 507 508 static int mchp_corespi_probe(struct platform_device *pdev) 509 { 510 struct spi_master *master; 511 struct mchp_corespi *spi; 512 struct resource *res; 513 u32 num_cs; 514 int ret = 0; 515 516 master = devm_spi_alloc_master(&pdev->dev, sizeof(*spi)); 517 if (!master) 518 return dev_err_probe(&pdev->dev, -ENOMEM, 519 "unable to allocate master for SPI controller\n"); 520 521 platform_set_drvdata(pdev, master); 522 523 if (of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs)) 524 num_cs = MAX_CS; 525 526 master->num_chipselect = num_cs; 527 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 528 master->setup = mchp_corespi_setup; 529 master->bits_per_word_mask = SPI_BPW_MASK(8); 530 master->transfer_one = mchp_corespi_transfer_one; 531 master->prepare_message = mchp_corespi_prepare_message; 532 master->set_cs = mchp_corespi_set_cs; 533 master->dev.of_node = pdev->dev.of_node; 534 535 spi = spi_master_get_devdata(master); 536 537 spi->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 538 if (IS_ERR(spi->regs)) 539 return PTR_ERR(spi->regs); 540 541 spi->irq = platform_get_irq(pdev, 0); 542 if (spi->irq <= 0) 543 return dev_err_probe(&pdev->dev, -ENXIO, 544 "invalid IRQ %d for SPI controller\n", 545 spi->irq); 546 547 ret = devm_request_irq(&pdev->dev, spi->irq, mchp_corespi_interrupt, 548 IRQF_SHARED, dev_name(&pdev->dev), master); 549 if (ret) 550 return dev_err_probe(&pdev->dev, ret, 551 "could not request irq: %d\n", ret); 552 553 spi->clk = devm_clk_get(&pdev->dev, NULL); 554 if (IS_ERR(spi->clk)) 555 return dev_err_probe(&pdev->dev, PTR_ERR(spi->clk), 556 "could not get clk: %d\n", ret); 557 558 ret = clk_prepare_enable(spi->clk); 559 if (ret) 560 return dev_err_probe(&pdev->dev, ret, 561 "failed to enable clock\n"); 562 563 mchp_corespi_init(master, spi); 564 565 ret = devm_spi_register_master(&pdev->dev, master); 566 if (ret) { 567 mchp_corespi_disable(spi); 568 clk_disable_unprepare(spi->clk); 569 return dev_err_probe(&pdev->dev, ret, 570 "unable to register master for SPI controller\n"); 571 } 572 573 dev_info(&pdev->dev, "Registered SPI controller %d\n", master->bus_num); 574 575 return 0; 576 } 577 578 static int mchp_corespi_remove(struct platform_device *pdev) 579 { 580 struct spi_master *master = platform_get_drvdata(pdev); 581 struct mchp_corespi *spi = spi_master_get_devdata(master); 582 583 mchp_corespi_disable_ints(spi); 584 clk_disable_unprepare(spi->clk); 585 mchp_corespi_disable(spi); 586 587 return 0; 588 } 589 590 #define MICROCHIP_SPI_PM_OPS (NULL) 591 592 /* 593 * Platform driver data structure 594 */ 595 596 #if defined(CONFIG_OF) 597 static const struct of_device_id mchp_corespi_dt_ids[] = { 598 { .compatible = "microchip,mpfs-spi" }, 599 { /* sentinel */ } 600 }; 601 MODULE_DEVICE_TABLE(of, mchp_corespi_dt_ids); 602 #endif 603 604 static struct platform_driver mchp_corespi_driver = { 605 .probe = mchp_corespi_probe, 606 .driver = { 607 .name = "microchip-corespi", 608 .pm = MICROCHIP_SPI_PM_OPS, 609 .of_match_table = of_match_ptr(mchp_corespi_dt_ids), 610 }, 611 .remove = mchp_corespi_remove, 612 }; 613 module_platform_driver(mchp_corespi_driver); 614 MODULE_DESCRIPTION("Microchip coreSPI SPI controller driver"); 615 MODULE_AUTHOR("Daire McNamara <daire.mcnamara@microchip.com>"); 616 MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>"); 617 MODULE_LICENSE("GPL"); 618