1 /* 2 * Driver for Amlogic Meson SPI communication controller (SPICC) 3 * 4 * Copyright (C) BayLibre, SAS 5 * Author: Neil Armstrong <narmstrong@baylibre.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/clk.h> 12 #include <linux/clk-provider.h> 13 #include <linux/device.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/of_device.h> 19 #include <linux/platform_device.h> 20 #include <linux/spi/spi.h> 21 #include <linux/types.h> 22 #include <linux/interrupt.h> 23 #include <linux/reset.h> 24 25 /* 26 * The Meson SPICC controller could support DMA based transfers, but is not 27 * implemented by the vendor code, and while having the registers documentation 28 * it has never worked on the GXL Hardware. 29 * The PIO mode is the only mode implemented, and due to badly designed HW : 30 * - all transfers are cutted in 16 words burst because the FIFO hangs on 31 * TX underflow, and there is no TX "Half-Empty" interrupt, so we go by 32 * FIFO max size chunk only 33 * - CS management is dumb, and goes UP between every burst, so is really a 34 * "Data Valid" signal than a Chip Select, GPIO link should be used instead 35 * to have a CS go down over the full transfer 36 */ 37 38 #define SPICC_MAX_BURST 128 39 40 /* Register Map */ 41 #define SPICC_RXDATA 0x00 42 43 #define SPICC_TXDATA 0x04 44 45 #define SPICC_CONREG 0x08 46 #define SPICC_ENABLE BIT(0) 47 #define SPICC_MODE_MASTER BIT(1) 48 #define SPICC_XCH BIT(2) 49 #define SPICC_SMC BIT(3) 50 #define SPICC_POL BIT(4) 51 #define SPICC_PHA BIT(5) 52 #define SPICC_SSCTL BIT(6) 53 #define SPICC_SSPOL BIT(7) 54 #define SPICC_DRCTL_MASK GENMASK(9, 8) 55 #define SPICC_DRCTL_IGNORE 0 56 #define SPICC_DRCTL_FALLING 1 57 #define SPICC_DRCTL_LOWLEVEL 2 58 #define SPICC_CS_MASK GENMASK(13, 12) 59 #define SPICC_DATARATE_MASK GENMASK(18, 16) 60 #define SPICC_DATARATE_DIV4 0 61 #define SPICC_DATARATE_DIV8 1 62 #define SPICC_DATARATE_DIV16 2 63 #define SPICC_DATARATE_DIV32 3 64 #define SPICC_BITLENGTH_MASK GENMASK(24, 19) 65 #define SPICC_BURSTLENGTH_MASK GENMASK(31, 25) 66 67 #define SPICC_INTREG 0x0c 68 #define SPICC_TE_EN BIT(0) /* TX FIFO Empty Interrupt */ 69 #define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */ 70 #define SPICC_TF_EN BIT(2) /* TX FIFO Full Interrupt */ 71 #define SPICC_RR_EN BIT(3) /* RX FIFO Ready Interrupt */ 72 #define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */ 73 #define SPICC_RF_EN BIT(5) /* RX FIFO Full Interrupt */ 74 #define SPICC_RO_EN BIT(6) /* RX FIFO Overflow Interrupt */ 75 #define SPICC_TC_EN BIT(7) /* Transfert Complete Interrupt */ 76 77 #define SPICC_DMAREG 0x10 78 #define SPICC_DMA_ENABLE BIT(0) 79 #define SPICC_TXFIFO_THRESHOLD_MASK GENMASK(5, 1) 80 #define SPICC_RXFIFO_THRESHOLD_MASK GENMASK(10, 6) 81 #define SPICC_READ_BURST_MASK GENMASK(14, 11) 82 #define SPICC_WRITE_BURST_MASK GENMASK(18, 15) 83 #define SPICC_DMA_URGENT BIT(19) 84 #define SPICC_DMA_THREADID_MASK GENMASK(25, 20) 85 #define SPICC_DMA_BURSTNUM_MASK GENMASK(31, 26) 86 87 #define SPICC_STATREG 0x14 88 #define SPICC_TE BIT(0) /* TX FIFO Empty Interrupt */ 89 #define SPICC_TH BIT(1) /* TX FIFO Half-Full Interrupt */ 90 #define SPICC_TF BIT(2) /* TX FIFO Full Interrupt */ 91 #define SPICC_RR BIT(3) /* RX FIFO Ready Interrupt */ 92 #define SPICC_RH BIT(4) /* RX FIFO Half-Full Interrupt */ 93 #define SPICC_RF BIT(5) /* RX FIFO Full Interrupt */ 94 #define SPICC_RO BIT(6) /* RX FIFO Overflow Interrupt */ 95 #define SPICC_TC BIT(7) /* Transfert Complete Interrupt */ 96 97 #define SPICC_PERIODREG 0x18 98 #define SPICC_PERIOD GENMASK(14, 0) /* Wait cycles */ 99 100 #define SPICC_TESTREG 0x1c 101 #define SPICC_TXCNT_MASK GENMASK(4, 0) /* TX FIFO Counter */ 102 #define SPICC_RXCNT_MASK GENMASK(9, 5) /* RX FIFO Counter */ 103 #define SPICC_SMSTATUS_MASK GENMASK(12, 10) /* State Machine Status */ 104 #define SPICC_LBC_RO BIT(13) /* Loop Back Control Read-Only */ 105 #define SPICC_LBC_W1 BIT(14) /* Loop Back Control Write-Only */ 106 #define SPICC_SWAP_RO BIT(14) /* RX FIFO Data Swap Read-Only */ 107 #define SPICC_SWAP_W1 BIT(15) /* RX FIFO Data Swap Write-Only */ 108 #define SPICC_DLYCTL_RO_MASK GENMASK(20, 15) /* Delay Control Read-Only */ 109 #define SPICC_MO_DELAY_MASK GENMASK(17, 16) /* Master Output Delay */ 110 #define SPICC_MO_NO_DELAY 0 111 #define SPICC_MO_DELAY_1_CYCLE 1 112 #define SPICC_MO_DELAY_2_CYCLE 2 113 #define SPICC_MO_DELAY_3_CYCLE 3 114 #define SPICC_MI_DELAY_MASK GENMASK(19, 18) /* Master Input Delay */ 115 #define SPICC_MI_NO_DELAY 0 116 #define SPICC_MI_DELAY_1_CYCLE 1 117 #define SPICC_MI_DELAY_2_CYCLE 2 118 #define SPICC_MI_DELAY_3_CYCLE 3 119 #define SPICC_MI_CAP_DELAY_MASK GENMASK(21, 20) /* Master Capture Delay */ 120 #define SPICC_CAP_AHEAD_2_CYCLE 0 121 #define SPICC_CAP_AHEAD_1_CYCLE 1 122 #define SPICC_CAP_NO_DELAY 2 123 #define SPICC_CAP_DELAY_1_CYCLE 3 124 #define SPICC_FIFORST_RO_MASK GENMASK(22, 21) /* FIFO Softreset Read-Only */ 125 #define SPICC_FIFORST_W1_MASK GENMASK(23, 22) /* FIFO Softreset Write-Only */ 126 127 #define SPICC_DRADDR 0x20 /* Read Address of DMA */ 128 129 #define SPICC_DWADDR 0x24 /* Write Address of DMA */ 130 131 #define SPICC_ENH_CTL0 0x38 /* Enhanced Feature */ 132 #define SPICC_ENH_CLK_CS_DELAY_MASK GENMASK(15, 0) 133 #define SPICC_ENH_DATARATE_MASK GENMASK(23, 16) 134 #define SPICC_ENH_DATARATE_EN BIT(24) 135 #define SPICC_ENH_MOSI_OEN BIT(25) 136 #define SPICC_ENH_CLK_OEN BIT(26) 137 #define SPICC_ENH_CS_OEN BIT(27) 138 #define SPICC_ENH_CLK_CS_DELAY_EN BIT(28) 139 #define SPICC_ENH_MAIN_CLK_AO BIT(29) 140 141 #define writel_bits_relaxed(mask, val, addr) \ 142 writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr) 143 144 struct meson_spicc_data { 145 unsigned int max_speed_hz; 146 unsigned int min_speed_hz; 147 unsigned int fifo_size; 148 bool has_oen; 149 bool has_enhance_clk_div; 150 bool has_pclk; 151 }; 152 153 struct meson_spicc_device { 154 struct spi_master *master; 155 struct platform_device *pdev; 156 void __iomem *base; 157 struct clk *core; 158 struct clk *pclk; 159 struct clk_divider pow2_div; 160 struct clk *clk; 161 struct spi_message *message; 162 struct spi_transfer *xfer; 163 const struct meson_spicc_data *data; 164 u8 *tx_buf; 165 u8 *rx_buf; 166 unsigned int bytes_per_word; 167 unsigned long tx_remain; 168 unsigned long rx_remain; 169 unsigned long xfer_remain; 170 }; 171 172 #define pow2_clk_to_spicc(_div) container_of(_div, struct meson_spicc_device, pow2_div) 173 174 static void meson_spicc_oen_enable(struct meson_spicc_device *spicc) 175 { 176 u32 conf; 177 178 if (!spicc->data->has_oen) 179 return; 180 181 conf = readl_relaxed(spicc->base + SPICC_ENH_CTL0) | 182 SPICC_ENH_MOSI_OEN | SPICC_ENH_CLK_OEN | SPICC_ENH_CS_OEN; 183 184 writel_relaxed(conf, spicc->base + SPICC_ENH_CTL0); 185 } 186 187 static inline bool meson_spicc_txfull(struct meson_spicc_device *spicc) 188 { 189 return !!FIELD_GET(SPICC_TF, 190 readl_relaxed(spicc->base + SPICC_STATREG)); 191 } 192 193 static inline bool meson_spicc_rxready(struct meson_spicc_device *spicc) 194 { 195 return FIELD_GET(SPICC_RH | SPICC_RR | SPICC_RF, 196 readl_relaxed(spicc->base + SPICC_STATREG)); 197 } 198 199 static inline u32 meson_spicc_pull_data(struct meson_spicc_device *spicc) 200 { 201 unsigned int bytes = spicc->bytes_per_word; 202 unsigned int byte_shift = 0; 203 u32 data = 0; 204 u8 byte; 205 206 while (bytes--) { 207 byte = *spicc->tx_buf++; 208 data |= (byte & 0xff) << byte_shift; 209 byte_shift += 8; 210 } 211 212 spicc->tx_remain--; 213 return data; 214 } 215 216 static inline void meson_spicc_push_data(struct meson_spicc_device *spicc, 217 u32 data) 218 { 219 unsigned int bytes = spicc->bytes_per_word; 220 unsigned int byte_shift = 0; 221 u8 byte; 222 223 while (bytes--) { 224 byte = (data >> byte_shift) & 0xff; 225 *spicc->rx_buf++ = byte; 226 byte_shift += 8; 227 } 228 229 spicc->rx_remain--; 230 } 231 232 static inline void meson_spicc_rx(struct meson_spicc_device *spicc) 233 { 234 /* Empty RX FIFO */ 235 while (spicc->rx_remain && 236 meson_spicc_rxready(spicc)) 237 meson_spicc_push_data(spicc, 238 readl_relaxed(spicc->base + SPICC_RXDATA)); 239 } 240 241 static inline void meson_spicc_tx(struct meson_spicc_device *spicc) 242 { 243 /* Fill Up TX FIFO */ 244 while (spicc->tx_remain && 245 !meson_spicc_txfull(spicc)) 246 writel_relaxed(meson_spicc_pull_data(spicc), 247 spicc->base + SPICC_TXDATA); 248 } 249 250 static inline void meson_spicc_setup_burst(struct meson_spicc_device *spicc) 251 { 252 253 unsigned int burst_len = min_t(unsigned int, 254 spicc->xfer_remain / 255 spicc->bytes_per_word, 256 spicc->data->fifo_size); 257 /* Setup Xfer variables */ 258 spicc->tx_remain = burst_len; 259 spicc->rx_remain = burst_len; 260 spicc->xfer_remain -= burst_len * spicc->bytes_per_word; 261 262 /* Setup burst length */ 263 writel_bits_relaxed(SPICC_BURSTLENGTH_MASK, 264 FIELD_PREP(SPICC_BURSTLENGTH_MASK, 265 burst_len - 1), 266 spicc->base + SPICC_CONREG); 267 268 /* Fill TX FIFO */ 269 meson_spicc_tx(spicc); 270 } 271 272 static irqreturn_t meson_spicc_irq(int irq, void *data) 273 { 274 struct meson_spicc_device *spicc = (void *) data; 275 276 writel_bits_relaxed(SPICC_TC, SPICC_TC, spicc->base + SPICC_STATREG); 277 278 /* Empty RX FIFO */ 279 meson_spicc_rx(spicc); 280 281 if (!spicc->xfer_remain) { 282 /* Disable all IRQs */ 283 writel(0, spicc->base + SPICC_INTREG); 284 285 spi_finalize_current_transfer(spicc->master); 286 287 return IRQ_HANDLED; 288 } 289 290 /* Setup burst */ 291 meson_spicc_setup_burst(spicc); 292 293 /* Start burst */ 294 writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG); 295 296 return IRQ_HANDLED; 297 } 298 299 static void meson_spicc_auto_io_delay(struct meson_spicc_device *spicc) 300 { 301 u32 div, hz; 302 u32 mi_delay, cap_delay; 303 u32 conf; 304 305 if (spicc->data->has_enhance_clk_div) { 306 div = FIELD_GET(SPICC_ENH_DATARATE_MASK, 307 readl_relaxed(spicc->base + SPICC_ENH_CTL0)); 308 div++; 309 div <<= 1; 310 } else { 311 div = FIELD_GET(SPICC_DATARATE_MASK, 312 readl_relaxed(spicc->base + SPICC_CONREG)); 313 div += 2; 314 div = 1 << div; 315 } 316 317 mi_delay = SPICC_MI_NO_DELAY; 318 cap_delay = SPICC_CAP_AHEAD_2_CYCLE; 319 hz = clk_get_rate(spicc->clk); 320 321 if (hz >= 100000000) 322 cap_delay = SPICC_CAP_DELAY_1_CYCLE; 323 else if (hz >= 80000000) 324 cap_delay = SPICC_CAP_NO_DELAY; 325 else if (hz >= 40000000) 326 cap_delay = SPICC_CAP_AHEAD_1_CYCLE; 327 else if (div >= 16) 328 mi_delay = SPICC_MI_DELAY_3_CYCLE; 329 else if (div >= 8) 330 mi_delay = SPICC_MI_DELAY_2_CYCLE; 331 else if (div >= 6) 332 mi_delay = SPICC_MI_DELAY_1_CYCLE; 333 334 conf = readl_relaxed(spicc->base + SPICC_TESTREG); 335 conf &= ~(SPICC_MO_DELAY_MASK | SPICC_MI_DELAY_MASK 336 | SPICC_MI_CAP_DELAY_MASK); 337 conf |= FIELD_PREP(SPICC_MI_DELAY_MASK, mi_delay); 338 conf |= FIELD_PREP(SPICC_MI_CAP_DELAY_MASK, cap_delay); 339 writel_relaxed(conf, spicc->base + SPICC_TESTREG); 340 } 341 342 static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc, 343 struct spi_transfer *xfer) 344 { 345 u32 conf, conf_orig; 346 347 /* Read original configuration */ 348 conf = conf_orig = readl_relaxed(spicc->base + SPICC_CONREG); 349 350 /* Setup word width */ 351 conf &= ~SPICC_BITLENGTH_MASK; 352 conf |= FIELD_PREP(SPICC_BITLENGTH_MASK, 353 (spicc->bytes_per_word << 3) - 1); 354 355 /* Ignore if unchanged */ 356 if (conf != conf_orig) 357 writel_relaxed(conf, spicc->base + SPICC_CONREG); 358 359 clk_set_rate(spicc->clk, xfer->speed_hz); 360 361 meson_spicc_auto_io_delay(spicc); 362 363 writel_relaxed(0, spicc->base + SPICC_DMAREG); 364 } 365 366 static void meson_spicc_reset_fifo(struct meson_spicc_device *spicc) 367 { 368 if (spicc->data->has_oen) 369 writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO, 370 SPICC_ENH_MAIN_CLK_AO, 371 spicc->base + SPICC_ENH_CTL0); 372 373 writel_bits_relaxed(SPICC_FIFORST_W1_MASK, SPICC_FIFORST_W1_MASK, 374 spicc->base + SPICC_TESTREG); 375 376 while (meson_spicc_rxready(spicc)) 377 readl_relaxed(spicc->base + SPICC_RXDATA); 378 379 if (spicc->data->has_oen) 380 writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO, 0, 381 spicc->base + SPICC_ENH_CTL0); 382 } 383 384 static int meson_spicc_transfer_one(struct spi_master *master, 385 struct spi_device *spi, 386 struct spi_transfer *xfer) 387 { 388 struct meson_spicc_device *spicc = spi_master_get_devdata(master); 389 390 /* Store current transfer */ 391 spicc->xfer = xfer; 392 393 /* Setup transfer parameters */ 394 spicc->tx_buf = (u8 *)xfer->tx_buf; 395 spicc->rx_buf = (u8 *)xfer->rx_buf; 396 spicc->xfer_remain = xfer->len; 397 398 /* Pre-calculate word size */ 399 spicc->bytes_per_word = 400 DIV_ROUND_UP(spicc->xfer->bits_per_word, 8); 401 402 if (xfer->len % spicc->bytes_per_word) 403 return -EINVAL; 404 405 /* Setup transfer parameters */ 406 meson_spicc_setup_xfer(spicc, xfer); 407 408 meson_spicc_reset_fifo(spicc); 409 410 /* Setup burst */ 411 meson_spicc_setup_burst(spicc); 412 413 /* Start burst */ 414 writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG); 415 416 /* Enable interrupts */ 417 writel_relaxed(SPICC_TC_EN, spicc->base + SPICC_INTREG); 418 419 return 1; 420 } 421 422 static int meson_spicc_prepare_message(struct spi_master *master, 423 struct spi_message *message) 424 { 425 struct meson_spicc_device *spicc = spi_master_get_devdata(master); 426 struct spi_device *spi = message->spi; 427 u32 conf = readl_relaxed(spicc->base + SPICC_CONREG) & SPICC_DATARATE_MASK; 428 429 /* Store current message */ 430 spicc->message = message; 431 432 /* Enable Master */ 433 conf |= SPICC_ENABLE; 434 conf |= SPICC_MODE_MASTER; 435 436 /* SMC = 0 */ 437 438 /* Setup transfer mode */ 439 if (spi->mode & SPI_CPOL) 440 conf |= SPICC_POL; 441 else 442 conf &= ~SPICC_POL; 443 444 if (spi->mode & SPI_CPHA) 445 conf |= SPICC_PHA; 446 else 447 conf &= ~SPICC_PHA; 448 449 /* SSCTL = 0 */ 450 451 if (spi->mode & SPI_CS_HIGH) 452 conf |= SPICC_SSPOL; 453 else 454 conf &= ~SPICC_SSPOL; 455 456 if (spi->mode & SPI_READY) 457 conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_LOWLEVEL); 458 else 459 conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_IGNORE); 460 461 /* Select CS */ 462 conf |= FIELD_PREP(SPICC_CS_MASK, spi->chip_select); 463 464 /* Default 8bit word */ 465 conf |= FIELD_PREP(SPICC_BITLENGTH_MASK, 8 - 1); 466 467 writel_relaxed(conf, spicc->base + SPICC_CONREG); 468 469 /* Setup no wait cycles by default */ 470 writel_relaxed(0, spicc->base + SPICC_PERIODREG); 471 472 writel_bits_relaxed(SPICC_LBC_W1, 0, spicc->base + SPICC_TESTREG); 473 474 return 0; 475 } 476 477 static int meson_spicc_unprepare_transfer(struct spi_master *master) 478 { 479 struct meson_spicc_device *spicc = spi_master_get_devdata(master); 480 u32 conf = readl_relaxed(spicc->base + SPICC_CONREG) & SPICC_DATARATE_MASK; 481 482 /* Disable all IRQs */ 483 writel(0, spicc->base + SPICC_INTREG); 484 485 device_reset_optional(&spicc->pdev->dev); 486 487 /* Set default configuration, keeping datarate field */ 488 writel_relaxed(conf, spicc->base + SPICC_CONREG); 489 490 return 0; 491 } 492 493 static int meson_spicc_setup(struct spi_device *spi) 494 { 495 if (!spi->controller_state) 496 spi->controller_state = spi_master_get_devdata(spi->master); 497 498 return 0; 499 } 500 501 static void meson_spicc_cleanup(struct spi_device *spi) 502 { 503 spi->controller_state = NULL; 504 } 505 506 /* 507 * The Clock Mux 508 * x-----------------x x------------x x------\ 509 * |---| pow2 fixed div |---| pow2 div |----| | 510 * | x-----------------x x------------x | | 511 * src ---| | mux |-- out 512 * | x-----------------x x------------x | | 513 * |---| enh fixed div |---| enh div |0---| | 514 * x-----------------x x------------x x------/ 515 * 516 * Clk path for GX series: 517 * src -> pow2 fixed div -> pow2 div -> out 518 * 519 * Clk path for AXG series: 520 * src -> pow2 fixed div -> pow2 div -> mux -> out 521 * src -> enh fixed div -> enh div -> mux -> out 522 * 523 * Clk path for G12A series: 524 * pclk -> pow2 fixed div -> pow2 div -> mux -> out 525 * pclk -> enh fixed div -> enh div -> mux -> out 526 * 527 * The pow2 divider is tied to the controller HW state, and the 528 * divider is only valid when the controller is initialized. 529 * 530 * A set of clock ops is added to make sure we don't read/set this 531 * clock rate while the controller is in an unknown state. 532 */ 533 534 static unsigned long meson_spicc_pow2_recalc_rate(struct clk_hw *hw, 535 unsigned long parent_rate) 536 { 537 struct clk_divider *divider = to_clk_divider(hw); 538 struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider); 539 540 if (!spicc->master->cur_msg || !spicc->master->busy) 541 return 0; 542 543 return clk_divider_ops.recalc_rate(hw, parent_rate); 544 } 545 546 static int meson_spicc_pow2_determine_rate(struct clk_hw *hw, 547 struct clk_rate_request *req) 548 { 549 struct clk_divider *divider = to_clk_divider(hw); 550 struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider); 551 552 if (!spicc->master->cur_msg || !spicc->master->busy) 553 return -EINVAL; 554 555 return clk_divider_ops.determine_rate(hw, req); 556 } 557 558 static int meson_spicc_pow2_set_rate(struct clk_hw *hw, unsigned long rate, 559 unsigned long parent_rate) 560 { 561 struct clk_divider *divider = to_clk_divider(hw); 562 struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider); 563 564 if (!spicc->master->cur_msg || !spicc->master->busy) 565 return -EINVAL; 566 567 return clk_divider_ops.set_rate(hw, rate, parent_rate); 568 } 569 570 const struct clk_ops meson_spicc_pow2_clk_ops = { 571 .recalc_rate = meson_spicc_pow2_recalc_rate, 572 .determine_rate = meson_spicc_pow2_determine_rate, 573 .set_rate = meson_spicc_pow2_set_rate, 574 }; 575 576 static int meson_spicc_pow2_clk_init(struct meson_spicc_device *spicc) 577 { 578 struct device *dev = &spicc->pdev->dev; 579 struct clk_fixed_factor *pow2_fixed_div; 580 struct clk_init_data init; 581 struct clk *clk; 582 struct clk_parent_data parent_data[2]; 583 char name[64]; 584 585 memset(&init, 0, sizeof(init)); 586 memset(&parent_data, 0, sizeof(parent_data)); 587 588 init.parent_data = parent_data; 589 590 /* algorithm for pow2 div: rate = freq / 4 / (2 ^ N) */ 591 592 pow2_fixed_div = devm_kzalloc(dev, sizeof(*pow2_fixed_div), GFP_KERNEL); 593 if (!pow2_fixed_div) 594 return -ENOMEM; 595 596 snprintf(name, sizeof(name), "%s#pow2_fixed_div", dev_name(dev)); 597 init.name = name; 598 init.ops = &clk_fixed_factor_ops; 599 init.flags = 0; 600 if (spicc->data->has_pclk) 601 parent_data[0].hw = __clk_get_hw(spicc->pclk); 602 else 603 parent_data[0].hw = __clk_get_hw(spicc->core); 604 init.num_parents = 1; 605 606 pow2_fixed_div->mult = 1, 607 pow2_fixed_div->div = 4, 608 pow2_fixed_div->hw.init = &init; 609 610 clk = devm_clk_register(dev, &pow2_fixed_div->hw); 611 if (WARN_ON(IS_ERR(clk))) 612 return PTR_ERR(clk); 613 614 snprintf(name, sizeof(name), "%s#pow2_div", dev_name(dev)); 615 init.name = name; 616 init.ops = &meson_spicc_pow2_clk_ops; 617 /* 618 * Set NOCACHE here to make sure we read the actual HW value 619 * since we reset the HW after each transfer. 620 */ 621 init.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE; 622 parent_data[0].hw = &pow2_fixed_div->hw; 623 init.num_parents = 1; 624 625 spicc->pow2_div.shift = 16, 626 spicc->pow2_div.width = 3, 627 spicc->pow2_div.flags = CLK_DIVIDER_POWER_OF_TWO, 628 spicc->pow2_div.reg = spicc->base + SPICC_CONREG; 629 spicc->pow2_div.hw.init = &init; 630 631 spicc->clk = devm_clk_register(dev, &spicc->pow2_div.hw); 632 if (WARN_ON(IS_ERR(spicc->clk))) 633 return PTR_ERR(spicc->clk); 634 635 return 0; 636 } 637 638 static int meson_spicc_enh_clk_init(struct meson_spicc_device *spicc) 639 { 640 struct device *dev = &spicc->pdev->dev; 641 struct clk_fixed_factor *enh_fixed_div; 642 struct clk_divider *enh_div; 643 struct clk_mux *mux; 644 struct clk_init_data init; 645 struct clk *clk; 646 struct clk_parent_data parent_data[2]; 647 char name[64]; 648 649 memset(&init, 0, sizeof(init)); 650 memset(&parent_data, 0, sizeof(parent_data)); 651 652 init.parent_data = parent_data; 653 654 /* algorithm for enh div: rate = freq / 2 / (N + 1) */ 655 656 enh_fixed_div = devm_kzalloc(dev, sizeof(*enh_fixed_div), GFP_KERNEL); 657 if (!enh_fixed_div) 658 return -ENOMEM; 659 660 snprintf(name, sizeof(name), "%s#enh_fixed_div", dev_name(dev)); 661 init.name = name; 662 init.ops = &clk_fixed_factor_ops; 663 init.flags = 0; 664 if (spicc->data->has_pclk) 665 parent_data[0].hw = __clk_get_hw(spicc->pclk); 666 else 667 parent_data[0].hw = __clk_get_hw(spicc->core); 668 init.num_parents = 1; 669 670 enh_fixed_div->mult = 1, 671 enh_fixed_div->div = 2, 672 enh_fixed_div->hw.init = &init; 673 674 clk = devm_clk_register(dev, &enh_fixed_div->hw); 675 if (WARN_ON(IS_ERR(clk))) 676 return PTR_ERR(clk); 677 678 enh_div = devm_kzalloc(dev, sizeof(*enh_div), GFP_KERNEL); 679 if (!enh_div) 680 return -ENOMEM; 681 682 snprintf(name, sizeof(name), "%s#enh_div", dev_name(dev)); 683 init.name = name; 684 init.ops = &clk_divider_ops; 685 init.flags = CLK_SET_RATE_PARENT; 686 parent_data[0].hw = &enh_fixed_div->hw; 687 init.num_parents = 1; 688 689 enh_div->shift = 16, 690 enh_div->width = 8, 691 enh_div->reg = spicc->base + SPICC_ENH_CTL0; 692 enh_div->hw.init = &init; 693 694 clk = devm_clk_register(dev, &enh_div->hw); 695 if (WARN_ON(IS_ERR(clk))) 696 return PTR_ERR(clk); 697 698 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); 699 if (!mux) 700 return -ENOMEM; 701 702 snprintf(name, sizeof(name), "%s#sel", dev_name(dev)); 703 init.name = name; 704 init.ops = &clk_mux_ops; 705 parent_data[0].hw = &spicc->pow2_div.hw; 706 parent_data[1].hw = &enh_div->hw; 707 init.num_parents = 2; 708 init.flags = CLK_SET_RATE_PARENT; 709 710 mux->mask = 0x1, 711 mux->shift = 24, 712 mux->reg = spicc->base + SPICC_ENH_CTL0; 713 mux->hw.init = &init; 714 715 spicc->clk = devm_clk_register(dev, &mux->hw); 716 if (WARN_ON(IS_ERR(spicc->clk))) 717 return PTR_ERR(spicc->clk); 718 719 return 0; 720 } 721 722 static int meson_spicc_probe(struct platform_device *pdev) 723 { 724 struct spi_master *master; 725 struct meson_spicc_device *spicc; 726 int ret, irq; 727 728 master = spi_alloc_master(&pdev->dev, sizeof(*spicc)); 729 if (!master) { 730 dev_err(&pdev->dev, "master allocation failed\n"); 731 return -ENOMEM; 732 } 733 spicc = spi_master_get_devdata(master); 734 spicc->master = master; 735 736 spicc->data = of_device_get_match_data(&pdev->dev); 737 if (!spicc->data) { 738 dev_err(&pdev->dev, "failed to get match data\n"); 739 ret = -EINVAL; 740 goto out_master; 741 } 742 743 spicc->pdev = pdev; 744 platform_set_drvdata(pdev, spicc); 745 746 spicc->base = devm_platform_ioremap_resource(pdev, 0); 747 if (IS_ERR(spicc->base)) { 748 dev_err(&pdev->dev, "io resource mapping failed\n"); 749 ret = PTR_ERR(spicc->base); 750 goto out_master; 751 } 752 753 /* Set master mode and enable controller */ 754 writel_relaxed(SPICC_ENABLE | SPICC_MODE_MASTER, 755 spicc->base + SPICC_CONREG); 756 757 /* Disable all IRQs */ 758 writel_relaxed(0, spicc->base + SPICC_INTREG); 759 760 irq = platform_get_irq(pdev, 0); 761 if (irq < 0) { 762 ret = irq; 763 goto out_master; 764 } 765 766 ret = devm_request_irq(&pdev->dev, irq, meson_spicc_irq, 767 0, NULL, spicc); 768 if (ret) { 769 dev_err(&pdev->dev, "irq request failed\n"); 770 goto out_master; 771 } 772 773 spicc->core = devm_clk_get(&pdev->dev, "core"); 774 if (IS_ERR(spicc->core)) { 775 dev_err(&pdev->dev, "core clock request failed\n"); 776 ret = PTR_ERR(spicc->core); 777 goto out_master; 778 } 779 780 if (spicc->data->has_pclk) { 781 spicc->pclk = devm_clk_get(&pdev->dev, "pclk"); 782 if (IS_ERR(spicc->pclk)) { 783 dev_err(&pdev->dev, "pclk clock request failed\n"); 784 ret = PTR_ERR(spicc->pclk); 785 goto out_master; 786 } 787 } 788 789 ret = clk_prepare_enable(spicc->core); 790 if (ret) { 791 dev_err(&pdev->dev, "core clock enable failed\n"); 792 goto out_master; 793 } 794 795 ret = clk_prepare_enable(spicc->pclk); 796 if (ret) { 797 dev_err(&pdev->dev, "pclk clock enable failed\n"); 798 goto out_core_clk; 799 } 800 801 device_reset_optional(&pdev->dev); 802 803 master->num_chipselect = 4; 804 master->dev.of_node = pdev->dev.of_node; 805 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH; 806 master->bits_per_word_mask = SPI_BPW_MASK(32) | 807 SPI_BPW_MASK(24) | 808 SPI_BPW_MASK(16) | 809 SPI_BPW_MASK(8); 810 master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX); 811 master->min_speed_hz = spicc->data->min_speed_hz; 812 master->max_speed_hz = spicc->data->max_speed_hz; 813 master->setup = meson_spicc_setup; 814 master->cleanup = meson_spicc_cleanup; 815 master->prepare_message = meson_spicc_prepare_message; 816 master->unprepare_transfer_hardware = meson_spicc_unprepare_transfer; 817 master->transfer_one = meson_spicc_transfer_one; 818 master->use_gpio_descriptors = true; 819 820 meson_spicc_oen_enable(spicc); 821 822 ret = meson_spicc_pow2_clk_init(spicc); 823 if (ret) { 824 dev_err(&pdev->dev, "pow2 clock registration failed\n"); 825 goto out_clk; 826 } 827 828 if (spicc->data->has_enhance_clk_div) { 829 ret = meson_spicc_enh_clk_init(spicc); 830 if (ret) { 831 dev_err(&pdev->dev, "clock registration failed\n"); 832 goto out_clk; 833 } 834 } 835 836 ret = devm_spi_register_master(&pdev->dev, master); 837 if (ret) { 838 dev_err(&pdev->dev, "spi master registration failed\n"); 839 goto out_clk; 840 } 841 842 return 0; 843 844 out_clk: 845 clk_disable_unprepare(spicc->pclk); 846 847 out_core_clk: 848 clk_disable_unprepare(spicc->core); 849 850 out_master: 851 spi_master_put(master); 852 853 return ret; 854 } 855 856 static int meson_spicc_remove(struct platform_device *pdev) 857 { 858 struct meson_spicc_device *spicc = platform_get_drvdata(pdev); 859 860 /* Disable SPI */ 861 writel(0, spicc->base + SPICC_CONREG); 862 863 clk_disable_unprepare(spicc->core); 864 clk_disable_unprepare(spicc->pclk); 865 866 spi_master_put(spicc->master); 867 868 return 0; 869 } 870 871 static const struct meson_spicc_data meson_spicc_gx_data = { 872 .max_speed_hz = 30000000, 873 .min_speed_hz = 325000, 874 .fifo_size = 16, 875 }; 876 877 static const struct meson_spicc_data meson_spicc_axg_data = { 878 .max_speed_hz = 80000000, 879 .min_speed_hz = 325000, 880 .fifo_size = 16, 881 .has_oen = true, 882 .has_enhance_clk_div = true, 883 }; 884 885 static const struct meson_spicc_data meson_spicc_g12a_data = { 886 .max_speed_hz = 166666666, 887 .min_speed_hz = 50000, 888 .fifo_size = 15, 889 .has_oen = true, 890 .has_enhance_clk_div = true, 891 .has_pclk = true, 892 }; 893 894 static const struct of_device_id meson_spicc_of_match[] = { 895 { 896 .compatible = "amlogic,meson-gx-spicc", 897 .data = &meson_spicc_gx_data, 898 }, 899 { 900 .compatible = "amlogic,meson-axg-spicc", 901 .data = &meson_spicc_axg_data, 902 }, 903 { 904 .compatible = "amlogic,meson-g12a-spicc", 905 .data = &meson_spicc_g12a_data, 906 }, 907 { /* sentinel */ } 908 }; 909 MODULE_DEVICE_TABLE(of, meson_spicc_of_match); 910 911 static struct platform_driver meson_spicc_driver = { 912 .probe = meson_spicc_probe, 913 .remove = meson_spicc_remove, 914 .driver = { 915 .name = "meson-spicc", 916 .of_match_table = of_match_ptr(meson_spicc_of_match), 917 }, 918 }; 919 920 module_platform_driver(meson_spicc_driver); 921 922 MODULE_DESCRIPTION("Meson SPI Communication Controller driver"); 923 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>"); 924 MODULE_LICENSE("GPL"); 925