1454fa271SNeil Armstrong /* 2454fa271SNeil Armstrong * Driver for Amlogic Meson SPI communication controller (SPICC) 3454fa271SNeil Armstrong * 4454fa271SNeil Armstrong * Copyright (C) BayLibre, SAS 5454fa271SNeil Armstrong * Author: Neil Armstrong <narmstrong@baylibre.com> 6454fa271SNeil Armstrong * 7454fa271SNeil Armstrong * SPDX-License-Identifier: GPL-2.0+ 8454fa271SNeil Armstrong */ 9454fa271SNeil Armstrong 10454fa271SNeil Armstrong #include <linux/bitfield.h> 11454fa271SNeil Armstrong #include <linux/clk.h> 12a6cda1f9SSunny Luo #include <linux/clk-provider.h> 13454fa271SNeil Armstrong #include <linux/device.h> 14454fa271SNeil Armstrong #include <linux/io.h> 15454fa271SNeil Armstrong #include <linux/kernel.h> 16454fa271SNeil Armstrong #include <linux/module.h> 17454fa271SNeil Armstrong #include <linux/of.h> 18a6cda1f9SSunny Luo #include <linux/of_device.h> 19454fa271SNeil Armstrong #include <linux/platform_device.h> 20454fa271SNeil Armstrong #include <linux/spi/spi.h> 21454fa271SNeil Armstrong #include <linux/types.h> 22454fa271SNeil Armstrong #include <linux/interrupt.h> 23454fa271SNeil Armstrong #include <linux/reset.h> 24454fa271SNeil Armstrong 25454fa271SNeil Armstrong /* 26454fa271SNeil Armstrong * The Meson SPICC controller could support DMA based transfers, but is not 27454fa271SNeil Armstrong * implemented by the vendor code, and while having the registers documentation 28454fa271SNeil Armstrong * it has never worked on the GXL Hardware. 29454fa271SNeil Armstrong * The PIO mode is the only mode implemented, and due to badly designed HW : 30454fa271SNeil Armstrong * - all transfers are cutted in 16 words burst because the FIFO hangs on 31454fa271SNeil Armstrong * TX underflow, and there is no TX "Half-Empty" interrupt, so we go by 32454fa271SNeil Armstrong * FIFO max size chunk only 33454fa271SNeil Armstrong * - CS management is dumb, and goes UP between every burst, so is really a 34454fa271SNeil Armstrong * "Data Valid" signal than a Chip Select, GPIO link should be used instead 35454fa271SNeil Armstrong * to have a CS go down over the full transfer 36454fa271SNeil Armstrong */ 37454fa271SNeil Armstrong 38454fa271SNeil Armstrong #define SPICC_MAX_BURST 128 39454fa271SNeil Armstrong 40454fa271SNeil Armstrong /* Register Map */ 41454fa271SNeil Armstrong #define SPICC_RXDATA 0x00 42454fa271SNeil Armstrong 43454fa271SNeil Armstrong #define SPICC_TXDATA 0x04 44454fa271SNeil Armstrong 45454fa271SNeil Armstrong #define SPICC_CONREG 0x08 46454fa271SNeil Armstrong #define SPICC_ENABLE BIT(0) 47454fa271SNeil Armstrong #define SPICC_MODE_MASTER BIT(1) 48454fa271SNeil Armstrong #define SPICC_XCH BIT(2) 49454fa271SNeil Armstrong #define SPICC_SMC BIT(3) 50454fa271SNeil Armstrong #define SPICC_POL BIT(4) 51454fa271SNeil Armstrong #define SPICC_PHA BIT(5) 52454fa271SNeil Armstrong #define SPICC_SSCTL BIT(6) 53454fa271SNeil Armstrong #define SPICC_SSPOL BIT(7) 54454fa271SNeil Armstrong #define SPICC_DRCTL_MASK GENMASK(9, 8) 55454fa271SNeil Armstrong #define SPICC_DRCTL_IGNORE 0 56454fa271SNeil Armstrong #define SPICC_DRCTL_FALLING 1 57454fa271SNeil Armstrong #define SPICC_DRCTL_LOWLEVEL 2 58454fa271SNeil Armstrong #define SPICC_CS_MASK GENMASK(13, 12) 59454fa271SNeil Armstrong #define SPICC_DATARATE_MASK GENMASK(18, 16) 60454fa271SNeil Armstrong #define SPICC_DATARATE_DIV4 0 61454fa271SNeil Armstrong #define SPICC_DATARATE_DIV8 1 62454fa271SNeil Armstrong #define SPICC_DATARATE_DIV16 2 63454fa271SNeil Armstrong #define SPICC_DATARATE_DIV32 3 64454fa271SNeil Armstrong #define SPICC_BITLENGTH_MASK GENMASK(24, 19) 65454fa271SNeil Armstrong #define SPICC_BURSTLENGTH_MASK GENMASK(31, 25) 66454fa271SNeil Armstrong 67454fa271SNeil Armstrong #define SPICC_INTREG 0x0c 68454fa271SNeil Armstrong #define SPICC_TE_EN BIT(0) /* TX FIFO Empty Interrupt */ 69454fa271SNeil Armstrong #define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */ 70454fa271SNeil Armstrong #define SPICC_TF_EN BIT(2) /* TX FIFO Full Interrupt */ 71454fa271SNeil Armstrong #define SPICC_RR_EN BIT(3) /* RX FIFO Ready Interrupt */ 72454fa271SNeil Armstrong #define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */ 73454fa271SNeil Armstrong #define SPICC_RF_EN BIT(5) /* RX FIFO Full Interrupt */ 74454fa271SNeil Armstrong #define SPICC_RO_EN BIT(6) /* RX FIFO Overflow Interrupt */ 75454fa271SNeil Armstrong #define SPICC_TC_EN BIT(7) /* Transfert Complete Interrupt */ 76454fa271SNeil Armstrong 77454fa271SNeil Armstrong #define SPICC_DMAREG 0x10 78454fa271SNeil Armstrong #define SPICC_DMA_ENABLE BIT(0) 79454fa271SNeil Armstrong #define SPICC_TXFIFO_THRESHOLD_MASK GENMASK(5, 1) 80454fa271SNeil Armstrong #define SPICC_RXFIFO_THRESHOLD_MASK GENMASK(10, 6) 81454fa271SNeil Armstrong #define SPICC_READ_BURST_MASK GENMASK(14, 11) 82454fa271SNeil Armstrong #define SPICC_WRITE_BURST_MASK GENMASK(18, 15) 83454fa271SNeil Armstrong #define SPICC_DMA_URGENT BIT(19) 84454fa271SNeil Armstrong #define SPICC_DMA_THREADID_MASK GENMASK(25, 20) 85454fa271SNeil Armstrong #define SPICC_DMA_BURSTNUM_MASK GENMASK(31, 26) 86454fa271SNeil Armstrong 87454fa271SNeil Armstrong #define SPICC_STATREG 0x14 88454fa271SNeil Armstrong #define SPICC_TE BIT(0) /* TX FIFO Empty Interrupt */ 89454fa271SNeil Armstrong #define SPICC_TH BIT(1) /* TX FIFO Half-Full Interrupt */ 90454fa271SNeil Armstrong #define SPICC_TF BIT(2) /* TX FIFO Full Interrupt */ 91454fa271SNeil Armstrong #define SPICC_RR BIT(3) /* RX FIFO Ready Interrupt */ 92454fa271SNeil Armstrong #define SPICC_RH BIT(4) /* RX FIFO Half-Full Interrupt */ 93454fa271SNeil Armstrong #define SPICC_RF BIT(5) /* RX FIFO Full Interrupt */ 94454fa271SNeil Armstrong #define SPICC_RO BIT(6) /* RX FIFO Overflow Interrupt */ 95454fa271SNeil Armstrong #define SPICC_TC BIT(7) /* Transfert Complete Interrupt */ 96454fa271SNeil Armstrong 97454fa271SNeil Armstrong #define SPICC_PERIODREG 0x18 98454fa271SNeil Armstrong #define SPICC_PERIOD GENMASK(14, 0) /* Wait cycles */ 99454fa271SNeil Armstrong 100454fa271SNeil Armstrong #define SPICC_TESTREG 0x1c 101454fa271SNeil Armstrong #define SPICC_TXCNT_MASK GENMASK(4, 0) /* TX FIFO Counter */ 102454fa271SNeil Armstrong #define SPICC_RXCNT_MASK GENMASK(9, 5) /* RX FIFO Counter */ 103454fa271SNeil Armstrong #define SPICC_SMSTATUS_MASK GENMASK(12, 10) /* State Machine Status */ 104454fa271SNeil Armstrong #define SPICC_LBC_RO BIT(13) /* Loop Back Control Read-Only */ 105454fa271SNeil Armstrong #define SPICC_LBC_W1 BIT(14) /* Loop Back Control Write-Only */ 106454fa271SNeil Armstrong #define SPICC_SWAP_RO BIT(14) /* RX FIFO Data Swap Read-Only */ 107454fa271SNeil Armstrong #define SPICC_SWAP_W1 BIT(15) /* RX FIFO Data Swap Write-Only */ 108454fa271SNeil Armstrong #define SPICC_DLYCTL_RO_MASK GENMASK(20, 15) /* Delay Control Read-Only */ 109f27bff47SNeil Armstrong #define SPICC_MO_DELAY_MASK GENMASK(17, 16) /* Master Output Delay */ 110f27bff47SNeil Armstrong #define SPICC_MO_NO_DELAY 0 111f27bff47SNeil Armstrong #define SPICC_MO_DELAY_1_CYCLE 1 112f27bff47SNeil Armstrong #define SPICC_MO_DELAY_2_CYCLE 2 113f27bff47SNeil Armstrong #define SPICC_MO_DELAY_3_CYCLE 3 114f27bff47SNeil Armstrong #define SPICC_MI_DELAY_MASK GENMASK(19, 18) /* Master Input Delay */ 115f27bff47SNeil Armstrong #define SPICC_MI_NO_DELAY 0 116f27bff47SNeil Armstrong #define SPICC_MI_DELAY_1_CYCLE 1 117f27bff47SNeil Armstrong #define SPICC_MI_DELAY_2_CYCLE 2 118f27bff47SNeil Armstrong #define SPICC_MI_DELAY_3_CYCLE 3 119f27bff47SNeil Armstrong #define SPICC_MI_CAP_DELAY_MASK GENMASK(21, 20) /* Master Capture Delay */ 120f27bff47SNeil Armstrong #define SPICC_CAP_AHEAD_2_CYCLE 0 121f27bff47SNeil Armstrong #define SPICC_CAP_AHEAD_1_CYCLE 1 122f27bff47SNeil Armstrong #define SPICC_CAP_NO_DELAY 2 123f27bff47SNeil Armstrong #define SPICC_CAP_DELAY_1_CYCLE 3 124454fa271SNeil Armstrong #define SPICC_FIFORST_RO_MASK GENMASK(22, 21) /* FIFO Softreset Read-Only */ 125454fa271SNeil Armstrong #define SPICC_FIFORST_W1_MASK GENMASK(23, 22) /* FIFO Softreset Write-Only */ 126454fa271SNeil Armstrong 127454fa271SNeil Armstrong #define SPICC_DRADDR 0x20 /* Read Address of DMA */ 128454fa271SNeil Armstrong 129454fa271SNeil Armstrong #define SPICC_DWADDR 0x24 /* Write Address of DMA */ 130454fa271SNeil Armstrong 131a6cda1f9SSunny Luo #define SPICC_ENH_CTL0 0x38 /* Enhanced Feature */ 1323e0cf4d3SSunny Luo #define SPICC_ENH_CLK_CS_DELAY_MASK GENMASK(15, 0) 1333e0cf4d3SSunny Luo #define SPICC_ENH_DATARATE_MASK GENMASK(23, 16) 1343e0cf4d3SSunny Luo #define SPICC_ENH_DATARATE_EN BIT(24) 135a6cda1f9SSunny Luo #define SPICC_ENH_MOSI_OEN BIT(25) 136a6cda1f9SSunny Luo #define SPICC_ENH_CLK_OEN BIT(26) 137a6cda1f9SSunny Luo #define SPICC_ENH_CS_OEN BIT(27) 138a6cda1f9SSunny Luo #define SPICC_ENH_CLK_CS_DELAY_EN BIT(28) 139a6cda1f9SSunny Luo #define SPICC_ENH_MAIN_CLK_AO BIT(29) 140a6cda1f9SSunny Luo 141454fa271SNeil Armstrong #define writel_bits_relaxed(mask, val, addr) \ 142454fa271SNeil Armstrong writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr) 143454fa271SNeil Armstrong 144a6cda1f9SSunny Luo struct meson_spicc_data { 1453196816fSNeil Armstrong unsigned int max_speed_hz; 1468791068dSNeil Armstrong unsigned int min_speed_hz; 1470eb707acSNeil Armstrong unsigned int fifo_size; 148a6cda1f9SSunny Luo bool has_oen; 1493e0cf4d3SSunny Luo bool has_enhance_clk_div; 1504e3d3220SNeil Armstrong bool has_pclk; 151a6cda1f9SSunny Luo }; 152a6cda1f9SSunny Luo 153454fa271SNeil Armstrong struct meson_spicc_device { 154454fa271SNeil Armstrong struct spi_master *master; 155454fa271SNeil Armstrong struct platform_device *pdev; 156454fa271SNeil Armstrong void __iomem *base; 157454fa271SNeil Armstrong struct clk *core; 1584e3d3220SNeil Armstrong struct clk *pclk; 1593e0cf4d3SSunny Luo struct clk *clk; 160454fa271SNeil Armstrong struct spi_message *message; 161454fa271SNeil Armstrong struct spi_transfer *xfer; 162a6cda1f9SSunny Luo const struct meson_spicc_data *data; 163454fa271SNeil Armstrong u8 *tx_buf; 164454fa271SNeil Armstrong u8 *rx_buf; 165454fa271SNeil Armstrong unsigned int bytes_per_word; 166454fa271SNeil Armstrong unsigned long tx_remain; 167454fa271SNeil Armstrong unsigned long rx_remain; 168454fa271SNeil Armstrong unsigned long xfer_remain; 169454fa271SNeil Armstrong }; 170454fa271SNeil Armstrong 171a6cda1f9SSunny Luo static void meson_spicc_oen_enable(struct meson_spicc_device *spicc) 172a6cda1f9SSunny Luo { 173a6cda1f9SSunny Luo u32 conf; 174a6cda1f9SSunny Luo 175a6cda1f9SSunny Luo if (!spicc->data->has_oen) 176a6cda1f9SSunny Luo return; 177a6cda1f9SSunny Luo 178a6cda1f9SSunny Luo conf = readl_relaxed(spicc->base + SPICC_ENH_CTL0) | 179a6cda1f9SSunny Luo SPICC_ENH_MOSI_OEN | SPICC_ENH_CLK_OEN | SPICC_ENH_CS_OEN; 180a6cda1f9SSunny Luo 181a6cda1f9SSunny Luo writel_relaxed(conf, spicc->base + SPICC_ENH_CTL0); 182a6cda1f9SSunny Luo } 183a6cda1f9SSunny Luo 184454fa271SNeil Armstrong static inline bool meson_spicc_txfull(struct meson_spicc_device *spicc) 185454fa271SNeil Armstrong { 186454fa271SNeil Armstrong return !!FIELD_GET(SPICC_TF, 187454fa271SNeil Armstrong readl_relaxed(spicc->base + SPICC_STATREG)); 188454fa271SNeil Armstrong } 189454fa271SNeil Armstrong 190454fa271SNeil Armstrong static inline bool meson_spicc_rxready(struct meson_spicc_device *spicc) 191454fa271SNeil Armstrong { 1920eb707acSNeil Armstrong return FIELD_GET(SPICC_RH | SPICC_RR | SPICC_RF, 193454fa271SNeil Armstrong readl_relaxed(spicc->base + SPICC_STATREG)); 194454fa271SNeil Armstrong } 195454fa271SNeil Armstrong 196454fa271SNeil Armstrong static inline u32 meson_spicc_pull_data(struct meson_spicc_device *spicc) 197454fa271SNeil Armstrong { 198454fa271SNeil Armstrong unsigned int bytes = spicc->bytes_per_word; 199454fa271SNeil Armstrong unsigned int byte_shift = 0; 200454fa271SNeil Armstrong u32 data = 0; 201454fa271SNeil Armstrong u8 byte; 202454fa271SNeil Armstrong 203454fa271SNeil Armstrong while (bytes--) { 204454fa271SNeil Armstrong byte = *spicc->tx_buf++; 205454fa271SNeil Armstrong data |= (byte & 0xff) << byte_shift; 206454fa271SNeil Armstrong byte_shift += 8; 207454fa271SNeil Armstrong } 208454fa271SNeil Armstrong 209454fa271SNeil Armstrong spicc->tx_remain--; 210454fa271SNeil Armstrong return data; 211454fa271SNeil Armstrong } 212454fa271SNeil Armstrong 213454fa271SNeil Armstrong static inline void meson_spicc_push_data(struct meson_spicc_device *spicc, 214454fa271SNeil Armstrong u32 data) 215454fa271SNeil Armstrong { 216454fa271SNeil Armstrong unsigned int bytes = spicc->bytes_per_word; 217454fa271SNeil Armstrong unsigned int byte_shift = 0; 218454fa271SNeil Armstrong u8 byte; 219454fa271SNeil Armstrong 220454fa271SNeil Armstrong while (bytes--) { 221454fa271SNeil Armstrong byte = (data >> byte_shift) & 0xff; 222454fa271SNeil Armstrong *spicc->rx_buf++ = byte; 223454fa271SNeil Armstrong byte_shift += 8; 224454fa271SNeil Armstrong } 225454fa271SNeil Armstrong 226454fa271SNeil Armstrong spicc->rx_remain--; 227454fa271SNeil Armstrong } 228454fa271SNeil Armstrong 229454fa271SNeil Armstrong static inline void meson_spicc_rx(struct meson_spicc_device *spicc) 230454fa271SNeil Armstrong { 231454fa271SNeil Armstrong /* Empty RX FIFO */ 232454fa271SNeil Armstrong while (spicc->rx_remain && 233454fa271SNeil Armstrong meson_spicc_rxready(spicc)) 234454fa271SNeil Armstrong meson_spicc_push_data(spicc, 235454fa271SNeil Armstrong readl_relaxed(spicc->base + SPICC_RXDATA)); 236454fa271SNeil Armstrong } 237454fa271SNeil Armstrong 238454fa271SNeil Armstrong static inline void meson_spicc_tx(struct meson_spicc_device *spicc) 239454fa271SNeil Armstrong { 240454fa271SNeil Armstrong /* Fill Up TX FIFO */ 241454fa271SNeil Armstrong while (spicc->tx_remain && 242454fa271SNeil Armstrong !meson_spicc_txfull(spicc)) 243454fa271SNeil Armstrong writel_relaxed(meson_spicc_pull_data(spicc), 244454fa271SNeil Armstrong spicc->base + SPICC_TXDATA); 245454fa271SNeil Armstrong } 246454fa271SNeil Armstrong 2470eb707acSNeil Armstrong static inline void meson_spicc_setup_burst(struct meson_spicc_device *spicc) 248454fa271SNeil Armstrong { 249454fa271SNeil Armstrong 2500eb707acSNeil Armstrong unsigned int burst_len = min_t(unsigned int, 2510eb707acSNeil Armstrong spicc->xfer_remain / 2520eb707acSNeil Armstrong spicc->bytes_per_word, 2530eb707acSNeil Armstrong spicc->data->fifo_size); 254454fa271SNeil Armstrong /* Setup Xfer variables */ 255454fa271SNeil Armstrong spicc->tx_remain = burst_len; 256454fa271SNeil Armstrong spicc->rx_remain = burst_len; 257454fa271SNeil Armstrong spicc->xfer_remain -= burst_len * spicc->bytes_per_word; 258454fa271SNeil Armstrong 259454fa271SNeil Armstrong /* Setup burst length */ 260454fa271SNeil Armstrong writel_bits_relaxed(SPICC_BURSTLENGTH_MASK, 261454fa271SNeil Armstrong FIELD_PREP(SPICC_BURSTLENGTH_MASK, 2620eb707acSNeil Armstrong burst_len - 1), 263454fa271SNeil Armstrong spicc->base + SPICC_CONREG); 264454fa271SNeil Armstrong 265454fa271SNeil Armstrong /* Fill TX FIFO */ 266454fa271SNeil Armstrong meson_spicc_tx(spicc); 267454fa271SNeil Armstrong } 268454fa271SNeil Armstrong 269454fa271SNeil Armstrong static irqreturn_t meson_spicc_irq(int irq, void *data) 270454fa271SNeil Armstrong { 271454fa271SNeil Armstrong struct meson_spicc_device *spicc = (void *) data; 272454fa271SNeil Armstrong 2730eb707acSNeil Armstrong writel_bits_relaxed(SPICC_TC, SPICC_TC, spicc->base + SPICC_STATREG); 274454fa271SNeil Armstrong 275454fa271SNeil Armstrong /* Empty RX FIFO */ 276454fa271SNeil Armstrong meson_spicc_rx(spicc); 277454fa271SNeil Armstrong 2780eb707acSNeil Armstrong if (!spicc->xfer_remain) { 279454fa271SNeil Armstrong /* Disable all IRQs */ 280454fa271SNeil Armstrong writel(0, spicc->base + SPICC_INTREG); 281454fa271SNeil Armstrong 282454fa271SNeil Armstrong spi_finalize_current_transfer(spicc->master); 283454fa271SNeil Armstrong 284454fa271SNeil Armstrong return IRQ_HANDLED; 285454fa271SNeil Armstrong } 286454fa271SNeil Armstrong 287454fa271SNeil Armstrong /* Setup burst */ 2880eb707acSNeil Armstrong meson_spicc_setup_burst(spicc); 289454fa271SNeil Armstrong 2900eb707acSNeil Armstrong /* Start burst */ 2910eb707acSNeil Armstrong writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG); 292454fa271SNeil Armstrong 293454fa271SNeil Armstrong return IRQ_HANDLED; 294454fa271SNeil Armstrong } 295454fa271SNeil Armstrong 296f27bff47SNeil Armstrong static void meson_spicc_auto_io_delay(struct meson_spicc_device *spicc) 297f27bff47SNeil Armstrong { 298f27bff47SNeil Armstrong u32 div, hz; 299f27bff47SNeil Armstrong u32 mi_delay, cap_delay; 300f27bff47SNeil Armstrong u32 conf; 301f27bff47SNeil Armstrong 302f27bff47SNeil Armstrong if (spicc->data->has_enhance_clk_div) { 303f27bff47SNeil Armstrong div = FIELD_GET(SPICC_ENH_DATARATE_MASK, 304f27bff47SNeil Armstrong readl_relaxed(spicc->base + SPICC_ENH_CTL0)); 305f27bff47SNeil Armstrong div++; 306f27bff47SNeil Armstrong div <<= 1; 307f27bff47SNeil Armstrong } else { 308f27bff47SNeil Armstrong div = FIELD_GET(SPICC_DATARATE_MASK, 309f27bff47SNeil Armstrong readl_relaxed(spicc->base + SPICC_CONREG)); 310f27bff47SNeil Armstrong div += 2; 311f27bff47SNeil Armstrong div = 1 << div; 312f27bff47SNeil Armstrong } 313f27bff47SNeil Armstrong 314f27bff47SNeil Armstrong mi_delay = SPICC_MI_NO_DELAY; 315f27bff47SNeil Armstrong cap_delay = SPICC_CAP_AHEAD_2_CYCLE; 316f27bff47SNeil Armstrong hz = clk_get_rate(spicc->clk); 317f27bff47SNeil Armstrong 318f27bff47SNeil Armstrong if (hz >= 100000000) 319f27bff47SNeil Armstrong cap_delay = SPICC_CAP_DELAY_1_CYCLE; 320f27bff47SNeil Armstrong else if (hz >= 80000000) 321f27bff47SNeil Armstrong cap_delay = SPICC_CAP_NO_DELAY; 322f27bff47SNeil Armstrong else if (hz >= 40000000) 323f27bff47SNeil Armstrong cap_delay = SPICC_CAP_AHEAD_1_CYCLE; 324f27bff47SNeil Armstrong else if (div >= 16) 325f27bff47SNeil Armstrong mi_delay = SPICC_MI_DELAY_3_CYCLE; 326f27bff47SNeil Armstrong else if (div >= 8) 327f27bff47SNeil Armstrong mi_delay = SPICC_MI_DELAY_2_CYCLE; 328f27bff47SNeil Armstrong else if (div >= 6) 329f27bff47SNeil Armstrong mi_delay = SPICC_MI_DELAY_1_CYCLE; 330f27bff47SNeil Armstrong 331f27bff47SNeil Armstrong conf = readl_relaxed(spicc->base + SPICC_TESTREG); 332f27bff47SNeil Armstrong conf &= ~(SPICC_MO_DELAY_MASK | SPICC_MI_DELAY_MASK 333f27bff47SNeil Armstrong | SPICC_MI_CAP_DELAY_MASK); 334f27bff47SNeil Armstrong conf |= FIELD_PREP(SPICC_MI_DELAY_MASK, mi_delay); 335f27bff47SNeil Armstrong conf |= FIELD_PREP(SPICC_MI_CAP_DELAY_MASK, cap_delay); 336f27bff47SNeil Armstrong writel_relaxed(conf, spicc->base + SPICC_TESTREG); 337f27bff47SNeil Armstrong } 338f27bff47SNeil Armstrong 339454fa271SNeil Armstrong static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc, 340454fa271SNeil Armstrong struct spi_transfer *xfer) 341454fa271SNeil Armstrong { 342454fa271SNeil Armstrong u32 conf, conf_orig; 343454fa271SNeil Armstrong 344454fa271SNeil Armstrong /* Read original configuration */ 345454fa271SNeil Armstrong conf = conf_orig = readl_relaxed(spicc->base + SPICC_CONREG); 346454fa271SNeil Armstrong 347454fa271SNeil Armstrong /* Setup word width */ 348454fa271SNeil Armstrong conf &= ~SPICC_BITLENGTH_MASK; 349454fa271SNeil Armstrong conf |= FIELD_PREP(SPICC_BITLENGTH_MASK, 350454fa271SNeil Armstrong (spicc->bytes_per_word << 3) - 1); 351454fa271SNeil Armstrong 352454fa271SNeil Armstrong /* Ignore if unchanged */ 353454fa271SNeil Armstrong if (conf != conf_orig) 354454fa271SNeil Armstrong writel_relaxed(conf, spicc->base + SPICC_CONREG); 3553e0cf4d3SSunny Luo 3563e0cf4d3SSunny Luo clk_set_rate(spicc->clk, xfer->speed_hz); 357f27bff47SNeil Armstrong 358f27bff47SNeil Armstrong meson_spicc_auto_io_delay(spicc); 3590eb707acSNeil Armstrong 3600eb707acSNeil Armstrong writel_relaxed(0, spicc->base + SPICC_DMAREG); 3610eb707acSNeil Armstrong } 3620eb707acSNeil Armstrong 3630eb707acSNeil Armstrong static void meson_spicc_reset_fifo(struct meson_spicc_device *spicc) 3640eb707acSNeil Armstrong { 3650eb707acSNeil Armstrong if (spicc->data->has_oen) 3660eb707acSNeil Armstrong writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO, 3670eb707acSNeil Armstrong SPICC_ENH_MAIN_CLK_AO, 3680eb707acSNeil Armstrong spicc->base + SPICC_ENH_CTL0); 3690eb707acSNeil Armstrong 3700eb707acSNeil Armstrong writel_bits_relaxed(SPICC_FIFORST_W1_MASK, SPICC_FIFORST_W1_MASK, 3710eb707acSNeil Armstrong spicc->base + SPICC_TESTREG); 3720eb707acSNeil Armstrong 3730eb707acSNeil Armstrong while (meson_spicc_rxready(spicc)) 374d9b883aeSLee Jones readl_relaxed(spicc->base + SPICC_RXDATA); 3750eb707acSNeil Armstrong 3760eb707acSNeil Armstrong if (spicc->data->has_oen) 3770eb707acSNeil Armstrong writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO, 0, 3780eb707acSNeil Armstrong spicc->base + SPICC_ENH_CTL0); 379454fa271SNeil Armstrong } 380454fa271SNeil Armstrong 381454fa271SNeil Armstrong static int meson_spicc_transfer_one(struct spi_master *master, 382454fa271SNeil Armstrong struct spi_device *spi, 383454fa271SNeil Armstrong struct spi_transfer *xfer) 384454fa271SNeil Armstrong { 385454fa271SNeil Armstrong struct meson_spicc_device *spicc = spi_master_get_devdata(master); 386454fa271SNeil Armstrong 387454fa271SNeil Armstrong /* Store current transfer */ 388454fa271SNeil Armstrong spicc->xfer = xfer; 389454fa271SNeil Armstrong 390454fa271SNeil Armstrong /* Setup transfer parameters */ 391454fa271SNeil Armstrong spicc->tx_buf = (u8 *)xfer->tx_buf; 392454fa271SNeil Armstrong spicc->rx_buf = (u8 *)xfer->rx_buf; 393454fa271SNeil Armstrong spicc->xfer_remain = xfer->len; 394454fa271SNeil Armstrong 395454fa271SNeil Armstrong /* Pre-calculate word size */ 396454fa271SNeil Armstrong spicc->bytes_per_word = 397454fa271SNeil Armstrong DIV_ROUND_UP(spicc->xfer->bits_per_word, 8); 398454fa271SNeil Armstrong 3990eb707acSNeil Armstrong if (xfer->len % spicc->bytes_per_word) 4000eb707acSNeil Armstrong return -EINVAL; 4010eb707acSNeil Armstrong 402454fa271SNeil Armstrong /* Setup transfer parameters */ 403454fa271SNeil Armstrong meson_spicc_setup_xfer(spicc, xfer); 404454fa271SNeil Armstrong 4050eb707acSNeil Armstrong meson_spicc_reset_fifo(spicc); 406454fa271SNeil Armstrong 4070eb707acSNeil Armstrong /* Setup burst */ 4080eb707acSNeil Armstrong meson_spicc_setup_burst(spicc); 409454fa271SNeil Armstrong 410454fa271SNeil Armstrong /* Start burst */ 411454fa271SNeil Armstrong writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG); 412454fa271SNeil Armstrong 413454fa271SNeil Armstrong /* Enable interrupts */ 4140eb707acSNeil Armstrong writel_relaxed(SPICC_TC_EN, spicc->base + SPICC_INTREG); 415454fa271SNeil Armstrong 416454fa271SNeil Armstrong return 1; 417454fa271SNeil Armstrong } 418454fa271SNeil Armstrong 419454fa271SNeil Armstrong static int meson_spicc_prepare_message(struct spi_master *master, 420454fa271SNeil Armstrong struct spi_message *message) 421454fa271SNeil Armstrong { 422454fa271SNeil Armstrong struct meson_spicc_device *spicc = spi_master_get_devdata(master); 423454fa271SNeil Armstrong struct spi_device *spi = message->spi; 424454fa271SNeil Armstrong u32 conf = 0; 425454fa271SNeil Armstrong 426454fa271SNeil Armstrong /* Store current message */ 427454fa271SNeil Armstrong spicc->message = message; 428454fa271SNeil Armstrong 429454fa271SNeil Armstrong /* Enable Master */ 430454fa271SNeil Armstrong conf |= SPICC_ENABLE; 431454fa271SNeil Armstrong conf |= SPICC_MODE_MASTER; 432454fa271SNeil Armstrong 433454fa271SNeil Armstrong /* SMC = 0 */ 434454fa271SNeil Armstrong 435454fa271SNeil Armstrong /* Setup transfer mode */ 436454fa271SNeil Armstrong if (spi->mode & SPI_CPOL) 437454fa271SNeil Armstrong conf |= SPICC_POL; 438454fa271SNeil Armstrong else 439454fa271SNeil Armstrong conf &= ~SPICC_POL; 440454fa271SNeil Armstrong 441454fa271SNeil Armstrong if (spi->mode & SPI_CPHA) 442454fa271SNeil Armstrong conf |= SPICC_PHA; 443454fa271SNeil Armstrong else 444454fa271SNeil Armstrong conf &= ~SPICC_PHA; 445454fa271SNeil Armstrong 446454fa271SNeil Armstrong /* SSCTL = 0 */ 447454fa271SNeil Armstrong 448454fa271SNeil Armstrong if (spi->mode & SPI_CS_HIGH) 449454fa271SNeil Armstrong conf |= SPICC_SSPOL; 450454fa271SNeil Armstrong else 451454fa271SNeil Armstrong conf &= ~SPICC_SSPOL; 452454fa271SNeil Armstrong 453454fa271SNeil Armstrong if (spi->mode & SPI_READY) 454454fa271SNeil Armstrong conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_LOWLEVEL); 455454fa271SNeil Armstrong else 456454fa271SNeil Armstrong conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_IGNORE); 457454fa271SNeil Armstrong 458454fa271SNeil Armstrong /* Select CS */ 459454fa271SNeil Armstrong conf |= FIELD_PREP(SPICC_CS_MASK, spi->chip_select); 460454fa271SNeil Armstrong 461454fa271SNeil Armstrong /* Default Clock rate core/4 */ 462454fa271SNeil Armstrong 463454fa271SNeil Armstrong /* Default 8bit word */ 464454fa271SNeil Armstrong conf |= FIELD_PREP(SPICC_BITLENGTH_MASK, 8 - 1); 465454fa271SNeil Armstrong 466454fa271SNeil Armstrong writel_relaxed(conf, spicc->base + SPICC_CONREG); 467454fa271SNeil Armstrong 468454fa271SNeil Armstrong /* Setup no wait cycles by default */ 469454fa271SNeil Armstrong writel_relaxed(0, spicc->base + SPICC_PERIODREG); 470454fa271SNeil Armstrong 4710eb707acSNeil Armstrong writel_bits_relaxed(SPICC_LBC_W1, 0, spicc->base + SPICC_TESTREG); 472454fa271SNeil Armstrong 473454fa271SNeil Armstrong return 0; 474454fa271SNeil Armstrong } 475454fa271SNeil Armstrong 476454fa271SNeil Armstrong static int meson_spicc_unprepare_transfer(struct spi_master *master) 477454fa271SNeil Armstrong { 478454fa271SNeil Armstrong struct meson_spicc_device *spicc = spi_master_get_devdata(master); 479454fa271SNeil Armstrong 480454fa271SNeil Armstrong /* Disable all IRQs */ 481454fa271SNeil Armstrong writel(0, spicc->base + SPICC_INTREG); 482454fa271SNeil Armstrong 483454fa271SNeil Armstrong device_reset_optional(&spicc->pdev->dev); 484454fa271SNeil Armstrong 485454fa271SNeil Armstrong return 0; 486454fa271SNeil Armstrong } 487454fa271SNeil Armstrong 488454fa271SNeil Armstrong static int meson_spicc_setup(struct spi_device *spi) 489454fa271SNeil Armstrong { 490454fa271SNeil Armstrong if (!spi->controller_state) 491454fa271SNeil Armstrong spi->controller_state = spi_master_get_devdata(spi->master); 492cd8fb859SLinus Walleij 493454fa271SNeil Armstrong return 0; 494454fa271SNeil Armstrong } 495454fa271SNeil Armstrong 496454fa271SNeil Armstrong static void meson_spicc_cleanup(struct spi_device *spi) 497454fa271SNeil Armstrong { 498454fa271SNeil Armstrong spi->controller_state = NULL; 499454fa271SNeil Armstrong } 500454fa271SNeil Armstrong 5013e0cf4d3SSunny Luo /* 5023e0cf4d3SSunny Luo * The Clock Mux 5033e0cf4d3SSunny Luo * x-----------------x x------------x x------\ 5043e0cf4d3SSunny Luo * |---| pow2 fixed div |---| pow2 div |----| | 5053e0cf4d3SSunny Luo * | x-----------------x x------------x | | 5063e0cf4d3SSunny Luo * src ---| | mux |-- out 5073e0cf4d3SSunny Luo * | x-----------------x x------------x | | 5083e0cf4d3SSunny Luo * |---| enh fixed div |---| enh div |0---| | 5093e0cf4d3SSunny Luo * x-----------------x x------------x x------/ 5103e0cf4d3SSunny Luo * 5113e0cf4d3SSunny Luo * Clk path for GX series: 5123e0cf4d3SSunny Luo * src -> pow2 fixed div -> pow2 div -> out 5133e0cf4d3SSunny Luo * 5143e0cf4d3SSunny Luo * Clk path for AXG series: 5153e0cf4d3SSunny Luo * src -> pow2 fixed div -> pow2 div -> mux -> out 5163e0cf4d3SSunny Luo * src -> enh fixed div -> enh div -> mux -> out 5174e3d3220SNeil Armstrong * 5184e3d3220SNeil Armstrong * Clk path for G12A series: 5194e3d3220SNeil Armstrong * pclk -> pow2 fixed div -> pow2 div -> mux -> out 5204e3d3220SNeil Armstrong * pclk -> enh fixed div -> enh div -> mux -> out 5213e0cf4d3SSunny Luo */ 5223e0cf4d3SSunny Luo 5233e0cf4d3SSunny Luo static int meson_spicc_clk_init(struct meson_spicc_device *spicc) 5243e0cf4d3SSunny Luo { 5253e0cf4d3SSunny Luo struct device *dev = &spicc->pdev->dev; 5263e0cf4d3SSunny Luo struct clk_fixed_factor *pow2_fixed_div, *enh_fixed_div; 5273e0cf4d3SSunny Luo struct clk_divider *pow2_div, *enh_div; 5283e0cf4d3SSunny Luo struct clk_mux *mux; 5293e0cf4d3SSunny Luo struct clk_init_data init; 5303e0cf4d3SSunny Luo struct clk *clk; 5313e0cf4d3SSunny Luo struct clk_parent_data parent_data[2]; 5323e0cf4d3SSunny Luo char name[64]; 5333e0cf4d3SSunny Luo 5343e0cf4d3SSunny Luo memset(&init, 0, sizeof(init)); 5353e0cf4d3SSunny Luo memset(&parent_data, 0, sizeof(parent_data)); 5363e0cf4d3SSunny Luo 5373e0cf4d3SSunny Luo init.parent_data = parent_data; 5383e0cf4d3SSunny Luo 5393e0cf4d3SSunny Luo /* algorithm for pow2 div: rate = freq / 4 / (2 ^ N) */ 5403e0cf4d3SSunny Luo 5413e0cf4d3SSunny Luo pow2_fixed_div = devm_kzalloc(dev, sizeof(*pow2_fixed_div), GFP_KERNEL); 5423e0cf4d3SSunny Luo if (!pow2_fixed_div) 5433e0cf4d3SSunny Luo return -ENOMEM; 5443e0cf4d3SSunny Luo 5453e0cf4d3SSunny Luo snprintf(name, sizeof(name), "%s#pow2_fixed_div", dev_name(dev)); 5463e0cf4d3SSunny Luo init.name = name; 5473e0cf4d3SSunny Luo init.ops = &clk_fixed_factor_ops; 5483e0cf4d3SSunny Luo init.flags = 0; 5494e3d3220SNeil Armstrong if (spicc->data->has_pclk) 5504e3d3220SNeil Armstrong parent_data[0].hw = __clk_get_hw(spicc->pclk); 5514e3d3220SNeil Armstrong else 5523e0cf4d3SSunny Luo parent_data[0].hw = __clk_get_hw(spicc->core); 5533e0cf4d3SSunny Luo init.num_parents = 1; 5543e0cf4d3SSunny Luo 5553e0cf4d3SSunny Luo pow2_fixed_div->mult = 1, 5563e0cf4d3SSunny Luo pow2_fixed_div->div = 4, 5573e0cf4d3SSunny Luo pow2_fixed_div->hw.init = &init; 5583e0cf4d3SSunny Luo 5593e0cf4d3SSunny Luo clk = devm_clk_register(dev, &pow2_fixed_div->hw); 5603e0cf4d3SSunny Luo if (WARN_ON(IS_ERR(clk))) 5613e0cf4d3SSunny Luo return PTR_ERR(clk); 5623e0cf4d3SSunny Luo 5633e0cf4d3SSunny Luo pow2_div = devm_kzalloc(dev, sizeof(*pow2_div), GFP_KERNEL); 5643e0cf4d3SSunny Luo if (!pow2_div) 5653e0cf4d3SSunny Luo return -ENOMEM; 5663e0cf4d3SSunny Luo 5673e0cf4d3SSunny Luo snprintf(name, sizeof(name), "%s#pow2_div", dev_name(dev)); 5683e0cf4d3SSunny Luo init.name = name; 5693e0cf4d3SSunny Luo init.ops = &clk_divider_ops; 5703e0cf4d3SSunny Luo init.flags = CLK_SET_RATE_PARENT; 5713e0cf4d3SSunny Luo parent_data[0].hw = &pow2_fixed_div->hw; 5723e0cf4d3SSunny Luo init.num_parents = 1; 5733e0cf4d3SSunny Luo 5743e0cf4d3SSunny Luo pow2_div->shift = 16, 5753e0cf4d3SSunny Luo pow2_div->width = 3, 5763e0cf4d3SSunny Luo pow2_div->flags = CLK_DIVIDER_POWER_OF_TWO, 5773e0cf4d3SSunny Luo pow2_div->reg = spicc->base + SPICC_CONREG; 5783e0cf4d3SSunny Luo pow2_div->hw.init = &init; 5793e0cf4d3SSunny Luo 5803e0cf4d3SSunny Luo clk = devm_clk_register(dev, &pow2_div->hw); 5813e0cf4d3SSunny Luo if (WARN_ON(IS_ERR(clk))) 5823e0cf4d3SSunny Luo return PTR_ERR(clk); 5833e0cf4d3SSunny Luo 5843e0cf4d3SSunny Luo if (!spicc->data->has_enhance_clk_div) { 5853e0cf4d3SSunny Luo spicc->clk = clk; 5863e0cf4d3SSunny Luo return 0; 5873e0cf4d3SSunny Luo } 5883e0cf4d3SSunny Luo 5893e0cf4d3SSunny Luo /* algorithm for enh div: rate = freq / 2 / (N + 1) */ 5903e0cf4d3SSunny Luo 5913e0cf4d3SSunny Luo enh_fixed_div = devm_kzalloc(dev, sizeof(*enh_fixed_div), GFP_KERNEL); 5923e0cf4d3SSunny Luo if (!enh_fixed_div) 5933e0cf4d3SSunny Luo return -ENOMEM; 5943e0cf4d3SSunny Luo 5953e0cf4d3SSunny Luo snprintf(name, sizeof(name), "%s#enh_fixed_div", dev_name(dev)); 5963e0cf4d3SSunny Luo init.name = name; 5973e0cf4d3SSunny Luo init.ops = &clk_fixed_factor_ops; 5983e0cf4d3SSunny Luo init.flags = 0; 5994e3d3220SNeil Armstrong if (spicc->data->has_pclk) 6004e3d3220SNeil Armstrong parent_data[0].hw = __clk_get_hw(spicc->pclk); 6014e3d3220SNeil Armstrong else 6023e0cf4d3SSunny Luo parent_data[0].hw = __clk_get_hw(spicc->core); 6033e0cf4d3SSunny Luo init.num_parents = 1; 6043e0cf4d3SSunny Luo 6053e0cf4d3SSunny Luo enh_fixed_div->mult = 1, 6063e0cf4d3SSunny Luo enh_fixed_div->div = 2, 6073e0cf4d3SSunny Luo enh_fixed_div->hw.init = &init; 6083e0cf4d3SSunny Luo 6093e0cf4d3SSunny Luo clk = devm_clk_register(dev, &enh_fixed_div->hw); 6103e0cf4d3SSunny Luo if (WARN_ON(IS_ERR(clk))) 6113e0cf4d3SSunny Luo return PTR_ERR(clk); 6123e0cf4d3SSunny Luo 6133e0cf4d3SSunny Luo enh_div = devm_kzalloc(dev, sizeof(*enh_div), GFP_KERNEL); 6143e0cf4d3SSunny Luo if (!enh_div) 6153e0cf4d3SSunny Luo return -ENOMEM; 6163e0cf4d3SSunny Luo 6173e0cf4d3SSunny Luo snprintf(name, sizeof(name), "%s#enh_div", dev_name(dev)); 6183e0cf4d3SSunny Luo init.name = name; 6193e0cf4d3SSunny Luo init.ops = &clk_divider_ops; 6203e0cf4d3SSunny Luo init.flags = CLK_SET_RATE_PARENT; 6213e0cf4d3SSunny Luo parent_data[0].hw = &enh_fixed_div->hw; 6223e0cf4d3SSunny Luo init.num_parents = 1; 6233e0cf4d3SSunny Luo 6243e0cf4d3SSunny Luo enh_div->shift = 16, 6253e0cf4d3SSunny Luo enh_div->width = 8, 6263e0cf4d3SSunny Luo enh_div->reg = spicc->base + SPICC_ENH_CTL0; 6273e0cf4d3SSunny Luo enh_div->hw.init = &init; 6283e0cf4d3SSunny Luo 6293e0cf4d3SSunny Luo clk = devm_clk_register(dev, &enh_div->hw); 6303e0cf4d3SSunny Luo if (WARN_ON(IS_ERR(clk))) 6313e0cf4d3SSunny Luo return PTR_ERR(clk); 6323e0cf4d3SSunny Luo 6333e0cf4d3SSunny Luo mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); 6343e0cf4d3SSunny Luo if (!mux) 6353e0cf4d3SSunny Luo return -ENOMEM; 6363e0cf4d3SSunny Luo 6373e0cf4d3SSunny Luo snprintf(name, sizeof(name), "%s#sel", dev_name(dev)); 6383e0cf4d3SSunny Luo init.name = name; 6393e0cf4d3SSunny Luo init.ops = &clk_mux_ops; 6403e0cf4d3SSunny Luo parent_data[0].hw = &pow2_div->hw; 6413e0cf4d3SSunny Luo parent_data[1].hw = &enh_div->hw; 6423e0cf4d3SSunny Luo init.num_parents = 2; 6433e0cf4d3SSunny Luo init.flags = CLK_SET_RATE_PARENT; 6443e0cf4d3SSunny Luo 6453e0cf4d3SSunny Luo mux->mask = 0x1, 6463e0cf4d3SSunny Luo mux->shift = 24, 6473e0cf4d3SSunny Luo mux->reg = spicc->base + SPICC_ENH_CTL0; 6483e0cf4d3SSunny Luo mux->hw.init = &init; 6493e0cf4d3SSunny Luo 6503e0cf4d3SSunny Luo spicc->clk = devm_clk_register(dev, &mux->hw); 6513e0cf4d3SSunny Luo if (WARN_ON(IS_ERR(spicc->clk))) 6523e0cf4d3SSunny Luo return PTR_ERR(spicc->clk); 6533e0cf4d3SSunny Luo 6543e0cf4d3SSunny Luo return 0; 6553e0cf4d3SSunny Luo } 6563e0cf4d3SSunny Luo 657454fa271SNeil Armstrong static int meson_spicc_probe(struct platform_device *pdev) 658454fa271SNeil Armstrong { 659454fa271SNeil Armstrong struct spi_master *master; 660454fa271SNeil Armstrong struct meson_spicc_device *spicc; 6614e3d3220SNeil Armstrong int ret, irq; 662454fa271SNeil Armstrong 663454fa271SNeil Armstrong master = spi_alloc_master(&pdev->dev, sizeof(*spicc)); 664454fa271SNeil Armstrong if (!master) { 665454fa271SNeil Armstrong dev_err(&pdev->dev, "master allocation failed\n"); 666454fa271SNeil Armstrong return -ENOMEM; 667454fa271SNeil Armstrong } 668454fa271SNeil Armstrong spicc = spi_master_get_devdata(master); 669454fa271SNeil Armstrong spicc->master = master; 670454fa271SNeil Armstrong 671a6cda1f9SSunny Luo spicc->data = of_device_get_match_data(&pdev->dev); 672a6cda1f9SSunny Luo if (!spicc->data) { 673a6cda1f9SSunny Luo dev_err(&pdev->dev, "failed to get match data\n"); 674a6cda1f9SSunny Luo ret = -EINVAL; 675a6cda1f9SSunny Luo goto out_master; 676a6cda1f9SSunny Luo } 677a6cda1f9SSunny Luo 678454fa271SNeil Armstrong spicc->pdev = pdev; 679454fa271SNeil Armstrong platform_set_drvdata(pdev, spicc); 680454fa271SNeil Armstrong 681362385c0SYueHaibing spicc->base = devm_platform_ioremap_resource(pdev, 0); 682454fa271SNeil Armstrong if (IS_ERR(spicc->base)) { 683454fa271SNeil Armstrong dev_err(&pdev->dev, "io resource mapping failed\n"); 684454fa271SNeil Armstrong ret = PTR_ERR(spicc->base); 685454fa271SNeil Armstrong goto out_master; 686454fa271SNeil Armstrong } 687454fa271SNeil Armstrong 6883e0cf4d3SSunny Luo /* Set master mode and enable controller */ 6893e0cf4d3SSunny Luo writel_relaxed(SPICC_ENABLE | SPICC_MODE_MASTER, 6903e0cf4d3SSunny Luo spicc->base + SPICC_CONREG); 6913e0cf4d3SSunny Luo 692454fa271SNeil Armstrong /* Disable all IRQs */ 693454fa271SNeil Armstrong writel_relaxed(0, spicc->base + SPICC_INTREG); 694454fa271SNeil Armstrong 695454fa271SNeil Armstrong irq = platform_get_irq(pdev, 0); 696454fa271SNeil Armstrong ret = devm_request_irq(&pdev->dev, irq, meson_spicc_irq, 697454fa271SNeil Armstrong 0, NULL, spicc); 698454fa271SNeil Armstrong if (ret) { 699454fa271SNeil Armstrong dev_err(&pdev->dev, "irq request failed\n"); 700454fa271SNeil Armstrong goto out_master; 701454fa271SNeil Armstrong } 702454fa271SNeil Armstrong 703454fa271SNeil Armstrong spicc->core = devm_clk_get(&pdev->dev, "core"); 704454fa271SNeil Armstrong if (IS_ERR(spicc->core)) { 705454fa271SNeil Armstrong dev_err(&pdev->dev, "core clock request failed\n"); 706454fa271SNeil Armstrong ret = PTR_ERR(spicc->core); 707454fa271SNeil Armstrong goto out_master; 708454fa271SNeil Armstrong } 709454fa271SNeil Armstrong 7104e3d3220SNeil Armstrong if (spicc->data->has_pclk) { 7114e3d3220SNeil Armstrong spicc->pclk = devm_clk_get(&pdev->dev, "pclk"); 7124e3d3220SNeil Armstrong if (IS_ERR(spicc->pclk)) { 7134e3d3220SNeil Armstrong dev_err(&pdev->dev, "pclk clock request failed\n"); 7144e3d3220SNeil Armstrong ret = PTR_ERR(spicc->pclk); 7154e3d3220SNeil Armstrong goto out_master; 7164e3d3220SNeil Armstrong } 7174e3d3220SNeil Armstrong } 7184e3d3220SNeil Armstrong 719454fa271SNeil Armstrong ret = clk_prepare_enable(spicc->core); 720454fa271SNeil Armstrong if (ret) { 721454fa271SNeil Armstrong dev_err(&pdev->dev, "core clock enable failed\n"); 722454fa271SNeil Armstrong goto out_master; 723454fa271SNeil Armstrong } 7244e3d3220SNeil Armstrong 7254e3d3220SNeil Armstrong ret = clk_prepare_enable(spicc->pclk); 7264e3d3220SNeil Armstrong if (ret) { 7274e3d3220SNeil Armstrong dev_err(&pdev->dev, "pclk clock enable failed\n"); 72895730d5eSzpershuai goto out_core_clk; 7294e3d3220SNeil Armstrong } 730454fa271SNeil Armstrong 731454fa271SNeil Armstrong device_reset_optional(&pdev->dev); 732454fa271SNeil Armstrong 733454fa271SNeil Armstrong master->num_chipselect = 4; 734454fa271SNeil Armstrong master->dev.of_node = pdev->dev.of_node; 735454fa271SNeil Armstrong master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH; 736454fa271SNeil Armstrong master->bits_per_word_mask = SPI_BPW_MASK(32) | 737454fa271SNeil Armstrong SPI_BPW_MASK(24) | 738454fa271SNeil Armstrong SPI_BPW_MASK(16) | 739454fa271SNeil Armstrong SPI_BPW_MASK(8); 740454fa271SNeil Armstrong master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX); 7418791068dSNeil Armstrong master->min_speed_hz = spicc->data->min_speed_hz; 7424e3d3220SNeil Armstrong master->max_speed_hz = spicc->data->max_speed_hz; 743454fa271SNeil Armstrong master->setup = meson_spicc_setup; 744454fa271SNeil Armstrong master->cleanup = meson_spicc_cleanup; 745454fa271SNeil Armstrong master->prepare_message = meson_spicc_prepare_message; 746454fa271SNeil Armstrong master->unprepare_transfer_hardware = meson_spicc_unprepare_transfer; 747454fa271SNeil Armstrong master->transfer_one = meson_spicc_transfer_one; 748cd8fb859SLinus Walleij master->use_gpio_descriptors = true; 749454fa271SNeil Armstrong 750a6cda1f9SSunny Luo meson_spicc_oen_enable(spicc); 751a6cda1f9SSunny Luo 7523e0cf4d3SSunny Luo ret = meson_spicc_clk_init(spicc); 7533e0cf4d3SSunny Luo if (ret) { 7543e0cf4d3SSunny Luo dev_err(&pdev->dev, "clock registration failed\n"); 755*b2d501c1Szpershuai goto out_clk; 7563e0cf4d3SSunny Luo } 7573e0cf4d3SSunny Luo 758454fa271SNeil Armstrong ret = devm_spi_register_master(&pdev->dev, master); 759ded5fa4eSAlexey Khoroshilov if (ret) { 760ded5fa4eSAlexey Khoroshilov dev_err(&pdev->dev, "spi master registration failed\n"); 761ded5fa4eSAlexey Khoroshilov goto out_clk; 762ded5fa4eSAlexey Khoroshilov } 763ded5fa4eSAlexey Khoroshilov 764454fa271SNeil Armstrong return 0; 765454fa271SNeil Armstrong 766ded5fa4eSAlexey Khoroshilov out_clk: 7674e3d3220SNeil Armstrong clk_disable_unprepare(spicc->pclk); 768454fa271SNeil Armstrong 76995730d5eSzpershuai out_core_clk: 77095730d5eSzpershuai clk_disable_unprepare(spicc->core); 77195730d5eSzpershuai 772454fa271SNeil Armstrong out_master: 773454fa271SNeil Armstrong spi_master_put(master); 774454fa271SNeil Armstrong 775454fa271SNeil Armstrong return ret; 776454fa271SNeil Armstrong } 777454fa271SNeil Armstrong 778454fa271SNeil Armstrong static int meson_spicc_remove(struct platform_device *pdev) 779454fa271SNeil Armstrong { 780454fa271SNeil Armstrong struct meson_spicc_device *spicc = platform_get_drvdata(pdev); 781454fa271SNeil Armstrong 782454fa271SNeil Armstrong /* Disable SPI */ 783454fa271SNeil Armstrong writel(0, spicc->base + SPICC_CONREG); 784454fa271SNeil Armstrong 785454fa271SNeil Armstrong clk_disable_unprepare(spicc->core); 7864e3d3220SNeil Armstrong clk_disable_unprepare(spicc->pclk); 787454fa271SNeil Armstrong 788454fa271SNeil Armstrong return 0; 789454fa271SNeil Armstrong } 790454fa271SNeil Armstrong 791a6cda1f9SSunny Luo static const struct meson_spicc_data meson_spicc_gx_data = { 7923196816fSNeil Armstrong .max_speed_hz = 30000000, 7938791068dSNeil Armstrong .min_speed_hz = 325000, 7940eb707acSNeil Armstrong .fifo_size = 16, 795a6cda1f9SSunny Luo }; 796a6cda1f9SSunny Luo 797a6cda1f9SSunny Luo static const struct meson_spicc_data meson_spicc_axg_data = { 7983196816fSNeil Armstrong .max_speed_hz = 80000000, 7998791068dSNeil Armstrong .min_speed_hz = 325000, 8000eb707acSNeil Armstrong .fifo_size = 16, 801a6cda1f9SSunny Luo .has_oen = true, 8023e0cf4d3SSunny Luo .has_enhance_clk_div = true, 803a6cda1f9SSunny Luo }; 804a6cda1f9SSunny Luo 8054e3d3220SNeil Armstrong static const struct meson_spicc_data meson_spicc_g12a_data = { 8064e3d3220SNeil Armstrong .max_speed_hz = 166666666, 8074e3d3220SNeil Armstrong .min_speed_hz = 50000, 8084e3d3220SNeil Armstrong .fifo_size = 15, 8094e3d3220SNeil Armstrong .has_oen = true, 8104e3d3220SNeil Armstrong .has_enhance_clk_div = true, 8114e3d3220SNeil Armstrong .has_pclk = true, 8124e3d3220SNeil Armstrong }; 8134e3d3220SNeil Armstrong 814454fa271SNeil Armstrong static const struct of_device_id meson_spicc_of_match[] = { 815a6cda1f9SSunny Luo { 816a6cda1f9SSunny Luo .compatible = "amlogic,meson-gx-spicc", 817a6cda1f9SSunny Luo .data = &meson_spicc_gx_data, 818a6cda1f9SSunny Luo }, 819a6cda1f9SSunny Luo { 820a6cda1f9SSunny Luo .compatible = "amlogic,meson-axg-spicc", 821a6cda1f9SSunny Luo .data = &meson_spicc_axg_data, 822a6cda1f9SSunny Luo }, 8234e3d3220SNeil Armstrong { 8244e3d3220SNeil Armstrong .compatible = "amlogic,meson-g12a-spicc", 8254e3d3220SNeil Armstrong .data = &meson_spicc_g12a_data, 8264e3d3220SNeil Armstrong }, 827454fa271SNeil Armstrong { /* sentinel */ } 828454fa271SNeil Armstrong }; 829454fa271SNeil Armstrong MODULE_DEVICE_TABLE(of, meson_spicc_of_match); 830454fa271SNeil Armstrong 831454fa271SNeil Armstrong static struct platform_driver meson_spicc_driver = { 832454fa271SNeil Armstrong .probe = meson_spicc_probe, 833454fa271SNeil Armstrong .remove = meson_spicc_remove, 834454fa271SNeil Armstrong .driver = { 835454fa271SNeil Armstrong .name = "meson-spicc", 836454fa271SNeil Armstrong .of_match_table = of_match_ptr(meson_spicc_of_match), 837454fa271SNeil Armstrong }, 838454fa271SNeil Armstrong }; 839454fa271SNeil Armstrong 840454fa271SNeil Armstrong module_platform_driver(meson_spicc_driver); 841454fa271SNeil Armstrong 842454fa271SNeil Armstrong MODULE_DESCRIPTION("Meson SPI Communication Controller driver"); 843454fa271SNeil Armstrong MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>"); 844454fa271SNeil Armstrong MODULE_LICENSE("GPL"); 845