1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2011-2015 Daniel Schwierzeck <daniel.schwierzeck@gmail.com> 4 * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de> 5 */ 6 7 #include <linux/kernel.h> 8 #include <linux/module.h> 9 #include <linux/of_device.h> 10 #include <linux/clk.h> 11 #include <linux/io.h> 12 #include <linux/delay.h> 13 #include <linux/interrupt.h> 14 #include <linux/sched.h> 15 #include <linux/completion.h> 16 #include <linux/spinlock.h> 17 #include <linux/err.h> 18 #include <linux/gpio.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/spi/spi.h> 21 22 #ifdef CONFIG_LANTIQ 23 #include <lantiq_soc.h> 24 #endif 25 26 #define LTQ_SPI_RX_IRQ_NAME "spi_rx" 27 #define LTQ_SPI_TX_IRQ_NAME "spi_tx" 28 #define LTQ_SPI_ERR_IRQ_NAME "spi_err" 29 #define LTQ_SPI_FRM_IRQ_NAME "spi_frm" 30 31 #define LTQ_SPI_CLC 0x00 32 #define LTQ_SPI_PISEL 0x04 33 #define LTQ_SPI_ID 0x08 34 #define LTQ_SPI_CON 0x10 35 #define LTQ_SPI_STAT 0x14 36 #define LTQ_SPI_WHBSTATE 0x18 37 #define LTQ_SPI_TB 0x20 38 #define LTQ_SPI_RB 0x24 39 #define LTQ_SPI_RXFCON 0x30 40 #define LTQ_SPI_TXFCON 0x34 41 #define LTQ_SPI_FSTAT 0x38 42 #define LTQ_SPI_BRT 0x40 43 #define LTQ_SPI_BRSTAT 0x44 44 #define LTQ_SPI_SFCON 0x60 45 #define LTQ_SPI_SFSTAT 0x64 46 #define LTQ_SPI_GPOCON 0x70 47 #define LTQ_SPI_GPOSTAT 0x74 48 #define LTQ_SPI_FPGO 0x78 49 #define LTQ_SPI_RXREQ 0x80 50 #define LTQ_SPI_RXCNT 0x84 51 #define LTQ_SPI_DMACON 0xec 52 #define LTQ_SPI_IRNEN 0xf4 53 #define LTQ_SPI_IRNICR 0xf8 54 #define LTQ_SPI_IRNCR 0xfc 55 56 #define LTQ_SPI_CLC_SMC_S 16 /* Clock divider for sleep mode */ 57 #define LTQ_SPI_CLC_SMC_M (0xFF << LTQ_SPI_CLC_SMC_S) 58 #define LTQ_SPI_CLC_RMC_S 8 /* Clock divider for normal run mode */ 59 #define LTQ_SPI_CLC_RMC_M (0xFF << LTQ_SPI_CLC_RMC_S) 60 #define LTQ_SPI_CLC_DISS BIT(1) /* Disable status bit */ 61 #define LTQ_SPI_CLC_DISR BIT(0) /* Disable request bit */ 62 63 #define LTQ_SPI_ID_TXFS_S 24 /* Implemented TX FIFO size */ 64 #define LTQ_SPI_ID_TXFS_M (0x3F << LTQ_SPI_ID_TXFS_S) 65 #define LTQ_SPI_ID_RXFS_S 16 /* Implemented RX FIFO size */ 66 #define LTQ_SPI_ID_RXFS_M (0x3F << LTQ_SPI_ID_RXFS_S) 67 #define LTQ_SPI_ID_MOD_S 8 /* Module ID */ 68 #define LTQ_SPI_ID_MOD_M (0xff << LTQ_SPI_ID_MOD_S) 69 #define LTQ_SPI_ID_CFG_S 5 /* DMA interface support */ 70 #define LTQ_SPI_ID_CFG_M (1 << LTQ_SPI_ID_CFG_S) 71 #define LTQ_SPI_ID_REV_M 0x1F /* Hardware revision number */ 72 73 #define LTQ_SPI_CON_BM_S 16 /* Data width selection */ 74 #define LTQ_SPI_CON_BM_M (0x1F << LTQ_SPI_CON_BM_S) 75 #define LTQ_SPI_CON_EM BIT(24) /* Echo mode */ 76 #define LTQ_SPI_CON_IDLE BIT(23) /* Idle bit value */ 77 #define LTQ_SPI_CON_ENBV BIT(22) /* Enable byte valid control */ 78 #define LTQ_SPI_CON_RUEN BIT(12) /* Receive underflow error enable */ 79 #define LTQ_SPI_CON_TUEN BIT(11) /* Transmit underflow error enable */ 80 #define LTQ_SPI_CON_AEN BIT(10) /* Abort error enable */ 81 #define LTQ_SPI_CON_REN BIT(9) /* Receive overflow error enable */ 82 #define LTQ_SPI_CON_TEN BIT(8) /* Transmit overflow error enable */ 83 #define LTQ_SPI_CON_LB BIT(7) /* Loopback control */ 84 #define LTQ_SPI_CON_PO BIT(6) /* Clock polarity control */ 85 #define LTQ_SPI_CON_PH BIT(5) /* Clock phase control */ 86 #define LTQ_SPI_CON_HB BIT(4) /* Heading control */ 87 #define LTQ_SPI_CON_RXOFF BIT(1) /* Switch receiver off */ 88 #define LTQ_SPI_CON_TXOFF BIT(0) /* Switch transmitter off */ 89 90 #define LTQ_SPI_STAT_RXBV_S 28 91 #define LTQ_SPI_STAT_RXBV_M (0x7 << LTQ_SPI_STAT_RXBV_S) 92 #define LTQ_SPI_STAT_BSY BIT(13) /* Busy flag */ 93 #define LTQ_SPI_STAT_RUE BIT(12) /* Receive underflow error flag */ 94 #define LTQ_SPI_STAT_TUE BIT(11) /* Transmit underflow error flag */ 95 #define LTQ_SPI_STAT_AE BIT(10) /* Abort error flag */ 96 #define LTQ_SPI_STAT_RE BIT(9) /* Receive error flag */ 97 #define LTQ_SPI_STAT_TE BIT(8) /* Transmit error flag */ 98 #define LTQ_SPI_STAT_ME BIT(7) /* Mode error flag */ 99 #define LTQ_SPI_STAT_MS BIT(1) /* Master/slave select bit */ 100 #define LTQ_SPI_STAT_EN BIT(0) /* Enable bit */ 101 #define LTQ_SPI_STAT_ERRORS (LTQ_SPI_STAT_ME | LTQ_SPI_STAT_TE | \ 102 LTQ_SPI_STAT_RE | LTQ_SPI_STAT_AE | \ 103 LTQ_SPI_STAT_TUE | LTQ_SPI_STAT_RUE) 104 105 #define LTQ_SPI_WHBSTATE_SETTUE BIT(15) /* Set transmit underflow error flag */ 106 #define LTQ_SPI_WHBSTATE_SETAE BIT(14) /* Set abort error flag */ 107 #define LTQ_SPI_WHBSTATE_SETRE BIT(13) /* Set receive error flag */ 108 #define LTQ_SPI_WHBSTATE_SETTE BIT(12) /* Set transmit error flag */ 109 #define LTQ_SPI_WHBSTATE_CLRTUE BIT(11) /* Clear transmit underflow error flag */ 110 #define LTQ_SPI_WHBSTATE_CLRAE BIT(10) /* Clear abort error flag */ 111 #define LTQ_SPI_WHBSTATE_CLRRE BIT(9) /* Clear receive error flag */ 112 #define LTQ_SPI_WHBSTATE_CLRTE BIT(8) /* Clear transmit error flag */ 113 #define LTQ_SPI_WHBSTATE_SETME BIT(7) /* Set mode error flag */ 114 #define LTQ_SPI_WHBSTATE_CLRME BIT(6) /* Clear mode error flag */ 115 #define LTQ_SPI_WHBSTATE_SETRUE BIT(5) /* Set receive underflow error flag */ 116 #define LTQ_SPI_WHBSTATE_CLRRUE BIT(4) /* Clear receive underflow error flag */ 117 #define LTQ_SPI_WHBSTATE_SETMS BIT(3) /* Set master select bit */ 118 #define LTQ_SPI_WHBSTATE_CLRMS BIT(2) /* Clear master select bit */ 119 #define LTQ_SPI_WHBSTATE_SETEN BIT(1) /* Set enable bit (operational mode) */ 120 #define LTQ_SPI_WHBSTATE_CLREN BIT(0) /* Clear enable bit (config mode */ 121 #define LTQ_SPI_WHBSTATE_CLR_ERRORS (LTQ_SPI_WHBSTATE_CLRRUE | \ 122 LTQ_SPI_WHBSTATE_CLRME | \ 123 LTQ_SPI_WHBSTATE_CLRTE | \ 124 LTQ_SPI_WHBSTATE_CLRRE | \ 125 LTQ_SPI_WHBSTATE_CLRAE | \ 126 LTQ_SPI_WHBSTATE_CLRTUE) 127 128 #define LTQ_SPI_RXFCON_RXFITL_S 8 /* FIFO interrupt trigger level */ 129 #define LTQ_SPI_RXFCON_RXFITL_M (0x3F << LTQ_SPI_RXFCON_RXFITL_S) 130 #define LTQ_SPI_RXFCON_RXFLU BIT(1) /* FIFO flush */ 131 #define LTQ_SPI_RXFCON_RXFEN BIT(0) /* FIFO enable */ 132 133 #define LTQ_SPI_TXFCON_TXFITL_S 8 /* FIFO interrupt trigger level */ 134 #define LTQ_SPI_TXFCON_TXFITL_M (0x3F << LTQ_SPI_TXFCON_TXFITL_S) 135 #define LTQ_SPI_TXFCON_TXFLU BIT(1) /* FIFO flush */ 136 #define LTQ_SPI_TXFCON_TXFEN BIT(0) /* FIFO enable */ 137 138 #define LTQ_SPI_FSTAT_RXFFL_S 0 139 #define LTQ_SPI_FSTAT_RXFFL_M (0x3f << LTQ_SPI_FSTAT_RXFFL_S) 140 #define LTQ_SPI_FSTAT_TXFFL_S 8 141 #define LTQ_SPI_FSTAT_TXFFL_M (0x3f << LTQ_SPI_FSTAT_TXFFL_S) 142 143 #define LTQ_SPI_GPOCON_ISCSBN_S 8 144 #define LTQ_SPI_GPOCON_INVOUTN_S 0 145 146 #define LTQ_SPI_FGPO_SETOUTN_S 8 147 #define LTQ_SPI_FGPO_CLROUTN_S 0 148 149 #define LTQ_SPI_RXREQ_RXCNT_M 0xFFFF /* Receive count value */ 150 #define LTQ_SPI_RXCNT_TODO_M 0xFFFF /* Recevie to-do value */ 151 152 #define LTQ_SPI_IRNEN_TFI BIT(4) /* TX finished interrupt */ 153 #define LTQ_SPI_IRNEN_F BIT(3) /* Frame end interrupt request */ 154 #define LTQ_SPI_IRNEN_E BIT(2) /* Error end interrupt request */ 155 #define LTQ_SPI_IRNEN_T_XWAY BIT(1) /* Transmit end interrupt request */ 156 #define LTQ_SPI_IRNEN_R_XWAY BIT(0) /* Receive end interrupt request */ 157 #define LTQ_SPI_IRNEN_R_XRX BIT(1) /* Transmit end interrupt request */ 158 #define LTQ_SPI_IRNEN_T_XRX BIT(0) /* Receive end interrupt request */ 159 #define LTQ_SPI_IRNEN_ALL 0x1F 160 161 struct lantiq_ssc_hwcfg { 162 unsigned int irnen_r; 163 unsigned int irnen_t; 164 }; 165 166 struct lantiq_ssc_spi { 167 struct spi_master *master; 168 struct device *dev; 169 void __iomem *regbase; 170 struct clk *spi_clk; 171 struct clk *fpi_clk; 172 const struct lantiq_ssc_hwcfg *hwcfg; 173 174 spinlock_t lock; 175 struct workqueue_struct *wq; 176 struct work_struct work; 177 178 const u8 *tx; 179 u8 *rx; 180 unsigned int tx_todo; 181 unsigned int rx_todo; 182 unsigned int bits_per_word; 183 unsigned int speed_hz; 184 unsigned int tx_fifo_size; 185 unsigned int rx_fifo_size; 186 unsigned int base_cs; 187 }; 188 189 static u32 lantiq_ssc_readl(const struct lantiq_ssc_spi *spi, u32 reg) 190 { 191 return __raw_readl(spi->regbase + reg); 192 } 193 194 static void lantiq_ssc_writel(const struct lantiq_ssc_spi *spi, u32 val, 195 u32 reg) 196 { 197 __raw_writel(val, spi->regbase + reg); 198 } 199 200 static void lantiq_ssc_maskl(const struct lantiq_ssc_spi *spi, u32 clr, 201 u32 set, u32 reg) 202 { 203 u32 val = __raw_readl(spi->regbase + reg); 204 205 val &= ~clr; 206 val |= set; 207 __raw_writel(val, spi->regbase + reg); 208 } 209 210 static unsigned int tx_fifo_level(const struct lantiq_ssc_spi *spi) 211 { 212 u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT); 213 214 return (fstat & LTQ_SPI_FSTAT_TXFFL_M) >> LTQ_SPI_FSTAT_TXFFL_S; 215 } 216 217 static unsigned int rx_fifo_level(const struct lantiq_ssc_spi *spi) 218 { 219 u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT); 220 221 return fstat & LTQ_SPI_FSTAT_RXFFL_M; 222 } 223 224 static unsigned int tx_fifo_free(const struct lantiq_ssc_spi *spi) 225 { 226 return spi->tx_fifo_size - tx_fifo_level(spi); 227 } 228 229 static void rx_fifo_reset(const struct lantiq_ssc_spi *spi) 230 { 231 u32 val = spi->rx_fifo_size << LTQ_SPI_RXFCON_RXFITL_S; 232 233 val |= LTQ_SPI_RXFCON_RXFEN | LTQ_SPI_RXFCON_RXFLU; 234 lantiq_ssc_writel(spi, val, LTQ_SPI_RXFCON); 235 } 236 237 static void tx_fifo_reset(const struct lantiq_ssc_spi *spi) 238 { 239 u32 val = 1 << LTQ_SPI_TXFCON_TXFITL_S; 240 241 val |= LTQ_SPI_TXFCON_TXFEN | LTQ_SPI_TXFCON_TXFLU; 242 lantiq_ssc_writel(spi, val, LTQ_SPI_TXFCON); 243 } 244 245 static void rx_fifo_flush(const struct lantiq_ssc_spi *spi) 246 { 247 lantiq_ssc_maskl(spi, 0, LTQ_SPI_RXFCON_RXFLU, LTQ_SPI_RXFCON); 248 } 249 250 static void tx_fifo_flush(const struct lantiq_ssc_spi *spi) 251 { 252 lantiq_ssc_maskl(spi, 0, LTQ_SPI_TXFCON_TXFLU, LTQ_SPI_TXFCON); 253 } 254 255 static void hw_enter_config_mode(const struct lantiq_ssc_spi *spi) 256 { 257 lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_CLREN, LTQ_SPI_WHBSTATE); 258 } 259 260 static void hw_enter_active_mode(const struct lantiq_ssc_spi *spi) 261 { 262 lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_SETEN, LTQ_SPI_WHBSTATE); 263 } 264 265 static void hw_setup_speed_hz(const struct lantiq_ssc_spi *spi, 266 unsigned int max_speed_hz) 267 { 268 u32 spi_clk, brt; 269 270 /* 271 * SPI module clock is derived from FPI bus clock dependent on 272 * divider value in CLC.RMS which is always set to 1. 273 * 274 * f_SPI 275 * baudrate = -------------- 276 * 2 * (BR + 1) 277 */ 278 spi_clk = clk_get_rate(spi->fpi_clk) / 2; 279 280 if (max_speed_hz > spi_clk) 281 brt = 0; 282 else 283 brt = spi_clk / max_speed_hz - 1; 284 285 if (brt > 0xFFFF) 286 brt = 0xFFFF; 287 288 dev_dbg(spi->dev, "spi_clk %u, max_speed_hz %u, brt %u\n", 289 spi_clk, max_speed_hz, brt); 290 291 lantiq_ssc_writel(spi, brt, LTQ_SPI_BRT); 292 } 293 294 static void hw_setup_bits_per_word(const struct lantiq_ssc_spi *spi, 295 unsigned int bits_per_word) 296 { 297 u32 bm; 298 299 /* CON.BM value = bits_per_word - 1 */ 300 bm = (bits_per_word - 1) << LTQ_SPI_CON_BM_S; 301 302 lantiq_ssc_maskl(spi, LTQ_SPI_CON_BM_M, bm, LTQ_SPI_CON); 303 } 304 305 static void hw_setup_clock_mode(const struct lantiq_ssc_spi *spi, 306 unsigned int mode) 307 { 308 u32 con_set = 0, con_clr = 0; 309 310 /* 311 * SPI mode mapping in CON register: 312 * Mode CPOL CPHA CON.PO CON.PH 313 * 0 0 0 0 1 314 * 1 0 1 0 0 315 * 2 1 0 1 1 316 * 3 1 1 1 0 317 */ 318 if (mode & SPI_CPHA) 319 con_clr |= LTQ_SPI_CON_PH; 320 else 321 con_set |= LTQ_SPI_CON_PH; 322 323 if (mode & SPI_CPOL) 324 con_set |= LTQ_SPI_CON_PO | LTQ_SPI_CON_IDLE; 325 else 326 con_clr |= LTQ_SPI_CON_PO | LTQ_SPI_CON_IDLE; 327 328 /* Set heading control */ 329 if (mode & SPI_LSB_FIRST) 330 con_clr |= LTQ_SPI_CON_HB; 331 else 332 con_set |= LTQ_SPI_CON_HB; 333 334 /* Set loopback mode */ 335 if (mode & SPI_LOOP) 336 con_set |= LTQ_SPI_CON_LB; 337 else 338 con_clr |= LTQ_SPI_CON_LB; 339 340 lantiq_ssc_maskl(spi, con_clr, con_set, LTQ_SPI_CON); 341 } 342 343 static void lantiq_ssc_hw_init(const struct lantiq_ssc_spi *spi) 344 { 345 const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg; 346 347 /* 348 * Set clock divider for run mode to 1 to 349 * run at same frequency as FPI bus 350 */ 351 lantiq_ssc_writel(spi, 1 << LTQ_SPI_CLC_RMC_S, LTQ_SPI_CLC); 352 353 /* Put controller into config mode */ 354 hw_enter_config_mode(spi); 355 356 /* Clear error flags */ 357 lantiq_ssc_maskl(spi, 0, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE); 358 359 /* Enable error checking, disable TX/RX */ 360 lantiq_ssc_writel(spi, LTQ_SPI_CON_RUEN | LTQ_SPI_CON_AEN | 361 LTQ_SPI_CON_TEN | LTQ_SPI_CON_REN | LTQ_SPI_CON_TXOFF | 362 LTQ_SPI_CON_RXOFF, LTQ_SPI_CON); 363 364 /* Setup default SPI mode */ 365 hw_setup_bits_per_word(spi, spi->bits_per_word); 366 hw_setup_clock_mode(spi, SPI_MODE_0); 367 368 /* Enable master mode and clear error flags */ 369 lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_SETMS | 370 LTQ_SPI_WHBSTATE_CLR_ERRORS, 371 LTQ_SPI_WHBSTATE); 372 373 /* Reset GPIO/CS registers */ 374 lantiq_ssc_writel(spi, 0, LTQ_SPI_GPOCON); 375 lantiq_ssc_writel(spi, 0xFF00, LTQ_SPI_FPGO); 376 377 /* Enable and flush FIFOs */ 378 rx_fifo_reset(spi); 379 tx_fifo_reset(spi); 380 381 /* Enable interrupts */ 382 lantiq_ssc_writel(spi, hwcfg->irnen_t | hwcfg->irnen_r | 383 LTQ_SPI_IRNEN_E, LTQ_SPI_IRNEN); 384 } 385 386 static int lantiq_ssc_setup(struct spi_device *spidev) 387 { 388 struct spi_master *master = spidev->master; 389 struct lantiq_ssc_spi *spi = spi_master_get_devdata(master); 390 unsigned int cs = spidev->chip_select; 391 u32 gpocon; 392 393 /* GPIOs are used for CS */ 394 if (gpio_is_valid(spidev->cs_gpio)) 395 return 0; 396 397 dev_dbg(spi->dev, "using internal chipselect %u\n", cs); 398 399 if (cs < spi->base_cs) { 400 dev_err(spi->dev, 401 "chipselect %i too small (min %i)\n", cs, spi->base_cs); 402 return -EINVAL; 403 } 404 405 /* set GPO pin to CS mode */ 406 gpocon = 1 << ((cs - spi->base_cs) + LTQ_SPI_GPOCON_ISCSBN_S); 407 408 /* invert GPO pin */ 409 if (spidev->mode & SPI_CS_HIGH) 410 gpocon |= 1 << (cs - spi->base_cs); 411 412 lantiq_ssc_maskl(spi, 0, gpocon, LTQ_SPI_GPOCON); 413 414 return 0; 415 } 416 417 static int lantiq_ssc_prepare_message(struct spi_master *master, 418 struct spi_message *message) 419 { 420 struct lantiq_ssc_spi *spi = spi_master_get_devdata(master); 421 422 hw_enter_config_mode(spi); 423 hw_setup_clock_mode(spi, message->spi->mode); 424 hw_enter_active_mode(spi); 425 426 return 0; 427 } 428 429 static void hw_setup_transfer(struct lantiq_ssc_spi *spi, 430 struct spi_device *spidev, struct spi_transfer *t) 431 { 432 unsigned int speed_hz = t->speed_hz; 433 unsigned int bits_per_word = t->bits_per_word; 434 u32 con; 435 436 if (bits_per_word != spi->bits_per_word || 437 speed_hz != spi->speed_hz) { 438 hw_enter_config_mode(spi); 439 hw_setup_speed_hz(spi, speed_hz); 440 hw_setup_bits_per_word(spi, bits_per_word); 441 hw_enter_active_mode(spi); 442 443 spi->speed_hz = speed_hz; 444 spi->bits_per_word = bits_per_word; 445 } 446 447 /* Configure transmitter and receiver */ 448 con = lantiq_ssc_readl(spi, LTQ_SPI_CON); 449 if (t->tx_buf) 450 con &= ~LTQ_SPI_CON_TXOFF; 451 else 452 con |= LTQ_SPI_CON_TXOFF; 453 454 if (t->rx_buf) 455 con &= ~LTQ_SPI_CON_RXOFF; 456 else 457 con |= LTQ_SPI_CON_RXOFF; 458 459 lantiq_ssc_writel(spi, con, LTQ_SPI_CON); 460 } 461 462 static int lantiq_ssc_unprepare_message(struct spi_master *master, 463 struct spi_message *message) 464 { 465 struct lantiq_ssc_spi *spi = spi_master_get_devdata(master); 466 467 flush_workqueue(spi->wq); 468 469 /* Disable transmitter and receiver while idle */ 470 lantiq_ssc_maskl(spi, 0, LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF, 471 LTQ_SPI_CON); 472 473 return 0; 474 } 475 476 static void tx_fifo_write(struct lantiq_ssc_spi *spi) 477 { 478 const u8 *tx8; 479 const u16 *tx16; 480 const u32 *tx32; 481 u32 data; 482 unsigned int tx_free = tx_fifo_free(spi); 483 484 while (spi->tx_todo && tx_free) { 485 switch (spi->bits_per_word) { 486 case 2 ... 8: 487 tx8 = spi->tx; 488 data = *tx8; 489 spi->tx_todo--; 490 spi->tx++; 491 break; 492 case 16: 493 tx16 = (u16 *) spi->tx; 494 data = *tx16; 495 spi->tx_todo -= 2; 496 spi->tx += 2; 497 break; 498 case 32: 499 tx32 = (u32 *) spi->tx; 500 data = *tx32; 501 spi->tx_todo -= 4; 502 spi->tx += 4; 503 break; 504 default: 505 WARN_ON(1); 506 data = 0; 507 break; 508 } 509 510 lantiq_ssc_writel(spi, data, LTQ_SPI_TB); 511 tx_free--; 512 } 513 } 514 515 static void rx_fifo_read_full_duplex(struct lantiq_ssc_spi *spi) 516 { 517 u8 *rx8; 518 u16 *rx16; 519 u32 *rx32; 520 u32 data; 521 unsigned int rx_fill = rx_fifo_level(spi); 522 523 while (rx_fill) { 524 data = lantiq_ssc_readl(spi, LTQ_SPI_RB); 525 526 switch (spi->bits_per_word) { 527 case 2 ... 8: 528 rx8 = spi->rx; 529 *rx8 = data; 530 spi->rx_todo--; 531 spi->rx++; 532 break; 533 case 16: 534 rx16 = (u16 *) spi->rx; 535 *rx16 = data; 536 spi->rx_todo -= 2; 537 spi->rx += 2; 538 break; 539 case 32: 540 rx32 = (u32 *) spi->rx; 541 *rx32 = data; 542 spi->rx_todo -= 4; 543 spi->rx += 4; 544 break; 545 default: 546 WARN_ON(1); 547 break; 548 } 549 550 rx_fill--; 551 } 552 } 553 554 static void rx_fifo_read_half_duplex(struct lantiq_ssc_spi *spi) 555 { 556 u32 data, *rx32; 557 u8 *rx8; 558 unsigned int rxbv, shift; 559 unsigned int rx_fill = rx_fifo_level(spi); 560 561 /* 562 * In RX-only mode the bits per word value is ignored by HW. A value 563 * of 32 is used instead. Thus all 4 bytes per FIFO must be read. 564 * If remaining RX bytes are less than 4, the FIFO must be read 565 * differently. The amount of received and valid bytes is indicated 566 * by STAT.RXBV register value. 567 */ 568 while (rx_fill) { 569 if (spi->rx_todo < 4) { 570 rxbv = (lantiq_ssc_readl(spi, LTQ_SPI_STAT) & 571 LTQ_SPI_STAT_RXBV_M) >> LTQ_SPI_STAT_RXBV_S; 572 data = lantiq_ssc_readl(spi, LTQ_SPI_RB); 573 574 shift = (rxbv - 1) * 8; 575 rx8 = spi->rx; 576 577 while (rxbv) { 578 *rx8++ = (data >> shift) & 0xFF; 579 rxbv--; 580 shift -= 8; 581 spi->rx_todo--; 582 spi->rx++; 583 } 584 } else { 585 data = lantiq_ssc_readl(spi, LTQ_SPI_RB); 586 rx32 = (u32 *) spi->rx; 587 588 *rx32++ = data; 589 spi->rx_todo -= 4; 590 spi->rx += 4; 591 } 592 rx_fill--; 593 } 594 } 595 596 static void rx_request(struct lantiq_ssc_spi *spi) 597 { 598 unsigned int rxreq, rxreq_max; 599 600 /* 601 * To avoid receive overflows at high clocks it is better to request 602 * only the amount of bytes that fits into all FIFOs. This value 603 * depends on the FIFO size implemented in hardware. 604 */ 605 rxreq = spi->rx_todo; 606 rxreq_max = spi->rx_fifo_size * 4; 607 if (rxreq > rxreq_max) 608 rxreq = rxreq_max; 609 610 lantiq_ssc_writel(spi, rxreq, LTQ_SPI_RXREQ); 611 } 612 613 static irqreturn_t lantiq_ssc_xmit_interrupt(int irq, void *data) 614 { 615 struct lantiq_ssc_spi *spi = data; 616 617 if (spi->tx) { 618 if (spi->rx && spi->rx_todo) 619 rx_fifo_read_full_duplex(spi); 620 621 if (spi->tx_todo) 622 tx_fifo_write(spi); 623 else if (!tx_fifo_level(spi)) 624 goto completed; 625 } else if (spi->rx) { 626 if (spi->rx_todo) { 627 rx_fifo_read_half_duplex(spi); 628 629 if (spi->rx_todo) 630 rx_request(spi); 631 else 632 goto completed; 633 } else { 634 goto completed; 635 } 636 } 637 638 return IRQ_HANDLED; 639 640 completed: 641 queue_work(spi->wq, &spi->work); 642 643 return IRQ_HANDLED; 644 } 645 646 static irqreturn_t lantiq_ssc_err_interrupt(int irq, void *data) 647 { 648 struct lantiq_ssc_spi *spi = data; 649 u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT); 650 651 if (!(stat & LTQ_SPI_STAT_ERRORS)) 652 return IRQ_NONE; 653 654 if (stat & LTQ_SPI_STAT_RUE) 655 dev_err(spi->dev, "receive underflow error\n"); 656 if (stat & LTQ_SPI_STAT_TUE) 657 dev_err(spi->dev, "transmit underflow error\n"); 658 if (stat & LTQ_SPI_STAT_AE) 659 dev_err(spi->dev, "abort error\n"); 660 if (stat & LTQ_SPI_STAT_RE) 661 dev_err(spi->dev, "receive overflow error\n"); 662 if (stat & LTQ_SPI_STAT_TE) 663 dev_err(spi->dev, "transmit overflow error\n"); 664 if (stat & LTQ_SPI_STAT_ME) 665 dev_err(spi->dev, "mode error\n"); 666 667 /* Clear error flags */ 668 lantiq_ssc_maskl(spi, 0, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE); 669 670 /* set bad status so it can be retried */ 671 if (spi->master->cur_msg) 672 spi->master->cur_msg->status = -EIO; 673 queue_work(spi->wq, &spi->work); 674 675 return IRQ_HANDLED; 676 } 677 678 static int transfer_start(struct lantiq_ssc_spi *spi, struct spi_device *spidev, 679 struct spi_transfer *t) 680 { 681 unsigned long flags; 682 683 spin_lock_irqsave(&spi->lock, flags); 684 685 spi->tx = t->tx_buf; 686 spi->rx = t->rx_buf; 687 688 if (t->tx_buf) { 689 spi->tx_todo = t->len; 690 691 /* initially fill TX FIFO */ 692 tx_fifo_write(spi); 693 } 694 695 if (spi->rx) { 696 spi->rx_todo = t->len; 697 698 /* start shift clock in RX-only mode */ 699 if (!spi->tx) 700 rx_request(spi); 701 } 702 703 spin_unlock_irqrestore(&spi->lock, flags); 704 705 return t->len; 706 } 707 708 /* 709 * The driver only gets an interrupt when the FIFO is empty, but there 710 * is an additional shift register from which the data is written to 711 * the wire. We get the last interrupt when the controller starts to 712 * write the last word to the wire, not when it is finished. Do busy 713 * waiting till it finishes. 714 */ 715 static void lantiq_ssc_bussy_work(struct work_struct *work) 716 { 717 struct lantiq_ssc_spi *spi; 718 unsigned long long timeout = 8LL * 1000LL; 719 unsigned long end; 720 721 spi = container_of(work, typeof(*spi), work); 722 723 do_div(timeout, spi->speed_hz); 724 timeout += timeout + 100; /* some tolerance */ 725 726 end = jiffies + msecs_to_jiffies(timeout); 727 do { 728 u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT); 729 730 if (!(stat & LTQ_SPI_STAT_BSY)) { 731 spi_finalize_current_transfer(spi->master); 732 return; 733 } 734 735 cond_resched(); 736 } while (!time_after_eq(jiffies, end)); 737 738 if (spi->master->cur_msg) 739 spi->master->cur_msg->status = -EIO; 740 spi_finalize_current_transfer(spi->master); 741 } 742 743 static void lantiq_ssc_handle_err(struct spi_master *master, 744 struct spi_message *message) 745 { 746 struct lantiq_ssc_spi *spi = spi_master_get_devdata(master); 747 748 /* flush FIFOs on timeout */ 749 rx_fifo_flush(spi); 750 tx_fifo_flush(spi); 751 } 752 753 static void lantiq_ssc_set_cs(struct spi_device *spidev, bool enable) 754 { 755 struct lantiq_ssc_spi *spi = spi_master_get_devdata(spidev->master); 756 unsigned int cs = spidev->chip_select; 757 u32 fgpo; 758 759 if (!!(spidev->mode & SPI_CS_HIGH) == enable) 760 fgpo = (1 << (cs - spi->base_cs)); 761 else 762 fgpo = (1 << (cs - spi->base_cs + LTQ_SPI_FGPO_SETOUTN_S)); 763 764 lantiq_ssc_writel(spi, fgpo, LTQ_SPI_FPGO); 765 } 766 767 static int lantiq_ssc_transfer_one(struct spi_master *master, 768 struct spi_device *spidev, 769 struct spi_transfer *t) 770 { 771 struct lantiq_ssc_spi *spi = spi_master_get_devdata(master); 772 773 hw_setup_transfer(spi, spidev, t); 774 775 return transfer_start(spi, spidev, t); 776 } 777 778 static const struct lantiq_ssc_hwcfg lantiq_ssc_xway = { 779 .irnen_r = LTQ_SPI_IRNEN_R_XWAY, 780 .irnen_t = LTQ_SPI_IRNEN_T_XWAY, 781 }; 782 783 static const struct lantiq_ssc_hwcfg lantiq_ssc_xrx = { 784 .irnen_r = LTQ_SPI_IRNEN_R_XRX, 785 .irnen_t = LTQ_SPI_IRNEN_T_XRX, 786 }; 787 788 static const struct of_device_id lantiq_ssc_match[] = { 789 { .compatible = "lantiq,ase-spi", .data = &lantiq_ssc_xway, }, 790 { .compatible = "lantiq,falcon-spi", .data = &lantiq_ssc_xrx, }, 791 { .compatible = "lantiq,xrx100-spi", .data = &lantiq_ssc_xrx, }, 792 {}, 793 }; 794 MODULE_DEVICE_TABLE(of, lantiq_ssc_match); 795 796 static int lantiq_ssc_probe(struct platform_device *pdev) 797 { 798 struct device *dev = &pdev->dev; 799 struct spi_master *master; 800 struct resource *res; 801 struct lantiq_ssc_spi *spi; 802 const struct lantiq_ssc_hwcfg *hwcfg; 803 const struct of_device_id *match; 804 int err, rx_irq, tx_irq, err_irq; 805 u32 id, supports_dma, revision; 806 unsigned int num_cs; 807 808 match = of_match_device(lantiq_ssc_match, dev); 809 if (!match) { 810 dev_err(dev, "no device match\n"); 811 return -EINVAL; 812 } 813 hwcfg = match->data; 814 815 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 816 if (!res) { 817 dev_err(dev, "failed to get resources\n"); 818 return -ENXIO; 819 } 820 821 rx_irq = platform_get_irq_byname(pdev, LTQ_SPI_RX_IRQ_NAME); 822 if (rx_irq < 0) 823 return -ENXIO; 824 825 tx_irq = platform_get_irq_byname(pdev, LTQ_SPI_TX_IRQ_NAME); 826 if (tx_irq < 0) 827 return -ENXIO; 828 829 err_irq = platform_get_irq_byname(pdev, LTQ_SPI_ERR_IRQ_NAME); 830 if (err_irq < 0) 831 return -ENXIO; 832 833 master = spi_alloc_master(dev, sizeof(struct lantiq_ssc_spi)); 834 if (!master) 835 return -ENOMEM; 836 837 spi = spi_master_get_devdata(master); 838 spi->master = master; 839 spi->dev = dev; 840 spi->hwcfg = hwcfg; 841 platform_set_drvdata(pdev, spi); 842 843 spi->regbase = devm_ioremap_resource(dev, res); 844 if (IS_ERR(spi->regbase)) { 845 err = PTR_ERR(spi->regbase); 846 goto err_master_put; 847 } 848 849 err = devm_request_irq(dev, rx_irq, lantiq_ssc_xmit_interrupt, 850 0, LTQ_SPI_RX_IRQ_NAME, spi); 851 if (err) 852 goto err_master_put; 853 854 err = devm_request_irq(dev, tx_irq, lantiq_ssc_xmit_interrupt, 855 0, LTQ_SPI_TX_IRQ_NAME, spi); 856 if (err) 857 goto err_master_put; 858 859 err = devm_request_irq(dev, err_irq, lantiq_ssc_err_interrupt, 860 0, LTQ_SPI_ERR_IRQ_NAME, spi); 861 if (err) 862 goto err_master_put; 863 864 spi->spi_clk = devm_clk_get(dev, "gate"); 865 if (IS_ERR(spi->spi_clk)) { 866 err = PTR_ERR(spi->spi_clk); 867 goto err_master_put; 868 } 869 err = clk_prepare_enable(spi->spi_clk); 870 if (err) 871 goto err_master_put; 872 873 /* 874 * Use the old clk_get_fpi() function on Lantiq platform, till it 875 * supports common clk. 876 */ 877 #if defined(CONFIG_LANTIQ) && !defined(CONFIG_COMMON_CLK) 878 spi->fpi_clk = clk_get_fpi(); 879 #else 880 spi->fpi_clk = clk_get(dev, "freq"); 881 #endif 882 if (IS_ERR(spi->fpi_clk)) { 883 err = PTR_ERR(spi->fpi_clk); 884 goto err_clk_disable; 885 } 886 887 num_cs = 8; 888 of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs); 889 890 spi->base_cs = 1; 891 of_property_read_u32(pdev->dev.of_node, "base-cs", &spi->base_cs); 892 893 spin_lock_init(&spi->lock); 894 spi->bits_per_word = 8; 895 spi->speed_hz = 0; 896 897 master->dev.of_node = pdev->dev.of_node; 898 master->num_chipselect = num_cs; 899 master->setup = lantiq_ssc_setup; 900 master->set_cs = lantiq_ssc_set_cs; 901 master->handle_err = lantiq_ssc_handle_err; 902 master->prepare_message = lantiq_ssc_prepare_message; 903 master->unprepare_message = lantiq_ssc_unprepare_message; 904 master->transfer_one = lantiq_ssc_transfer_one; 905 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH | 906 SPI_LOOP; 907 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 8) | 908 SPI_BPW_MASK(16) | SPI_BPW_MASK(32); 909 910 spi->wq = alloc_ordered_workqueue(dev_name(dev), 0); 911 if (!spi->wq) { 912 err = -ENOMEM; 913 goto err_clk_put; 914 } 915 INIT_WORK(&spi->work, lantiq_ssc_bussy_work); 916 917 id = lantiq_ssc_readl(spi, LTQ_SPI_ID); 918 spi->tx_fifo_size = (id & LTQ_SPI_ID_TXFS_M) >> LTQ_SPI_ID_TXFS_S; 919 spi->rx_fifo_size = (id & LTQ_SPI_ID_RXFS_M) >> LTQ_SPI_ID_RXFS_S; 920 supports_dma = (id & LTQ_SPI_ID_CFG_M) >> LTQ_SPI_ID_CFG_S; 921 revision = id & LTQ_SPI_ID_REV_M; 922 923 lantiq_ssc_hw_init(spi); 924 925 dev_info(dev, 926 "Lantiq SSC SPI controller (Rev %i, TXFS %u, RXFS %u, DMA %u)\n", 927 revision, spi->tx_fifo_size, spi->rx_fifo_size, supports_dma); 928 929 err = devm_spi_register_master(dev, master); 930 if (err) { 931 dev_err(dev, "failed to register spi_master\n"); 932 goto err_wq_destroy; 933 } 934 935 return 0; 936 937 err_wq_destroy: 938 destroy_workqueue(spi->wq); 939 err_clk_put: 940 clk_put(spi->fpi_clk); 941 err_clk_disable: 942 clk_disable_unprepare(spi->spi_clk); 943 err_master_put: 944 spi_master_put(master); 945 946 return err; 947 } 948 949 static int lantiq_ssc_remove(struct platform_device *pdev) 950 { 951 struct lantiq_ssc_spi *spi = platform_get_drvdata(pdev); 952 953 lantiq_ssc_writel(spi, 0, LTQ_SPI_IRNEN); 954 lantiq_ssc_writel(spi, 0, LTQ_SPI_CLC); 955 rx_fifo_flush(spi); 956 tx_fifo_flush(spi); 957 hw_enter_config_mode(spi); 958 959 destroy_workqueue(spi->wq); 960 clk_disable_unprepare(spi->spi_clk); 961 clk_put(spi->fpi_clk); 962 963 return 0; 964 } 965 966 static struct platform_driver lantiq_ssc_driver = { 967 .probe = lantiq_ssc_probe, 968 .remove = lantiq_ssc_remove, 969 .driver = { 970 .name = "spi-lantiq-ssc", 971 .of_match_table = lantiq_ssc_match, 972 }, 973 }; 974 module_platform_driver(lantiq_ssc_driver); 975 976 MODULE_DESCRIPTION("Lantiq SSC SPI controller driver"); 977 MODULE_AUTHOR("Daniel Schwierzeck <daniel.schwierzeck@gmail.com>"); 978 MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>"); 979 MODULE_LICENSE("GPL"); 980 MODULE_ALIAS("platform:spi-lantiq-ssc"); 981