1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * J-Core SPI controller driver 4 * 5 * Copyright (C) 2012-2016 Smart Energy Instruments, Inc. 6 * 7 * Current version by Rich Felker 8 * Based loosely on initial version by Oleksandr G Zhadan 9 * 10 */ 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/errno.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/spi/spi.h> 17 #include <linux/clk.h> 18 #include <linux/err.h> 19 #include <linux/io.h> 20 #include <linux/of.h> 21 #include <linux/delay.h> 22 23 #define DRV_NAME "jcore_spi" 24 25 #define CTRL_REG 0x0 26 #define DATA_REG 0x4 27 28 #define JCORE_SPI_CTRL_XMIT 0x02 29 #define JCORE_SPI_STAT_BUSY 0x02 30 #define JCORE_SPI_CTRL_LOOP 0x08 31 #define JCORE_SPI_CTRL_CS_BITS 0x15 32 33 #define JCORE_SPI_WAIT_RDY_MAX_LOOP 2000000 34 35 struct jcore_spi { 36 struct spi_master *master; 37 void __iomem *base; 38 unsigned int cs_reg; 39 unsigned int speed_reg; 40 unsigned int speed_hz; 41 unsigned int clock_freq; 42 }; 43 44 static int jcore_spi_wait(void __iomem *ctrl_reg) 45 { 46 unsigned timeout = JCORE_SPI_WAIT_RDY_MAX_LOOP; 47 48 do { 49 if (!(readl(ctrl_reg) & JCORE_SPI_STAT_BUSY)) 50 return 0; 51 cpu_relax(); 52 } while (--timeout); 53 54 return -EBUSY; 55 } 56 57 static void jcore_spi_program(struct jcore_spi *hw) 58 { 59 void __iomem *ctrl_reg = hw->base + CTRL_REG; 60 61 if (jcore_spi_wait(ctrl_reg)) 62 dev_err(hw->master->dev.parent, 63 "timeout waiting to program ctrl reg.\n"); 64 65 writel(hw->cs_reg | hw->speed_reg, ctrl_reg); 66 } 67 68 static void jcore_spi_chipsel(struct spi_device *spi, bool value) 69 { 70 struct jcore_spi *hw = spi_master_get_devdata(spi->master); 71 u32 csbit = 1U << (2 * spi->chip_select); 72 73 dev_dbg(hw->master->dev.parent, "chipselect %d\n", spi->chip_select); 74 75 if (value) 76 hw->cs_reg |= csbit; 77 else 78 hw->cs_reg &= ~csbit; 79 80 jcore_spi_program(hw); 81 } 82 83 static void jcore_spi_baudrate(struct jcore_spi *hw, int speed) 84 { 85 if (speed == hw->speed_hz) return; 86 hw->speed_hz = speed; 87 if (speed >= hw->clock_freq / 2) 88 hw->speed_reg = 0; 89 else 90 hw->speed_reg = ((hw->clock_freq / 2 / speed) - 1) << 27; 91 jcore_spi_program(hw); 92 dev_dbg(hw->master->dev.parent, "speed=%d reg=0x%x\n", 93 speed, hw->speed_reg); 94 } 95 96 static int jcore_spi_txrx(struct spi_master *master, struct spi_device *spi, 97 struct spi_transfer *t) 98 { 99 struct jcore_spi *hw = spi_master_get_devdata(master); 100 101 void __iomem *ctrl_reg = hw->base + CTRL_REG; 102 void __iomem *data_reg = hw->base + DATA_REG; 103 u32 xmit; 104 105 /* data buffers */ 106 const unsigned char *tx; 107 unsigned char *rx; 108 unsigned int len; 109 unsigned int count; 110 111 jcore_spi_baudrate(hw, t->speed_hz); 112 113 xmit = hw->cs_reg | hw->speed_reg | JCORE_SPI_CTRL_XMIT; 114 tx = t->tx_buf; 115 rx = t->rx_buf; 116 len = t->len; 117 118 for (count = 0; count < len; count++) { 119 if (jcore_spi_wait(ctrl_reg)) 120 break; 121 122 writel(tx ? *tx++ : 0, data_reg); 123 writel(xmit, ctrl_reg); 124 125 if (jcore_spi_wait(ctrl_reg)) 126 break; 127 128 if (rx) 129 *rx++ = readl(data_reg); 130 } 131 132 spi_finalize_current_transfer(master); 133 134 if (count < len) 135 return -EREMOTEIO; 136 137 return 0; 138 } 139 140 static int jcore_spi_probe(struct platform_device *pdev) 141 { 142 struct device_node *node = pdev->dev.of_node; 143 struct jcore_spi *hw; 144 struct spi_master *master; 145 struct resource *res; 146 u32 clock_freq; 147 struct clk *clk; 148 int err = -ENODEV; 149 150 master = spi_alloc_master(&pdev->dev, sizeof(struct jcore_spi)); 151 if (!master) 152 return err; 153 154 /* Setup the master state. */ 155 master->num_chipselect = 3; 156 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 157 master->transfer_one = jcore_spi_txrx; 158 master->set_cs = jcore_spi_chipsel; 159 master->dev.of_node = node; 160 master->bus_num = pdev->id; 161 162 hw = spi_master_get_devdata(master); 163 hw->master = master; 164 platform_set_drvdata(pdev, hw); 165 166 /* Find and map our resources */ 167 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 168 if (!res) 169 goto exit_busy; 170 if (!devm_request_mem_region(&pdev->dev, res->start, 171 resource_size(res), pdev->name)) 172 goto exit_busy; 173 hw->base = devm_ioremap_nocache(&pdev->dev, res->start, 174 resource_size(res)); 175 if (!hw->base) 176 goto exit_busy; 177 178 /* 179 * The SPI clock rate controlled via a configurable clock divider 180 * which is applied to the reference clock. A 50 MHz reference is 181 * most suitable for obtaining standard SPI clock rates, but some 182 * designs may have a different reference clock, and the DT must 183 * make the driver aware so that it can properly program the 184 * requested rate. If the clock is omitted, 50 MHz is assumed. 185 */ 186 clock_freq = 50000000; 187 clk = devm_clk_get(&pdev->dev, "ref_clk"); 188 if (!IS_ERR(clk)) { 189 if (clk_prepare_enable(clk) == 0) { 190 clock_freq = clk_get_rate(clk); 191 clk_disable_unprepare(clk); 192 } else 193 dev_warn(&pdev->dev, "could not enable ref_clk\n"); 194 } 195 hw->clock_freq = clock_freq; 196 197 /* Initialize all CS bits to high. */ 198 hw->cs_reg = JCORE_SPI_CTRL_CS_BITS; 199 jcore_spi_baudrate(hw, 400000); 200 201 /* Register our spi controller */ 202 err = devm_spi_register_master(&pdev->dev, master); 203 if (err) 204 goto exit; 205 206 return 0; 207 208 exit_busy: 209 err = -EBUSY; 210 exit: 211 spi_master_put(master); 212 return err; 213 } 214 215 static const struct of_device_id jcore_spi_of_match[] = { 216 { .compatible = "jcore,spi2" }, 217 {}, 218 }; 219 MODULE_DEVICE_TABLE(of, jcore_spi_of_match); 220 221 static struct platform_driver jcore_spi_driver = { 222 .probe = jcore_spi_probe, 223 .driver = { 224 .name = DRV_NAME, 225 .of_match_table = jcore_spi_of_match, 226 }, 227 }; 228 229 module_platform_driver(jcore_spi_driver); 230 231 MODULE_DESCRIPTION("J-Core SPI driver"); 232 MODULE_AUTHOR("Rich Felker <dalias@libc.org>"); 233 MODULE_LICENSE("GPL"); 234 MODULE_ALIAS("platform:" DRV_NAME); 235