109c434b8SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
22cb1b3b3SRich Felker /*
32cb1b3b3SRich Felker * J-Core SPI controller driver
42cb1b3b3SRich Felker *
52cb1b3b3SRich Felker * Copyright (C) 2012-2016 Smart Energy Instruments, Inc.
62cb1b3b3SRich Felker *
72cb1b3b3SRich Felker * Current version by Rich Felker
82cb1b3b3SRich Felker * Based loosely on initial version by Oleksandr G Zhadan
92cb1b3b3SRich Felker *
102cb1b3b3SRich Felker */
112cb1b3b3SRich Felker #include <linux/init.h>
122cb1b3b3SRich Felker #include <linux/interrupt.h>
132cb1b3b3SRich Felker #include <linux/errno.h>
142cb1b3b3SRich Felker #include <linux/module.h>
152cb1b3b3SRich Felker #include <linux/platform_device.h>
162cb1b3b3SRich Felker #include <linux/spi/spi.h>
172cb1b3b3SRich Felker #include <linux/clk.h>
182cb1b3b3SRich Felker #include <linux/err.h>
192cb1b3b3SRich Felker #include <linux/io.h>
202cb1b3b3SRich Felker #include <linux/of.h>
212cb1b3b3SRich Felker #include <linux/delay.h>
222cb1b3b3SRich Felker
232cb1b3b3SRich Felker #define DRV_NAME "jcore_spi"
242cb1b3b3SRich Felker
252cb1b3b3SRich Felker #define CTRL_REG 0x0
262cb1b3b3SRich Felker #define DATA_REG 0x4
272cb1b3b3SRich Felker
282cb1b3b3SRich Felker #define JCORE_SPI_CTRL_XMIT 0x02
292cb1b3b3SRich Felker #define JCORE_SPI_STAT_BUSY 0x02
302cb1b3b3SRich Felker #define JCORE_SPI_CTRL_LOOP 0x08
312cb1b3b3SRich Felker #define JCORE_SPI_CTRL_CS_BITS 0x15
322cb1b3b3SRich Felker
332cb1b3b3SRich Felker #define JCORE_SPI_WAIT_RDY_MAX_LOOP 2000000
342cb1b3b3SRich Felker
352cb1b3b3SRich Felker struct jcore_spi {
36*810ee62dSYang Yingliang struct spi_controller *host;
372cb1b3b3SRich Felker void __iomem *base;
382cb1b3b3SRich Felker unsigned int cs_reg;
392cb1b3b3SRich Felker unsigned int speed_reg;
402cb1b3b3SRich Felker unsigned int speed_hz;
412cb1b3b3SRich Felker unsigned int clock_freq;
422cb1b3b3SRich Felker };
432cb1b3b3SRich Felker
jcore_spi_wait(void __iomem * ctrl_reg)442cb1b3b3SRich Felker static int jcore_spi_wait(void __iomem *ctrl_reg)
452cb1b3b3SRich Felker {
462cb1b3b3SRich Felker unsigned timeout = JCORE_SPI_WAIT_RDY_MAX_LOOP;
472cb1b3b3SRich Felker
482cb1b3b3SRich Felker do {
492cb1b3b3SRich Felker if (!(readl(ctrl_reg) & JCORE_SPI_STAT_BUSY))
502cb1b3b3SRich Felker return 0;
512cb1b3b3SRich Felker cpu_relax();
522cb1b3b3SRich Felker } while (--timeout);
532cb1b3b3SRich Felker
542cb1b3b3SRich Felker return -EBUSY;
552cb1b3b3SRich Felker }
562cb1b3b3SRich Felker
jcore_spi_program(struct jcore_spi * hw)572cb1b3b3SRich Felker static void jcore_spi_program(struct jcore_spi *hw)
582cb1b3b3SRich Felker {
592cb1b3b3SRich Felker void __iomem *ctrl_reg = hw->base + CTRL_REG;
602cb1b3b3SRich Felker
612cb1b3b3SRich Felker if (jcore_spi_wait(ctrl_reg))
62*810ee62dSYang Yingliang dev_err(hw->host->dev.parent,
632cb1b3b3SRich Felker "timeout waiting to program ctrl reg.\n");
642cb1b3b3SRich Felker
652cb1b3b3SRich Felker writel(hw->cs_reg | hw->speed_reg, ctrl_reg);
662cb1b3b3SRich Felker }
672cb1b3b3SRich Felker
jcore_spi_chipsel(struct spi_device * spi,bool value)682cb1b3b3SRich Felker static void jcore_spi_chipsel(struct spi_device *spi, bool value)
692cb1b3b3SRich Felker {
70*810ee62dSYang Yingliang struct jcore_spi *hw = spi_controller_get_devdata(spi->controller);
719e264f3fSAmit Kumar Mahapatra via Alsa-devel u32 csbit = 1U << (2 * spi_get_chipselect(spi, 0));
722cb1b3b3SRich Felker
73*810ee62dSYang Yingliang dev_dbg(hw->host->dev.parent, "chipselect %d\n", spi_get_chipselect(spi, 0));
742cb1b3b3SRich Felker
752cb1b3b3SRich Felker if (value)
762cb1b3b3SRich Felker hw->cs_reg |= csbit;
772cb1b3b3SRich Felker else
782cb1b3b3SRich Felker hw->cs_reg &= ~csbit;
792cb1b3b3SRich Felker
802cb1b3b3SRich Felker jcore_spi_program(hw);
812cb1b3b3SRich Felker }
822cb1b3b3SRich Felker
jcore_spi_baudrate(struct jcore_spi * hw,int speed)832cb1b3b3SRich Felker static void jcore_spi_baudrate(struct jcore_spi *hw, int speed)
842cb1b3b3SRich Felker {
8545793de7SJay Fang if (speed == hw->speed_hz)
8645793de7SJay Fang return;
872cb1b3b3SRich Felker hw->speed_hz = speed;
882cb1b3b3SRich Felker if (speed >= hw->clock_freq / 2)
892cb1b3b3SRich Felker hw->speed_reg = 0;
902cb1b3b3SRich Felker else
912cb1b3b3SRich Felker hw->speed_reg = ((hw->clock_freq / 2 / speed) - 1) << 27;
922cb1b3b3SRich Felker jcore_spi_program(hw);
93*810ee62dSYang Yingliang dev_dbg(hw->host->dev.parent, "speed=%d reg=0x%x\n",
942cb1b3b3SRich Felker speed, hw->speed_reg);
952cb1b3b3SRich Felker }
962cb1b3b3SRich Felker
jcore_spi_txrx(struct spi_controller * host,struct spi_device * spi,struct spi_transfer * t)97*810ee62dSYang Yingliang static int jcore_spi_txrx(struct spi_controller *host, struct spi_device *spi,
982cb1b3b3SRich Felker struct spi_transfer *t)
992cb1b3b3SRich Felker {
100*810ee62dSYang Yingliang struct jcore_spi *hw = spi_controller_get_devdata(host);
1012cb1b3b3SRich Felker
1022cb1b3b3SRich Felker void __iomem *ctrl_reg = hw->base + CTRL_REG;
1032cb1b3b3SRich Felker void __iomem *data_reg = hw->base + DATA_REG;
1042cb1b3b3SRich Felker u32 xmit;
1052cb1b3b3SRich Felker
1062cb1b3b3SRich Felker /* data buffers */
1072cb1b3b3SRich Felker const unsigned char *tx;
1082cb1b3b3SRich Felker unsigned char *rx;
1092cb1b3b3SRich Felker unsigned int len;
1102cb1b3b3SRich Felker unsigned int count;
1112cb1b3b3SRich Felker
1122cb1b3b3SRich Felker jcore_spi_baudrate(hw, t->speed_hz);
1132cb1b3b3SRich Felker
1142cb1b3b3SRich Felker xmit = hw->cs_reg | hw->speed_reg | JCORE_SPI_CTRL_XMIT;
1152cb1b3b3SRich Felker tx = t->tx_buf;
1162cb1b3b3SRich Felker rx = t->rx_buf;
1172cb1b3b3SRich Felker len = t->len;
1182cb1b3b3SRich Felker
1192cb1b3b3SRich Felker for (count = 0; count < len; count++) {
1202cb1b3b3SRich Felker if (jcore_spi_wait(ctrl_reg))
1212cb1b3b3SRich Felker break;
1222cb1b3b3SRich Felker
1232cb1b3b3SRich Felker writel(tx ? *tx++ : 0, data_reg);
1242cb1b3b3SRich Felker writel(xmit, ctrl_reg);
1252cb1b3b3SRich Felker
1262cb1b3b3SRich Felker if (jcore_spi_wait(ctrl_reg))
1272cb1b3b3SRich Felker break;
1282cb1b3b3SRich Felker
1292cb1b3b3SRich Felker if (rx)
1302cb1b3b3SRich Felker *rx++ = readl(data_reg);
1312cb1b3b3SRich Felker }
1322cb1b3b3SRich Felker
133*810ee62dSYang Yingliang spi_finalize_current_transfer(host);
1342cb1b3b3SRich Felker
1352cb1b3b3SRich Felker if (count < len)
1362cb1b3b3SRich Felker return -EREMOTEIO;
1372cb1b3b3SRich Felker
1382cb1b3b3SRich Felker return 0;
1392cb1b3b3SRich Felker }
1402cb1b3b3SRich Felker
jcore_spi_probe(struct platform_device * pdev)1412cb1b3b3SRich Felker static int jcore_spi_probe(struct platform_device *pdev)
1422cb1b3b3SRich Felker {
1432cb1b3b3SRich Felker struct device_node *node = pdev->dev.of_node;
1442cb1b3b3SRich Felker struct jcore_spi *hw;
145*810ee62dSYang Yingliang struct spi_controller *host;
1462cb1b3b3SRich Felker struct resource *res;
1472cb1b3b3SRich Felker u32 clock_freq;
1482cb1b3b3SRich Felker struct clk *clk;
1492cb1b3b3SRich Felker int err = -ENODEV;
1502cb1b3b3SRich Felker
151*810ee62dSYang Yingliang host = spi_alloc_host(&pdev->dev, sizeof(struct jcore_spi));
152*810ee62dSYang Yingliang if (!host)
1532cb1b3b3SRich Felker return err;
1542cb1b3b3SRich Felker
155*810ee62dSYang Yingliang /* Setup the host state. */
156*810ee62dSYang Yingliang host->num_chipselect = 3;
157*810ee62dSYang Yingliang host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
158*810ee62dSYang Yingliang host->transfer_one = jcore_spi_txrx;
159*810ee62dSYang Yingliang host->set_cs = jcore_spi_chipsel;
160*810ee62dSYang Yingliang host->dev.of_node = node;
161*810ee62dSYang Yingliang host->bus_num = pdev->id;
1622cb1b3b3SRich Felker
163*810ee62dSYang Yingliang hw = spi_controller_get_devdata(host);
164*810ee62dSYang Yingliang hw->host = host;
1652cb1b3b3SRich Felker platform_set_drvdata(pdev, hw);
1662cb1b3b3SRich Felker
1672cb1b3b3SRich Felker /* Find and map our resources */
1682cb1b3b3SRich Felker res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1692cb1b3b3SRich Felker if (!res)
1702cb1b3b3SRich Felker goto exit_busy;
1712cb1b3b3SRich Felker if (!devm_request_mem_region(&pdev->dev, res->start,
1722cb1b3b3SRich Felker resource_size(res), pdev->name))
1732cb1b3b3SRich Felker goto exit_busy;
1744bdc0d67SChristoph Hellwig hw->base = devm_ioremap(&pdev->dev, res->start,
1752cb1b3b3SRich Felker resource_size(res));
1762cb1b3b3SRich Felker if (!hw->base)
1772cb1b3b3SRich Felker goto exit_busy;
1782cb1b3b3SRich Felker
1792cb1b3b3SRich Felker /*
1802cb1b3b3SRich Felker * The SPI clock rate controlled via a configurable clock divider
1812cb1b3b3SRich Felker * which is applied to the reference clock. A 50 MHz reference is
1822cb1b3b3SRich Felker * most suitable for obtaining standard SPI clock rates, but some
1832cb1b3b3SRich Felker * designs may have a different reference clock, and the DT must
1842cb1b3b3SRich Felker * make the driver aware so that it can properly program the
1852cb1b3b3SRich Felker * requested rate. If the clock is omitted, 50 MHz is assumed.
1862cb1b3b3SRich Felker */
1872cb1b3b3SRich Felker clock_freq = 50000000;
1882cb1b3b3SRich Felker clk = devm_clk_get(&pdev->dev, "ref_clk");
1897c2861a6SAlexey Khoroshilov if (!IS_ERR(clk)) {
1907c2861a6SAlexey Khoroshilov if (clk_prepare_enable(clk) == 0) {
1912cb1b3b3SRich Felker clock_freq = clk_get_rate(clk);
1927c2861a6SAlexey Khoroshilov clk_disable_unprepare(clk);
1937c2861a6SAlexey Khoroshilov } else
1942cb1b3b3SRich Felker dev_warn(&pdev->dev, "could not enable ref_clk\n");
1952cb1b3b3SRich Felker }
1962cb1b3b3SRich Felker hw->clock_freq = clock_freq;
1972cb1b3b3SRich Felker
1982cb1b3b3SRich Felker /* Initialize all CS bits to high. */
1992cb1b3b3SRich Felker hw->cs_reg = JCORE_SPI_CTRL_CS_BITS;
2002cb1b3b3SRich Felker jcore_spi_baudrate(hw, 400000);
2012cb1b3b3SRich Felker
2022cb1b3b3SRich Felker /* Register our spi controller */
203*810ee62dSYang Yingliang err = devm_spi_register_controller(&pdev->dev, host);
2047c2861a6SAlexey Khoroshilov if (err)
2052cb1b3b3SRich Felker goto exit;
2062cb1b3b3SRich Felker
2072cb1b3b3SRich Felker return 0;
2082cb1b3b3SRich Felker
2092cb1b3b3SRich Felker exit_busy:
2102cb1b3b3SRich Felker err = -EBUSY;
2112cb1b3b3SRich Felker exit:
212*810ee62dSYang Yingliang spi_controller_put(host);
2132cb1b3b3SRich Felker return err;
2142cb1b3b3SRich Felker }
2152cb1b3b3SRich Felker
2162cb1b3b3SRich Felker static const struct of_device_id jcore_spi_of_match[] = {
2172cb1b3b3SRich Felker { .compatible = "jcore,spi2" },
2182cb1b3b3SRich Felker {},
2192cb1b3b3SRich Felker };
220aa12c1abSJavier Martinez Canillas MODULE_DEVICE_TABLE(of, jcore_spi_of_match);
2212cb1b3b3SRich Felker
2222cb1b3b3SRich Felker static struct platform_driver jcore_spi_driver = {
2232cb1b3b3SRich Felker .probe = jcore_spi_probe,
2242cb1b3b3SRich Felker .driver = {
2252cb1b3b3SRich Felker .name = DRV_NAME,
2262cb1b3b3SRich Felker .of_match_table = jcore_spi_of_match,
2272cb1b3b3SRich Felker },
2282cb1b3b3SRich Felker };
2292cb1b3b3SRich Felker
2302cb1b3b3SRich Felker module_platform_driver(jcore_spi_driver);
2312cb1b3b3SRich Felker
2322cb1b3b3SRich Felker MODULE_DESCRIPTION("J-Core SPI driver");
2332cb1b3b3SRich Felker MODULE_AUTHOR("Rich Felker <dalias@libc.org>");
2342cb1b3b3SRich Felker MODULE_LICENSE("GPL");
2352cb1b3b3SRich Felker MODULE_ALIAS("platform:" DRV_NAME);
236