1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Intel PCH/PCU SPI flash driver. 4 * 5 * Copyright (C) 2016 - 2022, Intel Corporation 6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com> 7 */ 8 9 #include <linux/iopoll.h> 10 #include <linux/module.h> 11 12 #include <linux/mtd/partitions.h> 13 #include <linux/mtd/spi-nor.h> 14 15 #include <linux/spi/flash.h> 16 #include <linux/spi/spi.h> 17 #include <linux/spi/spi-mem.h> 18 19 #include "spi-intel.h" 20 21 /* Offsets are from @ispi->base */ 22 #define BFPREG 0x00 23 24 #define HSFSTS_CTL 0x04 25 #define HSFSTS_CTL_FSMIE BIT(31) 26 #define HSFSTS_CTL_FDBC_SHIFT 24 27 #define HSFSTS_CTL_FDBC_MASK (0x3f << HSFSTS_CTL_FDBC_SHIFT) 28 29 #define HSFSTS_CTL_FCYCLE_SHIFT 17 30 #define HSFSTS_CTL_FCYCLE_MASK (0x0f << HSFSTS_CTL_FCYCLE_SHIFT) 31 /* HW sequencer opcodes */ 32 #define HSFSTS_CTL_FCYCLE_READ (0x00 << HSFSTS_CTL_FCYCLE_SHIFT) 33 #define HSFSTS_CTL_FCYCLE_WRITE (0x02 << HSFSTS_CTL_FCYCLE_SHIFT) 34 #define HSFSTS_CTL_FCYCLE_ERASE (0x03 << HSFSTS_CTL_FCYCLE_SHIFT) 35 #define HSFSTS_CTL_FCYCLE_ERASE_64K (0x04 << HSFSTS_CTL_FCYCLE_SHIFT) 36 #define HSFSTS_CTL_FCYCLE_RDID (0x06 << HSFSTS_CTL_FCYCLE_SHIFT) 37 #define HSFSTS_CTL_FCYCLE_WRSR (0x07 << HSFSTS_CTL_FCYCLE_SHIFT) 38 #define HSFSTS_CTL_FCYCLE_RDSR (0x08 << HSFSTS_CTL_FCYCLE_SHIFT) 39 40 #define HSFSTS_CTL_FGO BIT(16) 41 #define HSFSTS_CTL_FLOCKDN BIT(15) 42 #define HSFSTS_CTL_FDV BIT(14) 43 #define HSFSTS_CTL_SCIP BIT(5) 44 #define HSFSTS_CTL_AEL BIT(2) 45 #define HSFSTS_CTL_FCERR BIT(1) 46 #define HSFSTS_CTL_FDONE BIT(0) 47 48 #define FADDR 0x08 49 #define DLOCK 0x0c 50 #define FDATA(n) (0x10 + ((n) * 4)) 51 52 #define FRACC 0x50 53 54 #define FREG(n) (0x54 + ((n) * 4)) 55 #define FREG_BASE_MASK 0x3fff 56 #define FREG_LIMIT_SHIFT 16 57 #define FREG_LIMIT_MASK (0x03fff << FREG_LIMIT_SHIFT) 58 59 /* Offset is from @ispi->pregs */ 60 #define PR(n) ((n) * 4) 61 #define PR_WPE BIT(31) 62 #define PR_LIMIT_SHIFT 16 63 #define PR_LIMIT_MASK (0x3fff << PR_LIMIT_SHIFT) 64 #define PR_RPE BIT(15) 65 #define PR_BASE_MASK 0x3fff 66 67 /* Offsets are from @ispi->sregs */ 68 #define SSFSTS_CTL 0x00 69 #define SSFSTS_CTL_FSMIE BIT(23) 70 #define SSFSTS_CTL_DS BIT(22) 71 #define SSFSTS_CTL_DBC_SHIFT 16 72 #define SSFSTS_CTL_SPOP BIT(11) 73 #define SSFSTS_CTL_ACS BIT(10) 74 #define SSFSTS_CTL_SCGO BIT(9) 75 #define SSFSTS_CTL_COP_SHIFT 12 76 #define SSFSTS_CTL_FRS BIT(7) 77 #define SSFSTS_CTL_DOFRS BIT(6) 78 #define SSFSTS_CTL_AEL BIT(4) 79 #define SSFSTS_CTL_FCERR BIT(3) 80 #define SSFSTS_CTL_FDONE BIT(2) 81 #define SSFSTS_CTL_SCIP BIT(0) 82 83 #define PREOP_OPTYPE 0x04 84 #define OPMENU0 0x08 85 #define OPMENU1 0x0c 86 87 #define OPTYPE_READ_NO_ADDR 0 88 #define OPTYPE_WRITE_NO_ADDR 1 89 #define OPTYPE_READ_WITH_ADDR 2 90 #define OPTYPE_WRITE_WITH_ADDR 3 91 92 /* CPU specifics */ 93 #define BYT_PR 0x74 94 #define BYT_SSFSTS_CTL 0x90 95 #define BYT_FREG_NUM 5 96 #define BYT_PR_NUM 5 97 98 #define LPT_PR 0x74 99 #define LPT_SSFSTS_CTL 0x90 100 #define LPT_FREG_NUM 5 101 #define LPT_PR_NUM 5 102 103 #define BXT_PR 0x84 104 #define BXT_SSFSTS_CTL 0xa0 105 #define BXT_FREG_NUM 12 106 #define BXT_PR_NUM 6 107 108 #define CNL_PR 0x84 109 #define CNL_FREG_NUM 6 110 #define CNL_PR_NUM 5 111 112 #define LVSCC 0xc4 113 #define UVSCC 0xc8 114 #define ERASE_OPCODE_SHIFT 8 115 #define ERASE_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT) 116 #define ERASE_64K_OPCODE_SHIFT 16 117 #define ERASE_64K_OPCODE_MASK (0xff << ERASE_64K_OPCODE_SHIFT) 118 119 /* Flash descriptor fields */ 120 #define FLVALSIG_MAGIC 0x0ff0a55a 121 #define FLMAP0_NC_MASK GENMASK(9, 8) 122 #define FLMAP0_NC_SHIFT 8 123 #define FLMAP0_FCBA_MASK GENMASK(7, 0) 124 125 #define FLCOMP_C0DEN_MASK GENMASK(3, 0) 126 #define FLCOMP_C0DEN_512K 0x00 127 #define FLCOMP_C0DEN_1M 0x01 128 #define FLCOMP_C0DEN_2M 0x02 129 #define FLCOMP_C0DEN_4M 0x03 130 #define FLCOMP_C0DEN_8M 0x04 131 #define FLCOMP_C0DEN_16M 0x05 132 #define FLCOMP_C0DEN_32M 0x06 133 #define FLCOMP_C0DEN_64M 0x07 134 135 #define INTEL_SPI_TIMEOUT 5000 /* ms */ 136 #define INTEL_SPI_FIFO_SZ 64 137 138 /** 139 * struct intel_spi - Driver private data 140 * @dev: Device pointer 141 * @info: Pointer to board specific info 142 * @base: Beginning of MMIO space 143 * @pregs: Start of protection registers 144 * @sregs: Start of software sequencer registers 145 * @master: Pointer to the SPI controller structure 146 * @nregions: Maximum number of regions 147 * @pr_num: Maximum number of protected range registers 148 * @chip0_size: Size of the first flash chip in bytes 149 * @locked: Is SPI setting locked 150 * @swseq_reg: Use SW sequencer in register reads/writes 151 * @swseq_erase: Use SW sequencer in erase operation 152 * @atomic_preopcode: Holds preopcode when atomic sequence is requested 153 * @opcodes: Opcodes which are supported. This are programmed by BIOS 154 * before it locks down the controller. 155 * @mem_ops: Pointer to SPI MEM ops supported by the controller 156 */ 157 struct intel_spi { 158 struct device *dev; 159 const struct intel_spi_boardinfo *info; 160 void __iomem *base; 161 void __iomem *pregs; 162 void __iomem *sregs; 163 struct spi_controller *master; 164 size_t nregions; 165 size_t pr_num; 166 size_t chip0_size; 167 bool locked; 168 bool swseq_reg; 169 bool swseq_erase; 170 u8 atomic_preopcode; 171 u8 opcodes[8]; 172 const struct intel_spi_mem_op *mem_ops; 173 }; 174 175 struct intel_spi_mem_op { 176 struct spi_mem_op mem_op; 177 u32 replacement_op; 178 int (*exec_op)(struct intel_spi *ispi, 179 const struct spi_mem *mem, 180 const struct intel_spi_mem_op *iop, 181 const struct spi_mem_op *op); 182 }; 183 184 static bool writeable; 185 module_param(writeable, bool, 0); 186 MODULE_PARM_DESC(writeable, "Enable write access to SPI flash chip (default=0)"); 187 188 static void intel_spi_dump_regs(struct intel_spi *ispi) 189 { 190 u32 value; 191 int i; 192 193 dev_dbg(ispi->dev, "BFPREG=0x%08x\n", readl(ispi->base + BFPREG)); 194 195 value = readl(ispi->base + HSFSTS_CTL); 196 dev_dbg(ispi->dev, "HSFSTS_CTL=0x%08x\n", value); 197 if (value & HSFSTS_CTL_FLOCKDN) 198 dev_dbg(ispi->dev, "-> Locked\n"); 199 200 dev_dbg(ispi->dev, "FADDR=0x%08x\n", readl(ispi->base + FADDR)); 201 dev_dbg(ispi->dev, "DLOCK=0x%08x\n", readl(ispi->base + DLOCK)); 202 203 for (i = 0; i < 16; i++) 204 dev_dbg(ispi->dev, "FDATA(%d)=0x%08x\n", 205 i, readl(ispi->base + FDATA(i))); 206 207 dev_dbg(ispi->dev, "FRACC=0x%08x\n", readl(ispi->base + FRACC)); 208 209 for (i = 0; i < ispi->nregions; i++) 210 dev_dbg(ispi->dev, "FREG(%d)=0x%08x\n", i, 211 readl(ispi->base + FREG(i))); 212 for (i = 0; i < ispi->pr_num; i++) 213 dev_dbg(ispi->dev, "PR(%d)=0x%08x\n", i, 214 readl(ispi->pregs + PR(i))); 215 216 if (ispi->sregs) { 217 value = readl(ispi->sregs + SSFSTS_CTL); 218 dev_dbg(ispi->dev, "SSFSTS_CTL=0x%08x\n", value); 219 dev_dbg(ispi->dev, "PREOP_OPTYPE=0x%08x\n", 220 readl(ispi->sregs + PREOP_OPTYPE)); 221 dev_dbg(ispi->dev, "OPMENU0=0x%08x\n", 222 readl(ispi->sregs + OPMENU0)); 223 dev_dbg(ispi->dev, "OPMENU1=0x%08x\n", 224 readl(ispi->sregs + OPMENU1)); 225 } 226 227 dev_dbg(ispi->dev, "LVSCC=0x%08x\n", readl(ispi->base + LVSCC)); 228 dev_dbg(ispi->dev, "UVSCC=0x%08x\n", readl(ispi->base + UVSCC)); 229 230 dev_dbg(ispi->dev, "Protected regions:\n"); 231 for (i = 0; i < ispi->pr_num; i++) { 232 u32 base, limit; 233 234 value = readl(ispi->pregs + PR(i)); 235 if (!(value & (PR_WPE | PR_RPE))) 236 continue; 237 238 limit = (value & PR_LIMIT_MASK) >> PR_LIMIT_SHIFT; 239 base = value & PR_BASE_MASK; 240 241 dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x [%c%c]\n", 242 i, base << 12, (limit << 12) | 0xfff, 243 value & PR_WPE ? 'W' : '.', value & PR_RPE ? 'R' : '.'); 244 } 245 246 dev_dbg(ispi->dev, "Flash regions:\n"); 247 for (i = 0; i < ispi->nregions; i++) { 248 u32 region, base, limit; 249 250 region = readl(ispi->base + FREG(i)); 251 base = region & FREG_BASE_MASK; 252 limit = (region & FREG_LIMIT_MASK) >> FREG_LIMIT_SHIFT; 253 254 if (base >= limit || (i > 0 && limit == 0)) 255 dev_dbg(ispi->dev, " %02d disabled\n", i); 256 else 257 dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x\n", 258 i, base << 12, (limit << 12) | 0xfff); 259 } 260 261 dev_dbg(ispi->dev, "Using %cW sequencer for register access\n", 262 ispi->swseq_reg ? 'S' : 'H'); 263 dev_dbg(ispi->dev, "Using %cW sequencer for erase operation\n", 264 ispi->swseq_erase ? 'S' : 'H'); 265 } 266 267 /* Reads max INTEL_SPI_FIFO_SZ bytes from the device fifo */ 268 static int intel_spi_read_block(struct intel_spi *ispi, void *buf, size_t size) 269 { 270 size_t bytes; 271 int i = 0; 272 273 if (size > INTEL_SPI_FIFO_SZ) 274 return -EINVAL; 275 276 while (size > 0) { 277 bytes = min_t(size_t, size, 4); 278 memcpy_fromio(buf, ispi->base + FDATA(i), bytes); 279 size -= bytes; 280 buf += bytes; 281 i++; 282 } 283 284 return 0; 285 } 286 287 /* Writes max INTEL_SPI_FIFO_SZ bytes to the device fifo */ 288 static int intel_spi_write_block(struct intel_spi *ispi, const void *buf, 289 size_t size) 290 { 291 size_t bytes; 292 int i = 0; 293 294 if (size > INTEL_SPI_FIFO_SZ) 295 return -EINVAL; 296 297 while (size > 0) { 298 bytes = min_t(size_t, size, 4); 299 memcpy_toio(ispi->base + FDATA(i), buf, bytes); 300 size -= bytes; 301 buf += bytes; 302 i++; 303 } 304 305 return 0; 306 } 307 308 static int intel_spi_wait_hw_busy(struct intel_spi *ispi) 309 { 310 u32 val; 311 312 return readl_poll_timeout(ispi->base + HSFSTS_CTL, val, 313 !(val & HSFSTS_CTL_SCIP), 0, 314 INTEL_SPI_TIMEOUT * 1000); 315 } 316 317 static int intel_spi_wait_sw_busy(struct intel_spi *ispi) 318 { 319 u32 val; 320 321 return readl_poll_timeout(ispi->sregs + SSFSTS_CTL, val, 322 !(val & SSFSTS_CTL_SCIP), 0, 323 INTEL_SPI_TIMEOUT * 1000); 324 } 325 326 static bool intel_spi_set_writeable(struct intel_spi *ispi) 327 { 328 if (!ispi->info->set_writeable) 329 return false; 330 331 return ispi->info->set_writeable(ispi->base, ispi->info->data); 332 } 333 334 static int intel_spi_opcode_index(struct intel_spi *ispi, u8 opcode, int optype) 335 { 336 int i; 337 int preop; 338 339 if (ispi->locked) { 340 for (i = 0; i < ARRAY_SIZE(ispi->opcodes); i++) 341 if (ispi->opcodes[i] == opcode) 342 return i; 343 344 return -EINVAL; 345 } 346 347 /* The lock is off, so just use index 0 */ 348 writel(opcode, ispi->sregs + OPMENU0); 349 preop = readw(ispi->sregs + PREOP_OPTYPE); 350 writel(optype << 16 | preop, ispi->sregs + PREOP_OPTYPE); 351 352 return 0; 353 } 354 355 static int intel_spi_hw_cycle(struct intel_spi *ispi, 356 const struct intel_spi_mem_op *iop, size_t len) 357 { 358 u32 val, status; 359 int ret; 360 361 if (!iop->replacement_op) 362 return -EINVAL; 363 364 val = readl(ispi->base + HSFSTS_CTL); 365 val &= ~(HSFSTS_CTL_FCYCLE_MASK | HSFSTS_CTL_FDBC_MASK); 366 367 if (len > INTEL_SPI_FIFO_SZ) 368 return -EINVAL; 369 370 val |= (len - 1) << HSFSTS_CTL_FDBC_SHIFT; 371 val |= HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE; 372 val |= HSFSTS_CTL_FGO; 373 val |= iop->replacement_op; 374 writel(val, ispi->base + HSFSTS_CTL); 375 376 ret = intel_spi_wait_hw_busy(ispi); 377 if (ret) 378 return ret; 379 380 status = readl(ispi->base + HSFSTS_CTL); 381 if (status & HSFSTS_CTL_FCERR) 382 return -EIO; 383 else if (status & HSFSTS_CTL_AEL) 384 return -EACCES; 385 386 return 0; 387 } 388 389 static int intel_spi_sw_cycle(struct intel_spi *ispi, u8 opcode, size_t len, 390 int optype) 391 { 392 u32 val = 0, status; 393 u8 atomic_preopcode; 394 int ret; 395 396 ret = intel_spi_opcode_index(ispi, opcode, optype); 397 if (ret < 0) 398 return ret; 399 400 if (len > INTEL_SPI_FIFO_SZ) 401 return -EINVAL; 402 403 /* 404 * Always clear it after each SW sequencer operation regardless 405 * of whether it is successful or not. 406 */ 407 atomic_preopcode = ispi->atomic_preopcode; 408 ispi->atomic_preopcode = 0; 409 410 /* Only mark 'Data Cycle' bit when there is data to be transferred */ 411 if (len > 0) 412 val = ((len - 1) << SSFSTS_CTL_DBC_SHIFT) | SSFSTS_CTL_DS; 413 val |= ret << SSFSTS_CTL_COP_SHIFT; 414 val |= SSFSTS_CTL_FCERR | SSFSTS_CTL_FDONE; 415 val |= SSFSTS_CTL_SCGO; 416 if (atomic_preopcode) { 417 u16 preop; 418 419 switch (optype) { 420 case OPTYPE_WRITE_NO_ADDR: 421 case OPTYPE_WRITE_WITH_ADDR: 422 /* Pick matching preopcode for the atomic sequence */ 423 preop = readw(ispi->sregs + PREOP_OPTYPE); 424 if ((preop & 0xff) == atomic_preopcode) 425 ; /* Do nothing */ 426 else if ((preop >> 8) == atomic_preopcode) 427 val |= SSFSTS_CTL_SPOP; 428 else 429 return -EINVAL; 430 431 /* Enable atomic sequence */ 432 val |= SSFSTS_CTL_ACS; 433 break; 434 435 default: 436 return -EINVAL; 437 } 438 } 439 writel(val, ispi->sregs + SSFSTS_CTL); 440 441 ret = intel_spi_wait_sw_busy(ispi); 442 if (ret) 443 return ret; 444 445 status = readl(ispi->sregs + SSFSTS_CTL); 446 if (status & SSFSTS_CTL_FCERR) 447 return -EIO; 448 else if (status & SSFSTS_CTL_AEL) 449 return -EACCES; 450 451 return 0; 452 } 453 454 static u32 intel_spi_chip_addr(const struct intel_spi *ispi, 455 const struct spi_mem *mem) 456 { 457 /* Pick up the correct start address */ 458 if (!mem) 459 return 0; 460 return mem->spi->chip_select == 1 ? ispi->chip0_size : 0; 461 } 462 463 static int intel_spi_read_reg(struct intel_spi *ispi, const struct spi_mem *mem, 464 const struct intel_spi_mem_op *iop, 465 const struct spi_mem_op *op) 466 { 467 size_t nbytes = op->data.nbytes; 468 u8 opcode = op->cmd.opcode; 469 int ret; 470 471 writel(intel_spi_chip_addr(ispi, mem), ispi->base + FADDR); 472 473 if (ispi->swseq_reg) 474 ret = intel_spi_sw_cycle(ispi, opcode, nbytes, 475 OPTYPE_READ_NO_ADDR); 476 else 477 ret = intel_spi_hw_cycle(ispi, iop, nbytes); 478 479 if (ret) 480 return ret; 481 482 return intel_spi_read_block(ispi, op->data.buf.in, nbytes); 483 } 484 485 static int intel_spi_write_reg(struct intel_spi *ispi, const struct spi_mem *mem, 486 const struct intel_spi_mem_op *iop, 487 const struct spi_mem_op *op) 488 { 489 size_t nbytes = op->data.nbytes; 490 u8 opcode = op->cmd.opcode; 491 int ret; 492 493 /* 494 * This is handled with atomic operation and preop code in Intel 495 * controller so we only verify that it is available. If the 496 * controller is not locked, program the opcode to the PREOP 497 * register for later use. 498 * 499 * When hardware sequencer is used there is no need to program 500 * any opcodes (it handles them automatically as part of a command). 501 */ 502 if (opcode == SPINOR_OP_WREN) { 503 u16 preop; 504 505 if (!ispi->swseq_reg) 506 return 0; 507 508 preop = readw(ispi->sregs + PREOP_OPTYPE); 509 if ((preop & 0xff) != opcode && (preop >> 8) != opcode) { 510 if (ispi->locked) 511 return -EINVAL; 512 writel(opcode, ispi->sregs + PREOP_OPTYPE); 513 } 514 515 /* 516 * This enables atomic sequence on next SW sycle. Will 517 * be cleared after next operation. 518 */ 519 ispi->atomic_preopcode = opcode; 520 return 0; 521 } 522 523 /* 524 * We hope that HW sequencer will do the right thing automatically and 525 * with the SW sequencer we cannot use preopcode anyway, so just ignore 526 * the Write Disable operation and pretend it was completed 527 * successfully. 528 */ 529 if (opcode == SPINOR_OP_WRDI) 530 return 0; 531 532 writel(intel_spi_chip_addr(ispi, mem), ispi->base + FADDR); 533 534 /* Write the value beforehand */ 535 ret = intel_spi_write_block(ispi, op->data.buf.out, nbytes); 536 if (ret) 537 return ret; 538 539 if (ispi->swseq_reg) 540 return intel_spi_sw_cycle(ispi, opcode, nbytes, 541 OPTYPE_WRITE_NO_ADDR); 542 return intel_spi_hw_cycle(ispi, iop, nbytes); 543 } 544 545 static int intel_spi_read(struct intel_spi *ispi, const struct spi_mem *mem, 546 const struct intel_spi_mem_op *iop, 547 const struct spi_mem_op *op) 548 { 549 u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val; 550 size_t block_size, nbytes = op->data.nbytes; 551 void *read_buf = op->data.buf.in; 552 u32 val, status; 553 int ret; 554 555 /* 556 * Atomic sequence is not expected with HW sequencer reads. Make 557 * sure it is cleared regardless. 558 */ 559 if (WARN_ON_ONCE(ispi->atomic_preopcode)) 560 ispi->atomic_preopcode = 0; 561 562 while (nbytes > 0) { 563 block_size = min_t(size_t, nbytes, INTEL_SPI_FIFO_SZ); 564 565 /* Read cannot cross 4K boundary */ 566 block_size = min_t(loff_t, addr + block_size, 567 round_up(addr + 1, SZ_4K)) - addr; 568 569 writel(addr, ispi->base + FADDR); 570 571 val = readl(ispi->base + HSFSTS_CTL); 572 val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK); 573 val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE; 574 val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT; 575 val |= HSFSTS_CTL_FCYCLE_READ; 576 val |= HSFSTS_CTL_FGO; 577 writel(val, ispi->base + HSFSTS_CTL); 578 579 ret = intel_spi_wait_hw_busy(ispi); 580 if (ret) 581 return ret; 582 583 status = readl(ispi->base + HSFSTS_CTL); 584 if (status & HSFSTS_CTL_FCERR) 585 ret = -EIO; 586 else if (status & HSFSTS_CTL_AEL) 587 ret = -EACCES; 588 589 if (ret < 0) { 590 dev_err(ispi->dev, "read error: %x: %#x\n", addr, status); 591 return ret; 592 } 593 594 ret = intel_spi_read_block(ispi, read_buf, block_size); 595 if (ret) 596 return ret; 597 598 nbytes -= block_size; 599 addr += block_size; 600 read_buf += block_size; 601 } 602 603 return 0; 604 } 605 606 static int intel_spi_write(struct intel_spi *ispi, const struct spi_mem *mem, 607 const struct intel_spi_mem_op *iop, 608 const struct spi_mem_op *op) 609 { 610 u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val; 611 size_t block_size, nbytes = op->data.nbytes; 612 const void *write_buf = op->data.buf.out; 613 u32 val, status; 614 int ret; 615 616 /* Not needed with HW sequencer write, make sure it is cleared */ 617 ispi->atomic_preopcode = 0; 618 619 while (nbytes > 0) { 620 block_size = min_t(size_t, nbytes, INTEL_SPI_FIFO_SZ); 621 622 /* Write cannot cross 4K boundary */ 623 block_size = min_t(loff_t, addr + block_size, 624 round_up(addr + 1, SZ_4K)) - addr; 625 626 writel(addr, ispi->base + FADDR); 627 628 val = readl(ispi->base + HSFSTS_CTL); 629 val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK); 630 val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE; 631 val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT; 632 val |= HSFSTS_CTL_FCYCLE_WRITE; 633 634 ret = intel_spi_write_block(ispi, write_buf, block_size); 635 if (ret) { 636 dev_err(ispi->dev, "failed to write block\n"); 637 return ret; 638 } 639 640 /* Start the write now */ 641 val |= HSFSTS_CTL_FGO; 642 writel(val, ispi->base + HSFSTS_CTL); 643 644 ret = intel_spi_wait_hw_busy(ispi); 645 if (ret) { 646 dev_err(ispi->dev, "timeout\n"); 647 return ret; 648 } 649 650 status = readl(ispi->base + HSFSTS_CTL); 651 if (status & HSFSTS_CTL_FCERR) 652 ret = -EIO; 653 else if (status & HSFSTS_CTL_AEL) 654 ret = -EACCES; 655 656 if (ret < 0) { 657 dev_err(ispi->dev, "write error: %x: %#x\n", addr, status); 658 return ret; 659 } 660 661 nbytes -= block_size; 662 addr += block_size; 663 write_buf += block_size; 664 } 665 666 return 0; 667 } 668 669 static int intel_spi_erase(struct intel_spi *ispi, const struct spi_mem *mem, 670 const struct intel_spi_mem_op *iop, 671 const struct spi_mem_op *op) 672 { 673 u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val; 674 u8 opcode = op->cmd.opcode; 675 u32 val, status; 676 int ret; 677 678 writel(addr, ispi->base + FADDR); 679 680 if (ispi->swseq_erase) 681 return intel_spi_sw_cycle(ispi, opcode, 0, 682 OPTYPE_WRITE_WITH_ADDR); 683 684 /* Not needed with HW sequencer erase, make sure it is cleared */ 685 ispi->atomic_preopcode = 0; 686 687 val = readl(ispi->base + HSFSTS_CTL); 688 val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK); 689 val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE; 690 val |= HSFSTS_CTL_FGO; 691 val |= iop->replacement_op; 692 writel(val, ispi->base + HSFSTS_CTL); 693 694 ret = intel_spi_wait_hw_busy(ispi); 695 if (ret) 696 return ret; 697 698 status = readl(ispi->base + HSFSTS_CTL); 699 if (status & HSFSTS_CTL_FCERR) 700 return -EIO; 701 if (status & HSFSTS_CTL_AEL) 702 return -EACCES; 703 704 return 0; 705 } 706 707 static bool intel_spi_cmp_mem_op(const struct intel_spi_mem_op *iop, 708 const struct spi_mem_op *op) 709 { 710 if (iop->mem_op.cmd.nbytes != op->cmd.nbytes || 711 iop->mem_op.cmd.buswidth != op->cmd.buswidth || 712 iop->mem_op.cmd.dtr != op->cmd.dtr || 713 iop->mem_op.cmd.opcode != op->cmd.opcode) 714 return false; 715 716 if (iop->mem_op.addr.nbytes != op->addr.nbytes || 717 iop->mem_op.addr.dtr != op->addr.dtr) 718 return false; 719 720 if (iop->mem_op.data.dir != op->data.dir || 721 iop->mem_op.data.dtr != op->data.dtr) 722 return false; 723 724 if (iop->mem_op.data.dir != SPI_MEM_NO_DATA) { 725 if (iop->mem_op.data.buswidth != op->data.buswidth) 726 return false; 727 } 728 729 return true; 730 } 731 732 static const struct intel_spi_mem_op * 733 intel_spi_match_mem_op(struct intel_spi *ispi, const struct spi_mem_op *op) 734 { 735 const struct intel_spi_mem_op *iop; 736 737 for (iop = ispi->mem_ops; iop->mem_op.cmd.opcode; iop++) { 738 if (intel_spi_cmp_mem_op(iop, op)) 739 break; 740 } 741 742 return iop->mem_op.cmd.opcode ? iop : NULL; 743 } 744 745 static bool intel_spi_supports_mem_op(struct spi_mem *mem, 746 const struct spi_mem_op *op) 747 { 748 struct intel_spi *ispi = spi_master_get_devdata(mem->spi->master); 749 const struct intel_spi_mem_op *iop; 750 751 iop = intel_spi_match_mem_op(ispi, op); 752 if (!iop) { 753 dev_dbg(ispi->dev, "%#x not supported\n", op->cmd.opcode); 754 return false; 755 } 756 757 /* 758 * For software sequencer check that the opcode is actually 759 * present in the opmenu if it is locked. 760 */ 761 if (ispi->swseq_reg && ispi->locked) { 762 int i; 763 764 /* Check if it is in the locked opcodes list */ 765 for (i = 0; i < ARRAY_SIZE(ispi->opcodes); i++) { 766 if (ispi->opcodes[i] == op->cmd.opcode) 767 return true; 768 } 769 770 dev_dbg(ispi->dev, "%#x not supported\n", op->cmd.opcode); 771 return false; 772 } 773 774 return true; 775 } 776 777 static int intel_spi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) 778 { 779 struct intel_spi *ispi = spi_master_get_devdata(mem->spi->master); 780 const struct intel_spi_mem_op *iop; 781 782 iop = intel_spi_match_mem_op(ispi, op); 783 if (!iop) 784 return -EOPNOTSUPP; 785 786 return iop->exec_op(ispi, mem, iop, op); 787 } 788 789 static const char *intel_spi_get_name(struct spi_mem *mem) 790 { 791 const struct intel_spi *ispi = spi_master_get_devdata(mem->spi->master); 792 793 /* 794 * Return name of the flash controller device to be compatible 795 * with the MTD version. 796 */ 797 return dev_name(ispi->dev); 798 } 799 800 static int intel_spi_dirmap_create(struct spi_mem_dirmap_desc *desc) 801 { 802 struct intel_spi *ispi = spi_master_get_devdata(desc->mem->spi->master); 803 const struct intel_spi_mem_op *iop; 804 805 iop = intel_spi_match_mem_op(ispi, &desc->info.op_tmpl); 806 if (!iop) 807 return -EOPNOTSUPP; 808 809 desc->priv = (void *)iop; 810 return 0; 811 } 812 813 static ssize_t intel_spi_dirmap_read(struct spi_mem_dirmap_desc *desc, u64 offs, 814 size_t len, void *buf) 815 { 816 struct intel_spi *ispi = spi_master_get_devdata(desc->mem->spi->master); 817 const struct intel_spi_mem_op *iop = desc->priv; 818 struct spi_mem_op op = desc->info.op_tmpl; 819 int ret; 820 821 /* Fill in the gaps */ 822 op.addr.val = offs; 823 op.data.nbytes = len; 824 op.data.buf.in = buf; 825 826 ret = iop->exec_op(ispi, desc->mem, iop, &op); 827 return ret ? ret : len; 828 } 829 830 static ssize_t intel_spi_dirmap_write(struct spi_mem_dirmap_desc *desc, u64 offs, 831 size_t len, const void *buf) 832 { 833 struct intel_spi *ispi = spi_master_get_devdata(desc->mem->spi->master); 834 const struct intel_spi_mem_op *iop = desc->priv; 835 struct spi_mem_op op = desc->info.op_tmpl; 836 int ret; 837 838 op.addr.val = offs; 839 op.data.nbytes = len; 840 op.data.buf.out = buf; 841 842 ret = iop->exec_op(ispi, desc->mem, iop, &op); 843 return ret ? ret : len; 844 } 845 846 static const struct spi_controller_mem_ops intel_spi_mem_ops = { 847 .supports_op = intel_spi_supports_mem_op, 848 .exec_op = intel_spi_exec_mem_op, 849 .get_name = intel_spi_get_name, 850 .dirmap_create = intel_spi_dirmap_create, 851 .dirmap_read = intel_spi_dirmap_read, 852 .dirmap_write = intel_spi_dirmap_write, 853 }; 854 855 #define INTEL_SPI_OP_ADDR(__nbytes) \ 856 { \ 857 .nbytes = __nbytes, \ 858 } 859 860 #define INTEL_SPI_OP_NO_DATA \ 861 { \ 862 .dir = SPI_MEM_NO_DATA, \ 863 } 864 865 #define INTEL_SPI_OP_DATA_IN(__buswidth) \ 866 { \ 867 .dir = SPI_MEM_DATA_IN, \ 868 .buswidth = __buswidth, \ 869 } 870 871 #define INTEL_SPI_OP_DATA_OUT(__buswidth) \ 872 { \ 873 .dir = SPI_MEM_DATA_OUT, \ 874 .buswidth = __buswidth, \ 875 } 876 877 #define INTEL_SPI_MEM_OP(__cmd, __addr, __data, __exec_op) \ 878 { \ 879 .mem_op = { \ 880 .cmd = __cmd, \ 881 .addr = __addr, \ 882 .data = __data, \ 883 }, \ 884 .exec_op = __exec_op, \ 885 } 886 887 #define INTEL_SPI_MEM_OP_REPL(__cmd, __addr, __data, __exec_op, __repl) \ 888 { \ 889 .mem_op = { \ 890 .cmd = __cmd, \ 891 .addr = __addr, \ 892 .data = __data, \ 893 }, \ 894 .exec_op = __exec_op, \ 895 .replacement_op = __repl, \ 896 } 897 898 /* 899 * The controller handles pretty much everything internally based on the 900 * SFDP data but we want to make sure we only support the operations 901 * actually possible. Only check buswidth and transfer direction, the 902 * core validates data. 903 */ 904 #define INTEL_SPI_GENERIC_OPS \ 905 /* Status register operations */ \ 906 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1), \ 907 SPI_MEM_OP_NO_ADDR, \ 908 INTEL_SPI_OP_DATA_IN(1), \ 909 intel_spi_read_reg, \ 910 HSFSTS_CTL_FCYCLE_RDID), \ 911 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 1), \ 912 SPI_MEM_OP_NO_ADDR, \ 913 INTEL_SPI_OP_DATA_IN(1), \ 914 intel_spi_read_reg, \ 915 HSFSTS_CTL_FCYCLE_RDSR), \ 916 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 1), \ 917 SPI_MEM_OP_NO_ADDR, \ 918 INTEL_SPI_OP_DATA_OUT(1), \ 919 intel_spi_write_reg, \ 920 HSFSTS_CTL_FCYCLE_WRSR), \ 921 /* Normal read */ \ 922 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \ 923 INTEL_SPI_OP_ADDR(3), \ 924 INTEL_SPI_OP_DATA_IN(1), \ 925 intel_spi_read), \ 926 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \ 927 INTEL_SPI_OP_ADDR(3), \ 928 INTEL_SPI_OP_DATA_IN(2), \ 929 intel_spi_read), \ 930 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \ 931 INTEL_SPI_OP_ADDR(3), \ 932 INTEL_SPI_OP_DATA_IN(4), \ 933 intel_spi_read), \ 934 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \ 935 INTEL_SPI_OP_ADDR(4), \ 936 INTEL_SPI_OP_DATA_IN(1), \ 937 intel_spi_read), \ 938 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \ 939 INTEL_SPI_OP_ADDR(4), \ 940 INTEL_SPI_OP_DATA_IN(2), \ 941 intel_spi_read), \ 942 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \ 943 INTEL_SPI_OP_ADDR(4), \ 944 INTEL_SPI_OP_DATA_IN(4), \ 945 intel_spi_read), \ 946 /* Fast read */ \ 947 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST, 1), \ 948 INTEL_SPI_OP_ADDR(3), \ 949 INTEL_SPI_OP_DATA_IN(1), \ 950 intel_spi_read), \ 951 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST, 1), \ 952 INTEL_SPI_OP_ADDR(3), \ 953 INTEL_SPI_OP_DATA_IN(2), \ 954 intel_spi_read), \ 955 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST, 1), \ 956 INTEL_SPI_OP_ADDR(3), \ 957 INTEL_SPI_OP_DATA_IN(4), \ 958 intel_spi_read), \ 959 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST, 1), \ 960 INTEL_SPI_OP_ADDR(4), \ 961 INTEL_SPI_OP_DATA_IN(1), \ 962 intel_spi_read), \ 963 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST, 1), \ 964 INTEL_SPI_OP_ADDR(4), \ 965 INTEL_SPI_OP_DATA_IN(2), \ 966 intel_spi_read), \ 967 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST, 1), \ 968 INTEL_SPI_OP_ADDR(4), \ 969 INTEL_SPI_OP_DATA_IN(4), \ 970 intel_spi_read), \ 971 /* Read with 4-byte address opcode */ \ 972 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_4B, 1), \ 973 INTEL_SPI_OP_ADDR(4), \ 974 INTEL_SPI_OP_DATA_IN(1), \ 975 intel_spi_read), \ 976 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_4B, 1), \ 977 INTEL_SPI_OP_ADDR(4), \ 978 INTEL_SPI_OP_DATA_IN(2), \ 979 intel_spi_read), \ 980 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_4B, 1), \ 981 INTEL_SPI_OP_ADDR(4), \ 982 INTEL_SPI_OP_DATA_IN(4), \ 983 intel_spi_read), \ 984 /* Fast read with 4-byte address opcode */ \ 985 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST_4B, 1), \ 986 INTEL_SPI_OP_ADDR(4), \ 987 INTEL_SPI_OP_DATA_IN(1), \ 988 intel_spi_read), \ 989 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST_4B, 1), \ 990 INTEL_SPI_OP_ADDR(4), \ 991 INTEL_SPI_OP_DATA_IN(2), \ 992 intel_spi_read), \ 993 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST_4B, 1), \ 994 INTEL_SPI_OP_ADDR(4), \ 995 INTEL_SPI_OP_DATA_IN(4), \ 996 intel_spi_read), \ 997 /* Write operations */ \ 998 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_PP, 1), \ 999 INTEL_SPI_OP_ADDR(3), \ 1000 INTEL_SPI_OP_DATA_OUT(1), \ 1001 intel_spi_write), \ 1002 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_PP, 1), \ 1003 INTEL_SPI_OP_ADDR(4), \ 1004 INTEL_SPI_OP_DATA_OUT(1), \ 1005 intel_spi_write), \ 1006 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_PP_4B, 1), \ 1007 INTEL_SPI_OP_ADDR(4), \ 1008 INTEL_SPI_OP_DATA_OUT(1), \ 1009 intel_spi_write), \ 1010 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREN, 1), \ 1011 SPI_MEM_OP_NO_ADDR, \ 1012 SPI_MEM_OP_NO_DATA, \ 1013 intel_spi_write_reg), \ 1014 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRDI, 1), \ 1015 SPI_MEM_OP_NO_ADDR, \ 1016 SPI_MEM_OP_NO_DATA, \ 1017 intel_spi_write_reg), \ 1018 /* Erase operations */ \ 1019 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_BE_4K, 1), \ 1020 INTEL_SPI_OP_ADDR(3), \ 1021 SPI_MEM_OP_NO_DATA, \ 1022 intel_spi_erase, \ 1023 HSFSTS_CTL_FCYCLE_ERASE), \ 1024 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_BE_4K, 1), \ 1025 INTEL_SPI_OP_ADDR(4), \ 1026 SPI_MEM_OP_NO_DATA, \ 1027 intel_spi_erase, \ 1028 HSFSTS_CTL_FCYCLE_ERASE), \ 1029 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_BE_4K_4B, 1), \ 1030 INTEL_SPI_OP_ADDR(4), \ 1031 SPI_MEM_OP_NO_DATA, \ 1032 intel_spi_erase, \ 1033 HSFSTS_CTL_FCYCLE_ERASE) \ 1034 1035 static const struct intel_spi_mem_op generic_mem_ops[] = { 1036 INTEL_SPI_GENERIC_OPS, 1037 { }, 1038 }; 1039 1040 static const struct intel_spi_mem_op erase_64k_mem_ops[] = { 1041 INTEL_SPI_GENERIC_OPS, 1042 /* 64k sector erase operations */ 1043 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_SE, 1), 1044 INTEL_SPI_OP_ADDR(3), 1045 SPI_MEM_OP_NO_DATA, 1046 intel_spi_erase, 1047 HSFSTS_CTL_FCYCLE_ERASE_64K), 1048 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_SE, 1), 1049 INTEL_SPI_OP_ADDR(4), 1050 SPI_MEM_OP_NO_DATA, 1051 intel_spi_erase, 1052 HSFSTS_CTL_FCYCLE_ERASE_64K), 1053 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_SE_4B, 1), 1054 INTEL_SPI_OP_ADDR(4), 1055 SPI_MEM_OP_NO_DATA, 1056 intel_spi_erase, 1057 HSFSTS_CTL_FCYCLE_ERASE_64K), 1058 { }, 1059 }; 1060 1061 static int intel_spi_init(struct intel_spi *ispi) 1062 { 1063 u32 opmenu0, opmenu1, lvscc, uvscc, val; 1064 bool erase_64k = false; 1065 int i; 1066 1067 switch (ispi->info->type) { 1068 case INTEL_SPI_BYT: 1069 ispi->sregs = ispi->base + BYT_SSFSTS_CTL; 1070 ispi->pregs = ispi->base + BYT_PR; 1071 ispi->nregions = BYT_FREG_NUM; 1072 ispi->pr_num = BYT_PR_NUM; 1073 ispi->swseq_reg = true; 1074 break; 1075 1076 case INTEL_SPI_LPT: 1077 ispi->sregs = ispi->base + LPT_SSFSTS_CTL; 1078 ispi->pregs = ispi->base + LPT_PR; 1079 ispi->nregions = LPT_FREG_NUM; 1080 ispi->pr_num = LPT_PR_NUM; 1081 ispi->swseq_reg = true; 1082 break; 1083 1084 case INTEL_SPI_BXT: 1085 ispi->sregs = ispi->base + BXT_SSFSTS_CTL; 1086 ispi->pregs = ispi->base + BXT_PR; 1087 ispi->nregions = BXT_FREG_NUM; 1088 ispi->pr_num = BXT_PR_NUM; 1089 erase_64k = true; 1090 break; 1091 1092 case INTEL_SPI_CNL: 1093 ispi->sregs = NULL; 1094 ispi->pregs = ispi->base + CNL_PR; 1095 ispi->nregions = CNL_FREG_NUM; 1096 ispi->pr_num = CNL_PR_NUM; 1097 erase_64k = true; 1098 break; 1099 1100 default: 1101 return -EINVAL; 1102 } 1103 1104 /* Try to disable write protection if user asked to do so */ 1105 if (writeable && !intel_spi_set_writeable(ispi)) { 1106 dev_warn(ispi->dev, "can't disable chip write protection\n"); 1107 writeable = false; 1108 } 1109 1110 /* Disable #SMI generation from HW sequencer */ 1111 val = readl(ispi->base + HSFSTS_CTL); 1112 val &= ~HSFSTS_CTL_FSMIE; 1113 writel(val, ispi->base + HSFSTS_CTL); 1114 1115 /* 1116 * Determine whether erase operation should use HW or SW sequencer. 1117 * 1118 * The HW sequencer has a predefined list of opcodes, with only the 1119 * erase opcode being programmable in LVSCC and UVSCC registers. 1120 * If these registers don't contain a valid erase opcode, erase 1121 * cannot be done using HW sequencer. 1122 */ 1123 lvscc = readl(ispi->base + LVSCC); 1124 uvscc = readl(ispi->base + UVSCC); 1125 if (!(lvscc & ERASE_OPCODE_MASK) || !(uvscc & ERASE_OPCODE_MASK)) 1126 ispi->swseq_erase = true; 1127 /* SPI controller on Intel BXT supports 64K erase opcode */ 1128 if (ispi->info->type == INTEL_SPI_BXT && !ispi->swseq_erase) 1129 if (!(lvscc & ERASE_64K_OPCODE_MASK) || 1130 !(uvscc & ERASE_64K_OPCODE_MASK)) 1131 erase_64k = false; 1132 1133 if (!ispi->sregs && (ispi->swseq_reg || ispi->swseq_erase)) { 1134 dev_err(ispi->dev, "software sequencer not supported, but required\n"); 1135 return -EINVAL; 1136 } 1137 1138 /* 1139 * Some controllers can only do basic operations using hardware 1140 * sequencer. All other operations are supposed to be carried out 1141 * using software sequencer. 1142 */ 1143 if (ispi->swseq_reg) { 1144 /* Disable #SMI generation from SW sequencer */ 1145 val = readl(ispi->sregs + SSFSTS_CTL); 1146 val &= ~SSFSTS_CTL_FSMIE; 1147 writel(val, ispi->sregs + SSFSTS_CTL); 1148 } 1149 1150 /* Check controller's lock status */ 1151 val = readl(ispi->base + HSFSTS_CTL); 1152 ispi->locked = !!(val & HSFSTS_CTL_FLOCKDN); 1153 1154 if (ispi->locked && ispi->sregs) { 1155 /* 1156 * BIOS programs allowed opcodes and then locks down the 1157 * register. So read back what opcodes it decided to support. 1158 * That's the set we are going to support as well. 1159 */ 1160 opmenu0 = readl(ispi->sregs + OPMENU0); 1161 opmenu1 = readl(ispi->sregs + OPMENU1); 1162 1163 if (opmenu0 && opmenu1) { 1164 for (i = 0; i < ARRAY_SIZE(ispi->opcodes) / 2; i++) { 1165 ispi->opcodes[i] = opmenu0 >> i * 8; 1166 ispi->opcodes[i + 4] = opmenu1 >> i * 8; 1167 } 1168 } 1169 } 1170 1171 if (erase_64k) { 1172 dev_dbg(ispi->dev, "Using erase_64k memory operations"); 1173 ispi->mem_ops = erase_64k_mem_ops; 1174 } else { 1175 dev_dbg(ispi->dev, "Using generic memory operations"); 1176 ispi->mem_ops = generic_mem_ops; 1177 } 1178 1179 intel_spi_dump_regs(ispi); 1180 return 0; 1181 } 1182 1183 static bool intel_spi_is_protected(const struct intel_spi *ispi, 1184 unsigned int base, unsigned int limit) 1185 { 1186 int i; 1187 1188 for (i = 0; i < ispi->pr_num; i++) { 1189 u32 pr_base, pr_limit, pr_value; 1190 1191 pr_value = readl(ispi->pregs + PR(i)); 1192 if (!(pr_value & (PR_WPE | PR_RPE))) 1193 continue; 1194 1195 pr_limit = (pr_value & PR_LIMIT_MASK) >> PR_LIMIT_SHIFT; 1196 pr_base = pr_value & PR_BASE_MASK; 1197 1198 if (pr_base >= base && pr_limit <= limit) 1199 return true; 1200 } 1201 1202 return false; 1203 } 1204 1205 /* 1206 * There will be a single partition holding all enabled flash regions. We 1207 * call this "BIOS". 1208 */ 1209 static void intel_spi_fill_partition(struct intel_spi *ispi, 1210 struct mtd_partition *part) 1211 { 1212 u64 end; 1213 int i; 1214 1215 memset(part, 0, sizeof(*part)); 1216 1217 /* Start from the mandatory descriptor region */ 1218 part->size = 4096; 1219 part->name = "BIOS"; 1220 1221 /* 1222 * Now try to find where this partition ends based on the flash 1223 * region registers. 1224 */ 1225 for (i = 1; i < ispi->nregions; i++) { 1226 u32 region, base, limit; 1227 1228 region = readl(ispi->base + FREG(i)); 1229 base = region & FREG_BASE_MASK; 1230 limit = (region & FREG_LIMIT_MASK) >> FREG_LIMIT_SHIFT; 1231 1232 if (base >= limit || limit == 0) 1233 continue; 1234 1235 /* 1236 * If any of the regions have protection bits set, make the 1237 * whole partition read-only to be on the safe side. 1238 * 1239 * Also if the user did not ask the chip to be writeable 1240 * mask the bit too. 1241 */ 1242 if (!writeable || intel_spi_is_protected(ispi, base, limit)) 1243 part->mask_flags |= MTD_WRITEABLE; 1244 1245 end = (limit << 12) + 4096; 1246 if (end > part->size) 1247 part->size = end; 1248 } 1249 } 1250 1251 static int intel_spi_read_desc(struct intel_spi *ispi) 1252 { 1253 struct spi_mem_op op = 1254 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 0), 1255 SPI_MEM_OP_ADDR(3, 0, 0), 1256 SPI_MEM_OP_NO_DUMMY, 1257 SPI_MEM_OP_DATA_IN(0, NULL, 0)); 1258 u32 buf[2], nc, fcba, flcomp; 1259 ssize_t ret; 1260 1261 op.addr.val = 0x10; 1262 op.data.buf.in = buf; 1263 op.data.nbytes = sizeof(buf); 1264 1265 ret = intel_spi_read(ispi, NULL, NULL, &op); 1266 if (ret) { 1267 dev_warn(ispi->dev, "failed to read descriptor\n"); 1268 return ret; 1269 } 1270 1271 dev_dbg(ispi->dev, "FLVALSIG=0x%08x\n", buf[0]); 1272 dev_dbg(ispi->dev, "FLMAP0=0x%08x\n", buf[1]); 1273 1274 if (buf[0] != FLVALSIG_MAGIC) { 1275 dev_warn(ispi->dev, "descriptor signature not valid\n"); 1276 return -ENODEV; 1277 } 1278 1279 fcba = (buf[1] & FLMAP0_FCBA_MASK) << 4; 1280 dev_dbg(ispi->dev, "FCBA=%#x\n", fcba); 1281 1282 op.addr.val = fcba; 1283 op.data.buf.in = &flcomp; 1284 op.data.nbytes = sizeof(flcomp); 1285 1286 ret = intel_spi_read(ispi, NULL, NULL, &op); 1287 if (ret) { 1288 dev_warn(ispi->dev, "failed to read FLCOMP\n"); 1289 return -ENODEV; 1290 } 1291 1292 dev_dbg(ispi->dev, "FLCOMP=0x%08x\n", flcomp); 1293 1294 switch (flcomp & FLCOMP_C0DEN_MASK) { 1295 case FLCOMP_C0DEN_512K: 1296 ispi->chip0_size = SZ_512K; 1297 break; 1298 case FLCOMP_C0DEN_1M: 1299 ispi->chip0_size = SZ_1M; 1300 break; 1301 case FLCOMP_C0DEN_2M: 1302 ispi->chip0_size = SZ_2M; 1303 break; 1304 case FLCOMP_C0DEN_4M: 1305 ispi->chip0_size = SZ_4M; 1306 break; 1307 case FLCOMP_C0DEN_8M: 1308 ispi->chip0_size = SZ_8M; 1309 break; 1310 case FLCOMP_C0DEN_16M: 1311 ispi->chip0_size = SZ_16M; 1312 break; 1313 case FLCOMP_C0DEN_32M: 1314 ispi->chip0_size = SZ_32M; 1315 break; 1316 case FLCOMP_C0DEN_64M: 1317 ispi->chip0_size = SZ_64M; 1318 break; 1319 default: 1320 return -EINVAL; 1321 } 1322 1323 dev_dbg(ispi->dev, "chip0 size %zd KB\n", ispi->chip0_size / SZ_1K); 1324 1325 nc = (buf[1] & FLMAP0_NC_MASK) >> FLMAP0_NC_SHIFT; 1326 if (!nc) 1327 ispi->master->num_chipselect = 1; 1328 else if (nc == 1) 1329 ispi->master->num_chipselect = 2; 1330 else 1331 return -EINVAL; 1332 1333 dev_dbg(ispi->dev, "%u flash components found\n", 1334 ispi->master->num_chipselect); 1335 return 0; 1336 } 1337 1338 static int intel_spi_populate_chip(struct intel_spi *ispi) 1339 { 1340 struct flash_platform_data *pdata; 1341 struct spi_board_info chip; 1342 int ret; 1343 1344 pdata = devm_kzalloc(ispi->dev, sizeof(*pdata), GFP_KERNEL); 1345 if (!pdata) 1346 return -ENOMEM; 1347 1348 pdata->nr_parts = 1; 1349 pdata->parts = devm_kcalloc(ispi->dev, pdata->nr_parts, 1350 sizeof(*pdata->parts), GFP_KERNEL); 1351 if (!pdata->parts) 1352 return -ENOMEM; 1353 1354 intel_spi_fill_partition(ispi, pdata->parts); 1355 1356 memset(&chip, 0, sizeof(chip)); 1357 snprintf(chip.modalias, 8, "spi-nor"); 1358 chip.platform_data = pdata; 1359 1360 if (!spi_new_device(ispi->master, &chip)) 1361 return -ENODEV; 1362 1363 /* Add the second chip if present */ 1364 if (ispi->master->num_chipselect < 2) 1365 return 0; 1366 1367 ret = intel_spi_read_desc(ispi); 1368 if (ret) 1369 return ret; 1370 1371 chip.platform_data = NULL; 1372 chip.chip_select = 1; 1373 1374 if (!spi_new_device(ispi->master, &chip)) 1375 return -ENODEV; 1376 return 0; 1377 } 1378 1379 /** 1380 * intel_spi_probe() - Probe the Intel SPI flash controller 1381 * @dev: Pointer to the parent device 1382 * @mem: MMIO resource 1383 * @info: Platform specific information 1384 * 1385 * Probes Intel SPI flash controller and creates the flash chip device. 1386 * Returns %0 on success and negative errno in case of failure. 1387 */ 1388 int intel_spi_probe(struct device *dev, struct resource *mem, 1389 const struct intel_spi_boardinfo *info) 1390 { 1391 struct spi_controller *master; 1392 struct intel_spi *ispi; 1393 int ret; 1394 1395 master = devm_spi_alloc_master(dev, sizeof(*ispi)); 1396 if (!master) 1397 return -ENOMEM; 1398 1399 master->mem_ops = &intel_spi_mem_ops; 1400 1401 ispi = spi_master_get_devdata(master); 1402 1403 ispi->base = devm_ioremap_resource(dev, mem); 1404 if (IS_ERR(ispi->base)) 1405 return PTR_ERR(ispi->base); 1406 1407 ispi->dev = dev; 1408 ispi->master = master; 1409 ispi->info = info; 1410 1411 ret = intel_spi_init(ispi); 1412 if (ret) 1413 return ret; 1414 1415 ret = devm_spi_register_master(dev, master); 1416 if (ret) 1417 return ret; 1418 1419 return intel_spi_populate_chip(ispi); 1420 } 1421 EXPORT_SYMBOL_GPL(intel_spi_probe); 1422 1423 MODULE_DESCRIPTION("Intel PCH/PCU SPI flash core driver"); 1424 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 1425 MODULE_LICENSE("GPL v2"); 1426