1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Intel PCH/PCU SPI flash driver. 4 * 5 * Copyright (C) 2016 - 2022, Intel Corporation 6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com> 7 */ 8 9 #include <linux/iopoll.h> 10 #include <linux/module.h> 11 12 #include <linux/mtd/partitions.h> 13 #include <linux/mtd/spi-nor.h> 14 15 #include <linux/spi/flash.h> 16 #include <linux/spi/spi.h> 17 #include <linux/spi/spi-mem.h> 18 19 #include "spi-intel.h" 20 21 /* Offsets are from @ispi->base */ 22 #define BFPREG 0x00 23 24 #define HSFSTS_CTL 0x04 25 #define HSFSTS_CTL_FSMIE BIT(31) 26 #define HSFSTS_CTL_FDBC_SHIFT 24 27 #define HSFSTS_CTL_FDBC_MASK (0x3f << HSFSTS_CTL_FDBC_SHIFT) 28 29 #define HSFSTS_CTL_FCYCLE_SHIFT 17 30 #define HSFSTS_CTL_FCYCLE_MASK (0x0f << HSFSTS_CTL_FCYCLE_SHIFT) 31 /* HW sequencer opcodes */ 32 #define HSFSTS_CTL_FCYCLE_READ (0x00 << HSFSTS_CTL_FCYCLE_SHIFT) 33 #define HSFSTS_CTL_FCYCLE_WRITE (0x02 << HSFSTS_CTL_FCYCLE_SHIFT) 34 #define HSFSTS_CTL_FCYCLE_ERASE (0x03 << HSFSTS_CTL_FCYCLE_SHIFT) 35 #define HSFSTS_CTL_FCYCLE_ERASE_64K (0x04 << HSFSTS_CTL_FCYCLE_SHIFT) 36 #define HSFSTS_CTL_FCYCLE_RDID (0x06 << HSFSTS_CTL_FCYCLE_SHIFT) 37 #define HSFSTS_CTL_FCYCLE_WRSR (0x07 << HSFSTS_CTL_FCYCLE_SHIFT) 38 #define HSFSTS_CTL_FCYCLE_RDSR (0x08 << HSFSTS_CTL_FCYCLE_SHIFT) 39 40 #define HSFSTS_CTL_FGO BIT(16) 41 #define HSFSTS_CTL_FLOCKDN BIT(15) 42 #define HSFSTS_CTL_FDV BIT(14) 43 #define HSFSTS_CTL_SCIP BIT(5) 44 #define HSFSTS_CTL_AEL BIT(2) 45 #define HSFSTS_CTL_FCERR BIT(1) 46 #define HSFSTS_CTL_FDONE BIT(0) 47 48 #define FADDR 0x08 49 #define DLOCK 0x0c 50 #define FDATA(n) (0x10 + ((n) * 4)) 51 52 #define FRACC 0x50 53 54 #define FREG(n) (0x54 + ((n) * 4)) 55 #define FREG_BASE_MASK 0x3fff 56 #define FREG_LIMIT_SHIFT 16 57 #define FREG_LIMIT_MASK (0x03fff << FREG_LIMIT_SHIFT) 58 59 /* Offset is from @ispi->pregs */ 60 #define PR(n) ((n) * 4) 61 #define PR_WPE BIT(31) 62 #define PR_LIMIT_SHIFT 16 63 #define PR_LIMIT_MASK (0x3fff << PR_LIMIT_SHIFT) 64 #define PR_RPE BIT(15) 65 #define PR_BASE_MASK 0x3fff 66 67 /* Offsets are from @ispi->sregs */ 68 #define SSFSTS_CTL 0x00 69 #define SSFSTS_CTL_FSMIE BIT(23) 70 #define SSFSTS_CTL_DS BIT(22) 71 #define SSFSTS_CTL_DBC_SHIFT 16 72 #define SSFSTS_CTL_SPOP BIT(11) 73 #define SSFSTS_CTL_ACS BIT(10) 74 #define SSFSTS_CTL_SCGO BIT(9) 75 #define SSFSTS_CTL_COP_SHIFT 12 76 #define SSFSTS_CTL_FRS BIT(7) 77 #define SSFSTS_CTL_DOFRS BIT(6) 78 #define SSFSTS_CTL_AEL BIT(4) 79 #define SSFSTS_CTL_FCERR BIT(3) 80 #define SSFSTS_CTL_FDONE BIT(2) 81 #define SSFSTS_CTL_SCIP BIT(0) 82 83 #define PREOP_OPTYPE 0x04 84 #define OPMENU0 0x08 85 #define OPMENU1 0x0c 86 87 #define OPTYPE_READ_NO_ADDR 0 88 #define OPTYPE_WRITE_NO_ADDR 1 89 #define OPTYPE_READ_WITH_ADDR 2 90 #define OPTYPE_WRITE_WITH_ADDR 3 91 92 /* CPU specifics */ 93 #define BYT_PR 0x74 94 #define BYT_SSFSTS_CTL 0x90 95 #define BYT_FREG_NUM 5 96 #define BYT_PR_NUM 5 97 98 #define LPT_PR 0x74 99 #define LPT_SSFSTS_CTL 0x90 100 #define LPT_FREG_NUM 5 101 #define LPT_PR_NUM 5 102 103 #define BXT_PR 0x84 104 #define BXT_SSFSTS_CTL 0xa0 105 #define BXT_FREG_NUM 12 106 #define BXT_PR_NUM 6 107 108 #define CNL_PR 0x84 109 #define CNL_FREG_NUM 6 110 #define CNL_PR_NUM 5 111 112 #define LVSCC 0xc4 113 #define UVSCC 0xc8 114 #define ERASE_OPCODE_SHIFT 8 115 #define ERASE_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT) 116 #define ERASE_64K_OPCODE_SHIFT 16 117 #define ERASE_64K_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT) 118 119 /* Flash descriptor fields */ 120 #define FLVALSIG_MAGIC 0x0ff0a55a 121 #define FLMAP0_NC_MASK GENMASK(9, 8) 122 #define FLMAP0_NC_SHIFT 8 123 #define FLMAP0_FCBA_MASK GENMASK(7, 0) 124 125 #define FLCOMP_C0DEN_MASK GENMASK(3, 0) 126 #define FLCOMP_C0DEN_512K 0x00 127 #define FLCOMP_C0DEN_1M 0x01 128 #define FLCOMP_C0DEN_2M 0x02 129 #define FLCOMP_C0DEN_4M 0x03 130 #define FLCOMP_C0DEN_8M 0x04 131 #define FLCOMP_C0DEN_16M 0x05 132 #define FLCOMP_C0DEN_32M 0x06 133 #define FLCOMP_C0DEN_64M 0x07 134 135 #define INTEL_SPI_TIMEOUT 5000 /* ms */ 136 #define INTEL_SPI_FIFO_SZ 64 137 138 /** 139 * struct intel_spi - Driver private data 140 * @dev: Device pointer 141 * @info: Pointer to board specific info 142 * @base: Beginning of MMIO space 143 * @pregs: Start of protection registers 144 * @sregs: Start of software sequencer registers 145 * @master: Pointer to the SPI controller structure 146 * @nregions: Maximum number of regions 147 * @pr_num: Maximum number of protected range registers 148 * @chip0_size: Size of the first flash chip in bytes 149 * @locked: Is SPI setting locked 150 * @swseq_reg: Use SW sequencer in register reads/writes 151 * @swseq_erase: Use SW sequencer in erase operation 152 * @atomic_preopcode: Holds preopcode when atomic sequence is requested 153 * @opcodes: Opcodes which are supported. This are programmed by BIOS 154 * before it locks down the controller. 155 * @mem_ops: Pointer to SPI MEM ops supported by the controller 156 */ 157 struct intel_spi { 158 struct device *dev; 159 const struct intel_spi_boardinfo *info; 160 void __iomem *base; 161 void __iomem *pregs; 162 void __iomem *sregs; 163 struct spi_controller *master; 164 size_t nregions; 165 size_t pr_num; 166 size_t chip0_size; 167 bool locked; 168 bool swseq_reg; 169 bool swseq_erase; 170 u8 atomic_preopcode; 171 u8 opcodes[8]; 172 const struct intel_spi_mem_op *mem_ops; 173 }; 174 175 struct intel_spi_mem_op { 176 struct spi_mem_op mem_op; 177 u32 replacement_op; 178 int (*exec_op)(struct intel_spi *ispi, 179 const struct spi_mem *mem, 180 const struct intel_spi_mem_op *iop, 181 const struct spi_mem_op *op); 182 }; 183 184 static bool writeable; 185 module_param(writeable, bool, 0); 186 MODULE_PARM_DESC(writeable, "Enable write access to SPI flash chip (default=0)"); 187 188 static void intel_spi_dump_regs(struct intel_spi *ispi) 189 { 190 u32 value; 191 int i; 192 193 dev_dbg(ispi->dev, "BFPREG=0x%08x\n", readl(ispi->base + BFPREG)); 194 195 value = readl(ispi->base + HSFSTS_CTL); 196 dev_dbg(ispi->dev, "HSFSTS_CTL=0x%08x\n", value); 197 if (value & HSFSTS_CTL_FLOCKDN) 198 dev_dbg(ispi->dev, "-> Locked\n"); 199 200 dev_dbg(ispi->dev, "FADDR=0x%08x\n", readl(ispi->base + FADDR)); 201 dev_dbg(ispi->dev, "DLOCK=0x%08x\n", readl(ispi->base + DLOCK)); 202 203 for (i = 0; i < 16; i++) 204 dev_dbg(ispi->dev, "FDATA(%d)=0x%08x\n", 205 i, readl(ispi->base + FDATA(i))); 206 207 dev_dbg(ispi->dev, "FRACC=0x%08x\n", readl(ispi->base + FRACC)); 208 209 for (i = 0; i < ispi->nregions; i++) 210 dev_dbg(ispi->dev, "FREG(%d)=0x%08x\n", i, 211 readl(ispi->base + FREG(i))); 212 for (i = 0; i < ispi->pr_num; i++) 213 dev_dbg(ispi->dev, "PR(%d)=0x%08x\n", i, 214 readl(ispi->pregs + PR(i))); 215 216 if (ispi->sregs) { 217 value = readl(ispi->sregs + SSFSTS_CTL); 218 dev_dbg(ispi->dev, "SSFSTS_CTL=0x%08x\n", value); 219 dev_dbg(ispi->dev, "PREOP_OPTYPE=0x%08x\n", 220 readl(ispi->sregs + PREOP_OPTYPE)); 221 dev_dbg(ispi->dev, "OPMENU0=0x%08x\n", 222 readl(ispi->sregs + OPMENU0)); 223 dev_dbg(ispi->dev, "OPMENU1=0x%08x\n", 224 readl(ispi->sregs + OPMENU1)); 225 } 226 227 dev_dbg(ispi->dev, "LVSCC=0x%08x\n", readl(ispi->base + LVSCC)); 228 dev_dbg(ispi->dev, "UVSCC=0x%08x\n", readl(ispi->base + UVSCC)); 229 230 dev_dbg(ispi->dev, "Protected regions:\n"); 231 for (i = 0; i < ispi->pr_num; i++) { 232 u32 base, limit; 233 234 value = readl(ispi->pregs + PR(i)); 235 if (!(value & (PR_WPE | PR_RPE))) 236 continue; 237 238 limit = (value & PR_LIMIT_MASK) >> PR_LIMIT_SHIFT; 239 base = value & PR_BASE_MASK; 240 241 dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x [%c%c]\n", 242 i, base << 12, (limit << 12) | 0xfff, 243 value & PR_WPE ? 'W' : '.', value & PR_RPE ? 'R' : '.'); 244 } 245 246 dev_dbg(ispi->dev, "Flash regions:\n"); 247 for (i = 0; i < ispi->nregions; i++) { 248 u32 region, base, limit; 249 250 region = readl(ispi->base + FREG(i)); 251 base = region & FREG_BASE_MASK; 252 limit = (region & FREG_LIMIT_MASK) >> FREG_LIMIT_SHIFT; 253 254 if (base >= limit || (i > 0 && limit == 0)) 255 dev_dbg(ispi->dev, " %02d disabled\n", i); 256 else 257 dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x\n", 258 i, base << 12, (limit << 12) | 0xfff); 259 } 260 261 dev_dbg(ispi->dev, "Using %cW sequencer for register access\n", 262 ispi->swseq_reg ? 'S' : 'H'); 263 dev_dbg(ispi->dev, "Using %cW sequencer for erase operation\n", 264 ispi->swseq_erase ? 'S' : 'H'); 265 } 266 267 /* Reads max INTEL_SPI_FIFO_SZ bytes from the device fifo */ 268 static int intel_spi_read_block(struct intel_spi *ispi, void *buf, size_t size) 269 { 270 size_t bytes; 271 int i = 0; 272 273 if (size > INTEL_SPI_FIFO_SZ) 274 return -EINVAL; 275 276 while (size > 0) { 277 bytes = min_t(size_t, size, 4); 278 memcpy_fromio(buf, ispi->base + FDATA(i), bytes); 279 size -= bytes; 280 buf += bytes; 281 i++; 282 } 283 284 return 0; 285 } 286 287 /* Writes max INTEL_SPI_FIFO_SZ bytes to the device fifo */ 288 static int intel_spi_write_block(struct intel_spi *ispi, const void *buf, 289 size_t size) 290 { 291 size_t bytes; 292 int i = 0; 293 294 if (size > INTEL_SPI_FIFO_SZ) 295 return -EINVAL; 296 297 while (size > 0) { 298 bytes = min_t(size_t, size, 4); 299 memcpy_toio(ispi->base + FDATA(i), buf, bytes); 300 size -= bytes; 301 buf += bytes; 302 i++; 303 } 304 305 return 0; 306 } 307 308 static int intel_spi_wait_hw_busy(struct intel_spi *ispi) 309 { 310 u32 val; 311 312 return readl_poll_timeout(ispi->base + HSFSTS_CTL, val, 313 !(val & HSFSTS_CTL_SCIP), 0, 314 INTEL_SPI_TIMEOUT * 1000); 315 } 316 317 static int intel_spi_wait_sw_busy(struct intel_spi *ispi) 318 { 319 u32 val; 320 321 return readl_poll_timeout(ispi->sregs + SSFSTS_CTL, val, 322 !(val & SSFSTS_CTL_SCIP), 0, 323 INTEL_SPI_TIMEOUT * 1000); 324 } 325 326 static bool intel_spi_set_writeable(struct intel_spi *ispi) 327 { 328 if (!ispi->info->set_writeable) 329 return false; 330 331 return ispi->info->set_writeable(ispi->base, ispi->info->data); 332 } 333 334 static int intel_spi_opcode_index(struct intel_spi *ispi, u8 opcode, int optype) 335 { 336 int i; 337 int preop; 338 339 if (ispi->locked) { 340 for (i = 0; i < ARRAY_SIZE(ispi->opcodes); i++) 341 if (ispi->opcodes[i] == opcode) 342 return i; 343 344 return -EINVAL; 345 } 346 347 /* The lock is off, so just use index 0 */ 348 writel(opcode, ispi->sregs + OPMENU0); 349 preop = readw(ispi->sregs + PREOP_OPTYPE); 350 writel(optype << 16 | preop, ispi->sregs + PREOP_OPTYPE); 351 352 return 0; 353 } 354 355 static int intel_spi_hw_cycle(struct intel_spi *ispi, u8 opcode, size_t len) 356 { 357 u32 val, status; 358 int ret; 359 360 val = readl(ispi->base + HSFSTS_CTL); 361 val &= ~(HSFSTS_CTL_FCYCLE_MASK | HSFSTS_CTL_FDBC_MASK); 362 363 switch (opcode) { 364 case SPINOR_OP_RDID: 365 val |= HSFSTS_CTL_FCYCLE_RDID; 366 break; 367 case SPINOR_OP_WRSR: 368 val |= HSFSTS_CTL_FCYCLE_WRSR; 369 break; 370 case SPINOR_OP_RDSR: 371 val |= HSFSTS_CTL_FCYCLE_RDSR; 372 break; 373 default: 374 return -EINVAL; 375 } 376 377 if (len > INTEL_SPI_FIFO_SZ) 378 return -EINVAL; 379 380 val |= (len - 1) << HSFSTS_CTL_FDBC_SHIFT; 381 val |= HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE; 382 val |= HSFSTS_CTL_FGO; 383 writel(val, ispi->base + HSFSTS_CTL); 384 385 ret = intel_spi_wait_hw_busy(ispi); 386 if (ret) 387 return ret; 388 389 status = readl(ispi->base + HSFSTS_CTL); 390 if (status & HSFSTS_CTL_FCERR) 391 return -EIO; 392 else if (status & HSFSTS_CTL_AEL) 393 return -EACCES; 394 395 return 0; 396 } 397 398 static int intel_spi_sw_cycle(struct intel_spi *ispi, u8 opcode, size_t len, 399 int optype) 400 { 401 u32 val = 0, status; 402 u8 atomic_preopcode; 403 int ret; 404 405 ret = intel_spi_opcode_index(ispi, opcode, optype); 406 if (ret < 0) 407 return ret; 408 409 if (len > INTEL_SPI_FIFO_SZ) 410 return -EINVAL; 411 412 /* 413 * Always clear it after each SW sequencer operation regardless 414 * of whether it is successful or not. 415 */ 416 atomic_preopcode = ispi->atomic_preopcode; 417 ispi->atomic_preopcode = 0; 418 419 /* Only mark 'Data Cycle' bit when there is data to be transferred */ 420 if (len > 0) 421 val = ((len - 1) << SSFSTS_CTL_DBC_SHIFT) | SSFSTS_CTL_DS; 422 val |= ret << SSFSTS_CTL_COP_SHIFT; 423 val |= SSFSTS_CTL_FCERR | SSFSTS_CTL_FDONE; 424 val |= SSFSTS_CTL_SCGO; 425 if (atomic_preopcode) { 426 u16 preop; 427 428 switch (optype) { 429 case OPTYPE_WRITE_NO_ADDR: 430 case OPTYPE_WRITE_WITH_ADDR: 431 /* Pick matching preopcode for the atomic sequence */ 432 preop = readw(ispi->sregs + PREOP_OPTYPE); 433 if ((preop & 0xff) == atomic_preopcode) 434 ; /* Do nothing */ 435 else if ((preop >> 8) == atomic_preopcode) 436 val |= SSFSTS_CTL_SPOP; 437 else 438 return -EINVAL; 439 440 /* Enable atomic sequence */ 441 val |= SSFSTS_CTL_ACS; 442 break; 443 444 default: 445 return -EINVAL; 446 } 447 } 448 writel(val, ispi->sregs + SSFSTS_CTL); 449 450 ret = intel_spi_wait_sw_busy(ispi); 451 if (ret) 452 return ret; 453 454 status = readl(ispi->sregs + SSFSTS_CTL); 455 if (status & SSFSTS_CTL_FCERR) 456 return -EIO; 457 else if (status & SSFSTS_CTL_AEL) 458 return -EACCES; 459 460 return 0; 461 } 462 463 static u32 intel_spi_chip_addr(const struct intel_spi *ispi, 464 const struct spi_mem *mem) 465 { 466 /* Pick up the correct start address */ 467 if (!mem) 468 return 0; 469 return mem->spi->chip_select == 1 ? ispi->chip0_size : 0; 470 } 471 472 static int intel_spi_read_reg(struct intel_spi *ispi, const struct spi_mem *mem, 473 const struct intel_spi_mem_op *iop, 474 const struct spi_mem_op *op) 475 { 476 size_t nbytes = op->data.nbytes; 477 u8 opcode = op->cmd.opcode; 478 int ret; 479 480 writel(intel_spi_chip_addr(ispi, mem), ispi->base + FADDR); 481 482 if (ispi->swseq_reg) 483 ret = intel_spi_sw_cycle(ispi, opcode, nbytes, 484 OPTYPE_READ_NO_ADDR); 485 else 486 ret = intel_spi_hw_cycle(ispi, opcode, nbytes); 487 488 if (ret) 489 return ret; 490 491 return intel_spi_read_block(ispi, op->data.buf.in, nbytes); 492 } 493 494 static int intel_spi_write_reg(struct intel_spi *ispi, const struct spi_mem *mem, 495 const struct intel_spi_mem_op *iop, 496 const struct spi_mem_op *op) 497 { 498 size_t nbytes = op->data.nbytes; 499 u8 opcode = op->cmd.opcode; 500 int ret; 501 502 /* 503 * This is handled with atomic operation and preop code in Intel 504 * controller so we only verify that it is available. If the 505 * controller is not locked, program the opcode to the PREOP 506 * register for later use. 507 * 508 * When hardware sequencer is used there is no need to program 509 * any opcodes (it handles them automatically as part of a command). 510 */ 511 if (opcode == SPINOR_OP_WREN) { 512 u16 preop; 513 514 if (!ispi->swseq_reg) 515 return 0; 516 517 preop = readw(ispi->sregs + PREOP_OPTYPE); 518 if ((preop & 0xff) != opcode && (preop >> 8) != opcode) { 519 if (ispi->locked) 520 return -EINVAL; 521 writel(opcode, ispi->sregs + PREOP_OPTYPE); 522 } 523 524 /* 525 * This enables atomic sequence on next SW sycle. Will 526 * be cleared after next operation. 527 */ 528 ispi->atomic_preopcode = opcode; 529 return 0; 530 } 531 532 /* 533 * We hope that HW sequencer will do the right thing automatically and 534 * with the SW sequencer we cannot use preopcode anyway, so just ignore 535 * the Write Disable operation and pretend it was completed 536 * successfully. 537 */ 538 if (opcode == SPINOR_OP_WRDI) 539 return 0; 540 541 writel(intel_spi_chip_addr(ispi, mem), ispi->base + FADDR); 542 543 /* Write the value beforehand */ 544 ret = intel_spi_write_block(ispi, op->data.buf.out, nbytes); 545 if (ret) 546 return ret; 547 548 if (ispi->swseq_reg) 549 return intel_spi_sw_cycle(ispi, opcode, nbytes, 550 OPTYPE_WRITE_NO_ADDR); 551 return intel_spi_hw_cycle(ispi, opcode, nbytes); 552 } 553 554 static int intel_spi_read(struct intel_spi *ispi, const struct spi_mem *mem, 555 const struct intel_spi_mem_op *iop, 556 const struct spi_mem_op *op) 557 { 558 u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val; 559 size_t block_size, nbytes = op->data.nbytes; 560 void *read_buf = op->data.buf.in; 561 u32 val, status; 562 int ret; 563 564 /* 565 * Atomic sequence is not expected with HW sequencer reads. Make 566 * sure it is cleared regardless. 567 */ 568 if (WARN_ON_ONCE(ispi->atomic_preopcode)) 569 ispi->atomic_preopcode = 0; 570 571 while (nbytes > 0) { 572 block_size = min_t(size_t, nbytes, INTEL_SPI_FIFO_SZ); 573 574 /* Read cannot cross 4K boundary */ 575 block_size = min_t(loff_t, addr + block_size, 576 round_up(addr + 1, SZ_4K)) - addr; 577 578 writel(addr, ispi->base + FADDR); 579 580 val = readl(ispi->base + HSFSTS_CTL); 581 val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK); 582 val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE; 583 val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT; 584 val |= HSFSTS_CTL_FCYCLE_READ; 585 val |= HSFSTS_CTL_FGO; 586 writel(val, ispi->base + HSFSTS_CTL); 587 588 ret = intel_spi_wait_hw_busy(ispi); 589 if (ret) 590 return ret; 591 592 status = readl(ispi->base + HSFSTS_CTL); 593 if (status & HSFSTS_CTL_FCERR) 594 ret = -EIO; 595 else if (status & HSFSTS_CTL_AEL) 596 ret = -EACCES; 597 598 if (ret < 0) { 599 dev_err(ispi->dev, "read error: %x: %#x\n", addr, status); 600 return ret; 601 } 602 603 ret = intel_spi_read_block(ispi, read_buf, block_size); 604 if (ret) 605 return ret; 606 607 nbytes -= block_size; 608 addr += block_size; 609 read_buf += block_size; 610 } 611 612 return 0; 613 } 614 615 static int intel_spi_write(struct intel_spi *ispi, const struct spi_mem *mem, 616 const struct intel_spi_mem_op *iop, 617 const struct spi_mem_op *op) 618 { 619 u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val; 620 size_t block_size, nbytes = op->data.nbytes; 621 const void *write_buf = op->data.buf.out; 622 u32 val, status; 623 int ret; 624 625 /* Not needed with HW sequencer write, make sure it is cleared */ 626 ispi->atomic_preopcode = 0; 627 628 while (nbytes > 0) { 629 block_size = min_t(size_t, nbytes, INTEL_SPI_FIFO_SZ); 630 631 /* Write cannot cross 4K boundary */ 632 block_size = min_t(loff_t, addr + block_size, 633 round_up(addr + 1, SZ_4K)) - addr; 634 635 writel(addr, ispi->base + FADDR); 636 637 val = readl(ispi->base + HSFSTS_CTL); 638 val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK); 639 val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE; 640 val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT; 641 val |= HSFSTS_CTL_FCYCLE_WRITE; 642 643 ret = intel_spi_write_block(ispi, write_buf, block_size); 644 if (ret) { 645 dev_err(ispi->dev, "failed to write block\n"); 646 return ret; 647 } 648 649 /* Start the write now */ 650 val |= HSFSTS_CTL_FGO; 651 writel(val, ispi->base + HSFSTS_CTL); 652 653 ret = intel_spi_wait_hw_busy(ispi); 654 if (ret) { 655 dev_err(ispi->dev, "timeout\n"); 656 return ret; 657 } 658 659 status = readl(ispi->base + HSFSTS_CTL); 660 if (status & HSFSTS_CTL_FCERR) 661 ret = -EIO; 662 else if (status & HSFSTS_CTL_AEL) 663 ret = -EACCES; 664 665 if (ret < 0) { 666 dev_err(ispi->dev, "write error: %x: %#x\n", addr, status); 667 return ret; 668 } 669 670 nbytes -= block_size; 671 addr += block_size; 672 write_buf += block_size; 673 } 674 675 return 0; 676 } 677 678 static int intel_spi_erase(struct intel_spi *ispi, const struct spi_mem *mem, 679 const struct intel_spi_mem_op *iop, 680 const struct spi_mem_op *op) 681 { 682 u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val; 683 u8 opcode = op->cmd.opcode; 684 u32 val, status; 685 int ret; 686 687 writel(addr, ispi->base + FADDR); 688 689 if (ispi->swseq_erase) 690 return intel_spi_sw_cycle(ispi, opcode, 0, 691 OPTYPE_WRITE_WITH_ADDR); 692 693 /* Not needed with HW sequencer erase, make sure it is cleared */ 694 ispi->atomic_preopcode = 0; 695 696 val = readl(ispi->base + HSFSTS_CTL); 697 val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK); 698 val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE; 699 val |= HSFSTS_CTL_FGO; 700 val |= iop->replacement_op; 701 writel(val, ispi->base + HSFSTS_CTL); 702 703 ret = intel_spi_wait_hw_busy(ispi); 704 if (ret) 705 return ret; 706 707 status = readl(ispi->base + HSFSTS_CTL); 708 if (status & HSFSTS_CTL_FCERR) 709 return -EIO; 710 if (status & HSFSTS_CTL_AEL) 711 return -EACCES; 712 713 return 0; 714 } 715 716 static bool intel_spi_cmp_mem_op(const struct intel_spi_mem_op *iop, 717 const struct spi_mem_op *op) 718 { 719 if (iop->mem_op.cmd.nbytes != op->cmd.nbytes || 720 iop->mem_op.cmd.buswidth != op->cmd.buswidth || 721 iop->mem_op.cmd.dtr != op->cmd.dtr || 722 iop->mem_op.cmd.opcode != op->cmd.opcode) 723 return false; 724 725 if (iop->mem_op.addr.nbytes != op->addr.nbytes || 726 iop->mem_op.addr.dtr != op->addr.dtr) 727 return false; 728 729 if (iop->mem_op.data.dir != op->data.dir || 730 iop->mem_op.data.dtr != op->data.dtr) 731 return false; 732 733 if (iop->mem_op.data.dir != SPI_MEM_NO_DATA) { 734 if (iop->mem_op.data.buswidth != op->data.buswidth) 735 return false; 736 } 737 738 return true; 739 } 740 741 static const struct intel_spi_mem_op * 742 intel_spi_match_mem_op(struct intel_spi *ispi, const struct spi_mem_op *op) 743 { 744 const struct intel_spi_mem_op *iop; 745 746 for (iop = ispi->mem_ops; iop->mem_op.cmd.opcode; iop++) { 747 if (intel_spi_cmp_mem_op(iop, op)) 748 break; 749 } 750 751 return iop->mem_op.cmd.opcode ? iop : NULL; 752 } 753 754 static bool intel_spi_supports_mem_op(struct spi_mem *mem, 755 const struct spi_mem_op *op) 756 { 757 struct intel_spi *ispi = spi_master_get_devdata(mem->spi->master); 758 const struct intel_spi_mem_op *iop; 759 760 iop = intel_spi_match_mem_op(ispi, op); 761 if (!iop) { 762 dev_dbg(ispi->dev, "%#x not supported\n", op->cmd.opcode); 763 return false; 764 } 765 766 /* 767 * For software sequencer check that the opcode is actually 768 * present in the opmenu if it is locked. 769 */ 770 if (ispi->swseq_reg && ispi->locked) { 771 int i; 772 773 /* Check if it is in the locked opcodes list */ 774 for (i = 0; i < ARRAY_SIZE(ispi->opcodes); i++) { 775 if (ispi->opcodes[i] == op->cmd.opcode) 776 return true; 777 } 778 779 dev_dbg(ispi->dev, "%#x not supported\n", op->cmd.opcode); 780 return false; 781 } 782 783 return true; 784 } 785 786 static int intel_spi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) 787 { 788 struct intel_spi *ispi = spi_master_get_devdata(mem->spi->master); 789 const struct intel_spi_mem_op *iop; 790 791 iop = intel_spi_match_mem_op(ispi, op); 792 if (!iop) 793 return -EOPNOTSUPP; 794 795 return iop->exec_op(ispi, mem, iop, op); 796 } 797 798 static const char *intel_spi_get_name(struct spi_mem *mem) 799 { 800 const struct intel_spi *ispi = spi_master_get_devdata(mem->spi->master); 801 802 /* 803 * Return name of the flash controller device to be compatible 804 * with the MTD version. 805 */ 806 return dev_name(ispi->dev); 807 } 808 809 static int intel_spi_dirmap_create(struct spi_mem_dirmap_desc *desc) 810 { 811 struct intel_spi *ispi = spi_master_get_devdata(desc->mem->spi->master); 812 const struct intel_spi_mem_op *iop; 813 814 iop = intel_spi_match_mem_op(ispi, &desc->info.op_tmpl); 815 if (!iop) 816 return -EOPNOTSUPP; 817 818 desc->priv = (void *)iop; 819 return 0; 820 } 821 822 static ssize_t intel_spi_dirmap_read(struct spi_mem_dirmap_desc *desc, u64 offs, 823 size_t len, void *buf) 824 { 825 struct intel_spi *ispi = spi_master_get_devdata(desc->mem->spi->master); 826 const struct intel_spi_mem_op *iop = desc->priv; 827 struct spi_mem_op op = desc->info.op_tmpl; 828 int ret; 829 830 /* Fill in the gaps */ 831 op.addr.val = offs; 832 op.data.nbytes = len; 833 op.data.buf.in = buf; 834 835 ret = iop->exec_op(ispi, desc->mem, iop, &op); 836 return ret ? ret : len; 837 } 838 839 static ssize_t intel_spi_dirmap_write(struct spi_mem_dirmap_desc *desc, u64 offs, 840 size_t len, const void *buf) 841 { 842 struct intel_spi *ispi = spi_master_get_devdata(desc->mem->spi->master); 843 const struct intel_spi_mem_op *iop = desc->priv; 844 struct spi_mem_op op = desc->info.op_tmpl; 845 int ret; 846 847 op.addr.val = offs; 848 op.data.nbytes = len; 849 op.data.buf.out = buf; 850 851 ret = iop->exec_op(ispi, desc->mem, iop, &op); 852 return ret ? ret : len; 853 } 854 855 static const struct spi_controller_mem_ops intel_spi_mem_ops = { 856 .supports_op = intel_spi_supports_mem_op, 857 .exec_op = intel_spi_exec_mem_op, 858 .get_name = intel_spi_get_name, 859 .dirmap_create = intel_spi_dirmap_create, 860 .dirmap_read = intel_spi_dirmap_read, 861 .dirmap_write = intel_spi_dirmap_write, 862 }; 863 864 #define INTEL_SPI_OP_ADDR(__nbytes) \ 865 { \ 866 .nbytes = __nbytes, \ 867 } 868 869 #define INTEL_SPI_OP_NO_DATA \ 870 { \ 871 .dir = SPI_MEM_NO_DATA, \ 872 } 873 874 #define INTEL_SPI_OP_DATA_IN(__buswidth) \ 875 { \ 876 .dir = SPI_MEM_DATA_IN, \ 877 .buswidth = __buswidth, \ 878 } 879 880 #define INTEL_SPI_OP_DATA_OUT(__buswidth) \ 881 { \ 882 .dir = SPI_MEM_DATA_OUT, \ 883 .buswidth = __buswidth, \ 884 } 885 886 #define INTEL_SPI_MEM_OP(__cmd, __addr, __data, __exec_op) \ 887 { \ 888 .mem_op = { \ 889 .cmd = __cmd, \ 890 .addr = __addr, \ 891 .data = __data, \ 892 }, \ 893 .exec_op = __exec_op, \ 894 } 895 896 #define INTEL_SPI_MEM_OP_REPL(__cmd, __addr, __data, __exec_op, __repl) \ 897 { \ 898 .mem_op = { \ 899 .cmd = __cmd, \ 900 .addr = __addr, \ 901 .data = __data, \ 902 }, \ 903 .exec_op = __exec_op, \ 904 .replacement_op = __repl, \ 905 } 906 907 /* 908 * The controller handles pretty much everything internally based on the 909 * SFDP data but we want to make sure we only support the operations 910 * actually possible. Only check buswidth and transfer direction, the 911 * core validates data. 912 */ 913 #define INTEL_SPI_GENERIC_OPS \ 914 /* Status register operations */ \ 915 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1), \ 916 SPI_MEM_OP_NO_ADDR, \ 917 INTEL_SPI_OP_DATA_IN(1), \ 918 intel_spi_read_reg), \ 919 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 1), \ 920 SPI_MEM_OP_NO_ADDR, \ 921 INTEL_SPI_OP_DATA_IN(1), \ 922 intel_spi_read_reg), \ 923 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 1), \ 924 SPI_MEM_OP_NO_ADDR, \ 925 INTEL_SPI_OP_DATA_OUT(1), \ 926 intel_spi_write_reg), \ 927 /* Normal read */ \ 928 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \ 929 INTEL_SPI_OP_ADDR(3), \ 930 INTEL_SPI_OP_DATA_IN(1), \ 931 intel_spi_read), \ 932 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \ 933 INTEL_SPI_OP_ADDR(3), \ 934 INTEL_SPI_OP_DATA_IN(2), \ 935 intel_spi_read), \ 936 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \ 937 INTEL_SPI_OP_ADDR(3), \ 938 INTEL_SPI_OP_DATA_IN(4), \ 939 intel_spi_read), \ 940 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \ 941 INTEL_SPI_OP_ADDR(4), \ 942 INTEL_SPI_OP_DATA_IN(1), \ 943 intel_spi_read), \ 944 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \ 945 INTEL_SPI_OP_ADDR(4), \ 946 INTEL_SPI_OP_DATA_IN(2), \ 947 intel_spi_read), \ 948 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \ 949 INTEL_SPI_OP_ADDR(4), \ 950 INTEL_SPI_OP_DATA_IN(4), \ 951 intel_spi_read), \ 952 /* Fast read */ \ 953 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST, 1), \ 954 INTEL_SPI_OP_ADDR(3), \ 955 INTEL_SPI_OP_DATA_IN(1), \ 956 intel_spi_read), \ 957 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST, 1), \ 958 INTEL_SPI_OP_ADDR(3), \ 959 INTEL_SPI_OP_DATA_IN(2), \ 960 intel_spi_read), \ 961 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST, 1), \ 962 INTEL_SPI_OP_ADDR(3), \ 963 INTEL_SPI_OP_DATA_IN(4), \ 964 intel_spi_read), \ 965 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST, 1), \ 966 INTEL_SPI_OP_ADDR(4), \ 967 INTEL_SPI_OP_DATA_IN(1), \ 968 intel_spi_read), \ 969 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST, 1), \ 970 INTEL_SPI_OP_ADDR(4), \ 971 INTEL_SPI_OP_DATA_IN(2), \ 972 intel_spi_read), \ 973 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST, 1), \ 974 INTEL_SPI_OP_ADDR(4), \ 975 INTEL_SPI_OP_DATA_IN(4), \ 976 intel_spi_read), \ 977 /* Read with 4-byte address opcode */ \ 978 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_4B, 1), \ 979 INTEL_SPI_OP_ADDR(4), \ 980 INTEL_SPI_OP_DATA_IN(1), \ 981 intel_spi_read), \ 982 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_4B, 1), \ 983 INTEL_SPI_OP_ADDR(4), \ 984 INTEL_SPI_OP_DATA_IN(2), \ 985 intel_spi_read), \ 986 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_4B, 1), \ 987 INTEL_SPI_OP_ADDR(4), \ 988 INTEL_SPI_OP_DATA_IN(4), \ 989 intel_spi_read), \ 990 /* Fast read with 4-byte address opcode */ \ 991 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST_4B, 1), \ 992 INTEL_SPI_OP_ADDR(4), \ 993 INTEL_SPI_OP_DATA_IN(1), \ 994 intel_spi_read), \ 995 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST_4B, 1), \ 996 INTEL_SPI_OP_ADDR(4), \ 997 INTEL_SPI_OP_DATA_IN(2), \ 998 intel_spi_read), \ 999 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST_4B, 1), \ 1000 INTEL_SPI_OP_ADDR(4), \ 1001 INTEL_SPI_OP_DATA_IN(4), \ 1002 intel_spi_read), \ 1003 /* Write operations */ \ 1004 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_PP, 1), \ 1005 INTEL_SPI_OP_ADDR(3), \ 1006 INTEL_SPI_OP_DATA_OUT(1), \ 1007 intel_spi_write), \ 1008 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_PP, 1), \ 1009 INTEL_SPI_OP_ADDR(4), \ 1010 INTEL_SPI_OP_DATA_OUT(1), \ 1011 intel_spi_write), \ 1012 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_PP_4B, 1), \ 1013 INTEL_SPI_OP_ADDR(4), \ 1014 INTEL_SPI_OP_DATA_OUT(1), \ 1015 intel_spi_write), \ 1016 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREN, 1), \ 1017 SPI_MEM_OP_NO_ADDR, \ 1018 SPI_MEM_OP_NO_DATA, \ 1019 intel_spi_write_reg), \ 1020 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRDI, 1), \ 1021 SPI_MEM_OP_NO_ADDR, \ 1022 SPI_MEM_OP_NO_DATA, \ 1023 intel_spi_write_reg), \ 1024 /* Erase operations */ \ 1025 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_BE_4K, 1), \ 1026 INTEL_SPI_OP_ADDR(3), \ 1027 SPI_MEM_OP_NO_DATA, \ 1028 intel_spi_erase, \ 1029 HSFSTS_CTL_FCYCLE_ERASE), \ 1030 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_BE_4K, 1), \ 1031 INTEL_SPI_OP_ADDR(4), \ 1032 SPI_MEM_OP_NO_DATA, \ 1033 intel_spi_erase, \ 1034 HSFSTS_CTL_FCYCLE_ERASE), \ 1035 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_BE_4K_4B, 1), \ 1036 INTEL_SPI_OP_ADDR(4), \ 1037 SPI_MEM_OP_NO_DATA, \ 1038 intel_spi_erase, \ 1039 HSFSTS_CTL_FCYCLE_ERASE) \ 1040 1041 static const struct intel_spi_mem_op generic_mem_ops[] = { 1042 INTEL_SPI_GENERIC_OPS, 1043 { }, 1044 }; 1045 1046 static const struct intel_spi_mem_op erase_64k_mem_ops[] = { 1047 INTEL_SPI_GENERIC_OPS, 1048 /* 64k sector erase operations */ 1049 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_SE, 1), 1050 INTEL_SPI_OP_ADDR(3), 1051 SPI_MEM_OP_NO_DATA, 1052 intel_spi_erase, 1053 HSFSTS_CTL_FCYCLE_ERASE_64K), 1054 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_SE, 1), 1055 INTEL_SPI_OP_ADDR(4), 1056 SPI_MEM_OP_NO_DATA, 1057 intel_spi_erase, 1058 HSFSTS_CTL_FCYCLE_ERASE_64K), 1059 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_SE_4B, 1), 1060 INTEL_SPI_OP_ADDR(4), 1061 SPI_MEM_OP_NO_DATA, 1062 intel_spi_erase, 1063 HSFSTS_CTL_FCYCLE_ERASE_64K), 1064 { }, 1065 }; 1066 1067 static int intel_spi_init(struct intel_spi *ispi) 1068 { 1069 u32 opmenu0, opmenu1, lvscc, uvscc, val; 1070 bool erase_64k = false; 1071 int i; 1072 1073 switch (ispi->info->type) { 1074 case INTEL_SPI_BYT: 1075 ispi->sregs = ispi->base + BYT_SSFSTS_CTL; 1076 ispi->pregs = ispi->base + BYT_PR; 1077 ispi->nregions = BYT_FREG_NUM; 1078 ispi->pr_num = BYT_PR_NUM; 1079 ispi->swseq_reg = true; 1080 break; 1081 1082 case INTEL_SPI_LPT: 1083 ispi->sregs = ispi->base + LPT_SSFSTS_CTL; 1084 ispi->pregs = ispi->base + LPT_PR; 1085 ispi->nregions = LPT_FREG_NUM; 1086 ispi->pr_num = LPT_PR_NUM; 1087 ispi->swseq_reg = true; 1088 break; 1089 1090 case INTEL_SPI_BXT: 1091 ispi->sregs = ispi->base + BXT_SSFSTS_CTL; 1092 ispi->pregs = ispi->base + BXT_PR; 1093 ispi->nregions = BXT_FREG_NUM; 1094 ispi->pr_num = BXT_PR_NUM; 1095 erase_64k = true; 1096 break; 1097 1098 case INTEL_SPI_CNL: 1099 ispi->sregs = NULL; 1100 ispi->pregs = ispi->base + CNL_PR; 1101 ispi->nregions = CNL_FREG_NUM; 1102 ispi->pr_num = CNL_PR_NUM; 1103 erase_64k = true; 1104 break; 1105 1106 default: 1107 return -EINVAL; 1108 } 1109 1110 /* Try to disable write protection if user asked to do so */ 1111 if (writeable && !intel_spi_set_writeable(ispi)) { 1112 dev_warn(ispi->dev, "can't disable chip write protection\n"); 1113 writeable = false; 1114 } 1115 1116 /* Disable #SMI generation from HW sequencer */ 1117 val = readl(ispi->base + HSFSTS_CTL); 1118 val &= ~HSFSTS_CTL_FSMIE; 1119 writel(val, ispi->base + HSFSTS_CTL); 1120 1121 /* 1122 * Determine whether erase operation should use HW or SW sequencer. 1123 * 1124 * The HW sequencer has a predefined list of opcodes, with only the 1125 * erase opcode being programmable in LVSCC and UVSCC registers. 1126 * If these registers don't contain a valid erase opcode, erase 1127 * cannot be done using HW sequencer. 1128 */ 1129 lvscc = readl(ispi->base + LVSCC); 1130 uvscc = readl(ispi->base + UVSCC); 1131 if (!(lvscc & ERASE_OPCODE_MASK) || !(uvscc & ERASE_OPCODE_MASK)) 1132 ispi->swseq_erase = true; 1133 /* SPI controller on Intel BXT supports 64K erase opcode */ 1134 if (ispi->info->type == INTEL_SPI_BXT && !ispi->swseq_erase) 1135 if (!(lvscc & ERASE_64K_OPCODE_MASK) || 1136 !(uvscc & ERASE_64K_OPCODE_MASK)) 1137 erase_64k = false; 1138 1139 if (!ispi->sregs && (ispi->swseq_reg || ispi->swseq_erase)) { 1140 dev_err(ispi->dev, "software sequencer not supported, but required\n"); 1141 return -EINVAL; 1142 } 1143 1144 /* 1145 * Some controllers can only do basic operations using hardware 1146 * sequencer. All other operations are supposed to be carried out 1147 * using software sequencer. 1148 */ 1149 if (ispi->swseq_reg) { 1150 /* Disable #SMI generation from SW sequencer */ 1151 val = readl(ispi->sregs + SSFSTS_CTL); 1152 val &= ~SSFSTS_CTL_FSMIE; 1153 writel(val, ispi->sregs + SSFSTS_CTL); 1154 } 1155 1156 /* Check controller's lock status */ 1157 val = readl(ispi->base + HSFSTS_CTL); 1158 ispi->locked = !!(val & HSFSTS_CTL_FLOCKDN); 1159 1160 if (ispi->locked && ispi->sregs) { 1161 /* 1162 * BIOS programs allowed opcodes and then locks down the 1163 * register. So read back what opcodes it decided to support. 1164 * That's the set we are going to support as well. 1165 */ 1166 opmenu0 = readl(ispi->sregs + OPMENU0); 1167 opmenu1 = readl(ispi->sregs + OPMENU1); 1168 1169 if (opmenu0 && opmenu1) { 1170 for (i = 0; i < ARRAY_SIZE(ispi->opcodes) / 2; i++) { 1171 ispi->opcodes[i] = opmenu0 >> i * 8; 1172 ispi->opcodes[i + 4] = opmenu1 >> i * 8; 1173 } 1174 } 1175 } 1176 1177 if (erase_64k) { 1178 dev_dbg(ispi->dev, "Using erase_64k memory operations"); 1179 ispi->mem_ops = erase_64k_mem_ops; 1180 } else { 1181 dev_dbg(ispi->dev, "Using generic memory operations"); 1182 ispi->mem_ops = generic_mem_ops; 1183 } 1184 1185 intel_spi_dump_regs(ispi); 1186 return 0; 1187 } 1188 1189 static bool intel_spi_is_protected(const struct intel_spi *ispi, 1190 unsigned int base, unsigned int limit) 1191 { 1192 int i; 1193 1194 for (i = 0; i < ispi->pr_num; i++) { 1195 u32 pr_base, pr_limit, pr_value; 1196 1197 pr_value = readl(ispi->pregs + PR(i)); 1198 if (!(pr_value & (PR_WPE | PR_RPE))) 1199 continue; 1200 1201 pr_limit = (pr_value & PR_LIMIT_MASK) >> PR_LIMIT_SHIFT; 1202 pr_base = pr_value & PR_BASE_MASK; 1203 1204 if (pr_base >= base && pr_limit <= limit) 1205 return true; 1206 } 1207 1208 return false; 1209 } 1210 1211 /* 1212 * There will be a single partition holding all enabled flash regions. We 1213 * call this "BIOS". 1214 */ 1215 static void intel_spi_fill_partition(struct intel_spi *ispi, 1216 struct mtd_partition *part) 1217 { 1218 u64 end; 1219 int i; 1220 1221 memset(part, 0, sizeof(*part)); 1222 1223 /* Start from the mandatory descriptor region */ 1224 part->size = 4096; 1225 part->name = "BIOS"; 1226 1227 /* 1228 * Now try to find where this partition ends based on the flash 1229 * region registers. 1230 */ 1231 for (i = 1; i < ispi->nregions; i++) { 1232 u32 region, base, limit; 1233 1234 region = readl(ispi->base + FREG(i)); 1235 base = region & FREG_BASE_MASK; 1236 limit = (region & FREG_LIMIT_MASK) >> FREG_LIMIT_SHIFT; 1237 1238 if (base >= limit || limit == 0) 1239 continue; 1240 1241 /* 1242 * If any of the regions have protection bits set, make the 1243 * whole partition read-only to be on the safe side. 1244 * 1245 * Also if the user did not ask the chip to be writeable 1246 * mask the bit too. 1247 */ 1248 if (!writeable || intel_spi_is_protected(ispi, base, limit)) 1249 part->mask_flags |= MTD_WRITEABLE; 1250 1251 end = (limit << 12) + 4096; 1252 if (end > part->size) 1253 part->size = end; 1254 } 1255 } 1256 1257 static int intel_spi_read_desc(struct intel_spi *ispi) 1258 { 1259 struct spi_mem_op op = 1260 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 0), 1261 SPI_MEM_OP_ADDR(3, 0, 0), 1262 SPI_MEM_OP_NO_DUMMY, 1263 SPI_MEM_OP_DATA_IN(0, NULL, 0)); 1264 u32 buf[2], nc, fcba, flcomp; 1265 ssize_t ret; 1266 1267 op.addr.val = 0x10; 1268 op.data.buf.in = buf; 1269 op.data.nbytes = sizeof(buf); 1270 1271 ret = intel_spi_read(ispi, NULL, NULL, &op); 1272 if (ret) { 1273 dev_warn(ispi->dev, "failed to read descriptor\n"); 1274 return ret; 1275 } 1276 1277 dev_dbg(ispi->dev, "FLVALSIG=0x%08x\n", buf[0]); 1278 dev_dbg(ispi->dev, "FLMAP0=0x%08x\n", buf[1]); 1279 1280 if (buf[0] != FLVALSIG_MAGIC) { 1281 dev_warn(ispi->dev, "descriptor signature not valid\n"); 1282 return -ENODEV; 1283 } 1284 1285 fcba = (buf[1] & FLMAP0_FCBA_MASK) << 4; 1286 dev_dbg(ispi->dev, "FCBA=%#x\n", fcba); 1287 1288 op.addr.val = fcba; 1289 op.data.buf.in = &flcomp; 1290 op.data.nbytes = sizeof(flcomp); 1291 1292 ret = intel_spi_read(ispi, NULL, NULL, &op); 1293 if (ret) { 1294 dev_warn(ispi->dev, "failed to read FLCOMP\n"); 1295 return -ENODEV; 1296 } 1297 1298 dev_dbg(ispi->dev, "FLCOMP=0x%08x\n", flcomp); 1299 1300 switch (flcomp & FLCOMP_C0DEN_MASK) { 1301 case FLCOMP_C0DEN_512K: 1302 ispi->chip0_size = SZ_512K; 1303 break; 1304 case FLCOMP_C0DEN_1M: 1305 ispi->chip0_size = SZ_1M; 1306 break; 1307 case FLCOMP_C0DEN_2M: 1308 ispi->chip0_size = SZ_2M; 1309 break; 1310 case FLCOMP_C0DEN_4M: 1311 ispi->chip0_size = SZ_4M; 1312 break; 1313 case FLCOMP_C0DEN_8M: 1314 ispi->chip0_size = SZ_8M; 1315 break; 1316 case FLCOMP_C0DEN_16M: 1317 ispi->chip0_size = SZ_16M; 1318 break; 1319 case FLCOMP_C0DEN_32M: 1320 ispi->chip0_size = SZ_32M; 1321 break; 1322 case FLCOMP_C0DEN_64M: 1323 ispi->chip0_size = SZ_64M; 1324 break; 1325 default: 1326 return -EINVAL; 1327 } 1328 1329 dev_dbg(ispi->dev, "chip0 size %zd KB\n", ispi->chip0_size / SZ_1K); 1330 1331 nc = (buf[1] & FLMAP0_NC_MASK) >> FLMAP0_NC_SHIFT; 1332 if (!nc) 1333 ispi->master->num_chipselect = 1; 1334 else if (nc == 1) 1335 ispi->master->num_chipselect = 2; 1336 else 1337 return -EINVAL; 1338 1339 dev_dbg(ispi->dev, "%u flash components found\n", 1340 ispi->master->num_chipselect); 1341 return 0; 1342 } 1343 1344 static int intel_spi_populate_chip(struct intel_spi *ispi) 1345 { 1346 struct flash_platform_data *pdata; 1347 struct spi_board_info chip; 1348 int ret; 1349 1350 pdata = devm_kzalloc(ispi->dev, sizeof(*pdata), GFP_KERNEL); 1351 if (!pdata) 1352 return -ENOMEM; 1353 1354 pdata->nr_parts = 1; 1355 pdata->parts = devm_kcalloc(ispi->dev, pdata->nr_parts, 1356 sizeof(*pdata->parts), GFP_KERNEL); 1357 if (!pdata->parts) 1358 return -ENOMEM; 1359 1360 intel_spi_fill_partition(ispi, pdata->parts); 1361 1362 memset(&chip, 0, sizeof(chip)); 1363 snprintf(chip.modalias, 8, "spi-nor"); 1364 chip.platform_data = pdata; 1365 1366 if (!spi_new_device(ispi->master, &chip)) 1367 return -ENODEV; 1368 1369 /* Add the second chip if present */ 1370 if (ispi->master->num_chipselect < 2) 1371 return 0; 1372 1373 ret = intel_spi_read_desc(ispi); 1374 if (ret) 1375 return ret; 1376 1377 chip.platform_data = NULL; 1378 chip.chip_select = 1; 1379 1380 if (!spi_new_device(ispi->master, &chip)) 1381 return -ENODEV; 1382 return 0; 1383 } 1384 1385 /** 1386 * intel_spi_probe() - Probe the Intel SPI flash controller 1387 * @dev: Pointer to the parent device 1388 * @mem: MMIO resource 1389 * @info: Platform specific information 1390 * 1391 * Probes Intel SPI flash controller and creates the flash chip device. 1392 * Returns %0 on success and negative errno in case of failure. 1393 */ 1394 int intel_spi_probe(struct device *dev, struct resource *mem, 1395 const struct intel_spi_boardinfo *info) 1396 { 1397 struct spi_controller *master; 1398 struct intel_spi *ispi; 1399 int ret; 1400 1401 master = devm_spi_alloc_master(dev, sizeof(*ispi)); 1402 if (!master) 1403 return -ENOMEM; 1404 1405 master->mem_ops = &intel_spi_mem_ops; 1406 1407 ispi = spi_master_get_devdata(master); 1408 1409 ispi->base = devm_ioremap_resource(dev, mem); 1410 if (IS_ERR(ispi->base)) 1411 return PTR_ERR(ispi->base); 1412 1413 ispi->dev = dev; 1414 ispi->master = master; 1415 ispi->info = info; 1416 1417 ret = intel_spi_init(ispi); 1418 if (ret) 1419 return ret; 1420 1421 ret = devm_spi_register_master(dev, master); 1422 if (ret) 1423 return ret; 1424 1425 return intel_spi_populate_chip(ispi); 1426 } 1427 EXPORT_SYMBOL_GPL(intel_spi_probe); 1428 1429 MODULE_DESCRIPTION("Intel PCH/PCU SPI flash core driver"); 1430 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 1431 MODULE_LICENSE("GPL v2"); 1432