1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Intel PCH/PCU SPI flash driver. 4 * 5 * Copyright (C) 2016 - 2022, Intel Corporation 6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com> 7 */ 8 9 #include <linux/iopoll.h> 10 #include <linux/module.h> 11 12 #include <linux/mtd/partitions.h> 13 #include <linux/mtd/spi-nor.h> 14 15 #include <linux/spi/flash.h> 16 #include <linux/spi/spi.h> 17 #include <linux/spi/spi-mem.h> 18 19 #include "spi-intel.h" 20 21 /* Offsets are from @ispi->base */ 22 #define BFPREG 0x00 23 24 #define HSFSTS_CTL 0x04 25 #define HSFSTS_CTL_FSMIE BIT(31) 26 #define HSFSTS_CTL_FDBC_SHIFT 24 27 #define HSFSTS_CTL_FDBC_MASK (0x3f << HSFSTS_CTL_FDBC_SHIFT) 28 29 #define HSFSTS_CTL_FCYCLE_SHIFT 17 30 #define HSFSTS_CTL_FCYCLE_MASK (0x0f << HSFSTS_CTL_FCYCLE_SHIFT) 31 /* HW sequencer opcodes */ 32 #define HSFSTS_CTL_FCYCLE_READ (0x00 << HSFSTS_CTL_FCYCLE_SHIFT) 33 #define HSFSTS_CTL_FCYCLE_WRITE (0x02 << HSFSTS_CTL_FCYCLE_SHIFT) 34 #define HSFSTS_CTL_FCYCLE_ERASE (0x03 << HSFSTS_CTL_FCYCLE_SHIFT) 35 #define HSFSTS_CTL_FCYCLE_ERASE_64K (0x04 << HSFSTS_CTL_FCYCLE_SHIFT) 36 #define HSFSTS_CTL_FCYCLE_RDID (0x06 << HSFSTS_CTL_FCYCLE_SHIFT) 37 #define HSFSTS_CTL_FCYCLE_WRSR (0x07 << HSFSTS_CTL_FCYCLE_SHIFT) 38 #define HSFSTS_CTL_FCYCLE_RDSR (0x08 << HSFSTS_CTL_FCYCLE_SHIFT) 39 40 #define HSFSTS_CTL_FGO BIT(16) 41 #define HSFSTS_CTL_FLOCKDN BIT(15) 42 #define HSFSTS_CTL_FDV BIT(14) 43 #define HSFSTS_CTL_SCIP BIT(5) 44 #define HSFSTS_CTL_AEL BIT(2) 45 #define HSFSTS_CTL_FCERR BIT(1) 46 #define HSFSTS_CTL_FDONE BIT(0) 47 48 #define FADDR 0x08 49 #define DLOCK 0x0c 50 #define FDATA(n) (0x10 + ((n) * 4)) 51 52 #define FRACC 0x50 53 54 #define FREG(n) (0x54 + ((n) * 4)) 55 #define FREG_BASE_MASK 0x3fff 56 #define FREG_LIMIT_SHIFT 16 57 #define FREG_LIMIT_MASK (0x03fff << FREG_LIMIT_SHIFT) 58 59 /* Offset is from @ispi->pregs */ 60 #define PR(n) ((n) * 4) 61 #define PR_WPE BIT(31) 62 #define PR_LIMIT_SHIFT 16 63 #define PR_LIMIT_MASK (0x3fff << PR_LIMIT_SHIFT) 64 #define PR_RPE BIT(15) 65 #define PR_BASE_MASK 0x3fff 66 67 /* Offsets are from @ispi->sregs */ 68 #define SSFSTS_CTL 0x00 69 #define SSFSTS_CTL_FSMIE BIT(23) 70 #define SSFSTS_CTL_DS BIT(22) 71 #define SSFSTS_CTL_DBC_SHIFT 16 72 #define SSFSTS_CTL_SPOP BIT(11) 73 #define SSFSTS_CTL_ACS BIT(10) 74 #define SSFSTS_CTL_SCGO BIT(9) 75 #define SSFSTS_CTL_COP_SHIFT 12 76 #define SSFSTS_CTL_FRS BIT(7) 77 #define SSFSTS_CTL_DOFRS BIT(6) 78 #define SSFSTS_CTL_AEL BIT(4) 79 #define SSFSTS_CTL_FCERR BIT(3) 80 #define SSFSTS_CTL_FDONE BIT(2) 81 #define SSFSTS_CTL_SCIP BIT(0) 82 83 #define PREOP_OPTYPE 0x04 84 #define OPMENU0 0x08 85 #define OPMENU1 0x0c 86 87 #define OPTYPE_READ_NO_ADDR 0 88 #define OPTYPE_WRITE_NO_ADDR 1 89 #define OPTYPE_READ_WITH_ADDR 2 90 #define OPTYPE_WRITE_WITH_ADDR 3 91 92 /* CPU specifics */ 93 #define BYT_PR 0x74 94 #define BYT_SSFSTS_CTL 0x90 95 #define BYT_FREG_NUM 5 96 #define BYT_PR_NUM 5 97 98 #define LPT_PR 0x74 99 #define LPT_SSFSTS_CTL 0x90 100 #define LPT_FREG_NUM 5 101 #define LPT_PR_NUM 5 102 103 #define BXT_PR 0x84 104 #define BXT_SSFSTS_CTL 0xa0 105 #define BXT_FREG_NUM 12 106 #define BXT_PR_NUM 6 107 108 #define CNL_PR 0x84 109 #define CNL_FREG_NUM 6 110 #define CNL_PR_NUM 5 111 112 #define LVSCC 0xc4 113 #define UVSCC 0xc8 114 #define ERASE_OPCODE_SHIFT 8 115 #define ERASE_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT) 116 #define ERASE_64K_OPCODE_SHIFT 16 117 #define ERASE_64K_OPCODE_MASK (0xff << ERASE_64K_OPCODE_SHIFT) 118 119 /* Flash descriptor fields */ 120 #define FLVALSIG_MAGIC 0x0ff0a55a 121 #define FLMAP0_NC_MASK GENMASK(9, 8) 122 #define FLMAP0_NC_SHIFT 8 123 #define FLMAP0_FCBA_MASK GENMASK(7, 0) 124 125 #define FLCOMP_C0DEN_MASK GENMASK(3, 0) 126 #define FLCOMP_C0DEN_512K 0x00 127 #define FLCOMP_C0DEN_1M 0x01 128 #define FLCOMP_C0DEN_2M 0x02 129 #define FLCOMP_C0DEN_4M 0x03 130 #define FLCOMP_C0DEN_8M 0x04 131 #define FLCOMP_C0DEN_16M 0x05 132 #define FLCOMP_C0DEN_32M 0x06 133 #define FLCOMP_C0DEN_64M 0x07 134 135 #define INTEL_SPI_TIMEOUT 5000 /* ms */ 136 #define INTEL_SPI_FIFO_SZ 64 137 138 /** 139 * struct intel_spi - Driver private data 140 * @dev: Device pointer 141 * @info: Pointer to board specific info 142 * @base: Beginning of MMIO space 143 * @pregs: Start of protection registers 144 * @sregs: Start of software sequencer registers 145 * @master: Pointer to the SPI controller structure 146 * @nregions: Maximum number of regions 147 * @pr_num: Maximum number of protected range registers 148 * @chip0_size: Size of the first flash chip in bytes 149 * @locked: Is SPI setting locked 150 * @swseq_reg: Use SW sequencer in register reads/writes 151 * @swseq_erase: Use SW sequencer in erase operation 152 * @atomic_preopcode: Holds preopcode when atomic sequence is requested 153 * @opcodes: Opcodes which are supported. This are programmed by BIOS 154 * before it locks down the controller. 155 * @mem_ops: Pointer to SPI MEM ops supported by the controller 156 */ 157 struct intel_spi { 158 struct device *dev; 159 const struct intel_spi_boardinfo *info; 160 void __iomem *base; 161 void __iomem *pregs; 162 void __iomem *sregs; 163 struct spi_controller *master; 164 size_t nregions; 165 size_t pr_num; 166 size_t chip0_size; 167 bool locked; 168 bool swseq_reg; 169 bool swseq_erase; 170 u8 atomic_preopcode; 171 u8 opcodes[8]; 172 const struct intel_spi_mem_op *mem_ops; 173 }; 174 175 struct intel_spi_mem_op { 176 struct spi_mem_op mem_op; 177 u32 replacement_op; 178 int (*exec_op)(struct intel_spi *ispi, 179 const struct spi_mem *mem, 180 const struct intel_spi_mem_op *iop, 181 const struct spi_mem_op *op); 182 }; 183 184 static bool writeable; 185 module_param(writeable, bool, 0); 186 MODULE_PARM_DESC(writeable, "Enable write access to SPI flash chip (default=0)"); 187 188 static void intel_spi_dump_regs(struct intel_spi *ispi) 189 { 190 u32 value; 191 int i; 192 193 dev_dbg(ispi->dev, "BFPREG=0x%08x\n", readl(ispi->base + BFPREG)); 194 195 value = readl(ispi->base + HSFSTS_CTL); 196 dev_dbg(ispi->dev, "HSFSTS_CTL=0x%08x\n", value); 197 if (value & HSFSTS_CTL_FLOCKDN) 198 dev_dbg(ispi->dev, "-> Locked\n"); 199 200 dev_dbg(ispi->dev, "FADDR=0x%08x\n", readl(ispi->base + FADDR)); 201 dev_dbg(ispi->dev, "DLOCK=0x%08x\n", readl(ispi->base + DLOCK)); 202 203 for (i = 0; i < 16; i++) 204 dev_dbg(ispi->dev, "FDATA(%d)=0x%08x\n", 205 i, readl(ispi->base + FDATA(i))); 206 207 dev_dbg(ispi->dev, "FRACC=0x%08x\n", readl(ispi->base + FRACC)); 208 209 for (i = 0; i < ispi->nregions; i++) 210 dev_dbg(ispi->dev, "FREG(%d)=0x%08x\n", i, 211 readl(ispi->base + FREG(i))); 212 for (i = 0; i < ispi->pr_num; i++) 213 dev_dbg(ispi->dev, "PR(%d)=0x%08x\n", i, 214 readl(ispi->pregs + PR(i))); 215 216 if (ispi->sregs) { 217 value = readl(ispi->sregs + SSFSTS_CTL); 218 dev_dbg(ispi->dev, "SSFSTS_CTL=0x%08x\n", value); 219 dev_dbg(ispi->dev, "PREOP_OPTYPE=0x%08x\n", 220 readl(ispi->sregs + PREOP_OPTYPE)); 221 dev_dbg(ispi->dev, "OPMENU0=0x%08x\n", 222 readl(ispi->sregs + OPMENU0)); 223 dev_dbg(ispi->dev, "OPMENU1=0x%08x\n", 224 readl(ispi->sregs + OPMENU1)); 225 } 226 227 dev_dbg(ispi->dev, "LVSCC=0x%08x\n", readl(ispi->base + LVSCC)); 228 dev_dbg(ispi->dev, "UVSCC=0x%08x\n", readl(ispi->base + UVSCC)); 229 230 dev_dbg(ispi->dev, "Protected regions:\n"); 231 for (i = 0; i < ispi->pr_num; i++) { 232 u32 base, limit; 233 234 value = readl(ispi->pregs + PR(i)); 235 if (!(value & (PR_WPE | PR_RPE))) 236 continue; 237 238 limit = (value & PR_LIMIT_MASK) >> PR_LIMIT_SHIFT; 239 base = value & PR_BASE_MASK; 240 241 dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x [%c%c]\n", 242 i, base << 12, (limit << 12) | 0xfff, 243 value & PR_WPE ? 'W' : '.', value & PR_RPE ? 'R' : '.'); 244 } 245 246 dev_dbg(ispi->dev, "Flash regions:\n"); 247 for (i = 0; i < ispi->nregions; i++) { 248 u32 region, base, limit; 249 250 region = readl(ispi->base + FREG(i)); 251 base = region & FREG_BASE_MASK; 252 limit = (region & FREG_LIMIT_MASK) >> FREG_LIMIT_SHIFT; 253 254 if (base >= limit || (i > 0 && limit == 0)) 255 dev_dbg(ispi->dev, " %02d disabled\n", i); 256 else 257 dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x\n", 258 i, base << 12, (limit << 12) | 0xfff); 259 } 260 261 dev_dbg(ispi->dev, "Using %cW sequencer for register access\n", 262 ispi->swseq_reg ? 'S' : 'H'); 263 dev_dbg(ispi->dev, "Using %cW sequencer for erase operation\n", 264 ispi->swseq_erase ? 'S' : 'H'); 265 } 266 267 /* Reads max INTEL_SPI_FIFO_SZ bytes from the device fifo */ 268 static int intel_spi_read_block(struct intel_spi *ispi, void *buf, size_t size) 269 { 270 size_t bytes; 271 int i = 0; 272 273 if (size > INTEL_SPI_FIFO_SZ) 274 return -EINVAL; 275 276 while (size > 0) { 277 bytes = min_t(size_t, size, 4); 278 memcpy_fromio(buf, ispi->base + FDATA(i), bytes); 279 size -= bytes; 280 buf += bytes; 281 i++; 282 } 283 284 return 0; 285 } 286 287 /* Writes max INTEL_SPI_FIFO_SZ bytes to the device fifo */ 288 static int intel_spi_write_block(struct intel_spi *ispi, const void *buf, 289 size_t size) 290 { 291 size_t bytes; 292 int i = 0; 293 294 if (size > INTEL_SPI_FIFO_SZ) 295 return -EINVAL; 296 297 while (size > 0) { 298 bytes = min_t(size_t, size, 4); 299 memcpy_toio(ispi->base + FDATA(i), buf, bytes); 300 size -= bytes; 301 buf += bytes; 302 i++; 303 } 304 305 return 0; 306 } 307 308 static int intel_spi_wait_hw_busy(struct intel_spi *ispi) 309 { 310 u32 val; 311 312 return readl_poll_timeout(ispi->base + HSFSTS_CTL, val, 313 !(val & HSFSTS_CTL_SCIP), 0, 314 INTEL_SPI_TIMEOUT * 1000); 315 } 316 317 static int intel_spi_wait_sw_busy(struct intel_spi *ispi) 318 { 319 u32 val; 320 321 return readl_poll_timeout(ispi->sregs + SSFSTS_CTL, val, 322 !(val & SSFSTS_CTL_SCIP), 0, 323 INTEL_SPI_TIMEOUT * 1000); 324 } 325 326 static bool intel_spi_set_writeable(struct intel_spi *ispi) 327 { 328 if (!ispi->info->set_writeable) 329 return false; 330 331 return ispi->info->set_writeable(ispi->base, ispi->info->data); 332 } 333 334 static int intel_spi_opcode_index(struct intel_spi *ispi, u8 opcode, int optype) 335 { 336 int i; 337 int preop; 338 339 if (ispi->locked) { 340 for (i = 0; i < ARRAY_SIZE(ispi->opcodes); i++) 341 if (ispi->opcodes[i] == opcode) 342 return i; 343 344 return -EINVAL; 345 } 346 347 /* The lock is off, so just use index 0 */ 348 writel(opcode, ispi->sregs + OPMENU0); 349 preop = readw(ispi->sregs + PREOP_OPTYPE); 350 writel(optype << 16 | preop, ispi->sregs + PREOP_OPTYPE); 351 352 return 0; 353 } 354 355 static int intel_spi_hw_cycle(struct intel_spi *ispi, 356 const struct intel_spi_mem_op *iop, size_t len) 357 { 358 u32 val, status; 359 int ret; 360 361 if (!iop->replacement_op) 362 return -EINVAL; 363 364 val = readl(ispi->base + HSFSTS_CTL); 365 val &= ~(HSFSTS_CTL_FCYCLE_MASK | HSFSTS_CTL_FDBC_MASK); 366 val |= (len - 1) << HSFSTS_CTL_FDBC_SHIFT; 367 val |= HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE; 368 val |= HSFSTS_CTL_FGO; 369 val |= iop->replacement_op; 370 writel(val, ispi->base + HSFSTS_CTL); 371 372 ret = intel_spi_wait_hw_busy(ispi); 373 if (ret) 374 return ret; 375 376 status = readl(ispi->base + HSFSTS_CTL); 377 if (status & HSFSTS_CTL_FCERR) 378 return -EIO; 379 else if (status & HSFSTS_CTL_AEL) 380 return -EACCES; 381 382 return 0; 383 } 384 385 static int intel_spi_sw_cycle(struct intel_spi *ispi, u8 opcode, size_t len, 386 int optype) 387 { 388 u32 val = 0, status; 389 u8 atomic_preopcode; 390 int ret; 391 392 ret = intel_spi_opcode_index(ispi, opcode, optype); 393 if (ret < 0) 394 return ret; 395 396 /* 397 * Always clear it after each SW sequencer operation regardless 398 * of whether it is successful or not. 399 */ 400 atomic_preopcode = ispi->atomic_preopcode; 401 ispi->atomic_preopcode = 0; 402 403 /* Only mark 'Data Cycle' bit when there is data to be transferred */ 404 if (len > 0) 405 val = ((len - 1) << SSFSTS_CTL_DBC_SHIFT) | SSFSTS_CTL_DS; 406 val |= ret << SSFSTS_CTL_COP_SHIFT; 407 val |= SSFSTS_CTL_FCERR | SSFSTS_CTL_FDONE; 408 val |= SSFSTS_CTL_SCGO; 409 if (atomic_preopcode) { 410 u16 preop; 411 412 switch (optype) { 413 case OPTYPE_WRITE_NO_ADDR: 414 case OPTYPE_WRITE_WITH_ADDR: 415 /* Pick matching preopcode for the atomic sequence */ 416 preop = readw(ispi->sregs + PREOP_OPTYPE); 417 if ((preop & 0xff) == atomic_preopcode) 418 ; /* Do nothing */ 419 else if ((preop >> 8) == atomic_preopcode) 420 val |= SSFSTS_CTL_SPOP; 421 else 422 return -EINVAL; 423 424 /* Enable atomic sequence */ 425 val |= SSFSTS_CTL_ACS; 426 break; 427 428 default: 429 return -EINVAL; 430 } 431 } 432 writel(val, ispi->sregs + SSFSTS_CTL); 433 434 ret = intel_spi_wait_sw_busy(ispi); 435 if (ret) 436 return ret; 437 438 status = readl(ispi->sregs + SSFSTS_CTL); 439 if (status & SSFSTS_CTL_FCERR) 440 return -EIO; 441 else if (status & SSFSTS_CTL_AEL) 442 return -EACCES; 443 444 return 0; 445 } 446 447 static u32 intel_spi_chip_addr(const struct intel_spi *ispi, 448 const struct spi_mem *mem) 449 { 450 /* Pick up the correct start address */ 451 if (!mem) 452 return 0; 453 return mem->spi->chip_select == 1 ? ispi->chip0_size : 0; 454 } 455 456 static int intel_spi_read_reg(struct intel_spi *ispi, const struct spi_mem *mem, 457 const struct intel_spi_mem_op *iop, 458 const struct spi_mem_op *op) 459 { 460 u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val; 461 size_t nbytes = op->data.nbytes; 462 u8 opcode = op->cmd.opcode; 463 int ret; 464 465 writel(addr, ispi->base + FADDR); 466 467 if (ispi->swseq_reg) 468 ret = intel_spi_sw_cycle(ispi, opcode, nbytes, 469 OPTYPE_READ_NO_ADDR); 470 else 471 ret = intel_spi_hw_cycle(ispi, iop, nbytes); 472 473 if (ret) 474 return ret; 475 476 return intel_spi_read_block(ispi, op->data.buf.in, nbytes); 477 } 478 479 static int intel_spi_write_reg(struct intel_spi *ispi, const struct spi_mem *mem, 480 const struct intel_spi_mem_op *iop, 481 const struct spi_mem_op *op) 482 { 483 u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val; 484 size_t nbytes = op->data.nbytes; 485 u8 opcode = op->cmd.opcode; 486 int ret; 487 488 /* 489 * This is handled with atomic operation and preop code in Intel 490 * controller so we only verify that it is available. If the 491 * controller is not locked, program the opcode to the PREOP 492 * register for later use. 493 * 494 * When hardware sequencer is used there is no need to program 495 * any opcodes (it handles them automatically as part of a command). 496 */ 497 if (opcode == SPINOR_OP_WREN) { 498 u16 preop; 499 500 if (!ispi->swseq_reg) 501 return 0; 502 503 preop = readw(ispi->sregs + PREOP_OPTYPE); 504 if ((preop & 0xff) != opcode && (preop >> 8) != opcode) { 505 if (ispi->locked) 506 return -EINVAL; 507 writel(opcode, ispi->sregs + PREOP_OPTYPE); 508 } 509 510 /* 511 * This enables atomic sequence on next SW sycle. Will 512 * be cleared after next operation. 513 */ 514 ispi->atomic_preopcode = opcode; 515 return 0; 516 } 517 518 /* 519 * We hope that HW sequencer will do the right thing automatically and 520 * with the SW sequencer we cannot use preopcode anyway, so just ignore 521 * the Write Disable operation and pretend it was completed 522 * successfully. 523 */ 524 if (opcode == SPINOR_OP_WRDI) 525 return 0; 526 527 writel(addr, ispi->base + FADDR); 528 529 /* Write the value beforehand */ 530 ret = intel_spi_write_block(ispi, op->data.buf.out, nbytes); 531 if (ret) 532 return ret; 533 534 if (ispi->swseq_reg) 535 return intel_spi_sw_cycle(ispi, opcode, nbytes, 536 OPTYPE_WRITE_NO_ADDR); 537 return intel_spi_hw_cycle(ispi, iop, nbytes); 538 } 539 540 static int intel_spi_read(struct intel_spi *ispi, const struct spi_mem *mem, 541 const struct intel_spi_mem_op *iop, 542 const struct spi_mem_op *op) 543 { 544 u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val; 545 size_t block_size, nbytes = op->data.nbytes; 546 void *read_buf = op->data.buf.in; 547 u32 val, status; 548 int ret; 549 550 /* 551 * Atomic sequence is not expected with HW sequencer reads. Make 552 * sure it is cleared regardless. 553 */ 554 if (WARN_ON_ONCE(ispi->atomic_preopcode)) 555 ispi->atomic_preopcode = 0; 556 557 while (nbytes > 0) { 558 block_size = min_t(size_t, nbytes, INTEL_SPI_FIFO_SZ); 559 560 /* Read cannot cross 4K boundary */ 561 block_size = min_t(loff_t, addr + block_size, 562 round_up(addr + 1, SZ_4K)) - addr; 563 564 writel(addr, ispi->base + FADDR); 565 566 val = readl(ispi->base + HSFSTS_CTL); 567 val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK); 568 val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE; 569 val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT; 570 val |= HSFSTS_CTL_FCYCLE_READ; 571 val |= HSFSTS_CTL_FGO; 572 writel(val, ispi->base + HSFSTS_CTL); 573 574 ret = intel_spi_wait_hw_busy(ispi); 575 if (ret) 576 return ret; 577 578 status = readl(ispi->base + HSFSTS_CTL); 579 if (status & HSFSTS_CTL_FCERR) 580 ret = -EIO; 581 else if (status & HSFSTS_CTL_AEL) 582 ret = -EACCES; 583 584 if (ret < 0) { 585 dev_err(ispi->dev, "read error: %x: %#x\n", addr, status); 586 return ret; 587 } 588 589 ret = intel_spi_read_block(ispi, read_buf, block_size); 590 if (ret) 591 return ret; 592 593 nbytes -= block_size; 594 addr += block_size; 595 read_buf += block_size; 596 } 597 598 return 0; 599 } 600 601 static int intel_spi_write(struct intel_spi *ispi, const struct spi_mem *mem, 602 const struct intel_spi_mem_op *iop, 603 const struct spi_mem_op *op) 604 { 605 u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val; 606 size_t block_size, nbytes = op->data.nbytes; 607 const void *write_buf = op->data.buf.out; 608 u32 val, status; 609 int ret; 610 611 /* Not needed with HW sequencer write, make sure it is cleared */ 612 ispi->atomic_preopcode = 0; 613 614 while (nbytes > 0) { 615 block_size = min_t(size_t, nbytes, INTEL_SPI_FIFO_SZ); 616 617 /* Write cannot cross 4K boundary */ 618 block_size = min_t(loff_t, addr + block_size, 619 round_up(addr + 1, SZ_4K)) - addr; 620 621 writel(addr, ispi->base + FADDR); 622 623 val = readl(ispi->base + HSFSTS_CTL); 624 val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK); 625 val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE; 626 val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT; 627 val |= HSFSTS_CTL_FCYCLE_WRITE; 628 629 ret = intel_spi_write_block(ispi, write_buf, block_size); 630 if (ret) { 631 dev_err(ispi->dev, "failed to write block\n"); 632 return ret; 633 } 634 635 /* Start the write now */ 636 val |= HSFSTS_CTL_FGO; 637 writel(val, ispi->base + HSFSTS_CTL); 638 639 ret = intel_spi_wait_hw_busy(ispi); 640 if (ret) { 641 dev_err(ispi->dev, "timeout\n"); 642 return ret; 643 } 644 645 status = readl(ispi->base + HSFSTS_CTL); 646 if (status & HSFSTS_CTL_FCERR) 647 ret = -EIO; 648 else if (status & HSFSTS_CTL_AEL) 649 ret = -EACCES; 650 651 if (ret < 0) { 652 dev_err(ispi->dev, "write error: %x: %#x\n", addr, status); 653 return ret; 654 } 655 656 nbytes -= block_size; 657 addr += block_size; 658 write_buf += block_size; 659 } 660 661 return 0; 662 } 663 664 static int intel_spi_erase(struct intel_spi *ispi, const struct spi_mem *mem, 665 const struct intel_spi_mem_op *iop, 666 const struct spi_mem_op *op) 667 { 668 u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val; 669 u8 opcode = op->cmd.opcode; 670 u32 val, status; 671 int ret; 672 673 writel(addr, ispi->base + FADDR); 674 675 if (ispi->swseq_erase) 676 return intel_spi_sw_cycle(ispi, opcode, 0, 677 OPTYPE_WRITE_WITH_ADDR); 678 679 /* Not needed with HW sequencer erase, make sure it is cleared */ 680 ispi->atomic_preopcode = 0; 681 682 val = readl(ispi->base + HSFSTS_CTL); 683 val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK); 684 val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE; 685 val |= HSFSTS_CTL_FGO; 686 val |= iop->replacement_op; 687 writel(val, ispi->base + HSFSTS_CTL); 688 689 ret = intel_spi_wait_hw_busy(ispi); 690 if (ret) 691 return ret; 692 693 status = readl(ispi->base + HSFSTS_CTL); 694 if (status & HSFSTS_CTL_FCERR) 695 return -EIO; 696 if (status & HSFSTS_CTL_AEL) 697 return -EACCES; 698 699 return 0; 700 } 701 702 static int intel_spi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) 703 { 704 op->data.nbytes = clamp_val(op->data.nbytes, 0, INTEL_SPI_FIFO_SZ); 705 return 0; 706 } 707 708 static bool intel_spi_cmp_mem_op(const struct intel_spi_mem_op *iop, 709 const struct spi_mem_op *op) 710 { 711 if (iop->mem_op.cmd.nbytes != op->cmd.nbytes || 712 iop->mem_op.cmd.buswidth != op->cmd.buswidth || 713 iop->mem_op.cmd.dtr != op->cmd.dtr || 714 iop->mem_op.cmd.opcode != op->cmd.opcode) 715 return false; 716 717 if (iop->mem_op.addr.nbytes != op->addr.nbytes || 718 iop->mem_op.addr.dtr != op->addr.dtr) 719 return false; 720 721 if (iop->mem_op.data.dir != op->data.dir || 722 iop->mem_op.data.dtr != op->data.dtr) 723 return false; 724 725 if (iop->mem_op.data.dir != SPI_MEM_NO_DATA) { 726 if (iop->mem_op.data.buswidth != op->data.buswidth) 727 return false; 728 } 729 730 return true; 731 } 732 733 static const struct intel_spi_mem_op * 734 intel_spi_match_mem_op(struct intel_spi *ispi, const struct spi_mem_op *op) 735 { 736 const struct intel_spi_mem_op *iop; 737 738 for (iop = ispi->mem_ops; iop->mem_op.cmd.opcode; iop++) { 739 if (intel_spi_cmp_mem_op(iop, op)) 740 break; 741 } 742 743 return iop->mem_op.cmd.opcode ? iop : NULL; 744 } 745 746 static bool intel_spi_supports_mem_op(struct spi_mem *mem, 747 const struct spi_mem_op *op) 748 { 749 struct intel_spi *ispi = spi_master_get_devdata(mem->spi->master); 750 const struct intel_spi_mem_op *iop; 751 752 iop = intel_spi_match_mem_op(ispi, op); 753 if (!iop) { 754 dev_dbg(ispi->dev, "%#x not supported\n", op->cmd.opcode); 755 return false; 756 } 757 758 /* 759 * For software sequencer check that the opcode is actually 760 * present in the opmenu if it is locked. 761 */ 762 if (ispi->swseq_reg && ispi->locked) { 763 int i; 764 765 /* Check if it is in the locked opcodes list */ 766 for (i = 0; i < ARRAY_SIZE(ispi->opcodes); i++) { 767 if (ispi->opcodes[i] == op->cmd.opcode) 768 return true; 769 } 770 771 dev_dbg(ispi->dev, "%#x not supported\n", op->cmd.opcode); 772 return false; 773 } 774 775 return true; 776 } 777 778 static int intel_spi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) 779 { 780 struct intel_spi *ispi = spi_master_get_devdata(mem->spi->master); 781 const struct intel_spi_mem_op *iop; 782 783 iop = intel_spi_match_mem_op(ispi, op); 784 if (!iop) 785 return -EOPNOTSUPP; 786 787 return iop->exec_op(ispi, mem, iop, op); 788 } 789 790 static const char *intel_spi_get_name(struct spi_mem *mem) 791 { 792 const struct intel_spi *ispi = spi_master_get_devdata(mem->spi->master); 793 794 /* 795 * Return name of the flash controller device to be compatible 796 * with the MTD version. 797 */ 798 return dev_name(ispi->dev); 799 } 800 801 static int intel_spi_dirmap_create(struct spi_mem_dirmap_desc *desc) 802 { 803 struct intel_spi *ispi = spi_master_get_devdata(desc->mem->spi->master); 804 const struct intel_spi_mem_op *iop; 805 806 iop = intel_spi_match_mem_op(ispi, &desc->info.op_tmpl); 807 if (!iop) 808 return -EOPNOTSUPP; 809 810 desc->priv = (void *)iop; 811 return 0; 812 } 813 814 static ssize_t intel_spi_dirmap_read(struct spi_mem_dirmap_desc *desc, u64 offs, 815 size_t len, void *buf) 816 { 817 struct intel_spi *ispi = spi_master_get_devdata(desc->mem->spi->master); 818 const struct intel_spi_mem_op *iop = desc->priv; 819 struct spi_mem_op op = desc->info.op_tmpl; 820 int ret; 821 822 /* Fill in the gaps */ 823 op.addr.val = offs; 824 op.data.nbytes = len; 825 op.data.buf.in = buf; 826 827 ret = iop->exec_op(ispi, desc->mem, iop, &op); 828 return ret ? ret : len; 829 } 830 831 static ssize_t intel_spi_dirmap_write(struct spi_mem_dirmap_desc *desc, u64 offs, 832 size_t len, const void *buf) 833 { 834 struct intel_spi *ispi = spi_master_get_devdata(desc->mem->spi->master); 835 const struct intel_spi_mem_op *iop = desc->priv; 836 struct spi_mem_op op = desc->info.op_tmpl; 837 int ret; 838 839 op.addr.val = offs; 840 op.data.nbytes = len; 841 op.data.buf.out = buf; 842 843 ret = iop->exec_op(ispi, desc->mem, iop, &op); 844 return ret ? ret : len; 845 } 846 847 static const struct spi_controller_mem_ops intel_spi_mem_ops = { 848 .adjust_op_size = intel_spi_adjust_op_size, 849 .supports_op = intel_spi_supports_mem_op, 850 .exec_op = intel_spi_exec_mem_op, 851 .get_name = intel_spi_get_name, 852 .dirmap_create = intel_spi_dirmap_create, 853 .dirmap_read = intel_spi_dirmap_read, 854 .dirmap_write = intel_spi_dirmap_write, 855 }; 856 857 #define INTEL_SPI_OP_ADDR(__nbytes) \ 858 { \ 859 .nbytes = __nbytes, \ 860 } 861 862 #define INTEL_SPI_OP_NO_DATA \ 863 { \ 864 .dir = SPI_MEM_NO_DATA, \ 865 } 866 867 #define INTEL_SPI_OP_DATA_IN(__buswidth) \ 868 { \ 869 .dir = SPI_MEM_DATA_IN, \ 870 .buswidth = __buswidth, \ 871 } 872 873 #define INTEL_SPI_OP_DATA_OUT(__buswidth) \ 874 { \ 875 .dir = SPI_MEM_DATA_OUT, \ 876 .buswidth = __buswidth, \ 877 } 878 879 #define INTEL_SPI_MEM_OP(__cmd, __addr, __data, __exec_op) \ 880 { \ 881 .mem_op = { \ 882 .cmd = __cmd, \ 883 .addr = __addr, \ 884 .data = __data, \ 885 }, \ 886 .exec_op = __exec_op, \ 887 } 888 889 #define INTEL_SPI_MEM_OP_REPL(__cmd, __addr, __data, __exec_op, __repl) \ 890 { \ 891 .mem_op = { \ 892 .cmd = __cmd, \ 893 .addr = __addr, \ 894 .data = __data, \ 895 }, \ 896 .exec_op = __exec_op, \ 897 .replacement_op = __repl, \ 898 } 899 900 /* 901 * The controller handles pretty much everything internally based on the 902 * SFDP data but we want to make sure we only support the operations 903 * actually possible. Only check buswidth and transfer direction, the 904 * core validates data. 905 */ 906 #define INTEL_SPI_GENERIC_OPS \ 907 /* Status register operations */ \ 908 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1), \ 909 SPI_MEM_OP_NO_ADDR, \ 910 INTEL_SPI_OP_DATA_IN(1), \ 911 intel_spi_read_reg, \ 912 HSFSTS_CTL_FCYCLE_RDID), \ 913 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 1), \ 914 SPI_MEM_OP_NO_ADDR, \ 915 INTEL_SPI_OP_DATA_IN(1), \ 916 intel_spi_read_reg, \ 917 HSFSTS_CTL_FCYCLE_RDSR), \ 918 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 1), \ 919 SPI_MEM_OP_NO_ADDR, \ 920 INTEL_SPI_OP_DATA_OUT(1), \ 921 intel_spi_write_reg, \ 922 HSFSTS_CTL_FCYCLE_WRSR), \ 923 /* Normal read */ \ 924 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \ 925 INTEL_SPI_OP_ADDR(3), \ 926 INTEL_SPI_OP_DATA_IN(1), \ 927 intel_spi_read), \ 928 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \ 929 INTEL_SPI_OP_ADDR(3), \ 930 INTEL_SPI_OP_DATA_IN(2), \ 931 intel_spi_read), \ 932 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \ 933 INTEL_SPI_OP_ADDR(3), \ 934 INTEL_SPI_OP_DATA_IN(4), \ 935 intel_spi_read), \ 936 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \ 937 INTEL_SPI_OP_ADDR(4), \ 938 INTEL_SPI_OP_DATA_IN(1), \ 939 intel_spi_read), \ 940 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \ 941 INTEL_SPI_OP_ADDR(4), \ 942 INTEL_SPI_OP_DATA_IN(2), \ 943 intel_spi_read), \ 944 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \ 945 INTEL_SPI_OP_ADDR(4), \ 946 INTEL_SPI_OP_DATA_IN(4), \ 947 intel_spi_read), \ 948 /* Fast read */ \ 949 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST, 1), \ 950 INTEL_SPI_OP_ADDR(3), \ 951 INTEL_SPI_OP_DATA_IN(1), \ 952 intel_spi_read), \ 953 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST, 1), \ 954 INTEL_SPI_OP_ADDR(3), \ 955 INTEL_SPI_OP_DATA_IN(2), \ 956 intel_spi_read), \ 957 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST, 1), \ 958 INTEL_SPI_OP_ADDR(3), \ 959 INTEL_SPI_OP_DATA_IN(4), \ 960 intel_spi_read), \ 961 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST, 1), \ 962 INTEL_SPI_OP_ADDR(4), \ 963 INTEL_SPI_OP_DATA_IN(1), \ 964 intel_spi_read), \ 965 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST, 1), \ 966 INTEL_SPI_OP_ADDR(4), \ 967 INTEL_SPI_OP_DATA_IN(2), \ 968 intel_spi_read), \ 969 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST, 1), \ 970 INTEL_SPI_OP_ADDR(4), \ 971 INTEL_SPI_OP_DATA_IN(4), \ 972 intel_spi_read), \ 973 /* Read with 4-byte address opcode */ \ 974 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_4B, 1), \ 975 INTEL_SPI_OP_ADDR(4), \ 976 INTEL_SPI_OP_DATA_IN(1), \ 977 intel_spi_read), \ 978 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_4B, 1), \ 979 INTEL_SPI_OP_ADDR(4), \ 980 INTEL_SPI_OP_DATA_IN(2), \ 981 intel_spi_read), \ 982 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_4B, 1), \ 983 INTEL_SPI_OP_ADDR(4), \ 984 INTEL_SPI_OP_DATA_IN(4), \ 985 intel_spi_read), \ 986 /* Fast read with 4-byte address opcode */ \ 987 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST_4B, 1), \ 988 INTEL_SPI_OP_ADDR(4), \ 989 INTEL_SPI_OP_DATA_IN(1), \ 990 intel_spi_read), \ 991 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST_4B, 1), \ 992 INTEL_SPI_OP_ADDR(4), \ 993 INTEL_SPI_OP_DATA_IN(2), \ 994 intel_spi_read), \ 995 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST_4B, 1), \ 996 INTEL_SPI_OP_ADDR(4), \ 997 INTEL_SPI_OP_DATA_IN(4), \ 998 intel_spi_read), \ 999 /* Write operations */ \ 1000 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_PP, 1), \ 1001 INTEL_SPI_OP_ADDR(3), \ 1002 INTEL_SPI_OP_DATA_OUT(1), \ 1003 intel_spi_write), \ 1004 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_PP, 1), \ 1005 INTEL_SPI_OP_ADDR(4), \ 1006 INTEL_SPI_OP_DATA_OUT(1), \ 1007 intel_spi_write), \ 1008 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_PP_4B, 1), \ 1009 INTEL_SPI_OP_ADDR(4), \ 1010 INTEL_SPI_OP_DATA_OUT(1), \ 1011 intel_spi_write), \ 1012 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREN, 1), \ 1013 SPI_MEM_OP_NO_ADDR, \ 1014 SPI_MEM_OP_NO_DATA, \ 1015 intel_spi_write_reg), \ 1016 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRDI, 1), \ 1017 SPI_MEM_OP_NO_ADDR, \ 1018 SPI_MEM_OP_NO_DATA, \ 1019 intel_spi_write_reg), \ 1020 /* Erase operations */ \ 1021 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_BE_4K, 1), \ 1022 INTEL_SPI_OP_ADDR(3), \ 1023 SPI_MEM_OP_NO_DATA, \ 1024 intel_spi_erase, \ 1025 HSFSTS_CTL_FCYCLE_ERASE), \ 1026 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_BE_4K, 1), \ 1027 INTEL_SPI_OP_ADDR(4), \ 1028 SPI_MEM_OP_NO_DATA, \ 1029 intel_spi_erase, \ 1030 HSFSTS_CTL_FCYCLE_ERASE), \ 1031 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_BE_4K_4B, 1), \ 1032 INTEL_SPI_OP_ADDR(4), \ 1033 SPI_MEM_OP_NO_DATA, \ 1034 intel_spi_erase, \ 1035 HSFSTS_CTL_FCYCLE_ERASE) \ 1036 1037 static const struct intel_spi_mem_op generic_mem_ops[] = { 1038 INTEL_SPI_GENERIC_OPS, 1039 { }, 1040 }; 1041 1042 static const struct intel_spi_mem_op erase_64k_mem_ops[] = { 1043 INTEL_SPI_GENERIC_OPS, 1044 /* 64k sector erase operations */ 1045 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_SE, 1), 1046 INTEL_SPI_OP_ADDR(3), 1047 SPI_MEM_OP_NO_DATA, 1048 intel_spi_erase, 1049 HSFSTS_CTL_FCYCLE_ERASE_64K), 1050 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_SE, 1), 1051 INTEL_SPI_OP_ADDR(4), 1052 SPI_MEM_OP_NO_DATA, 1053 intel_spi_erase, 1054 HSFSTS_CTL_FCYCLE_ERASE_64K), 1055 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_SE_4B, 1), 1056 INTEL_SPI_OP_ADDR(4), 1057 SPI_MEM_OP_NO_DATA, 1058 intel_spi_erase, 1059 HSFSTS_CTL_FCYCLE_ERASE_64K), 1060 { }, 1061 }; 1062 1063 static int intel_spi_init(struct intel_spi *ispi) 1064 { 1065 u32 opmenu0, opmenu1, lvscc, uvscc, val; 1066 bool erase_64k = false; 1067 int i; 1068 1069 switch (ispi->info->type) { 1070 case INTEL_SPI_BYT: 1071 ispi->sregs = ispi->base + BYT_SSFSTS_CTL; 1072 ispi->pregs = ispi->base + BYT_PR; 1073 ispi->nregions = BYT_FREG_NUM; 1074 ispi->pr_num = BYT_PR_NUM; 1075 ispi->swseq_reg = true; 1076 break; 1077 1078 case INTEL_SPI_LPT: 1079 ispi->sregs = ispi->base + LPT_SSFSTS_CTL; 1080 ispi->pregs = ispi->base + LPT_PR; 1081 ispi->nregions = LPT_FREG_NUM; 1082 ispi->pr_num = LPT_PR_NUM; 1083 ispi->swseq_reg = true; 1084 break; 1085 1086 case INTEL_SPI_BXT: 1087 ispi->sregs = ispi->base + BXT_SSFSTS_CTL; 1088 ispi->pregs = ispi->base + BXT_PR; 1089 ispi->nregions = BXT_FREG_NUM; 1090 ispi->pr_num = BXT_PR_NUM; 1091 erase_64k = true; 1092 break; 1093 1094 case INTEL_SPI_CNL: 1095 ispi->sregs = NULL; 1096 ispi->pregs = ispi->base + CNL_PR; 1097 ispi->nregions = CNL_FREG_NUM; 1098 ispi->pr_num = CNL_PR_NUM; 1099 erase_64k = true; 1100 break; 1101 1102 default: 1103 return -EINVAL; 1104 } 1105 1106 /* Try to disable write protection if user asked to do so */ 1107 if (writeable && !intel_spi_set_writeable(ispi)) { 1108 dev_warn(ispi->dev, "can't disable chip write protection\n"); 1109 writeable = false; 1110 } 1111 1112 /* Disable #SMI generation from HW sequencer */ 1113 val = readl(ispi->base + HSFSTS_CTL); 1114 val &= ~HSFSTS_CTL_FSMIE; 1115 writel(val, ispi->base + HSFSTS_CTL); 1116 1117 /* 1118 * Determine whether erase operation should use HW or SW sequencer. 1119 * 1120 * The HW sequencer has a predefined list of opcodes, with only the 1121 * erase opcode being programmable in LVSCC and UVSCC registers. 1122 * If these registers don't contain a valid erase opcode, erase 1123 * cannot be done using HW sequencer. 1124 */ 1125 lvscc = readl(ispi->base + LVSCC); 1126 uvscc = readl(ispi->base + UVSCC); 1127 if (!(lvscc & ERASE_OPCODE_MASK) || !(uvscc & ERASE_OPCODE_MASK)) 1128 ispi->swseq_erase = true; 1129 /* SPI controller on Intel BXT supports 64K erase opcode */ 1130 if (ispi->info->type == INTEL_SPI_BXT && !ispi->swseq_erase) 1131 if (!(lvscc & ERASE_64K_OPCODE_MASK) || 1132 !(uvscc & ERASE_64K_OPCODE_MASK)) 1133 erase_64k = false; 1134 1135 if (!ispi->sregs && (ispi->swseq_reg || ispi->swseq_erase)) { 1136 dev_err(ispi->dev, "software sequencer not supported, but required\n"); 1137 return -EINVAL; 1138 } 1139 1140 /* 1141 * Some controllers can only do basic operations using hardware 1142 * sequencer. All other operations are supposed to be carried out 1143 * using software sequencer. 1144 */ 1145 if (ispi->swseq_reg) { 1146 /* Disable #SMI generation from SW sequencer */ 1147 val = readl(ispi->sregs + SSFSTS_CTL); 1148 val &= ~SSFSTS_CTL_FSMIE; 1149 writel(val, ispi->sregs + SSFSTS_CTL); 1150 } 1151 1152 /* Check controller's lock status */ 1153 val = readl(ispi->base + HSFSTS_CTL); 1154 ispi->locked = !!(val & HSFSTS_CTL_FLOCKDN); 1155 1156 if (ispi->locked && ispi->sregs) { 1157 /* 1158 * BIOS programs allowed opcodes and then locks down the 1159 * register. So read back what opcodes it decided to support. 1160 * That's the set we are going to support as well. 1161 */ 1162 opmenu0 = readl(ispi->sregs + OPMENU0); 1163 opmenu1 = readl(ispi->sregs + OPMENU1); 1164 1165 if (opmenu0 && opmenu1) { 1166 for (i = 0; i < ARRAY_SIZE(ispi->opcodes) / 2; i++) { 1167 ispi->opcodes[i] = opmenu0 >> i * 8; 1168 ispi->opcodes[i + 4] = opmenu1 >> i * 8; 1169 } 1170 } 1171 } 1172 1173 if (erase_64k) { 1174 dev_dbg(ispi->dev, "Using erase_64k memory operations"); 1175 ispi->mem_ops = erase_64k_mem_ops; 1176 } else { 1177 dev_dbg(ispi->dev, "Using generic memory operations"); 1178 ispi->mem_ops = generic_mem_ops; 1179 } 1180 1181 intel_spi_dump_regs(ispi); 1182 return 0; 1183 } 1184 1185 static bool intel_spi_is_protected(const struct intel_spi *ispi, 1186 unsigned int base, unsigned int limit) 1187 { 1188 int i; 1189 1190 for (i = 0; i < ispi->pr_num; i++) { 1191 u32 pr_base, pr_limit, pr_value; 1192 1193 pr_value = readl(ispi->pregs + PR(i)); 1194 if (!(pr_value & (PR_WPE | PR_RPE))) 1195 continue; 1196 1197 pr_limit = (pr_value & PR_LIMIT_MASK) >> PR_LIMIT_SHIFT; 1198 pr_base = pr_value & PR_BASE_MASK; 1199 1200 if (pr_base >= base && pr_limit <= limit) 1201 return true; 1202 } 1203 1204 return false; 1205 } 1206 1207 /* 1208 * There will be a single partition holding all enabled flash regions. We 1209 * call this "BIOS". 1210 */ 1211 static void intel_spi_fill_partition(struct intel_spi *ispi, 1212 struct mtd_partition *part) 1213 { 1214 u64 end; 1215 int i; 1216 1217 memset(part, 0, sizeof(*part)); 1218 1219 /* Start from the mandatory descriptor region */ 1220 part->size = 4096; 1221 part->name = "BIOS"; 1222 1223 /* 1224 * Now try to find where this partition ends based on the flash 1225 * region registers. 1226 */ 1227 for (i = 1; i < ispi->nregions; i++) { 1228 u32 region, base, limit; 1229 1230 region = readl(ispi->base + FREG(i)); 1231 base = region & FREG_BASE_MASK; 1232 limit = (region & FREG_LIMIT_MASK) >> FREG_LIMIT_SHIFT; 1233 1234 if (base >= limit || limit == 0) 1235 continue; 1236 1237 /* 1238 * If any of the regions have protection bits set, make the 1239 * whole partition read-only to be on the safe side. 1240 * 1241 * Also if the user did not ask the chip to be writeable 1242 * mask the bit too. 1243 */ 1244 if (!writeable || intel_spi_is_protected(ispi, base, limit)) 1245 part->mask_flags |= MTD_WRITEABLE; 1246 1247 end = (limit << 12) + 4096; 1248 if (end > part->size) 1249 part->size = end; 1250 } 1251 } 1252 1253 static int intel_spi_read_desc(struct intel_spi *ispi) 1254 { 1255 struct spi_mem_op op = 1256 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 0), 1257 SPI_MEM_OP_ADDR(3, 0, 0), 1258 SPI_MEM_OP_NO_DUMMY, 1259 SPI_MEM_OP_DATA_IN(0, NULL, 0)); 1260 u32 buf[2], nc, fcba, flcomp; 1261 ssize_t ret; 1262 1263 op.addr.val = 0x10; 1264 op.data.buf.in = buf; 1265 op.data.nbytes = sizeof(buf); 1266 1267 ret = intel_spi_read(ispi, NULL, NULL, &op); 1268 if (ret) { 1269 dev_warn(ispi->dev, "failed to read descriptor\n"); 1270 return ret; 1271 } 1272 1273 dev_dbg(ispi->dev, "FLVALSIG=0x%08x\n", buf[0]); 1274 dev_dbg(ispi->dev, "FLMAP0=0x%08x\n", buf[1]); 1275 1276 if (buf[0] != FLVALSIG_MAGIC) { 1277 dev_warn(ispi->dev, "descriptor signature not valid\n"); 1278 return -ENODEV; 1279 } 1280 1281 fcba = (buf[1] & FLMAP0_FCBA_MASK) << 4; 1282 dev_dbg(ispi->dev, "FCBA=%#x\n", fcba); 1283 1284 op.addr.val = fcba; 1285 op.data.buf.in = &flcomp; 1286 op.data.nbytes = sizeof(flcomp); 1287 1288 ret = intel_spi_read(ispi, NULL, NULL, &op); 1289 if (ret) { 1290 dev_warn(ispi->dev, "failed to read FLCOMP\n"); 1291 return -ENODEV; 1292 } 1293 1294 dev_dbg(ispi->dev, "FLCOMP=0x%08x\n", flcomp); 1295 1296 switch (flcomp & FLCOMP_C0DEN_MASK) { 1297 case FLCOMP_C0DEN_512K: 1298 ispi->chip0_size = SZ_512K; 1299 break; 1300 case FLCOMP_C0DEN_1M: 1301 ispi->chip0_size = SZ_1M; 1302 break; 1303 case FLCOMP_C0DEN_2M: 1304 ispi->chip0_size = SZ_2M; 1305 break; 1306 case FLCOMP_C0DEN_4M: 1307 ispi->chip0_size = SZ_4M; 1308 break; 1309 case FLCOMP_C0DEN_8M: 1310 ispi->chip0_size = SZ_8M; 1311 break; 1312 case FLCOMP_C0DEN_16M: 1313 ispi->chip0_size = SZ_16M; 1314 break; 1315 case FLCOMP_C0DEN_32M: 1316 ispi->chip0_size = SZ_32M; 1317 break; 1318 case FLCOMP_C0DEN_64M: 1319 ispi->chip0_size = SZ_64M; 1320 break; 1321 default: 1322 return -EINVAL; 1323 } 1324 1325 dev_dbg(ispi->dev, "chip0 size %zd KB\n", ispi->chip0_size / SZ_1K); 1326 1327 nc = (buf[1] & FLMAP0_NC_MASK) >> FLMAP0_NC_SHIFT; 1328 if (!nc) 1329 ispi->master->num_chipselect = 1; 1330 else if (nc == 1) 1331 ispi->master->num_chipselect = 2; 1332 else 1333 return -EINVAL; 1334 1335 dev_dbg(ispi->dev, "%u flash components found\n", 1336 ispi->master->num_chipselect); 1337 return 0; 1338 } 1339 1340 static int intel_spi_populate_chip(struct intel_spi *ispi) 1341 { 1342 struct flash_platform_data *pdata; 1343 struct spi_board_info chip; 1344 int ret; 1345 1346 pdata = devm_kzalloc(ispi->dev, sizeof(*pdata), GFP_KERNEL); 1347 if (!pdata) 1348 return -ENOMEM; 1349 1350 pdata->nr_parts = 1; 1351 pdata->parts = devm_kcalloc(ispi->dev, pdata->nr_parts, 1352 sizeof(*pdata->parts), GFP_KERNEL); 1353 if (!pdata->parts) 1354 return -ENOMEM; 1355 1356 intel_spi_fill_partition(ispi, pdata->parts); 1357 1358 memset(&chip, 0, sizeof(chip)); 1359 snprintf(chip.modalias, 8, "spi-nor"); 1360 chip.platform_data = pdata; 1361 1362 if (!spi_new_device(ispi->master, &chip)) 1363 return -ENODEV; 1364 1365 /* Add the second chip if present */ 1366 if (ispi->master->num_chipselect < 2) 1367 return 0; 1368 1369 ret = intel_spi_read_desc(ispi); 1370 if (ret) 1371 return ret; 1372 1373 chip.platform_data = NULL; 1374 chip.chip_select = 1; 1375 1376 if (!spi_new_device(ispi->master, &chip)) 1377 return -ENODEV; 1378 return 0; 1379 } 1380 1381 /** 1382 * intel_spi_probe() - Probe the Intel SPI flash controller 1383 * @dev: Pointer to the parent device 1384 * @mem: MMIO resource 1385 * @info: Platform specific information 1386 * 1387 * Probes Intel SPI flash controller and creates the flash chip device. 1388 * Returns %0 on success and negative errno in case of failure. 1389 */ 1390 int intel_spi_probe(struct device *dev, struct resource *mem, 1391 const struct intel_spi_boardinfo *info) 1392 { 1393 struct spi_controller *master; 1394 struct intel_spi *ispi; 1395 int ret; 1396 1397 master = devm_spi_alloc_master(dev, sizeof(*ispi)); 1398 if (!master) 1399 return -ENOMEM; 1400 1401 master->mem_ops = &intel_spi_mem_ops; 1402 1403 ispi = spi_master_get_devdata(master); 1404 1405 ispi->base = devm_ioremap_resource(dev, mem); 1406 if (IS_ERR(ispi->base)) 1407 return PTR_ERR(ispi->base); 1408 1409 ispi->dev = dev; 1410 ispi->master = master; 1411 ispi->info = info; 1412 1413 ret = intel_spi_init(ispi); 1414 if (ret) 1415 return ret; 1416 1417 ret = devm_spi_register_master(dev, master); 1418 if (ret) 1419 return ret; 1420 1421 return intel_spi_populate_chip(ispi); 1422 } 1423 EXPORT_SYMBOL_GPL(intel_spi_probe); 1424 1425 MODULE_DESCRIPTION("Intel PCH/PCU SPI flash core driver"); 1426 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 1427 MODULE_LICENSE("GPL v2"); 1428