1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 3 // Copyright (C) 2008 Juergen Beisert 4 5 #include <linux/clk.h> 6 #include <linux/completion.h> 7 #include <linux/delay.h> 8 #include <linux/dmaengine.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/err.h> 11 #include <linux/gpio.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/irq.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/platform_device.h> 18 #include <linux/slab.h> 19 #include <linux/spi/spi.h> 20 #include <linux/spi/spi_bitbang.h> 21 #include <linux/types.h> 22 #include <linux/of.h> 23 #include <linux/of_device.h> 24 #include <linux/of_gpio.h> 25 26 #include <linux/platform_data/dma-imx.h> 27 #include <linux/platform_data/spi-imx.h> 28 29 #define DRIVER_NAME "spi_imx" 30 31 #define MXC_CSPIRXDATA 0x00 32 #define MXC_CSPITXDATA 0x04 33 #define MXC_CSPICTRL 0x08 34 #define MXC_CSPIINT 0x0c 35 #define MXC_RESET 0x1c 36 37 /* generic defines to abstract from the different register layouts */ 38 #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */ 39 #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */ 40 #define MXC_INT_RDR BIT(4) /* Receive date threshold interrupt */ 41 42 /* The maximum bytes that a sdma BD can transfer. */ 43 #define MAX_SDMA_BD_BYTES (1 << 15) 44 #define MX51_ECSPI_CTRL_MAX_BURST 512 45 /* The maximum bytes that IMX53_ECSPI can transfer in slave mode.*/ 46 #define MX53_MAX_TRANSFER_BYTES 512 47 48 enum spi_imx_devtype { 49 IMX1_CSPI, 50 IMX21_CSPI, 51 IMX27_CSPI, 52 IMX31_CSPI, 53 IMX35_CSPI, /* CSPI on all i.mx except above */ 54 IMX51_ECSPI, /* ECSPI on i.mx51 */ 55 IMX53_ECSPI, /* ECSPI on i.mx53 and later */ 56 }; 57 58 struct spi_imx_data; 59 60 struct spi_imx_devtype_data { 61 void (*intctrl)(struct spi_imx_data *, int); 62 int (*prepare_message)(struct spi_imx_data *, struct spi_message *); 63 int (*prepare_transfer)(struct spi_imx_data *, struct spi_device *, 64 struct spi_transfer *); 65 void (*trigger)(struct spi_imx_data *); 66 int (*rx_available)(struct spi_imx_data *); 67 void (*reset)(struct spi_imx_data *); 68 void (*setup_wml)(struct spi_imx_data *); 69 void (*disable)(struct spi_imx_data *); 70 bool has_dmamode; 71 bool has_slavemode; 72 unsigned int fifo_size; 73 bool dynamic_burst; 74 enum spi_imx_devtype devtype; 75 }; 76 77 struct spi_imx_data { 78 struct spi_bitbang bitbang; 79 struct device *dev; 80 81 struct completion xfer_done; 82 void __iomem *base; 83 unsigned long base_phys; 84 85 struct clk *clk_per; 86 struct clk *clk_ipg; 87 unsigned long spi_clk; 88 unsigned int spi_bus_clk; 89 90 unsigned int bits_per_word; 91 unsigned int spi_drctl; 92 93 unsigned int count, remainder; 94 void (*tx)(struct spi_imx_data *); 95 void (*rx)(struct spi_imx_data *); 96 void *rx_buf; 97 const void *tx_buf; 98 unsigned int txfifo; /* number of words pushed in tx FIFO */ 99 unsigned int dynamic_burst; 100 101 /* Slave mode */ 102 bool slave_mode; 103 bool slave_aborted; 104 unsigned int slave_burst; 105 106 /* DMA */ 107 bool usedma; 108 u32 wml; 109 struct completion dma_rx_completion; 110 struct completion dma_tx_completion; 111 112 const struct spi_imx_devtype_data *devtype_data; 113 }; 114 115 static inline int is_imx27_cspi(struct spi_imx_data *d) 116 { 117 return d->devtype_data->devtype == IMX27_CSPI; 118 } 119 120 static inline int is_imx35_cspi(struct spi_imx_data *d) 121 { 122 return d->devtype_data->devtype == IMX35_CSPI; 123 } 124 125 static inline int is_imx51_ecspi(struct spi_imx_data *d) 126 { 127 return d->devtype_data->devtype == IMX51_ECSPI; 128 } 129 130 static inline int is_imx53_ecspi(struct spi_imx_data *d) 131 { 132 return d->devtype_data->devtype == IMX53_ECSPI; 133 } 134 135 #define MXC_SPI_BUF_RX(type) \ 136 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \ 137 { \ 138 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \ 139 \ 140 if (spi_imx->rx_buf) { \ 141 *(type *)spi_imx->rx_buf = val; \ 142 spi_imx->rx_buf += sizeof(type); \ 143 } \ 144 \ 145 spi_imx->remainder -= sizeof(type); \ 146 } 147 148 #define MXC_SPI_BUF_TX(type) \ 149 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \ 150 { \ 151 type val = 0; \ 152 \ 153 if (spi_imx->tx_buf) { \ 154 val = *(type *)spi_imx->tx_buf; \ 155 spi_imx->tx_buf += sizeof(type); \ 156 } \ 157 \ 158 spi_imx->count -= sizeof(type); \ 159 \ 160 writel(val, spi_imx->base + MXC_CSPITXDATA); \ 161 } 162 163 MXC_SPI_BUF_RX(u8) 164 MXC_SPI_BUF_TX(u8) 165 MXC_SPI_BUF_RX(u16) 166 MXC_SPI_BUF_TX(u16) 167 MXC_SPI_BUF_RX(u32) 168 MXC_SPI_BUF_TX(u32) 169 170 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set 171 * (which is currently not the case in this driver) 172 */ 173 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192, 174 256, 384, 512, 768, 1024}; 175 176 /* MX21, MX27 */ 177 static unsigned int spi_imx_clkdiv_1(unsigned int fin, 178 unsigned int fspi, unsigned int max, unsigned int *fres) 179 { 180 int i; 181 182 for (i = 2; i < max; i++) 183 if (fspi * mxc_clkdivs[i] >= fin) 184 break; 185 186 *fres = fin / mxc_clkdivs[i]; 187 return i; 188 } 189 190 /* MX1, MX31, MX35, MX51 CSPI */ 191 static unsigned int spi_imx_clkdiv_2(unsigned int fin, 192 unsigned int fspi, unsigned int *fres) 193 { 194 int i, div = 4; 195 196 for (i = 0; i < 7; i++) { 197 if (fspi * div >= fin) 198 goto out; 199 div <<= 1; 200 } 201 202 out: 203 *fres = fin / div; 204 return i; 205 } 206 207 static int spi_imx_bytes_per_word(const int bits_per_word) 208 { 209 if (bits_per_word <= 8) 210 return 1; 211 else if (bits_per_word <= 16) 212 return 2; 213 else 214 return 4; 215 } 216 217 static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi, 218 struct spi_transfer *transfer) 219 { 220 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 221 222 if (!master->dma_rx) 223 return false; 224 225 if (spi_imx->slave_mode) 226 return false; 227 228 if (transfer->len < spi_imx->devtype_data->fifo_size) 229 return false; 230 231 spi_imx->dynamic_burst = 0; 232 233 return true; 234 } 235 236 #define MX51_ECSPI_CTRL 0x08 237 #define MX51_ECSPI_CTRL_ENABLE (1 << 0) 238 #define MX51_ECSPI_CTRL_XCH (1 << 2) 239 #define MX51_ECSPI_CTRL_SMC (1 << 3) 240 #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4) 241 #define MX51_ECSPI_CTRL_DRCTL(drctl) ((drctl) << 16) 242 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8 243 #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12 244 #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18) 245 #define MX51_ECSPI_CTRL_BL_OFFSET 20 246 #define MX51_ECSPI_CTRL_BL_MASK (0xfff << 20) 247 248 #define MX51_ECSPI_CONFIG 0x0c 249 #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0)) 250 #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4)) 251 #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8)) 252 #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12)) 253 #define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20)) 254 255 #define MX51_ECSPI_INT 0x10 256 #define MX51_ECSPI_INT_TEEN (1 << 0) 257 #define MX51_ECSPI_INT_RREN (1 << 3) 258 #define MX51_ECSPI_INT_RDREN (1 << 4) 259 260 #define MX51_ECSPI_DMA 0x14 261 #define MX51_ECSPI_DMA_TX_WML(wml) ((wml) & 0x3f) 262 #define MX51_ECSPI_DMA_RX_WML(wml) (((wml) & 0x3f) << 16) 263 #define MX51_ECSPI_DMA_RXT_WML(wml) (((wml) & 0x3f) << 24) 264 265 #define MX51_ECSPI_DMA_TEDEN (1 << 7) 266 #define MX51_ECSPI_DMA_RXDEN (1 << 23) 267 #define MX51_ECSPI_DMA_RXTDEN (1 << 31) 268 269 #define MX51_ECSPI_STAT 0x18 270 #define MX51_ECSPI_STAT_RR (1 << 3) 271 272 #define MX51_ECSPI_TESTREG 0x20 273 #define MX51_ECSPI_TESTREG_LBC BIT(31) 274 275 static void spi_imx_buf_rx_swap_u32(struct spi_imx_data *spi_imx) 276 { 277 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); 278 #ifdef __LITTLE_ENDIAN 279 unsigned int bytes_per_word; 280 #endif 281 282 if (spi_imx->rx_buf) { 283 #ifdef __LITTLE_ENDIAN 284 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); 285 if (bytes_per_word == 1) 286 val = cpu_to_be32(val); 287 else if (bytes_per_word == 2) 288 val = (val << 16) | (val >> 16); 289 #endif 290 *(u32 *)spi_imx->rx_buf = val; 291 spi_imx->rx_buf += sizeof(u32); 292 } 293 294 spi_imx->remainder -= sizeof(u32); 295 } 296 297 static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx) 298 { 299 int unaligned; 300 u32 val; 301 302 unaligned = spi_imx->remainder % 4; 303 304 if (!unaligned) { 305 spi_imx_buf_rx_swap_u32(spi_imx); 306 return; 307 } 308 309 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) { 310 spi_imx_buf_rx_u16(spi_imx); 311 return; 312 } 313 314 val = readl(spi_imx->base + MXC_CSPIRXDATA); 315 316 while (unaligned--) { 317 if (spi_imx->rx_buf) { 318 *(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff; 319 spi_imx->rx_buf++; 320 } 321 spi_imx->remainder--; 322 } 323 } 324 325 static void spi_imx_buf_tx_swap_u32(struct spi_imx_data *spi_imx) 326 { 327 u32 val = 0; 328 #ifdef __LITTLE_ENDIAN 329 unsigned int bytes_per_word; 330 #endif 331 332 if (spi_imx->tx_buf) { 333 val = *(u32 *)spi_imx->tx_buf; 334 spi_imx->tx_buf += sizeof(u32); 335 } 336 337 spi_imx->count -= sizeof(u32); 338 #ifdef __LITTLE_ENDIAN 339 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); 340 341 if (bytes_per_word == 1) 342 val = cpu_to_be32(val); 343 else if (bytes_per_word == 2) 344 val = (val << 16) | (val >> 16); 345 #endif 346 writel(val, spi_imx->base + MXC_CSPITXDATA); 347 } 348 349 static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx) 350 { 351 int unaligned; 352 u32 val = 0; 353 354 unaligned = spi_imx->count % 4; 355 356 if (!unaligned) { 357 spi_imx_buf_tx_swap_u32(spi_imx); 358 return; 359 } 360 361 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) { 362 spi_imx_buf_tx_u16(spi_imx); 363 return; 364 } 365 366 while (unaligned--) { 367 if (spi_imx->tx_buf) { 368 val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned); 369 spi_imx->tx_buf++; 370 } 371 spi_imx->count--; 372 } 373 374 writel(val, spi_imx->base + MXC_CSPITXDATA); 375 } 376 377 static void mx53_ecspi_rx_slave(struct spi_imx_data *spi_imx) 378 { 379 u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA)); 380 381 if (spi_imx->rx_buf) { 382 int n_bytes = spi_imx->slave_burst % sizeof(val); 383 384 if (!n_bytes) 385 n_bytes = sizeof(val); 386 387 memcpy(spi_imx->rx_buf, 388 ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes); 389 390 spi_imx->rx_buf += n_bytes; 391 spi_imx->slave_burst -= n_bytes; 392 } 393 394 spi_imx->remainder -= sizeof(u32); 395 } 396 397 static void mx53_ecspi_tx_slave(struct spi_imx_data *spi_imx) 398 { 399 u32 val = 0; 400 int n_bytes = spi_imx->count % sizeof(val); 401 402 if (!n_bytes) 403 n_bytes = sizeof(val); 404 405 if (spi_imx->tx_buf) { 406 memcpy(((u8 *)&val) + sizeof(val) - n_bytes, 407 spi_imx->tx_buf, n_bytes); 408 val = cpu_to_be32(val); 409 spi_imx->tx_buf += n_bytes; 410 } 411 412 spi_imx->count -= n_bytes; 413 414 writel(val, spi_imx->base + MXC_CSPITXDATA); 415 } 416 417 /* MX51 eCSPI */ 418 static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx, 419 unsigned int fspi, unsigned int *fres) 420 { 421 /* 422 * there are two 4-bit dividers, the pre-divider divides by 423 * $pre, the post-divider by 2^$post 424 */ 425 unsigned int pre, post; 426 unsigned int fin = spi_imx->spi_clk; 427 428 if (unlikely(fspi > fin)) 429 return 0; 430 431 post = fls(fin) - fls(fspi); 432 if (fin > fspi << post) 433 post++; 434 435 /* now we have: (fin <= fspi << post) with post being minimal */ 436 437 post = max(4U, post) - 4; 438 if (unlikely(post > 0xf)) { 439 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n", 440 fspi, fin); 441 return 0xff; 442 } 443 444 pre = DIV_ROUND_UP(fin, fspi << post) - 1; 445 446 dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n", 447 __func__, fin, fspi, post, pre); 448 449 /* Resulting frequency for the SCLK line. */ 450 *fres = (fin / (pre + 1)) >> post; 451 452 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) | 453 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET); 454 } 455 456 static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable) 457 { 458 unsigned val = 0; 459 460 if (enable & MXC_INT_TE) 461 val |= MX51_ECSPI_INT_TEEN; 462 463 if (enable & MXC_INT_RR) 464 val |= MX51_ECSPI_INT_RREN; 465 466 if (enable & MXC_INT_RDR) 467 val |= MX51_ECSPI_INT_RDREN; 468 469 writel(val, spi_imx->base + MX51_ECSPI_INT); 470 } 471 472 static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx) 473 { 474 u32 reg; 475 476 reg = readl(spi_imx->base + MX51_ECSPI_CTRL); 477 reg |= MX51_ECSPI_CTRL_XCH; 478 writel(reg, spi_imx->base + MX51_ECSPI_CTRL); 479 } 480 481 static void mx51_ecspi_disable(struct spi_imx_data *spi_imx) 482 { 483 u32 ctrl; 484 485 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); 486 ctrl &= ~MX51_ECSPI_CTRL_ENABLE; 487 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); 488 } 489 490 static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx, 491 struct spi_message *msg) 492 { 493 struct spi_device *spi = msg->spi; 494 u32 ctrl = MX51_ECSPI_CTRL_ENABLE; 495 u32 testreg; 496 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG); 497 498 /* set Master or Slave mode */ 499 if (spi_imx->slave_mode) 500 ctrl &= ~MX51_ECSPI_CTRL_MODE_MASK; 501 else 502 ctrl |= MX51_ECSPI_CTRL_MODE_MASK; 503 504 /* 505 * Enable SPI_RDY handling (falling edge/level triggered). 506 */ 507 if (spi->mode & SPI_READY) 508 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl); 509 510 /* set chip select to use */ 511 ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select); 512 513 /* 514 * The ctrl register must be written first, with the EN bit set other 515 * registers must not be written to. 516 */ 517 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); 518 519 testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG); 520 if (spi->mode & SPI_LOOP) 521 testreg |= MX51_ECSPI_TESTREG_LBC; 522 else 523 testreg &= ~MX51_ECSPI_TESTREG_LBC; 524 writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG); 525 526 /* 527 * eCSPI burst completion by Chip Select signal in Slave mode 528 * is not functional for imx53 Soc, config SPI burst completed when 529 * BURST_LENGTH + 1 bits are received 530 */ 531 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx)) 532 cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select); 533 else 534 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select); 535 536 if (spi->mode & SPI_CPHA) 537 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); 538 else 539 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); 540 541 if (spi->mode & SPI_CPOL) { 542 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); 543 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); 544 } else { 545 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); 546 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); 547 } 548 549 if (spi->mode & SPI_CS_HIGH) 550 cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select); 551 else 552 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select); 553 554 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); 555 556 return 0; 557 } 558 559 static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx, 560 struct spi_device *spi, 561 struct spi_transfer *t) 562 { 563 u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); 564 u32 clk = t->speed_hz, delay; 565 566 /* Clear BL field and set the right value */ 567 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK; 568 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx)) 569 ctrl |= (spi_imx->slave_burst * 8 - 1) 570 << MX51_ECSPI_CTRL_BL_OFFSET; 571 else 572 ctrl |= (spi_imx->bits_per_word - 1) 573 << MX51_ECSPI_CTRL_BL_OFFSET; 574 575 /* set clock speed */ 576 ctrl &= ~(0xf << MX51_ECSPI_CTRL_POSTDIV_OFFSET | 577 0xf << MX51_ECSPI_CTRL_PREDIV_OFFSET); 578 ctrl |= mx51_ecspi_clkdiv(spi_imx, t->speed_hz, &clk); 579 spi_imx->spi_bus_clk = clk; 580 581 if (spi_imx->usedma) 582 ctrl |= MX51_ECSPI_CTRL_SMC; 583 584 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); 585 586 /* 587 * Wait until the changes in the configuration register CONFIGREG 588 * propagate into the hardware. It takes exactly one tick of the 589 * SCLK clock, but we will wait two SCLK clock just to be sure. The 590 * effect of the delay it takes for the hardware to apply changes 591 * is noticable if the SCLK clock run very slow. In such a case, if 592 * the polarity of SCLK should be inverted, the GPIO ChipSelect might 593 * be asserted before the SCLK polarity changes, which would disrupt 594 * the SPI communication as the device on the other end would consider 595 * the change of SCLK polarity as a clock tick already. 596 */ 597 delay = (2 * 1000000) / clk; 598 if (likely(delay < 10)) /* SCLK is faster than 100 kHz */ 599 udelay(delay); 600 else /* SCLK is _very_ slow */ 601 usleep_range(delay, delay + 10); 602 603 return 0; 604 } 605 606 static void mx51_setup_wml(struct spi_imx_data *spi_imx) 607 { 608 /* 609 * Configure the DMA register: setup the watermark 610 * and enable DMA request. 611 */ 612 writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) | 613 MX51_ECSPI_DMA_TX_WML(spi_imx->wml) | 614 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) | 615 MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN | 616 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA); 617 } 618 619 static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx) 620 { 621 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR; 622 } 623 624 static void mx51_ecspi_reset(struct spi_imx_data *spi_imx) 625 { 626 /* drain receive buffer */ 627 while (mx51_ecspi_rx_available(spi_imx)) 628 readl(spi_imx->base + MXC_CSPIRXDATA); 629 } 630 631 #define MX31_INTREG_TEEN (1 << 0) 632 #define MX31_INTREG_RREN (1 << 3) 633 634 #define MX31_CSPICTRL_ENABLE (1 << 0) 635 #define MX31_CSPICTRL_MASTER (1 << 1) 636 #define MX31_CSPICTRL_XCH (1 << 2) 637 #define MX31_CSPICTRL_SMC (1 << 3) 638 #define MX31_CSPICTRL_POL (1 << 4) 639 #define MX31_CSPICTRL_PHA (1 << 5) 640 #define MX31_CSPICTRL_SSCTL (1 << 6) 641 #define MX31_CSPICTRL_SSPOL (1 << 7) 642 #define MX31_CSPICTRL_BC_SHIFT 8 643 #define MX35_CSPICTRL_BL_SHIFT 20 644 #define MX31_CSPICTRL_CS_SHIFT 24 645 #define MX35_CSPICTRL_CS_SHIFT 12 646 #define MX31_CSPICTRL_DR_SHIFT 16 647 648 #define MX31_CSPI_DMAREG 0x10 649 #define MX31_DMAREG_RH_DEN (1<<4) 650 #define MX31_DMAREG_TH_DEN (1<<1) 651 652 #define MX31_CSPISTATUS 0x14 653 #define MX31_STATUS_RR (1 << 3) 654 655 #define MX31_CSPI_TESTREG 0x1C 656 #define MX31_TEST_LBC (1 << 14) 657 658 /* These functions also work for the i.MX35, but be aware that 659 * the i.MX35 has a slightly different register layout for bits 660 * we do not use here. 661 */ 662 static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable) 663 { 664 unsigned int val = 0; 665 666 if (enable & MXC_INT_TE) 667 val |= MX31_INTREG_TEEN; 668 if (enable & MXC_INT_RR) 669 val |= MX31_INTREG_RREN; 670 671 writel(val, spi_imx->base + MXC_CSPIINT); 672 } 673 674 static void mx31_trigger(struct spi_imx_data *spi_imx) 675 { 676 unsigned int reg; 677 678 reg = readl(spi_imx->base + MXC_CSPICTRL); 679 reg |= MX31_CSPICTRL_XCH; 680 writel(reg, spi_imx->base + MXC_CSPICTRL); 681 } 682 683 static int mx31_prepare_message(struct spi_imx_data *spi_imx, 684 struct spi_message *msg) 685 { 686 return 0; 687 } 688 689 static int mx31_prepare_transfer(struct spi_imx_data *spi_imx, 690 struct spi_device *spi, 691 struct spi_transfer *t) 692 { 693 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER; 694 unsigned int clk; 695 696 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, t->speed_hz, &clk) << 697 MX31_CSPICTRL_DR_SHIFT; 698 spi_imx->spi_bus_clk = clk; 699 700 if (is_imx35_cspi(spi_imx)) { 701 reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT; 702 reg |= MX31_CSPICTRL_SSCTL; 703 } else { 704 reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT; 705 } 706 707 if (spi->mode & SPI_CPHA) 708 reg |= MX31_CSPICTRL_PHA; 709 if (spi->mode & SPI_CPOL) 710 reg |= MX31_CSPICTRL_POL; 711 if (spi->mode & SPI_CS_HIGH) 712 reg |= MX31_CSPICTRL_SSPOL; 713 if (!gpio_is_valid(spi->cs_gpio)) 714 reg |= (spi->chip_select) << 715 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT : 716 MX31_CSPICTRL_CS_SHIFT); 717 718 if (spi_imx->usedma) 719 reg |= MX31_CSPICTRL_SMC; 720 721 writel(reg, spi_imx->base + MXC_CSPICTRL); 722 723 reg = readl(spi_imx->base + MX31_CSPI_TESTREG); 724 if (spi->mode & SPI_LOOP) 725 reg |= MX31_TEST_LBC; 726 else 727 reg &= ~MX31_TEST_LBC; 728 writel(reg, spi_imx->base + MX31_CSPI_TESTREG); 729 730 if (spi_imx->usedma) { 731 /* 732 * configure DMA requests when RXFIFO is half full and 733 * when TXFIFO is half empty 734 */ 735 writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN, 736 spi_imx->base + MX31_CSPI_DMAREG); 737 } 738 739 return 0; 740 } 741 742 static int mx31_rx_available(struct spi_imx_data *spi_imx) 743 { 744 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; 745 } 746 747 static void mx31_reset(struct spi_imx_data *spi_imx) 748 { 749 /* drain receive buffer */ 750 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR) 751 readl(spi_imx->base + MXC_CSPIRXDATA); 752 } 753 754 #define MX21_INTREG_RR (1 << 4) 755 #define MX21_INTREG_TEEN (1 << 9) 756 #define MX21_INTREG_RREN (1 << 13) 757 758 #define MX21_CSPICTRL_POL (1 << 5) 759 #define MX21_CSPICTRL_PHA (1 << 6) 760 #define MX21_CSPICTRL_SSPOL (1 << 8) 761 #define MX21_CSPICTRL_XCH (1 << 9) 762 #define MX21_CSPICTRL_ENABLE (1 << 10) 763 #define MX21_CSPICTRL_MASTER (1 << 11) 764 #define MX21_CSPICTRL_DR_SHIFT 14 765 #define MX21_CSPICTRL_CS_SHIFT 19 766 767 static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable) 768 { 769 unsigned int val = 0; 770 771 if (enable & MXC_INT_TE) 772 val |= MX21_INTREG_TEEN; 773 if (enable & MXC_INT_RR) 774 val |= MX21_INTREG_RREN; 775 776 writel(val, spi_imx->base + MXC_CSPIINT); 777 } 778 779 static void mx21_trigger(struct spi_imx_data *spi_imx) 780 { 781 unsigned int reg; 782 783 reg = readl(spi_imx->base + MXC_CSPICTRL); 784 reg |= MX21_CSPICTRL_XCH; 785 writel(reg, spi_imx->base + MXC_CSPICTRL); 786 } 787 788 static int mx21_prepare_message(struct spi_imx_data *spi_imx, 789 struct spi_message *msg) 790 { 791 return 0; 792 } 793 794 static int mx21_prepare_transfer(struct spi_imx_data *spi_imx, 795 struct spi_device *spi, 796 struct spi_transfer *t) 797 { 798 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER; 799 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18; 800 unsigned int clk; 801 802 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, t->speed_hz, max, &clk) 803 << MX21_CSPICTRL_DR_SHIFT; 804 spi_imx->spi_bus_clk = clk; 805 806 reg |= spi_imx->bits_per_word - 1; 807 808 if (spi->mode & SPI_CPHA) 809 reg |= MX21_CSPICTRL_PHA; 810 if (spi->mode & SPI_CPOL) 811 reg |= MX21_CSPICTRL_POL; 812 if (spi->mode & SPI_CS_HIGH) 813 reg |= MX21_CSPICTRL_SSPOL; 814 if (!gpio_is_valid(spi->cs_gpio)) 815 reg |= spi->chip_select << MX21_CSPICTRL_CS_SHIFT; 816 817 writel(reg, spi_imx->base + MXC_CSPICTRL); 818 819 return 0; 820 } 821 822 static int mx21_rx_available(struct spi_imx_data *spi_imx) 823 { 824 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR; 825 } 826 827 static void mx21_reset(struct spi_imx_data *spi_imx) 828 { 829 writel(1, spi_imx->base + MXC_RESET); 830 } 831 832 #define MX1_INTREG_RR (1 << 3) 833 #define MX1_INTREG_TEEN (1 << 8) 834 #define MX1_INTREG_RREN (1 << 11) 835 836 #define MX1_CSPICTRL_POL (1 << 4) 837 #define MX1_CSPICTRL_PHA (1 << 5) 838 #define MX1_CSPICTRL_XCH (1 << 8) 839 #define MX1_CSPICTRL_ENABLE (1 << 9) 840 #define MX1_CSPICTRL_MASTER (1 << 10) 841 #define MX1_CSPICTRL_DR_SHIFT 13 842 843 static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable) 844 { 845 unsigned int val = 0; 846 847 if (enable & MXC_INT_TE) 848 val |= MX1_INTREG_TEEN; 849 if (enable & MXC_INT_RR) 850 val |= MX1_INTREG_RREN; 851 852 writel(val, spi_imx->base + MXC_CSPIINT); 853 } 854 855 static void mx1_trigger(struct spi_imx_data *spi_imx) 856 { 857 unsigned int reg; 858 859 reg = readl(spi_imx->base + MXC_CSPICTRL); 860 reg |= MX1_CSPICTRL_XCH; 861 writel(reg, spi_imx->base + MXC_CSPICTRL); 862 } 863 864 static int mx1_prepare_message(struct spi_imx_data *spi_imx, 865 struct spi_message *msg) 866 { 867 return 0; 868 } 869 870 static int mx1_prepare_transfer(struct spi_imx_data *spi_imx, 871 struct spi_device *spi, 872 struct spi_transfer *t) 873 { 874 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER; 875 unsigned int clk; 876 877 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, t->speed_hz, &clk) << 878 MX1_CSPICTRL_DR_SHIFT; 879 spi_imx->spi_bus_clk = clk; 880 881 reg |= spi_imx->bits_per_word - 1; 882 883 if (spi->mode & SPI_CPHA) 884 reg |= MX1_CSPICTRL_PHA; 885 if (spi->mode & SPI_CPOL) 886 reg |= MX1_CSPICTRL_POL; 887 888 writel(reg, spi_imx->base + MXC_CSPICTRL); 889 890 return 0; 891 } 892 893 static int mx1_rx_available(struct spi_imx_data *spi_imx) 894 { 895 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; 896 } 897 898 static void mx1_reset(struct spi_imx_data *spi_imx) 899 { 900 writel(1, spi_imx->base + MXC_RESET); 901 } 902 903 static struct spi_imx_devtype_data imx1_cspi_devtype_data = { 904 .intctrl = mx1_intctrl, 905 .prepare_message = mx1_prepare_message, 906 .prepare_transfer = mx1_prepare_transfer, 907 .trigger = mx1_trigger, 908 .rx_available = mx1_rx_available, 909 .reset = mx1_reset, 910 .fifo_size = 8, 911 .has_dmamode = false, 912 .dynamic_burst = false, 913 .has_slavemode = false, 914 .devtype = IMX1_CSPI, 915 }; 916 917 static struct spi_imx_devtype_data imx21_cspi_devtype_data = { 918 .intctrl = mx21_intctrl, 919 .prepare_message = mx21_prepare_message, 920 .prepare_transfer = mx21_prepare_transfer, 921 .trigger = mx21_trigger, 922 .rx_available = mx21_rx_available, 923 .reset = mx21_reset, 924 .fifo_size = 8, 925 .has_dmamode = false, 926 .dynamic_burst = false, 927 .has_slavemode = false, 928 .devtype = IMX21_CSPI, 929 }; 930 931 static struct spi_imx_devtype_data imx27_cspi_devtype_data = { 932 /* i.mx27 cspi shares the functions with i.mx21 one */ 933 .intctrl = mx21_intctrl, 934 .prepare_message = mx21_prepare_message, 935 .prepare_transfer = mx21_prepare_transfer, 936 .trigger = mx21_trigger, 937 .rx_available = mx21_rx_available, 938 .reset = mx21_reset, 939 .fifo_size = 8, 940 .has_dmamode = false, 941 .dynamic_burst = false, 942 .has_slavemode = false, 943 .devtype = IMX27_CSPI, 944 }; 945 946 static struct spi_imx_devtype_data imx31_cspi_devtype_data = { 947 .intctrl = mx31_intctrl, 948 .prepare_message = mx31_prepare_message, 949 .prepare_transfer = mx31_prepare_transfer, 950 .trigger = mx31_trigger, 951 .rx_available = mx31_rx_available, 952 .reset = mx31_reset, 953 .fifo_size = 8, 954 .has_dmamode = false, 955 .dynamic_burst = false, 956 .has_slavemode = false, 957 .devtype = IMX31_CSPI, 958 }; 959 960 static struct spi_imx_devtype_data imx35_cspi_devtype_data = { 961 /* i.mx35 and later cspi shares the functions with i.mx31 one */ 962 .intctrl = mx31_intctrl, 963 .prepare_message = mx31_prepare_message, 964 .prepare_transfer = mx31_prepare_transfer, 965 .trigger = mx31_trigger, 966 .rx_available = mx31_rx_available, 967 .reset = mx31_reset, 968 .fifo_size = 8, 969 .has_dmamode = true, 970 .dynamic_burst = false, 971 .has_slavemode = false, 972 .devtype = IMX35_CSPI, 973 }; 974 975 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = { 976 .intctrl = mx51_ecspi_intctrl, 977 .prepare_message = mx51_ecspi_prepare_message, 978 .prepare_transfer = mx51_ecspi_prepare_transfer, 979 .trigger = mx51_ecspi_trigger, 980 .rx_available = mx51_ecspi_rx_available, 981 .reset = mx51_ecspi_reset, 982 .setup_wml = mx51_setup_wml, 983 .fifo_size = 64, 984 .has_dmamode = true, 985 .dynamic_burst = true, 986 .has_slavemode = true, 987 .disable = mx51_ecspi_disable, 988 .devtype = IMX51_ECSPI, 989 }; 990 991 static struct spi_imx_devtype_data imx53_ecspi_devtype_data = { 992 .intctrl = mx51_ecspi_intctrl, 993 .prepare_message = mx51_ecspi_prepare_message, 994 .prepare_transfer = mx51_ecspi_prepare_transfer, 995 .trigger = mx51_ecspi_trigger, 996 .rx_available = mx51_ecspi_rx_available, 997 .reset = mx51_ecspi_reset, 998 .fifo_size = 64, 999 .has_dmamode = true, 1000 .has_slavemode = true, 1001 .disable = mx51_ecspi_disable, 1002 .devtype = IMX53_ECSPI, 1003 }; 1004 1005 static const struct platform_device_id spi_imx_devtype[] = { 1006 { 1007 .name = "imx1-cspi", 1008 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data, 1009 }, { 1010 .name = "imx21-cspi", 1011 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data, 1012 }, { 1013 .name = "imx27-cspi", 1014 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data, 1015 }, { 1016 .name = "imx31-cspi", 1017 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data, 1018 }, { 1019 .name = "imx35-cspi", 1020 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data, 1021 }, { 1022 .name = "imx51-ecspi", 1023 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data, 1024 }, { 1025 .name = "imx53-ecspi", 1026 .driver_data = (kernel_ulong_t) &imx53_ecspi_devtype_data, 1027 }, { 1028 /* sentinel */ 1029 } 1030 }; 1031 1032 static const struct of_device_id spi_imx_dt_ids[] = { 1033 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, }, 1034 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, }, 1035 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, }, 1036 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, }, 1037 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, }, 1038 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, }, 1039 { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, }, 1040 { /* sentinel */ } 1041 }; 1042 MODULE_DEVICE_TABLE(of, spi_imx_dt_ids); 1043 1044 static void spi_imx_chipselect(struct spi_device *spi, int is_active) 1045 { 1046 int active = is_active != BITBANG_CS_INACTIVE; 1047 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH); 1048 1049 if (spi->mode & SPI_NO_CS) 1050 return; 1051 1052 if (!gpio_is_valid(spi->cs_gpio)) 1053 return; 1054 1055 gpio_set_value(spi->cs_gpio, dev_is_lowactive ^ active); 1056 } 1057 1058 static void spi_imx_set_burst_len(struct spi_imx_data *spi_imx, int n_bits) 1059 { 1060 u32 ctrl; 1061 1062 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); 1063 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK; 1064 ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET); 1065 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); 1066 } 1067 1068 static void spi_imx_push(struct spi_imx_data *spi_imx) 1069 { 1070 unsigned int burst_len, fifo_words; 1071 1072 if (spi_imx->dynamic_burst) 1073 fifo_words = 4; 1074 else 1075 fifo_words = spi_imx_bytes_per_word(spi_imx->bits_per_word); 1076 /* 1077 * Reload the FIFO when the remaining bytes to be transferred in the 1078 * current burst is 0. This only applies when bits_per_word is a 1079 * multiple of 8. 1080 */ 1081 if (!spi_imx->remainder) { 1082 if (spi_imx->dynamic_burst) { 1083 1084 /* We need to deal unaligned data first */ 1085 burst_len = spi_imx->count % MX51_ECSPI_CTRL_MAX_BURST; 1086 1087 if (!burst_len) 1088 burst_len = MX51_ECSPI_CTRL_MAX_BURST; 1089 1090 spi_imx_set_burst_len(spi_imx, burst_len * 8); 1091 1092 spi_imx->remainder = burst_len; 1093 } else { 1094 spi_imx->remainder = fifo_words; 1095 } 1096 } 1097 1098 while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) { 1099 if (!spi_imx->count) 1100 break; 1101 if (spi_imx->dynamic_burst && 1102 spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder, 1103 fifo_words)) 1104 break; 1105 spi_imx->tx(spi_imx); 1106 spi_imx->txfifo++; 1107 } 1108 1109 if (!spi_imx->slave_mode) 1110 spi_imx->devtype_data->trigger(spi_imx); 1111 } 1112 1113 static irqreturn_t spi_imx_isr(int irq, void *dev_id) 1114 { 1115 struct spi_imx_data *spi_imx = dev_id; 1116 1117 while (spi_imx->txfifo && 1118 spi_imx->devtype_data->rx_available(spi_imx)) { 1119 spi_imx->rx(spi_imx); 1120 spi_imx->txfifo--; 1121 } 1122 1123 if (spi_imx->count) { 1124 spi_imx_push(spi_imx); 1125 return IRQ_HANDLED; 1126 } 1127 1128 if (spi_imx->txfifo) { 1129 /* No data left to push, but still waiting for rx data, 1130 * enable receive data available interrupt. 1131 */ 1132 spi_imx->devtype_data->intctrl( 1133 spi_imx, MXC_INT_RR); 1134 return IRQ_HANDLED; 1135 } 1136 1137 spi_imx->devtype_data->intctrl(spi_imx, 0); 1138 complete(&spi_imx->xfer_done); 1139 1140 return IRQ_HANDLED; 1141 } 1142 1143 static int spi_imx_dma_configure(struct spi_master *master) 1144 { 1145 int ret; 1146 enum dma_slave_buswidth buswidth; 1147 struct dma_slave_config rx = {}, tx = {}; 1148 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 1149 1150 switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) { 1151 case 4: 1152 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES; 1153 break; 1154 case 2: 1155 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES; 1156 break; 1157 case 1: 1158 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE; 1159 break; 1160 default: 1161 return -EINVAL; 1162 } 1163 1164 tx.direction = DMA_MEM_TO_DEV; 1165 tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA; 1166 tx.dst_addr_width = buswidth; 1167 tx.dst_maxburst = spi_imx->wml; 1168 ret = dmaengine_slave_config(master->dma_tx, &tx); 1169 if (ret) { 1170 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret); 1171 return ret; 1172 } 1173 1174 rx.direction = DMA_DEV_TO_MEM; 1175 rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA; 1176 rx.src_addr_width = buswidth; 1177 rx.src_maxburst = spi_imx->wml; 1178 ret = dmaengine_slave_config(master->dma_rx, &rx); 1179 if (ret) { 1180 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret); 1181 return ret; 1182 } 1183 1184 return 0; 1185 } 1186 1187 static int spi_imx_setupxfer(struct spi_device *spi, 1188 struct spi_transfer *t) 1189 { 1190 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 1191 1192 if (!t) 1193 return 0; 1194 1195 spi_imx->bits_per_word = t->bits_per_word; 1196 1197 /* 1198 * Initialize the functions for transfer. To transfer non byte-aligned 1199 * words, we have to use multiple word-size bursts, we can't use 1200 * dynamic_burst in that case. 1201 */ 1202 if (spi_imx->devtype_data->dynamic_burst && !spi_imx->slave_mode && 1203 (spi_imx->bits_per_word == 8 || 1204 spi_imx->bits_per_word == 16 || 1205 spi_imx->bits_per_word == 32)) { 1206 1207 spi_imx->rx = spi_imx_buf_rx_swap; 1208 spi_imx->tx = spi_imx_buf_tx_swap; 1209 spi_imx->dynamic_burst = 1; 1210 1211 } else { 1212 if (spi_imx->bits_per_word <= 8) { 1213 spi_imx->rx = spi_imx_buf_rx_u8; 1214 spi_imx->tx = spi_imx_buf_tx_u8; 1215 } else if (spi_imx->bits_per_word <= 16) { 1216 spi_imx->rx = spi_imx_buf_rx_u16; 1217 spi_imx->tx = spi_imx_buf_tx_u16; 1218 } else { 1219 spi_imx->rx = spi_imx_buf_rx_u32; 1220 spi_imx->tx = spi_imx_buf_tx_u32; 1221 } 1222 spi_imx->dynamic_burst = 0; 1223 } 1224 1225 if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t)) 1226 spi_imx->usedma = 1; 1227 else 1228 spi_imx->usedma = 0; 1229 1230 if (is_imx53_ecspi(spi_imx) && spi_imx->slave_mode) { 1231 spi_imx->rx = mx53_ecspi_rx_slave; 1232 spi_imx->tx = mx53_ecspi_tx_slave; 1233 spi_imx->slave_burst = t->len; 1234 } 1235 1236 spi_imx->devtype_data->prepare_transfer(spi_imx, spi, t); 1237 1238 return 0; 1239 } 1240 1241 static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx) 1242 { 1243 struct spi_master *master = spi_imx->bitbang.master; 1244 1245 if (master->dma_rx) { 1246 dma_release_channel(master->dma_rx); 1247 master->dma_rx = NULL; 1248 } 1249 1250 if (master->dma_tx) { 1251 dma_release_channel(master->dma_tx); 1252 master->dma_tx = NULL; 1253 } 1254 } 1255 1256 static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx, 1257 struct spi_master *master) 1258 { 1259 int ret; 1260 1261 /* use pio mode for i.mx6dl chip TKT238285 */ 1262 if (of_machine_is_compatible("fsl,imx6dl")) 1263 return 0; 1264 1265 spi_imx->wml = spi_imx->devtype_data->fifo_size / 2; 1266 1267 /* Prepare for TX DMA: */ 1268 master->dma_tx = dma_request_slave_channel_reason(dev, "tx"); 1269 if (IS_ERR(master->dma_tx)) { 1270 ret = PTR_ERR(master->dma_tx); 1271 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret); 1272 master->dma_tx = NULL; 1273 goto err; 1274 } 1275 1276 /* Prepare for RX : */ 1277 master->dma_rx = dma_request_slave_channel_reason(dev, "rx"); 1278 if (IS_ERR(master->dma_rx)) { 1279 ret = PTR_ERR(master->dma_rx); 1280 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret); 1281 master->dma_rx = NULL; 1282 goto err; 1283 } 1284 1285 init_completion(&spi_imx->dma_rx_completion); 1286 init_completion(&spi_imx->dma_tx_completion); 1287 master->can_dma = spi_imx_can_dma; 1288 master->max_dma_len = MAX_SDMA_BD_BYTES; 1289 spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX | 1290 SPI_MASTER_MUST_TX; 1291 1292 return 0; 1293 err: 1294 spi_imx_sdma_exit(spi_imx); 1295 return ret; 1296 } 1297 1298 static void spi_imx_dma_rx_callback(void *cookie) 1299 { 1300 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie; 1301 1302 complete(&spi_imx->dma_rx_completion); 1303 } 1304 1305 static void spi_imx_dma_tx_callback(void *cookie) 1306 { 1307 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie; 1308 1309 complete(&spi_imx->dma_tx_completion); 1310 } 1311 1312 static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size) 1313 { 1314 unsigned long timeout = 0; 1315 1316 /* Time with actual data transfer and CS change delay related to HW */ 1317 timeout = (8 + 4) * size / spi_imx->spi_bus_clk; 1318 1319 /* Add extra second for scheduler related activities */ 1320 timeout += 1; 1321 1322 /* Double calculated timeout */ 1323 return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC); 1324 } 1325 1326 static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx, 1327 struct spi_transfer *transfer) 1328 { 1329 struct dma_async_tx_descriptor *desc_tx, *desc_rx; 1330 unsigned long transfer_timeout; 1331 unsigned long timeout; 1332 struct spi_master *master = spi_imx->bitbang.master; 1333 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg; 1334 struct scatterlist *last_sg = sg_last(rx->sgl, rx->nents); 1335 unsigned int bytes_per_word, i; 1336 int ret; 1337 1338 /* Get the right burst length from the last sg to ensure no tail data */ 1339 bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word); 1340 for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) { 1341 if (!(sg_dma_len(last_sg) % (i * bytes_per_word))) 1342 break; 1343 } 1344 /* Use 1 as wml in case no available burst length got */ 1345 if (i == 0) 1346 i = 1; 1347 1348 spi_imx->wml = i; 1349 1350 ret = spi_imx_dma_configure(master); 1351 if (ret) 1352 return ret; 1353 1354 if (!spi_imx->devtype_data->setup_wml) { 1355 dev_err(spi_imx->dev, "No setup_wml()?\n"); 1356 return -EINVAL; 1357 } 1358 spi_imx->devtype_data->setup_wml(spi_imx); 1359 1360 /* 1361 * The TX DMA setup starts the transfer, so make sure RX is configured 1362 * before TX. 1363 */ 1364 desc_rx = dmaengine_prep_slave_sg(master->dma_rx, 1365 rx->sgl, rx->nents, DMA_DEV_TO_MEM, 1366 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1367 if (!desc_rx) 1368 return -EINVAL; 1369 1370 desc_rx->callback = spi_imx_dma_rx_callback; 1371 desc_rx->callback_param = (void *)spi_imx; 1372 dmaengine_submit(desc_rx); 1373 reinit_completion(&spi_imx->dma_rx_completion); 1374 dma_async_issue_pending(master->dma_rx); 1375 1376 desc_tx = dmaengine_prep_slave_sg(master->dma_tx, 1377 tx->sgl, tx->nents, DMA_MEM_TO_DEV, 1378 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1379 if (!desc_tx) { 1380 dmaengine_terminate_all(master->dma_tx); 1381 return -EINVAL; 1382 } 1383 1384 desc_tx->callback = spi_imx_dma_tx_callback; 1385 desc_tx->callback_param = (void *)spi_imx; 1386 dmaengine_submit(desc_tx); 1387 reinit_completion(&spi_imx->dma_tx_completion); 1388 dma_async_issue_pending(master->dma_tx); 1389 1390 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); 1391 1392 /* Wait SDMA to finish the data transfer.*/ 1393 timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion, 1394 transfer_timeout); 1395 if (!timeout) { 1396 dev_err(spi_imx->dev, "I/O Error in DMA TX\n"); 1397 dmaengine_terminate_all(master->dma_tx); 1398 dmaengine_terminate_all(master->dma_rx); 1399 return -ETIMEDOUT; 1400 } 1401 1402 timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion, 1403 transfer_timeout); 1404 if (!timeout) { 1405 dev_err(&master->dev, "I/O Error in DMA RX\n"); 1406 spi_imx->devtype_data->reset(spi_imx); 1407 dmaengine_terminate_all(master->dma_rx); 1408 return -ETIMEDOUT; 1409 } 1410 1411 return transfer->len; 1412 } 1413 1414 static int spi_imx_pio_transfer(struct spi_device *spi, 1415 struct spi_transfer *transfer) 1416 { 1417 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 1418 unsigned long transfer_timeout; 1419 unsigned long timeout; 1420 1421 spi_imx->tx_buf = transfer->tx_buf; 1422 spi_imx->rx_buf = transfer->rx_buf; 1423 spi_imx->count = transfer->len; 1424 spi_imx->txfifo = 0; 1425 spi_imx->remainder = 0; 1426 1427 reinit_completion(&spi_imx->xfer_done); 1428 1429 spi_imx_push(spi_imx); 1430 1431 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE); 1432 1433 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); 1434 1435 timeout = wait_for_completion_timeout(&spi_imx->xfer_done, 1436 transfer_timeout); 1437 if (!timeout) { 1438 dev_err(&spi->dev, "I/O Error in PIO\n"); 1439 spi_imx->devtype_data->reset(spi_imx); 1440 return -ETIMEDOUT; 1441 } 1442 1443 return transfer->len; 1444 } 1445 1446 static int spi_imx_pio_transfer_slave(struct spi_device *spi, 1447 struct spi_transfer *transfer) 1448 { 1449 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 1450 int ret = transfer->len; 1451 1452 if (is_imx53_ecspi(spi_imx) && 1453 transfer->len > MX53_MAX_TRANSFER_BYTES) { 1454 dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n", 1455 MX53_MAX_TRANSFER_BYTES); 1456 return -EMSGSIZE; 1457 } 1458 1459 spi_imx->tx_buf = transfer->tx_buf; 1460 spi_imx->rx_buf = transfer->rx_buf; 1461 spi_imx->count = transfer->len; 1462 spi_imx->txfifo = 0; 1463 spi_imx->remainder = 0; 1464 1465 reinit_completion(&spi_imx->xfer_done); 1466 spi_imx->slave_aborted = false; 1467 1468 spi_imx_push(spi_imx); 1469 1470 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR); 1471 1472 if (wait_for_completion_interruptible(&spi_imx->xfer_done) || 1473 spi_imx->slave_aborted) { 1474 dev_dbg(&spi->dev, "interrupted\n"); 1475 ret = -EINTR; 1476 } 1477 1478 /* ecspi has a HW issue when works in Slave mode, 1479 * after 64 words writtern to TXFIFO, even TXFIFO becomes empty, 1480 * ECSPI_TXDATA keeps shift out the last word data, 1481 * so we have to disable ECSPI when in slave mode after the 1482 * transfer completes 1483 */ 1484 if (spi_imx->devtype_data->disable) 1485 spi_imx->devtype_data->disable(spi_imx); 1486 1487 return ret; 1488 } 1489 1490 static int spi_imx_transfer(struct spi_device *spi, 1491 struct spi_transfer *transfer) 1492 { 1493 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 1494 1495 /* flush rxfifo before transfer */ 1496 while (spi_imx->devtype_data->rx_available(spi_imx)) 1497 spi_imx->rx(spi_imx); 1498 1499 if (spi_imx->slave_mode) 1500 return spi_imx_pio_transfer_slave(spi, transfer); 1501 1502 if (spi_imx->usedma) 1503 return spi_imx_dma_transfer(spi_imx, transfer); 1504 else 1505 return spi_imx_pio_transfer(spi, transfer); 1506 } 1507 1508 static int spi_imx_setup(struct spi_device *spi) 1509 { 1510 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__, 1511 spi->mode, spi->bits_per_word, spi->max_speed_hz); 1512 1513 if (spi->mode & SPI_NO_CS) 1514 return 0; 1515 1516 if (gpio_is_valid(spi->cs_gpio)) 1517 gpio_direction_output(spi->cs_gpio, 1518 spi->mode & SPI_CS_HIGH ? 0 : 1); 1519 1520 spi_imx_chipselect(spi, BITBANG_CS_INACTIVE); 1521 1522 return 0; 1523 } 1524 1525 static void spi_imx_cleanup(struct spi_device *spi) 1526 { 1527 } 1528 1529 static int 1530 spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg) 1531 { 1532 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 1533 int ret; 1534 1535 ret = clk_enable(spi_imx->clk_per); 1536 if (ret) 1537 return ret; 1538 1539 ret = clk_enable(spi_imx->clk_ipg); 1540 if (ret) { 1541 clk_disable(spi_imx->clk_per); 1542 return ret; 1543 } 1544 1545 ret = spi_imx->devtype_data->prepare_message(spi_imx, msg); 1546 if (ret) { 1547 clk_disable(spi_imx->clk_ipg); 1548 clk_disable(spi_imx->clk_per); 1549 } 1550 1551 return ret; 1552 } 1553 1554 static int 1555 spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg) 1556 { 1557 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 1558 1559 clk_disable(spi_imx->clk_ipg); 1560 clk_disable(spi_imx->clk_per); 1561 return 0; 1562 } 1563 1564 static int spi_imx_slave_abort(struct spi_master *master) 1565 { 1566 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 1567 1568 spi_imx->slave_aborted = true; 1569 complete(&spi_imx->xfer_done); 1570 1571 return 0; 1572 } 1573 1574 static int spi_imx_probe(struct platform_device *pdev) 1575 { 1576 struct device_node *np = pdev->dev.of_node; 1577 const struct of_device_id *of_id = 1578 of_match_device(spi_imx_dt_ids, &pdev->dev); 1579 struct spi_imx_master *mxc_platform_info = 1580 dev_get_platdata(&pdev->dev); 1581 struct spi_master *master; 1582 struct spi_imx_data *spi_imx; 1583 struct resource *res; 1584 int i, ret, irq, spi_drctl; 1585 const struct spi_imx_devtype_data *devtype_data = of_id ? of_id->data : 1586 (struct spi_imx_devtype_data *)pdev->id_entry->driver_data; 1587 bool slave_mode; 1588 1589 if (!np && !mxc_platform_info) { 1590 dev_err(&pdev->dev, "can't get the platform data\n"); 1591 return -EINVAL; 1592 } 1593 1594 slave_mode = devtype_data->has_slavemode && 1595 of_property_read_bool(np, "spi-slave"); 1596 if (slave_mode) 1597 master = spi_alloc_slave(&pdev->dev, 1598 sizeof(struct spi_imx_data)); 1599 else 1600 master = spi_alloc_master(&pdev->dev, 1601 sizeof(struct spi_imx_data)); 1602 if (!master) 1603 return -ENOMEM; 1604 1605 ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl); 1606 if ((ret < 0) || (spi_drctl >= 0x3)) { 1607 /* '11' is reserved */ 1608 spi_drctl = 0; 1609 } 1610 1611 platform_set_drvdata(pdev, master); 1612 1613 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); 1614 master->bus_num = np ? -1 : pdev->id; 1615 1616 spi_imx = spi_master_get_devdata(master); 1617 spi_imx->bitbang.master = master; 1618 spi_imx->dev = &pdev->dev; 1619 spi_imx->slave_mode = slave_mode; 1620 1621 spi_imx->devtype_data = devtype_data; 1622 1623 /* Get number of chip selects, either platform data or OF */ 1624 if (mxc_platform_info) { 1625 master->num_chipselect = mxc_platform_info->num_chipselect; 1626 if (mxc_platform_info->chipselect) { 1627 master->cs_gpios = devm_kcalloc(&master->dev, 1628 master->num_chipselect, sizeof(int), 1629 GFP_KERNEL); 1630 if (!master->cs_gpios) 1631 return -ENOMEM; 1632 1633 for (i = 0; i < master->num_chipselect; i++) 1634 master->cs_gpios[i] = mxc_platform_info->chipselect[i]; 1635 } 1636 } else { 1637 u32 num_cs; 1638 1639 if (!of_property_read_u32(np, "num-cs", &num_cs)) 1640 master->num_chipselect = num_cs; 1641 /* If not preset, default value of 1 is used */ 1642 } 1643 1644 spi_imx->bitbang.chipselect = spi_imx_chipselect; 1645 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer; 1646 spi_imx->bitbang.txrx_bufs = spi_imx_transfer; 1647 spi_imx->bitbang.master->setup = spi_imx_setup; 1648 spi_imx->bitbang.master->cleanup = spi_imx_cleanup; 1649 spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message; 1650 spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message; 1651 spi_imx->bitbang.master->slave_abort = spi_imx_slave_abort; 1652 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \ 1653 | SPI_NO_CS; 1654 if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) || 1655 is_imx53_ecspi(spi_imx)) 1656 spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY; 1657 1658 spi_imx->spi_drctl = spi_drctl; 1659 1660 init_completion(&spi_imx->xfer_done); 1661 1662 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1663 spi_imx->base = devm_ioremap_resource(&pdev->dev, res); 1664 if (IS_ERR(spi_imx->base)) { 1665 ret = PTR_ERR(spi_imx->base); 1666 goto out_master_put; 1667 } 1668 spi_imx->base_phys = res->start; 1669 1670 irq = platform_get_irq(pdev, 0); 1671 if (irq < 0) { 1672 ret = irq; 1673 goto out_master_put; 1674 } 1675 1676 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0, 1677 dev_name(&pdev->dev), spi_imx); 1678 if (ret) { 1679 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret); 1680 goto out_master_put; 1681 } 1682 1683 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1684 if (IS_ERR(spi_imx->clk_ipg)) { 1685 ret = PTR_ERR(spi_imx->clk_ipg); 1686 goto out_master_put; 1687 } 1688 1689 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per"); 1690 if (IS_ERR(spi_imx->clk_per)) { 1691 ret = PTR_ERR(spi_imx->clk_per); 1692 goto out_master_put; 1693 } 1694 1695 ret = clk_prepare_enable(spi_imx->clk_per); 1696 if (ret) 1697 goto out_master_put; 1698 1699 ret = clk_prepare_enable(spi_imx->clk_ipg); 1700 if (ret) 1701 goto out_put_per; 1702 1703 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per); 1704 /* 1705 * Only validated on i.mx35 and i.mx6 now, can remove the constraint 1706 * if validated on other chips. 1707 */ 1708 if (spi_imx->devtype_data->has_dmamode) { 1709 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master); 1710 if (ret == -EPROBE_DEFER) 1711 goto out_clk_put; 1712 1713 if (ret < 0) 1714 dev_err(&pdev->dev, "dma setup error %d, use pio\n", 1715 ret); 1716 } 1717 1718 spi_imx->devtype_data->reset(spi_imx); 1719 1720 spi_imx->devtype_data->intctrl(spi_imx, 0); 1721 1722 master->dev.of_node = pdev->dev.of_node; 1723 ret = spi_bitbang_start(&spi_imx->bitbang); 1724 if (ret) { 1725 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret); 1726 goto out_clk_put; 1727 } 1728 1729 /* Request GPIO CS lines, if any */ 1730 if (!spi_imx->slave_mode && master->cs_gpios) { 1731 for (i = 0; i < master->num_chipselect; i++) { 1732 if (!gpio_is_valid(master->cs_gpios[i])) 1733 continue; 1734 1735 ret = devm_gpio_request(&pdev->dev, 1736 master->cs_gpios[i], 1737 DRIVER_NAME); 1738 if (ret) { 1739 dev_err(&pdev->dev, "Can't get CS GPIO %i\n", 1740 master->cs_gpios[i]); 1741 goto out_spi_bitbang; 1742 } 1743 } 1744 } 1745 1746 dev_info(&pdev->dev, "probed\n"); 1747 1748 clk_disable(spi_imx->clk_ipg); 1749 clk_disable(spi_imx->clk_per); 1750 return ret; 1751 1752 out_spi_bitbang: 1753 spi_bitbang_stop(&spi_imx->bitbang); 1754 out_clk_put: 1755 clk_disable_unprepare(spi_imx->clk_ipg); 1756 out_put_per: 1757 clk_disable_unprepare(spi_imx->clk_per); 1758 out_master_put: 1759 spi_master_put(master); 1760 1761 return ret; 1762 } 1763 1764 static int spi_imx_remove(struct platform_device *pdev) 1765 { 1766 struct spi_master *master = platform_get_drvdata(pdev); 1767 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 1768 int ret; 1769 1770 spi_bitbang_stop(&spi_imx->bitbang); 1771 1772 ret = clk_enable(spi_imx->clk_per); 1773 if (ret) 1774 return ret; 1775 1776 ret = clk_enable(spi_imx->clk_ipg); 1777 if (ret) { 1778 clk_disable(spi_imx->clk_per); 1779 return ret; 1780 } 1781 1782 writel(0, spi_imx->base + MXC_CSPICTRL); 1783 clk_disable_unprepare(spi_imx->clk_ipg); 1784 clk_disable_unprepare(spi_imx->clk_per); 1785 spi_imx_sdma_exit(spi_imx); 1786 spi_master_put(master); 1787 1788 return 0; 1789 } 1790 1791 static struct platform_driver spi_imx_driver = { 1792 .driver = { 1793 .name = DRIVER_NAME, 1794 .of_match_table = spi_imx_dt_ids, 1795 }, 1796 .id_table = spi_imx_devtype, 1797 .probe = spi_imx_probe, 1798 .remove = spi_imx_remove, 1799 }; 1800 module_platform_driver(spi_imx_driver); 1801 1802 MODULE_DESCRIPTION("SPI Controller driver"); 1803 MODULE_AUTHOR("Sascha Hauer, Pengutronix"); 1804 MODULE_LICENSE("GPL"); 1805 MODULE_ALIAS("platform:" DRIVER_NAME); 1806