1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 3 // Copyright (C) 2008 Juergen Beisert 4 5 #include <linux/clk.h> 6 #include <linux/completion.h> 7 #include <linux/delay.h> 8 #include <linux/dmaengine.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/err.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/irq.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/pinctrl/consumer.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/slab.h> 20 #include <linux/spi/spi.h> 21 #include <linux/spi/spi_bitbang.h> 22 #include <linux/types.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/property.h> 26 27 #include <linux/platform_data/dma-imx.h> 28 29 #define DRIVER_NAME "spi_imx" 30 31 static bool use_dma = true; 32 module_param(use_dma, bool, 0644); 33 MODULE_PARM_DESC(use_dma, "Enable usage of DMA when available (default)"); 34 35 #define MXC_RPM_TIMEOUT 2000 /* 2000ms */ 36 37 #define MXC_CSPIRXDATA 0x00 38 #define MXC_CSPITXDATA 0x04 39 #define MXC_CSPICTRL 0x08 40 #define MXC_CSPIINT 0x0c 41 #define MXC_RESET 0x1c 42 43 /* generic defines to abstract from the different register layouts */ 44 #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */ 45 #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */ 46 #define MXC_INT_RDR BIT(4) /* Receive date threshold interrupt */ 47 48 /* The maximum bytes that a sdma BD can transfer. */ 49 #define MAX_SDMA_BD_BYTES (1 << 15) 50 #define MX51_ECSPI_CTRL_MAX_BURST 512 51 /* The maximum bytes that IMX53_ECSPI can transfer in slave mode.*/ 52 #define MX53_MAX_TRANSFER_BYTES 512 53 54 enum spi_imx_devtype { 55 IMX1_CSPI, 56 IMX21_CSPI, 57 IMX27_CSPI, 58 IMX31_CSPI, 59 IMX35_CSPI, /* CSPI on all i.mx except above */ 60 IMX51_ECSPI, /* ECSPI on i.mx51 */ 61 IMX53_ECSPI, /* ECSPI on i.mx53 and later */ 62 }; 63 64 struct spi_imx_data; 65 66 struct spi_imx_devtype_data { 67 void (*intctrl)(struct spi_imx_data *, int); 68 int (*prepare_message)(struct spi_imx_data *, struct spi_message *); 69 int (*prepare_transfer)(struct spi_imx_data *, struct spi_device *); 70 void (*trigger)(struct spi_imx_data *); 71 int (*rx_available)(struct spi_imx_data *); 72 void (*reset)(struct spi_imx_data *); 73 void (*setup_wml)(struct spi_imx_data *); 74 void (*disable)(struct spi_imx_data *); 75 void (*disable_dma)(struct spi_imx_data *); 76 bool has_dmamode; 77 bool has_slavemode; 78 unsigned int fifo_size; 79 bool dynamic_burst; 80 enum spi_imx_devtype devtype; 81 }; 82 83 struct spi_imx_data { 84 struct spi_bitbang bitbang; 85 struct device *dev; 86 87 struct completion xfer_done; 88 void __iomem *base; 89 unsigned long base_phys; 90 91 struct clk *clk_per; 92 struct clk *clk_ipg; 93 unsigned long spi_clk; 94 unsigned int spi_bus_clk; 95 96 unsigned int bits_per_word; 97 unsigned int spi_drctl; 98 99 unsigned int count, remainder; 100 void (*tx)(struct spi_imx_data *); 101 void (*rx)(struct spi_imx_data *); 102 void *rx_buf; 103 const void *tx_buf; 104 unsigned int txfifo; /* number of words pushed in tx FIFO */ 105 unsigned int dynamic_burst; 106 107 /* Slave mode */ 108 bool slave_mode; 109 bool slave_aborted; 110 unsigned int slave_burst; 111 112 /* DMA */ 113 bool usedma; 114 u32 wml; 115 struct completion dma_rx_completion; 116 struct completion dma_tx_completion; 117 118 const struct spi_imx_devtype_data *devtype_data; 119 }; 120 121 static inline int is_imx27_cspi(struct spi_imx_data *d) 122 { 123 return d->devtype_data->devtype == IMX27_CSPI; 124 } 125 126 static inline int is_imx35_cspi(struct spi_imx_data *d) 127 { 128 return d->devtype_data->devtype == IMX35_CSPI; 129 } 130 131 static inline int is_imx51_ecspi(struct spi_imx_data *d) 132 { 133 return d->devtype_data->devtype == IMX51_ECSPI; 134 } 135 136 static inline int is_imx53_ecspi(struct spi_imx_data *d) 137 { 138 return d->devtype_data->devtype == IMX53_ECSPI; 139 } 140 141 #define MXC_SPI_BUF_RX(type) \ 142 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \ 143 { \ 144 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \ 145 \ 146 if (spi_imx->rx_buf) { \ 147 *(type *)spi_imx->rx_buf = val; \ 148 spi_imx->rx_buf += sizeof(type); \ 149 } \ 150 \ 151 spi_imx->remainder -= sizeof(type); \ 152 } 153 154 #define MXC_SPI_BUF_TX(type) \ 155 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \ 156 { \ 157 type val = 0; \ 158 \ 159 if (spi_imx->tx_buf) { \ 160 val = *(type *)spi_imx->tx_buf; \ 161 spi_imx->tx_buf += sizeof(type); \ 162 } \ 163 \ 164 spi_imx->count -= sizeof(type); \ 165 \ 166 writel(val, spi_imx->base + MXC_CSPITXDATA); \ 167 } 168 169 MXC_SPI_BUF_RX(u8) 170 MXC_SPI_BUF_TX(u8) 171 MXC_SPI_BUF_RX(u16) 172 MXC_SPI_BUF_TX(u16) 173 MXC_SPI_BUF_RX(u32) 174 MXC_SPI_BUF_TX(u32) 175 176 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set 177 * (which is currently not the case in this driver) 178 */ 179 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192, 180 256, 384, 512, 768, 1024}; 181 182 /* MX21, MX27 */ 183 static unsigned int spi_imx_clkdiv_1(unsigned int fin, 184 unsigned int fspi, unsigned int max, unsigned int *fres) 185 { 186 int i; 187 188 for (i = 2; i < max; i++) 189 if (fspi * mxc_clkdivs[i] >= fin) 190 break; 191 192 *fres = fin / mxc_clkdivs[i]; 193 return i; 194 } 195 196 /* MX1, MX31, MX35, MX51 CSPI */ 197 static unsigned int spi_imx_clkdiv_2(unsigned int fin, 198 unsigned int fspi, unsigned int *fres) 199 { 200 int i, div = 4; 201 202 for (i = 0; i < 7; i++) { 203 if (fspi * div >= fin) 204 goto out; 205 div <<= 1; 206 } 207 208 out: 209 *fres = fin / div; 210 return i; 211 } 212 213 static int spi_imx_bytes_per_word(const int bits_per_word) 214 { 215 if (bits_per_word <= 8) 216 return 1; 217 else if (bits_per_word <= 16) 218 return 2; 219 else 220 return 4; 221 } 222 223 static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi, 224 struct spi_transfer *transfer) 225 { 226 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 227 228 if (!use_dma || master->fallback) 229 return false; 230 231 if (!master->dma_rx) 232 return false; 233 234 if (spi_imx->slave_mode) 235 return false; 236 237 if (transfer->len < spi_imx->devtype_data->fifo_size) 238 return false; 239 240 spi_imx->dynamic_burst = 0; 241 242 return true; 243 } 244 245 #define MX51_ECSPI_CTRL 0x08 246 #define MX51_ECSPI_CTRL_ENABLE (1 << 0) 247 #define MX51_ECSPI_CTRL_XCH (1 << 2) 248 #define MX51_ECSPI_CTRL_SMC (1 << 3) 249 #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4) 250 #define MX51_ECSPI_CTRL_DRCTL(drctl) ((drctl) << 16) 251 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8 252 #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12 253 #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18) 254 #define MX51_ECSPI_CTRL_BL_OFFSET 20 255 #define MX51_ECSPI_CTRL_BL_MASK (0xfff << 20) 256 257 #define MX51_ECSPI_CONFIG 0x0c 258 #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0)) 259 #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4)) 260 #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8)) 261 #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12)) 262 #define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20)) 263 264 #define MX51_ECSPI_INT 0x10 265 #define MX51_ECSPI_INT_TEEN (1 << 0) 266 #define MX51_ECSPI_INT_RREN (1 << 3) 267 #define MX51_ECSPI_INT_RDREN (1 << 4) 268 269 #define MX51_ECSPI_DMA 0x14 270 #define MX51_ECSPI_DMA_TX_WML(wml) ((wml) & 0x3f) 271 #define MX51_ECSPI_DMA_RX_WML(wml) (((wml) & 0x3f) << 16) 272 #define MX51_ECSPI_DMA_RXT_WML(wml) (((wml) & 0x3f) << 24) 273 274 #define MX51_ECSPI_DMA_TEDEN (1 << 7) 275 #define MX51_ECSPI_DMA_RXDEN (1 << 23) 276 #define MX51_ECSPI_DMA_RXTDEN (1 << 31) 277 278 #define MX51_ECSPI_STAT 0x18 279 #define MX51_ECSPI_STAT_RR (1 << 3) 280 281 #define MX51_ECSPI_TESTREG 0x20 282 #define MX51_ECSPI_TESTREG_LBC BIT(31) 283 284 static void spi_imx_buf_rx_swap_u32(struct spi_imx_data *spi_imx) 285 { 286 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); 287 #ifdef __LITTLE_ENDIAN 288 unsigned int bytes_per_word; 289 #endif 290 291 if (spi_imx->rx_buf) { 292 #ifdef __LITTLE_ENDIAN 293 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); 294 if (bytes_per_word == 1) 295 val = cpu_to_be32(val); 296 else if (bytes_per_word == 2) 297 val = (val << 16) | (val >> 16); 298 #endif 299 *(u32 *)spi_imx->rx_buf = val; 300 spi_imx->rx_buf += sizeof(u32); 301 } 302 303 spi_imx->remainder -= sizeof(u32); 304 } 305 306 static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx) 307 { 308 int unaligned; 309 u32 val; 310 311 unaligned = spi_imx->remainder % 4; 312 313 if (!unaligned) { 314 spi_imx_buf_rx_swap_u32(spi_imx); 315 return; 316 } 317 318 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) { 319 spi_imx_buf_rx_u16(spi_imx); 320 return; 321 } 322 323 val = readl(spi_imx->base + MXC_CSPIRXDATA); 324 325 while (unaligned--) { 326 if (spi_imx->rx_buf) { 327 *(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff; 328 spi_imx->rx_buf++; 329 } 330 spi_imx->remainder--; 331 } 332 } 333 334 static void spi_imx_buf_tx_swap_u32(struct spi_imx_data *spi_imx) 335 { 336 u32 val = 0; 337 #ifdef __LITTLE_ENDIAN 338 unsigned int bytes_per_word; 339 #endif 340 341 if (spi_imx->tx_buf) { 342 val = *(u32 *)spi_imx->tx_buf; 343 spi_imx->tx_buf += sizeof(u32); 344 } 345 346 spi_imx->count -= sizeof(u32); 347 #ifdef __LITTLE_ENDIAN 348 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); 349 350 if (bytes_per_word == 1) 351 val = cpu_to_be32(val); 352 else if (bytes_per_word == 2) 353 val = (val << 16) | (val >> 16); 354 #endif 355 writel(val, spi_imx->base + MXC_CSPITXDATA); 356 } 357 358 static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx) 359 { 360 int unaligned; 361 u32 val = 0; 362 363 unaligned = spi_imx->count % 4; 364 365 if (!unaligned) { 366 spi_imx_buf_tx_swap_u32(spi_imx); 367 return; 368 } 369 370 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) { 371 spi_imx_buf_tx_u16(spi_imx); 372 return; 373 } 374 375 while (unaligned--) { 376 if (spi_imx->tx_buf) { 377 val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned); 378 spi_imx->tx_buf++; 379 } 380 spi_imx->count--; 381 } 382 383 writel(val, spi_imx->base + MXC_CSPITXDATA); 384 } 385 386 static void mx53_ecspi_rx_slave(struct spi_imx_data *spi_imx) 387 { 388 u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA)); 389 390 if (spi_imx->rx_buf) { 391 int n_bytes = spi_imx->slave_burst % sizeof(val); 392 393 if (!n_bytes) 394 n_bytes = sizeof(val); 395 396 memcpy(spi_imx->rx_buf, 397 ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes); 398 399 spi_imx->rx_buf += n_bytes; 400 spi_imx->slave_burst -= n_bytes; 401 } 402 403 spi_imx->remainder -= sizeof(u32); 404 } 405 406 static void mx53_ecspi_tx_slave(struct spi_imx_data *spi_imx) 407 { 408 u32 val = 0; 409 int n_bytes = spi_imx->count % sizeof(val); 410 411 if (!n_bytes) 412 n_bytes = sizeof(val); 413 414 if (spi_imx->tx_buf) { 415 memcpy(((u8 *)&val) + sizeof(val) - n_bytes, 416 spi_imx->tx_buf, n_bytes); 417 val = cpu_to_be32(val); 418 spi_imx->tx_buf += n_bytes; 419 } 420 421 spi_imx->count -= n_bytes; 422 423 writel(val, spi_imx->base + MXC_CSPITXDATA); 424 } 425 426 /* MX51 eCSPI */ 427 static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx, 428 unsigned int fspi, unsigned int *fres) 429 { 430 /* 431 * there are two 4-bit dividers, the pre-divider divides by 432 * $pre, the post-divider by 2^$post 433 */ 434 unsigned int pre, post; 435 unsigned int fin = spi_imx->spi_clk; 436 437 if (unlikely(fspi > fin)) 438 return 0; 439 440 post = fls(fin) - fls(fspi); 441 if (fin > fspi << post) 442 post++; 443 444 /* now we have: (fin <= fspi << post) with post being minimal */ 445 446 post = max(4U, post) - 4; 447 if (unlikely(post > 0xf)) { 448 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n", 449 fspi, fin); 450 return 0xff; 451 } 452 453 pre = DIV_ROUND_UP(fin, fspi << post) - 1; 454 455 dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n", 456 __func__, fin, fspi, post, pre); 457 458 /* Resulting frequency for the SCLK line. */ 459 *fres = (fin / (pre + 1)) >> post; 460 461 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) | 462 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET); 463 } 464 465 static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable) 466 { 467 unsigned val = 0; 468 469 if (enable & MXC_INT_TE) 470 val |= MX51_ECSPI_INT_TEEN; 471 472 if (enable & MXC_INT_RR) 473 val |= MX51_ECSPI_INT_RREN; 474 475 if (enable & MXC_INT_RDR) 476 val |= MX51_ECSPI_INT_RDREN; 477 478 writel(val, spi_imx->base + MX51_ECSPI_INT); 479 } 480 481 static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx) 482 { 483 u32 reg; 484 485 reg = readl(spi_imx->base + MX51_ECSPI_CTRL); 486 reg |= MX51_ECSPI_CTRL_XCH; 487 writel(reg, spi_imx->base + MX51_ECSPI_CTRL); 488 } 489 490 static void mx51_disable_dma(struct spi_imx_data *spi_imx) 491 { 492 writel(0, spi_imx->base + MX51_ECSPI_DMA); 493 } 494 495 static void mx51_ecspi_disable(struct spi_imx_data *spi_imx) 496 { 497 u32 ctrl; 498 499 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); 500 ctrl &= ~MX51_ECSPI_CTRL_ENABLE; 501 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); 502 } 503 504 static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx, 505 struct spi_message *msg) 506 { 507 struct spi_device *spi = msg->spi; 508 u32 ctrl = MX51_ECSPI_CTRL_ENABLE; 509 u32 testreg; 510 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG); 511 512 /* set Master or Slave mode */ 513 if (spi_imx->slave_mode) 514 ctrl &= ~MX51_ECSPI_CTRL_MODE_MASK; 515 else 516 ctrl |= MX51_ECSPI_CTRL_MODE_MASK; 517 518 /* 519 * Enable SPI_RDY handling (falling edge/level triggered). 520 */ 521 if (spi->mode & SPI_READY) 522 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl); 523 524 /* set chip select to use */ 525 ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select); 526 527 /* 528 * The ctrl register must be written first, with the EN bit set other 529 * registers must not be written to. 530 */ 531 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); 532 533 testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG); 534 if (spi->mode & SPI_LOOP) 535 testreg |= MX51_ECSPI_TESTREG_LBC; 536 else 537 testreg &= ~MX51_ECSPI_TESTREG_LBC; 538 writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG); 539 540 /* 541 * eCSPI burst completion by Chip Select signal in Slave mode 542 * is not functional for imx53 Soc, config SPI burst completed when 543 * BURST_LENGTH + 1 bits are received 544 */ 545 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx)) 546 cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select); 547 else 548 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select); 549 550 if (spi->mode & SPI_CPHA) 551 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); 552 else 553 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); 554 555 if (spi->mode & SPI_CPOL) { 556 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); 557 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); 558 } else { 559 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); 560 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); 561 } 562 563 if (spi->mode & SPI_CS_HIGH) 564 cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select); 565 else 566 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select); 567 568 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); 569 570 return 0; 571 } 572 573 static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx, 574 struct spi_device *spi) 575 { 576 u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); 577 u32 clk, delay; 578 579 /* Clear BL field and set the right value */ 580 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK; 581 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx)) 582 ctrl |= (spi_imx->slave_burst * 8 - 1) 583 << MX51_ECSPI_CTRL_BL_OFFSET; 584 else 585 ctrl |= (spi_imx->bits_per_word - 1) 586 << MX51_ECSPI_CTRL_BL_OFFSET; 587 588 /* set clock speed */ 589 ctrl &= ~(0xf << MX51_ECSPI_CTRL_POSTDIV_OFFSET | 590 0xf << MX51_ECSPI_CTRL_PREDIV_OFFSET); 591 ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->spi_bus_clk, &clk); 592 spi_imx->spi_bus_clk = clk; 593 594 if (spi_imx->usedma) 595 ctrl |= MX51_ECSPI_CTRL_SMC; 596 597 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); 598 599 /* 600 * Wait until the changes in the configuration register CONFIGREG 601 * propagate into the hardware. It takes exactly one tick of the 602 * SCLK clock, but we will wait two SCLK clock just to be sure. The 603 * effect of the delay it takes for the hardware to apply changes 604 * is noticable if the SCLK clock run very slow. In such a case, if 605 * the polarity of SCLK should be inverted, the GPIO ChipSelect might 606 * be asserted before the SCLK polarity changes, which would disrupt 607 * the SPI communication as the device on the other end would consider 608 * the change of SCLK polarity as a clock tick already. 609 */ 610 delay = (2 * 1000000) / clk; 611 if (likely(delay < 10)) /* SCLK is faster than 100 kHz */ 612 udelay(delay); 613 else /* SCLK is _very_ slow */ 614 usleep_range(delay, delay + 10); 615 616 return 0; 617 } 618 619 static void mx51_setup_wml(struct spi_imx_data *spi_imx) 620 { 621 /* 622 * Configure the DMA register: setup the watermark 623 * and enable DMA request. 624 */ 625 writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) | 626 MX51_ECSPI_DMA_TX_WML(spi_imx->wml) | 627 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) | 628 MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN | 629 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA); 630 } 631 632 static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx) 633 { 634 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR; 635 } 636 637 static void mx51_ecspi_reset(struct spi_imx_data *spi_imx) 638 { 639 /* drain receive buffer */ 640 while (mx51_ecspi_rx_available(spi_imx)) 641 readl(spi_imx->base + MXC_CSPIRXDATA); 642 } 643 644 #define MX31_INTREG_TEEN (1 << 0) 645 #define MX31_INTREG_RREN (1 << 3) 646 647 #define MX31_CSPICTRL_ENABLE (1 << 0) 648 #define MX31_CSPICTRL_MASTER (1 << 1) 649 #define MX31_CSPICTRL_XCH (1 << 2) 650 #define MX31_CSPICTRL_SMC (1 << 3) 651 #define MX31_CSPICTRL_POL (1 << 4) 652 #define MX31_CSPICTRL_PHA (1 << 5) 653 #define MX31_CSPICTRL_SSCTL (1 << 6) 654 #define MX31_CSPICTRL_SSPOL (1 << 7) 655 #define MX31_CSPICTRL_BC_SHIFT 8 656 #define MX35_CSPICTRL_BL_SHIFT 20 657 #define MX31_CSPICTRL_CS_SHIFT 24 658 #define MX35_CSPICTRL_CS_SHIFT 12 659 #define MX31_CSPICTRL_DR_SHIFT 16 660 661 #define MX31_CSPI_DMAREG 0x10 662 #define MX31_DMAREG_RH_DEN (1<<4) 663 #define MX31_DMAREG_TH_DEN (1<<1) 664 665 #define MX31_CSPISTATUS 0x14 666 #define MX31_STATUS_RR (1 << 3) 667 668 #define MX31_CSPI_TESTREG 0x1C 669 #define MX31_TEST_LBC (1 << 14) 670 671 /* These functions also work for the i.MX35, but be aware that 672 * the i.MX35 has a slightly different register layout for bits 673 * we do not use here. 674 */ 675 static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable) 676 { 677 unsigned int val = 0; 678 679 if (enable & MXC_INT_TE) 680 val |= MX31_INTREG_TEEN; 681 if (enable & MXC_INT_RR) 682 val |= MX31_INTREG_RREN; 683 684 writel(val, spi_imx->base + MXC_CSPIINT); 685 } 686 687 static void mx31_trigger(struct spi_imx_data *spi_imx) 688 { 689 unsigned int reg; 690 691 reg = readl(spi_imx->base + MXC_CSPICTRL); 692 reg |= MX31_CSPICTRL_XCH; 693 writel(reg, spi_imx->base + MXC_CSPICTRL); 694 } 695 696 static int mx31_prepare_message(struct spi_imx_data *spi_imx, 697 struct spi_message *msg) 698 { 699 return 0; 700 } 701 702 static int mx31_prepare_transfer(struct spi_imx_data *spi_imx, 703 struct spi_device *spi) 704 { 705 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER; 706 unsigned int clk; 707 708 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) << 709 MX31_CSPICTRL_DR_SHIFT; 710 spi_imx->spi_bus_clk = clk; 711 712 if (is_imx35_cspi(spi_imx)) { 713 reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT; 714 reg |= MX31_CSPICTRL_SSCTL; 715 } else { 716 reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT; 717 } 718 719 if (spi->mode & SPI_CPHA) 720 reg |= MX31_CSPICTRL_PHA; 721 if (spi->mode & SPI_CPOL) 722 reg |= MX31_CSPICTRL_POL; 723 if (spi->mode & SPI_CS_HIGH) 724 reg |= MX31_CSPICTRL_SSPOL; 725 if (!spi->cs_gpiod) 726 reg |= (spi->chip_select) << 727 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT : 728 MX31_CSPICTRL_CS_SHIFT); 729 730 if (spi_imx->usedma) 731 reg |= MX31_CSPICTRL_SMC; 732 733 writel(reg, spi_imx->base + MXC_CSPICTRL); 734 735 reg = readl(spi_imx->base + MX31_CSPI_TESTREG); 736 if (spi->mode & SPI_LOOP) 737 reg |= MX31_TEST_LBC; 738 else 739 reg &= ~MX31_TEST_LBC; 740 writel(reg, spi_imx->base + MX31_CSPI_TESTREG); 741 742 if (spi_imx->usedma) { 743 /* 744 * configure DMA requests when RXFIFO is half full and 745 * when TXFIFO is half empty 746 */ 747 writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN, 748 spi_imx->base + MX31_CSPI_DMAREG); 749 } 750 751 return 0; 752 } 753 754 static int mx31_rx_available(struct spi_imx_data *spi_imx) 755 { 756 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; 757 } 758 759 static void mx31_reset(struct spi_imx_data *spi_imx) 760 { 761 /* drain receive buffer */ 762 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR) 763 readl(spi_imx->base + MXC_CSPIRXDATA); 764 } 765 766 #define MX21_INTREG_RR (1 << 4) 767 #define MX21_INTREG_TEEN (1 << 9) 768 #define MX21_INTREG_RREN (1 << 13) 769 770 #define MX21_CSPICTRL_POL (1 << 5) 771 #define MX21_CSPICTRL_PHA (1 << 6) 772 #define MX21_CSPICTRL_SSPOL (1 << 8) 773 #define MX21_CSPICTRL_XCH (1 << 9) 774 #define MX21_CSPICTRL_ENABLE (1 << 10) 775 #define MX21_CSPICTRL_MASTER (1 << 11) 776 #define MX21_CSPICTRL_DR_SHIFT 14 777 #define MX21_CSPICTRL_CS_SHIFT 19 778 779 static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable) 780 { 781 unsigned int val = 0; 782 783 if (enable & MXC_INT_TE) 784 val |= MX21_INTREG_TEEN; 785 if (enable & MXC_INT_RR) 786 val |= MX21_INTREG_RREN; 787 788 writel(val, spi_imx->base + MXC_CSPIINT); 789 } 790 791 static void mx21_trigger(struct spi_imx_data *spi_imx) 792 { 793 unsigned int reg; 794 795 reg = readl(spi_imx->base + MXC_CSPICTRL); 796 reg |= MX21_CSPICTRL_XCH; 797 writel(reg, spi_imx->base + MXC_CSPICTRL); 798 } 799 800 static int mx21_prepare_message(struct spi_imx_data *spi_imx, 801 struct spi_message *msg) 802 { 803 return 0; 804 } 805 806 static int mx21_prepare_transfer(struct spi_imx_data *spi_imx, 807 struct spi_device *spi) 808 { 809 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER; 810 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18; 811 unsigned int clk; 812 813 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, spi_imx->spi_bus_clk, max, &clk) 814 << MX21_CSPICTRL_DR_SHIFT; 815 spi_imx->spi_bus_clk = clk; 816 817 reg |= spi_imx->bits_per_word - 1; 818 819 if (spi->mode & SPI_CPHA) 820 reg |= MX21_CSPICTRL_PHA; 821 if (spi->mode & SPI_CPOL) 822 reg |= MX21_CSPICTRL_POL; 823 if (spi->mode & SPI_CS_HIGH) 824 reg |= MX21_CSPICTRL_SSPOL; 825 if (!spi->cs_gpiod) 826 reg |= spi->chip_select << MX21_CSPICTRL_CS_SHIFT; 827 828 writel(reg, spi_imx->base + MXC_CSPICTRL); 829 830 return 0; 831 } 832 833 static int mx21_rx_available(struct spi_imx_data *spi_imx) 834 { 835 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR; 836 } 837 838 static void mx21_reset(struct spi_imx_data *spi_imx) 839 { 840 writel(1, spi_imx->base + MXC_RESET); 841 } 842 843 #define MX1_INTREG_RR (1 << 3) 844 #define MX1_INTREG_TEEN (1 << 8) 845 #define MX1_INTREG_RREN (1 << 11) 846 847 #define MX1_CSPICTRL_POL (1 << 4) 848 #define MX1_CSPICTRL_PHA (1 << 5) 849 #define MX1_CSPICTRL_XCH (1 << 8) 850 #define MX1_CSPICTRL_ENABLE (1 << 9) 851 #define MX1_CSPICTRL_MASTER (1 << 10) 852 #define MX1_CSPICTRL_DR_SHIFT 13 853 854 static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable) 855 { 856 unsigned int val = 0; 857 858 if (enable & MXC_INT_TE) 859 val |= MX1_INTREG_TEEN; 860 if (enable & MXC_INT_RR) 861 val |= MX1_INTREG_RREN; 862 863 writel(val, spi_imx->base + MXC_CSPIINT); 864 } 865 866 static void mx1_trigger(struct spi_imx_data *spi_imx) 867 { 868 unsigned int reg; 869 870 reg = readl(spi_imx->base + MXC_CSPICTRL); 871 reg |= MX1_CSPICTRL_XCH; 872 writel(reg, spi_imx->base + MXC_CSPICTRL); 873 } 874 875 static int mx1_prepare_message(struct spi_imx_data *spi_imx, 876 struct spi_message *msg) 877 { 878 return 0; 879 } 880 881 static int mx1_prepare_transfer(struct spi_imx_data *spi_imx, 882 struct spi_device *spi) 883 { 884 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER; 885 unsigned int clk; 886 887 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) << 888 MX1_CSPICTRL_DR_SHIFT; 889 spi_imx->spi_bus_clk = clk; 890 891 reg |= spi_imx->bits_per_word - 1; 892 893 if (spi->mode & SPI_CPHA) 894 reg |= MX1_CSPICTRL_PHA; 895 if (spi->mode & SPI_CPOL) 896 reg |= MX1_CSPICTRL_POL; 897 898 writel(reg, spi_imx->base + MXC_CSPICTRL); 899 900 return 0; 901 } 902 903 static int mx1_rx_available(struct spi_imx_data *spi_imx) 904 { 905 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; 906 } 907 908 static void mx1_reset(struct spi_imx_data *spi_imx) 909 { 910 writel(1, spi_imx->base + MXC_RESET); 911 } 912 913 static struct spi_imx_devtype_data imx1_cspi_devtype_data = { 914 .intctrl = mx1_intctrl, 915 .prepare_message = mx1_prepare_message, 916 .prepare_transfer = mx1_prepare_transfer, 917 .trigger = mx1_trigger, 918 .rx_available = mx1_rx_available, 919 .reset = mx1_reset, 920 .fifo_size = 8, 921 .has_dmamode = false, 922 .dynamic_burst = false, 923 .has_slavemode = false, 924 .devtype = IMX1_CSPI, 925 }; 926 927 static struct spi_imx_devtype_data imx21_cspi_devtype_data = { 928 .intctrl = mx21_intctrl, 929 .prepare_message = mx21_prepare_message, 930 .prepare_transfer = mx21_prepare_transfer, 931 .trigger = mx21_trigger, 932 .rx_available = mx21_rx_available, 933 .reset = mx21_reset, 934 .fifo_size = 8, 935 .has_dmamode = false, 936 .dynamic_burst = false, 937 .has_slavemode = false, 938 .devtype = IMX21_CSPI, 939 }; 940 941 static struct spi_imx_devtype_data imx27_cspi_devtype_data = { 942 /* i.mx27 cspi shares the functions with i.mx21 one */ 943 .intctrl = mx21_intctrl, 944 .prepare_message = mx21_prepare_message, 945 .prepare_transfer = mx21_prepare_transfer, 946 .trigger = mx21_trigger, 947 .rx_available = mx21_rx_available, 948 .reset = mx21_reset, 949 .fifo_size = 8, 950 .has_dmamode = false, 951 .dynamic_burst = false, 952 .has_slavemode = false, 953 .devtype = IMX27_CSPI, 954 }; 955 956 static struct spi_imx_devtype_data imx31_cspi_devtype_data = { 957 .intctrl = mx31_intctrl, 958 .prepare_message = mx31_prepare_message, 959 .prepare_transfer = mx31_prepare_transfer, 960 .trigger = mx31_trigger, 961 .rx_available = mx31_rx_available, 962 .reset = mx31_reset, 963 .fifo_size = 8, 964 .has_dmamode = false, 965 .dynamic_burst = false, 966 .has_slavemode = false, 967 .devtype = IMX31_CSPI, 968 }; 969 970 static struct spi_imx_devtype_data imx35_cspi_devtype_data = { 971 /* i.mx35 and later cspi shares the functions with i.mx31 one */ 972 .intctrl = mx31_intctrl, 973 .prepare_message = mx31_prepare_message, 974 .prepare_transfer = mx31_prepare_transfer, 975 .trigger = mx31_trigger, 976 .rx_available = mx31_rx_available, 977 .reset = mx31_reset, 978 .fifo_size = 8, 979 .has_dmamode = true, 980 .dynamic_burst = false, 981 .has_slavemode = false, 982 .devtype = IMX35_CSPI, 983 }; 984 985 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = { 986 .intctrl = mx51_ecspi_intctrl, 987 .prepare_message = mx51_ecspi_prepare_message, 988 .prepare_transfer = mx51_ecspi_prepare_transfer, 989 .trigger = mx51_ecspi_trigger, 990 .rx_available = mx51_ecspi_rx_available, 991 .reset = mx51_ecspi_reset, 992 .setup_wml = mx51_setup_wml, 993 .disable_dma = mx51_disable_dma, 994 .fifo_size = 64, 995 .has_dmamode = true, 996 .dynamic_burst = true, 997 .has_slavemode = true, 998 .disable = mx51_ecspi_disable, 999 .devtype = IMX51_ECSPI, 1000 }; 1001 1002 static struct spi_imx_devtype_data imx53_ecspi_devtype_data = { 1003 .intctrl = mx51_ecspi_intctrl, 1004 .prepare_message = mx51_ecspi_prepare_message, 1005 .prepare_transfer = mx51_ecspi_prepare_transfer, 1006 .trigger = mx51_ecspi_trigger, 1007 .rx_available = mx51_ecspi_rx_available, 1008 .disable_dma = mx51_disable_dma, 1009 .reset = mx51_ecspi_reset, 1010 .fifo_size = 64, 1011 .has_dmamode = true, 1012 .has_slavemode = true, 1013 .disable = mx51_ecspi_disable, 1014 .devtype = IMX53_ECSPI, 1015 }; 1016 1017 static const struct of_device_id spi_imx_dt_ids[] = { 1018 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, }, 1019 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, }, 1020 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, }, 1021 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, }, 1022 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, }, 1023 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, }, 1024 { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, }, 1025 { /* sentinel */ } 1026 }; 1027 MODULE_DEVICE_TABLE(of, spi_imx_dt_ids); 1028 1029 static void spi_imx_set_burst_len(struct spi_imx_data *spi_imx, int n_bits) 1030 { 1031 u32 ctrl; 1032 1033 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); 1034 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK; 1035 ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET); 1036 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); 1037 } 1038 1039 static void spi_imx_push(struct spi_imx_data *spi_imx) 1040 { 1041 unsigned int burst_len, fifo_words; 1042 1043 if (spi_imx->dynamic_burst) 1044 fifo_words = 4; 1045 else 1046 fifo_words = spi_imx_bytes_per_word(spi_imx->bits_per_word); 1047 /* 1048 * Reload the FIFO when the remaining bytes to be transferred in the 1049 * current burst is 0. This only applies when bits_per_word is a 1050 * multiple of 8. 1051 */ 1052 if (!spi_imx->remainder) { 1053 if (spi_imx->dynamic_burst) { 1054 1055 /* We need to deal unaligned data first */ 1056 burst_len = spi_imx->count % MX51_ECSPI_CTRL_MAX_BURST; 1057 1058 if (!burst_len) 1059 burst_len = MX51_ECSPI_CTRL_MAX_BURST; 1060 1061 spi_imx_set_burst_len(spi_imx, burst_len * 8); 1062 1063 spi_imx->remainder = burst_len; 1064 } else { 1065 spi_imx->remainder = fifo_words; 1066 } 1067 } 1068 1069 while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) { 1070 if (!spi_imx->count) 1071 break; 1072 if (spi_imx->dynamic_burst && 1073 spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder, 1074 fifo_words)) 1075 break; 1076 spi_imx->tx(spi_imx); 1077 spi_imx->txfifo++; 1078 } 1079 1080 if (!spi_imx->slave_mode) 1081 spi_imx->devtype_data->trigger(spi_imx); 1082 } 1083 1084 static irqreturn_t spi_imx_isr(int irq, void *dev_id) 1085 { 1086 struct spi_imx_data *spi_imx = dev_id; 1087 1088 while (spi_imx->txfifo && 1089 spi_imx->devtype_data->rx_available(spi_imx)) { 1090 spi_imx->rx(spi_imx); 1091 spi_imx->txfifo--; 1092 } 1093 1094 if (spi_imx->count) { 1095 spi_imx_push(spi_imx); 1096 return IRQ_HANDLED; 1097 } 1098 1099 if (spi_imx->txfifo) { 1100 /* No data left to push, but still waiting for rx data, 1101 * enable receive data available interrupt. 1102 */ 1103 spi_imx->devtype_data->intctrl( 1104 spi_imx, MXC_INT_RR); 1105 return IRQ_HANDLED; 1106 } 1107 1108 spi_imx->devtype_data->intctrl(spi_imx, 0); 1109 complete(&spi_imx->xfer_done); 1110 1111 return IRQ_HANDLED; 1112 } 1113 1114 static int spi_imx_dma_configure(struct spi_master *master) 1115 { 1116 int ret; 1117 enum dma_slave_buswidth buswidth; 1118 struct dma_slave_config rx = {}, tx = {}; 1119 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 1120 1121 switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) { 1122 case 4: 1123 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES; 1124 break; 1125 case 2: 1126 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES; 1127 break; 1128 case 1: 1129 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE; 1130 break; 1131 default: 1132 return -EINVAL; 1133 } 1134 1135 tx.direction = DMA_MEM_TO_DEV; 1136 tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA; 1137 tx.dst_addr_width = buswidth; 1138 tx.dst_maxburst = spi_imx->wml; 1139 ret = dmaengine_slave_config(master->dma_tx, &tx); 1140 if (ret) { 1141 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret); 1142 return ret; 1143 } 1144 1145 rx.direction = DMA_DEV_TO_MEM; 1146 rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA; 1147 rx.src_addr_width = buswidth; 1148 rx.src_maxburst = spi_imx->wml; 1149 ret = dmaengine_slave_config(master->dma_rx, &rx); 1150 if (ret) { 1151 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret); 1152 return ret; 1153 } 1154 1155 return 0; 1156 } 1157 1158 static int spi_imx_setupxfer(struct spi_device *spi, 1159 struct spi_transfer *t) 1160 { 1161 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 1162 1163 if (!t) 1164 return 0; 1165 1166 if (!t->speed_hz) { 1167 if (!spi->max_speed_hz) { 1168 dev_err(&spi->dev, "no speed_hz provided!\n"); 1169 return -EINVAL; 1170 } 1171 dev_dbg(&spi->dev, "using spi->max_speed_hz!\n"); 1172 spi_imx->spi_bus_clk = spi->max_speed_hz; 1173 } else 1174 spi_imx->spi_bus_clk = t->speed_hz; 1175 1176 spi_imx->bits_per_word = t->bits_per_word; 1177 1178 /* 1179 * Initialize the functions for transfer. To transfer non byte-aligned 1180 * words, we have to use multiple word-size bursts, we can't use 1181 * dynamic_burst in that case. 1182 */ 1183 if (spi_imx->devtype_data->dynamic_burst && !spi_imx->slave_mode && 1184 (spi_imx->bits_per_word == 8 || 1185 spi_imx->bits_per_word == 16 || 1186 spi_imx->bits_per_word == 32)) { 1187 1188 spi_imx->rx = spi_imx_buf_rx_swap; 1189 spi_imx->tx = spi_imx_buf_tx_swap; 1190 spi_imx->dynamic_burst = 1; 1191 1192 } else { 1193 if (spi_imx->bits_per_word <= 8) { 1194 spi_imx->rx = spi_imx_buf_rx_u8; 1195 spi_imx->tx = spi_imx_buf_tx_u8; 1196 } else if (spi_imx->bits_per_word <= 16) { 1197 spi_imx->rx = spi_imx_buf_rx_u16; 1198 spi_imx->tx = spi_imx_buf_tx_u16; 1199 } else { 1200 spi_imx->rx = spi_imx_buf_rx_u32; 1201 spi_imx->tx = spi_imx_buf_tx_u32; 1202 } 1203 spi_imx->dynamic_burst = 0; 1204 } 1205 1206 if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t)) 1207 spi_imx->usedma = true; 1208 else 1209 spi_imx->usedma = false; 1210 1211 if (is_imx53_ecspi(spi_imx) && spi_imx->slave_mode) { 1212 spi_imx->rx = mx53_ecspi_rx_slave; 1213 spi_imx->tx = mx53_ecspi_tx_slave; 1214 spi_imx->slave_burst = t->len; 1215 } 1216 1217 spi_imx->devtype_data->prepare_transfer(spi_imx, spi); 1218 1219 return 0; 1220 } 1221 1222 static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx) 1223 { 1224 struct spi_master *master = spi_imx->bitbang.master; 1225 1226 if (master->dma_rx) { 1227 dma_release_channel(master->dma_rx); 1228 master->dma_rx = NULL; 1229 } 1230 1231 if (master->dma_tx) { 1232 dma_release_channel(master->dma_tx); 1233 master->dma_tx = NULL; 1234 } 1235 } 1236 1237 static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx, 1238 struct spi_master *master) 1239 { 1240 int ret; 1241 1242 /* use pio mode for i.mx6dl chip TKT238285 */ 1243 if (of_machine_is_compatible("fsl,imx6dl")) 1244 return 0; 1245 1246 spi_imx->wml = spi_imx->devtype_data->fifo_size / 2; 1247 1248 /* Prepare for TX DMA: */ 1249 master->dma_tx = dma_request_chan(dev, "tx"); 1250 if (IS_ERR(master->dma_tx)) { 1251 ret = PTR_ERR(master->dma_tx); 1252 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret); 1253 master->dma_tx = NULL; 1254 goto err; 1255 } 1256 1257 /* Prepare for RX : */ 1258 master->dma_rx = dma_request_chan(dev, "rx"); 1259 if (IS_ERR(master->dma_rx)) { 1260 ret = PTR_ERR(master->dma_rx); 1261 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret); 1262 master->dma_rx = NULL; 1263 goto err; 1264 } 1265 1266 init_completion(&spi_imx->dma_rx_completion); 1267 init_completion(&spi_imx->dma_tx_completion); 1268 master->can_dma = spi_imx_can_dma; 1269 master->max_dma_len = MAX_SDMA_BD_BYTES; 1270 spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX | 1271 SPI_MASTER_MUST_TX; 1272 1273 return 0; 1274 err: 1275 spi_imx_sdma_exit(spi_imx); 1276 return ret; 1277 } 1278 1279 static void spi_imx_dma_rx_callback(void *cookie) 1280 { 1281 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie; 1282 1283 complete(&spi_imx->dma_rx_completion); 1284 } 1285 1286 static void spi_imx_dma_tx_callback(void *cookie) 1287 { 1288 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie; 1289 1290 complete(&spi_imx->dma_tx_completion); 1291 } 1292 1293 static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size) 1294 { 1295 unsigned long timeout = 0; 1296 1297 /* Time with actual data transfer and CS change delay related to HW */ 1298 timeout = (8 + 4) * size / spi_imx->spi_bus_clk; 1299 1300 /* Add extra second for scheduler related activities */ 1301 timeout += 1; 1302 1303 /* Double calculated timeout */ 1304 return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC); 1305 } 1306 1307 static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx, 1308 struct spi_transfer *transfer) 1309 { 1310 struct dma_async_tx_descriptor *desc_tx, *desc_rx; 1311 unsigned long transfer_timeout; 1312 unsigned long timeout; 1313 struct spi_master *master = spi_imx->bitbang.master; 1314 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg; 1315 struct scatterlist *last_sg = sg_last(rx->sgl, rx->nents); 1316 unsigned int bytes_per_word, i; 1317 int ret; 1318 1319 /* Get the right burst length from the last sg to ensure no tail data */ 1320 bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word); 1321 for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) { 1322 if (!(sg_dma_len(last_sg) % (i * bytes_per_word))) 1323 break; 1324 } 1325 /* Use 1 as wml in case no available burst length got */ 1326 if (i == 0) 1327 i = 1; 1328 1329 spi_imx->wml = i; 1330 1331 ret = spi_imx_dma_configure(master); 1332 if (ret) 1333 goto dma_failure_no_start; 1334 1335 if (!spi_imx->devtype_data->setup_wml) { 1336 dev_err(spi_imx->dev, "No setup_wml()?\n"); 1337 ret = -EINVAL; 1338 goto dma_failure_no_start; 1339 } 1340 spi_imx->devtype_data->setup_wml(spi_imx); 1341 1342 /* 1343 * The TX DMA setup starts the transfer, so make sure RX is configured 1344 * before TX. 1345 */ 1346 desc_rx = dmaengine_prep_slave_sg(master->dma_rx, 1347 rx->sgl, rx->nents, DMA_DEV_TO_MEM, 1348 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1349 if (!desc_rx) { 1350 ret = -EINVAL; 1351 goto dma_failure_no_start; 1352 } 1353 1354 desc_rx->callback = spi_imx_dma_rx_callback; 1355 desc_rx->callback_param = (void *)spi_imx; 1356 dmaengine_submit(desc_rx); 1357 reinit_completion(&spi_imx->dma_rx_completion); 1358 dma_async_issue_pending(master->dma_rx); 1359 1360 desc_tx = dmaengine_prep_slave_sg(master->dma_tx, 1361 tx->sgl, tx->nents, DMA_MEM_TO_DEV, 1362 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1363 if (!desc_tx) { 1364 dmaengine_terminate_all(master->dma_tx); 1365 dmaengine_terminate_all(master->dma_rx); 1366 return -EINVAL; 1367 } 1368 1369 desc_tx->callback = spi_imx_dma_tx_callback; 1370 desc_tx->callback_param = (void *)spi_imx; 1371 dmaengine_submit(desc_tx); 1372 reinit_completion(&spi_imx->dma_tx_completion); 1373 dma_async_issue_pending(master->dma_tx); 1374 1375 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); 1376 1377 /* Wait SDMA to finish the data transfer.*/ 1378 timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion, 1379 transfer_timeout); 1380 if (!timeout) { 1381 dev_err(spi_imx->dev, "I/O Error in DMA TX\n"); 1382 dmaengine_terminate_all(master->dma_tx); 1383 dmaengine_terminate_all(master->dma_rx); 1384 return -ETIMEDOUT; 1385 } 1386 1387 timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion, 1388 transfer_timeout); 1389 if (!timeout) { 1390 dev_err(&master->dev, "I/O Error in DMA RX\n"); 1391 spi_imx->devtype_data->reset(spi_imx); 1392 dmaengine_terminate_all(master->dma_rx); 1393 return -ETIMEDOUT; 1394 } 1395 1396 return transfer->len; 1397 /* fallback to pio */ 1398 dma_failure_no_start: 1399 transfer->error |= SPI_TRANS_FAIL_NO_START; 1400 return ret; 1401 } 1402 1403 static int spi_imx_pio_transfer(struct spi_device *spi, 1404 struct spi_transfer *transfer) 1405 { 1406 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 1407 unsigned long transfer_timeout; 1408 unsigned long timeout; 1409 1410 spi_imx->tx_buf = transfer->tx_buf; 1411 spi_imx->rx_buf = transfer->rx_buf; 1412 spi_imx->count = transfer->len; 1413 spi_imx->txfifo = 0; 1414 spi_imx->remainder = 0; 1415 1416 reinit_completion(&spi_imx->xfer_done); 1417 1418 spi_imx_push(spi_imx); 1419 1420 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE); 1421 1422 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); 1423 1424 timeout = wait_for_completion_timeout(&spi_imx->xfer_done, 1425 transfer_timeout); 1426 if (!timeout) { 1427 dev_err(&spi->dev, "I/O Error in PIO\n"); 1428 spi_imx->devtype_data->reset(spi_imx); 1429 return -ETIMEDOUT; 1430 } 1431 1432 return transfer->len; 1433 } 1434 1435 static int spi_imx_pio_transfer_slave(struct spi_device *spi, 1436 struct spi_transfer *transfer) 1437 { 1438 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 1439 int ret = transfer->len; 1440 1441 if (is_imx53_ecspi(spi_imx) && 1442 transfer->len > MX53_MAX_TRANSFER_BYTES) { 1443 dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n", 1444 MX53_MAX_TRANSFER_BYTES); 1445 return -EMSGSIZE; 1446 } 1447 1448 spi_imx->tx_buf = transfer->tx_buf; 1449 spi_imx->rx_buf = transfer->rx_buf; 1450 spi_imx->count = transfer->len; 1451 spi_imx->txfifo = 0; 1452 spi_imx->remainder = 0; 1453 1454 reinit_completion(&spi_imx->xfer_done); 1455 spi_imx->slave_aborted = false; 1456 1457 spi_imx_push(spi_imx); 1458 1459 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR); 1460 1461 if (wait_for_completion_interruptible(&spi_imx->xfer_done) || 1462 spi_imx->slave_aborted) { 1463 dev_dbg(&spi->dev, "interrupted\n"); 1464 ret = -EINTR; 1465 } 1466 1467 /* ecspi has a HW issue when works in Slave mode, 1468 * after 64 words writtern to TXFIFO, even TXFIFO becomes empty, 1469 * ECSPI_TXDATA keeps shift out the last word data, 1470 * so we have to disable ECSPI when in slave mode after the 1471 * transfer completes 1472 */ 1473 if (spi_imx->devtype_data->disable) 1474 spi_imx->devtype_data->disable(spi_imx); 1475 1476 return ret; 1477 } 1478 1479 static int spi_imx_transfer(struct spi_device *spi, 1480 struct spi_transfer *transfer) 1481 { 1482 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 1483 1484 transfer->effective_speed_hz = spi_imx->spi_bus_clk; 1485 1486 /* flush rxfifo before transfer */ 1487 while (spi_imx->devtype_data->rx_available(spi_imx)) 1488 readl(spi_imx->base + MXC_CSPIRXDATA); 1489 1490 if (spi_imx->slave_mode) 1491 return spi_imx_pio_transfer_slave(spi, transfer); 1492 1493 if (spi_imx->usedma) 1494 return spi_imx_dma_transfer(spi_imx, transfer); 1495 1496 return spi_imx_pio_transfer(spi, transfer); 1497 } 1498 1499 static int spi_imx_setup(struct spi_device *spi) 1500 { 1501 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__, 1502 spi->mode, spi->bits_per_word, spi->max_speed_hz); 1503 1504 return 0; 1505 } 1506 1507 static void spi_imx_cleanup(struct spi_device *spi) 1508 { 1509 } 1510 1511 static int 1512 spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg) 1513 { 1514 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 1515 int ret; 1516 1517 ret = pm_runtime_get_sync(spi_imx->dev); 1518 if (ret < 0) { 1519 pm_runtime_put_noidle(spi_imx->dev); 1520 dev_err(spi_imx->dev, "failed to enable clock\n"); 1521 return ret; 1522 } 1523 1524 ret = spi_imx->devtype_data->prepare_message(spi_imx, msg); 1525 if (ret) { 1526 pm_runtime_mark_last_busy(spi_imx->dev); 1527 pm_runtime_put_autosuspend(spi_imx->dev); 1528 } 1529 1530 return ret; 1531 } 1532 1533 static int 1534 spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg) 1535 { 1536 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 1537 1538 pm_runtime_mark_last_busy(spi_imx->dev); 1539 pm_runtime_put_autosuspend(spi_imx->dev); 1540 return 0; 1541 } 1542 1543 static int spi_imx_slave_abort(struct spi_master *master) 1544 { 1545 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 1546 1547 spi_imx->slave_aborted = true; 1548 complete(&spi_imx->xfer_done); 1549 1550 return 0; 1551 } 1552 1553 static int spi_imx_probe(struct platform_device *pdev) 1554 { 1555 struct device_node *np = pdev->dev.of_node; 1556 struct spi_master *master; 1557 struct spi_imx_data *spi_imx; 1558 struct resource *res; 1559 int ret, irq, spi_drctl; 1560 const struct spi_imx_devtype_data *devtype_data = 1561 of_device_get_match_data(&pdev->dev); 1562 bool slave_mode; 1563 u32 val; 1564 1565 slave_mode = devtype_data->has_slavemode && 1566 of_property_read_bool(np, "spi-slave"); 1567 if (slave_mode) 1568 master = spi_alloc_slave(&pdev->dev, 1569 sizeof(struct spi_imx_data)); 1570 else 1571 master = spi_alloc_master(&pdev->dev, 1572 sizeof(struct spi_imx_data)); 1573 if (!master) 1574 return -ENOMEM; 1575 1576 ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl); 1577 if ((ret < 0) || (spi_drctl >= 0x3)) { 1578 /* '11' is reserved */ 1579 spi_drctl = 0; 1580 } 1581 1582 platform_set_drvdata(pdev, master); 1583 1584 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); 1585 master->bus_num = np ? -1 : pdev->id; 1586 master->use_gpio_descriptors = true; 1587 1588 spi_imx = spi_master_get_devdata(master); 1589 spi_imx->bitbang.master = master; 1590 spi_imx->dev = &pdev->dev; 1591 spi_imx->slave_mode = slave_mode; 1592 1593 spi_imx->devtype_data = devtype_data; 1594 1595 /* 1596 * Get number of chip selects from device properties. This can be 1597 * coming from device tree or boardfiles, if it is not defined, 1598 * a default value of 3 chip selects will be used, as all the legacy 1599 * board files have <= 3 chip selects. 1600 */ 1601 if (!device_property_read_u32(&pdev->dev, "num-cs", &val)) 1602 master->num_chipselect = val; 1603 else 1604 master->num_chipselect = 3; 1605 1606 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer; 1607 spi_imx->bitbang.txrx_bufs = spi_imx_transfer; 1608 spi_imx->bitbang.master->setup = spi_imx_setup; 1609 spi_imx->bitbang.master->cleanup = spi_imx_cleanup; 1610 spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message; 1611 spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message; 1612 spi_imx->bitbang.master->slave_abort = spi_imx_slave_abort; 1613 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \ 1614 | SPI_NO_CS; 1615 if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) || 1616 is_imx53_ecspi(spi_imx)) 1617 spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY; 1618 1619 spi_imx->spi_drctl = spi_drctl; 1620 1621 init_completion(&spi_imx->xfer_done); 1622 1623 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1624 spi_imx->base = devm_ioremap_resource(&pdev->dev, res); 1625 if (IS_ERR(spi_imx->base)) { 1626 ret = PTR_ERR(spi_imx->base); 1627 goto out_master_put; 1628 } 1629 spi_imx->base_phys = res->start; 1630 1631 irq = platform_get_irq(pdev, 0); 1632 if (irq < 0) { 1633 ret = irq; 1634 goto out_master_put; 1635 } 1636 1637 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0, 1638 dev_name(&pdev->dev), spi_imx); 1639 if (ret) { 1640 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret); 1641 goto out_master_put; 1642 } 1643 1644 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1645 if (IS_ERR(spi_imx->clk_ipg)) { 1646 ret = PTR_ERR(spi_imx->clk_ipg); 1647 goto out_master_put; 1648 } 1649 1650 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per"); 1651 if (IS_ERR(spi_imx->clk_per)) { 1652 ret = PTR_ERR(spi_imx->clk_per); 1653 goto out_master_put; 1654 } 1655 1656 ret = clk_prepare_enable(spi_imx->clk_per); 1657 if (ret) 1658 goto out_master_put; 1659 1660 ret = clk_prepare_enable(spi_imx->clk_ipg); 1661 if (ret) 1662 goto out_put_per; 1663 1664 pm_runtime_set_autosuspend_delay(spi_imx->dev, MXC_RPM_TIMEOUT); 1665 pm_runtime_use_autosuspend(spi_imx->dev); 1666 pm_runtime_get_noresume(spi_imx->dev); 1667 pm_runtime_set_active(spi_imx->dev); 1668 pm_runtime_enable(spi_imx->dev); 1669 1670 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per); 1671 /* 1672 * Only validated on i.mx35 and i.mx6 now, can remove the constraint 1673 * if validated on other chips. 1674 */ 1675 if (spi_imx->devtype_data->has_dmamode) { 1676 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master); 1677 if (ret == -EPROBE_DEFER) 1678 goto out_runtime_pm_put; 1679 1680 if (ret < 0) 1681 dev_dbg(&pdev->dev, "dma setup error %d, use pio\n", 1682 ret); 1683 } 1684 1685 spi_imx->devtype_data->reset(spi_imx); 1686 1687 spi_imx->devtype_data->intctrl(spi_imx, 0); 1688 1689 master->dev.of_node = pdev->dev.of_node; 1690 ret = spi_bitbang_start(&spi_imx->bitbang); 1691 if (ret) { 1692 dev_err_probe(&pdev->dev, ret, "bitbang start failed\n"); 1693 goto out_bitbang_start; 1694 } 1695 1696 pm_runtime_mark_last_busy(spi_imx->dev); 1697 pm_runtime_put_autosuspend(spi_imx->dev); 1698 1699 return ret; 1700 1701 out_bitbang_start: 1702 if (spi_imx->devtype_data->has_dmamode) 1703 spi_imx_sdma_exit(spi_imx); 1704 out_runtime_pm_put: 1705 pm_runtime_dont_use_autosuspend(spi_imx->dev); 1706 pm_runtime_set_suspended(&pdev->dev); 1707 pm_runtime_disable(spi_imx->dev); 1708 1709 clk_disable_unprepare(spi_imx->clk_ipg); 1710 out_put_per: 1711 clk_disable_unprepare(spi_imx->clk_per); 1712 out_master_put: 1713 spi_master_put(master); 1714 1715 return ret; 1716 } 1717 1718 static int spi_imx_remove(struct platform_device *pdev) 1719 { 1720 struct spi_master *master = platform_get_drvdata(pdev); 1721 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 1722 int ret; 1723 1724 spi_bitbang_stop(&spi_imx->bitbang); 1725 1726 ret = pm_runtime_get_sync(spi_imx->dev); 1727 if (ret < 0) { 1728 pm_runtime_put_noidle(spi_imx->dev); 1729 dev_err(spi_imx->dev, "failed to enable clock\n"); 1730 return ret; 1731 } 1732 1733 writel(0, spi_imx->base + MXC_CSPICTRL); 1734 1735 pm_runtime_dont_use_autosuspend(spi_imx->dev); 1736 pm_runtime_put_sync(spi_imx->dev); 1737 pm_runtime_disable(spi_imx->dev); 1738 1739 spi_imx_sdma_exit(spi_imx); 1740 spi_master_put(master); 1741 1742 return 0; 1743 } 1744 1745 static int __maybe_unused spi_imx_runtime_resume(struct device *dev) 1746 { 1747 struct spi_master *master = dev_get_drvdata(dev); 1748 struct spi_imx_data *spi_imx; 1749 int ret; 1750 1751 spi_imx = spi_master_get_devdata(master); 1752 1753 ret = clk_prepare_enable(spi_imx->clk_per); 1754 if (ret) 1755 return ret; 1756 1757 ret = clk_prepare_enable(spi_imx->clk_ipg); 1758 if (ret) { 1759 clk_disable_unprepare(spi_imx->clk_per); 1760 return ret; 1761 } 1762 1763 return 0; 1764 } 1765 1766 static int __maybe_unused spi_imx_runtime_suspend(struct device *dev) 1767 { 1768 struct spi_master *master = dev_get_drvdata(dev); 1769 struct spi_imx_data *spi_imx; 1770 1771 spi_imx = spi_master_get_devdata(master); 1772 1773 clk_disable_unprepare(spi_imx->clk_per); 1774 clk_disable_unprepare(spi_imx->clk_ipg); 1775 1776 return 0; 1777 } 1778 1779 static int __maybe_unused spi_imx_suspend(struct device *dev) 1780 { 1781 pinctrl_pm_select_sleep_state(dev); 1782 return 0; 1783 } 1784 1785 static int __maybe_unused spi_imx_resume(struct device *dev) 1786 { 1787 pinctrl_pm_select_default_state(dev); 1788 return 0; 1789 } 1790 1791 static const struct dev_pm_ops imx_spi_pm = { 1792 SET_RUNTIME_PM_OPS(spi_imx_runtime_suspend, 1793 spi_imx_runtime_resume, NULL) 1794 SET_SYSTEM_SLEEP_PM_OPS(spi_imx_suspend, spi_imx_resume) 1795 }; 1796 1797 static struct platform_driver spi_imx_driver = { 1798 .driver = { 1799 .name = DRIVER_NAME, 1800 .of_match_table = spi_imx_dt_ids, 1801 .pm = &imx_spi_pm, 1802 }, 1803 .probe = spi_imx_probe, 1804 .remove = spi_imx_remove, 1805 }; 1806 module_platform_driver(spi_imx_driver); 1807 1808 MODULE_DESCRIPTION("i.MX SPI Controller driver"); 1809 MODULE_AUTHOR("Sascha Hauer, Pengutronix"); 1810 MODULE_LICENSE("GPL"); 1811 MODULE_ALIAS("platform:" DRIVER_NAME); 1812