1 /* 2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 3 * Copyright (C) 2008 Juergen Beisert 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 2 8 * of the License, or (at your option) any later version. 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the 16 * Free Software Foundation 17 * 51 Franklin Street, Fifth Floor 18 * Boston, MA 02110-1301, USA. 19 */ 20 21 #include <linux/clk.h> 22 #include <linux/completion.h> 23 #include <linux/delay.h> 24 #include <linux/dmaengine.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/err.h> 27 #include <linux/gpio.h> 28 #include <linux/interrupt.h> 29 #include <linux/io.h> 30 #include <linux/irq.h> 31 #include <linux/kernel.h> 32 #include <linux/module.h> 33 #include <linux/platform_device.h> 34 #include <linux/slab.h> 35 #include <linux/spi/spi.h> 36 #include <linux/spi/spi_bitbang.h> 37 #include <linux/types.h> 38 #include <linux/of.h> 39 #include <linux/of_device.h> 40 #include <linux/of_gpio.h> 41 42 #include <linux/platform_data/dma-imx.h> 43 #include <linux/platform_data/spi-imx.h> 44 45 #define DRIVER_NAME "spi_imx" 46 47 #define MXC_CSPIRXDATA 0x00 48 #define MXC_CSPITXDATA 0x04 49 #define MXC_CSPICTRL 0x08 50 #define MXC_CSPIINT 0x0c 51 #define MXC_RESET 0x1c 52 53 /* generic defines to abstract from the different register layouts */ 54 #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */ 55 #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */ 56 57 /* The maximum bytes that a sdma BD can transfer.*/ 58 #define MAX_SDMA_BD_BYTES (1 << 15) 59 #define IMX_DMA_TIMEOUT (msecs_to_jiffies(3000)) 60 struct spi_imx_config { 61 unsigned int speed_hz; 62 unsigned int bpw; 63 unsigned int mode; 64 u8 cs; 65 }; 66 67 enum spi_imx_devtype { 68 IMX1_CSPI, 69 IMX21_CSPI, 70 IMX27_CSPI, 71 IMX31_CSPI, 72 IMX35_CSPI, /* CSPI on all i.mx except above */ 73 IMX51_ECSPI, /* ECSPI on i.mx51 and later */ 74 }; 75 76 struct spi_imx_data; 77 78 struct spi_imx_devtype_data { 79 void (*intctrl)(struct spi_imx_data *, int); 80 int (*config)(struct spi_imx_data *, struct spi_imx_config *); 81 void (*trigger)(struct spi_imx_data *); 82 int (*rx_available)(struct spi_imx_data *); 83 void (*reset)(struct spi_imx_data *); 84 enum spi_imx_devtype devtype; 85 }; 86 87 struct spi_imx_data { 88 struct spi_bitbang bitbang; 89 90 struct completion xfer_done; 91 void __iomem *base; 92 struct clk *clk_per; 93 struct clk *clk_ipg; 94 unsigned long spi_clk; 95 96 unsigned int count; 97 void (*tx)(struct spi_imx_data *); 98 void (*rx)(struct spi_imx_data *); 99 void *rx_buf; 100 const void *tx_buf; 101 unsigned int txfifo; /* number of words pushed in tx FIFO */ 102 103 /* DMA */ 104 unsigned int dma_is_inited; 105 unsigned int dma_finished; 106 bool usedma; 107 u32 wml; 108 struct completion dma_rx_completion; 109 struct completion dma_tx_completion; 110 111 const struct spi_imx_devtype_data *devtype_data; 112 int chipselect[0]; 113 }; 114 115 static inline int is_imx27_cspi(struct spi_imx_data *d) 116 { 117 return d->devtype_data->devtype == IMX27_CSPI; 118 } 119 120 static inline int is_imx35_cspi(struct spi_imx_data *d) 121 { 122 return d->devtype_data->devtype == IMX35_CSPI; 123 } 124 125 static inline int is_imx51_ecspi(struct spi_imx_data *d) 126 { 127 return d->devtype_data->devtype == IMX51_ECSPI; 128 } 129 130 static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d) 131 { 132 return is_imx51_ecspi(d) ? 64 : 8; 133 } 134 135 #define MXC_SPI_BUF_RX(type) \ 136 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \ 137 { \ 138 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \ 139 \ 140 if (spi_imx->rx_buf) { \ 141 *(type *)spi_imx->rx_buf = val; \ 142 spi_imx->rx_buf += sizeof(type); \ 143 } \ 144 } 145 146 #define MXC_SPI_BUF_TX(type) \ 147 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \ 148 { \ 149 type val = 0; \ 150 \ 151 if (spi_imx->tx_buf) { \ 152 val = *(type *)spi_imx->tx_buf; \ 153 spi_imx->tx_buf += sizeof(type); \ 154 } \ 155 \ 156 spi_imx->count -= sizeof(type); \ 157 \ 158 writel(val, spi_imx->base + MXC_CSPITXDATA); \ 159 } 160 161 MXC_SPI_BUF_RX(u8) 162 MXC_SPI_BUF_TX(u8) 163 MXC_SPI_BUF_RX(u16) 164 MXC_SPI_BUF_TX(u16) 165 MXC_SPI_BUF_RX(u32) 166 MXC_SPI_BUF_TX(u32) 167 168 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set 169 * (which is currently not the case in this driver) 170 */ 171 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192, 172 256, 384, 512, 768, 1024}; 173 174 /* MX21, MX27 */ 175 static unsigned int spi_imx_clkdiv_1(unsigned int fin, 176 unsigned int fspi, unsigned int max) 177 { 178 int i; 179 180 for (i = 2; i < max; i++) 181 if (fspi * mxc_clkdivs[i] >= fin) 182 return i; 183 184 return max; 185 } 186 187 /* MX1, MX31, MX35, MX51 CSPI */ 188 static unsigned int spi_imx_clkdiv_2(unsigned int fin, 189 unsigned int fspi) 190 { 191 int i, div = 4; 192 193 for (i = 0; i < 7; i++) { 194 if (fspi * div >= fin) 195 return i; 196 div <<= 1; 197 } 198 199 return 7; 200 } 201 202 static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi, 203 struct spi_transfer *transfer) 204 { 205 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 206 207 if (spi_imx->dma_is_inited && 208 transfer->len > spi_imx->wml * sizeof(u32)) 209 return true; 210 return false; 211 } 212 213 #define MX51_ECSPI_CTRL 0x08 214 #define MX51_ECSPI_CTRL_ENABLE (1 << 0) 215 #define MX51_ECSPI_CTRL_XCH (1 << 2) 216 #define MX51_ECSPI_CTRL_SMC (1 << 3) 217 #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4) 218 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8 219 #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12 220 #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18) 221 #define MX51_ECSPI_CTRL_BL_OFFSET 20 222 223 #define MX51_ECSPI_CONFIG 0x0c 224 #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0)) 225 #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4)) 226 #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8)) 227 #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12)) 228 #define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20)) 229 230 #define MX51_ECSPI_INT 0x10 231 #define MX51_ECSPI_INT_TEEN (1 << 0) 232 #define MX51_ECSPI_INT_RREN (1 << 3) 233 234 #define MX51_ECSPI_DMA 0x14 235 #define MX51_ECSPI_DMA_TX_WML_OFFSET 0 236 #define MX51_ECSPI_DMA_TX_WML_MASK 0x3F 237 #define MX51_ECSPI_DMA_RX_WML_OFFSET 16 238 #define MX51_ECSPI_DMA_RX_WML_MASK (0x3F << 16) 239 #define MX51_ECSPI_DMA_RXT_WML_OFFSET 24 240 #define MX51_ECSPI_DMA_RXT_WML_MASK (0x3F << 24) 241 242 #define MX51_ECSPI_DMA_TEDEN_OFFSET 7 243 #define MX51_ECSPI_DMA_RXDEN_OFFSET 23 244 #define MX51_ECSPI_DMA_RXTDEN_OFFSET 31 245 246 #define MX51_ECSPI_STAT 0x18 247 #define MX51_ECSPI_STAT_RR (1 << 3) 248 249 #define MX51_ECSPI_TESTREG 0x20 250 #define MX51_ECSPI_TESTREG_LBC BIT(31) 251 252 /* MX51 eCSPI */ 253 static unsigned int mx51_ecspi_clkdiv(unsigned int fin, unsigned int fspi, 254 unsigned int *fres) 255 { 256 /* 257 * there are two 4-bit dividers, the pre-divider divides by 258 * $pre, the post-divider by 2^$post 259 */ 260 unsigned int pre, post; 261 262 if (unlikely(fspi > fin)) 263 return 0; 264 265 post = fls(fin) - fls(fspi); 266 if (fin > fspi << post) 267 post++; 268 269 /* now we have: (fin <= fspi << post) with post being minimal */ 270 271 post = max(4U, post) - 4; 272 if (unlikely(post > 0xf)) { 273 pr_err("%s: cannot set clock freq: %u (base freq: %u)\n", 274 __func__, fspi, fin); 275 return 0xff; 276 } 277 278 pre = DIV_ROUND_UP(fin, fspi << post) - 1; 279 280 pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n", 281 __func__, fin, fspi, post, pre); 282 283 /* Resulting frequency for the SCLK line. */ 284 *fres = (fin / (pre + 1)) >> post; 285 286 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) | 287 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET); 288 } 289 290 static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable) 291 { 292 unsigned val = 0; 293 294 if (enable & MXC_INT_TE) 295 val |= MX51_ECSPI_INT_TEEN; 296 297 if (enable & MXC_INT_RR) 298 val |= MX51_ECSPI_INT_RREN; 299 300 writel(val, spi_imx->base + MX51_ECSPI_INT); 301 } 302 303 static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx) 304 { 305 u32 reg = readl(spi_imx->base + MX51_ECSPI_CTRL); 306 307 if (!spi_imx->usedma) 308 reg |= MX51_ECSPI_CTRL_XCH; 309 else if (!spi_imx->dma_finished) 310 reg |= MX51_ECSPI_CTRL_SMC; 311 else 312 reg &= ~MX51_ECSPI_CTRL_SMC; 313 writel(reg, spi_imx->base + MX51_ECSPI_CTRL); 314 } 315 316 static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx, 317 struct spi_imx_config *config) 318 { 319 u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0, dma = 0; 320 u32 tx_wml_cfg, rx_wml_cfg, rxt_wml_cfg; 321 u32 clk = config->speed_hz, delay, reg; 322 323 /* 324 * The hardware seems to have a race condition when changing modes. The 325 * current assumption is that the selection of the channel arrives 326 * earlier in the hardware than the mode bits when they are written at 327 * the same time. 328 * So set master mode for all channels as we do not support slave mode. 329 */ 330 ctrl |= MX51_ECSPI_CTRL_MODE_MASK; 331 332 /* set clock speed */ 333 ctrl |= mx51_ecspi_clkdiv(spi_imx->spi_clk, config->speed_hz, &clk); 334 335 /* set chip select to use */ 336 ctrl |= MX51_ECSPI_CTRL_CS(config->cs); 337 338 ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET; 339 340 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(config->cs); 341 342 if (config->mode & SPI_CPHA) 343 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs); 344 else 345 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(config->cs); 346 347 if (config->mode & SPI_CPOL) { 348 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs); 349 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(config->cs); 350 } else { 351 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(config->cs); 352 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(config->cs); 353 } 354 if (config->mode & SPI_CS_HIGH) 355 cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs); 356 else 357 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(config->cs); 358 359 /* CTRL register always go first to bring out controller from reset */ 360 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); 361 362 reg = readl(spi_imx->base + MX51_ECSPI_TESTREG); 363 if (config->mode & SPI_LOOP) 364 reg |= MX51_ECSPI_TESTREG_LBC; 365 else 366 reg &= ~MX51_ECSPI_TESTREG_LBC; 367 writel(reg, spi_imx->base + MX51_ECSPI_TESTREG); 368 369 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); 370 371 /* 372 * Wait until the changes in the configuration register CONFIGREG 373 * propagate into the hardware. It takes exactly one tick of the 374 * SCLK clock, but we will wait two SCLK clock just to be sure. The 375 * effect of the delay it takes for the hardware to apply changes 376 * is noticable if the SCLK clock run very slow. In such a case, if 377 * the polarity of SCLK should be inverted, the GPIO ChipSelect might 378 * be asserted before the SCLK polarity changes, which would disrupt 379 * the SPI communication as the device on the other end would consider 380 * the change of SCLK polarity as a clock tick already. 381 */ 382 delay = (2 * 1000000) / clk; 383 if (likely(delay < 10)) /* SCLK is faster than 100 kHz */ 384 udelay(delay); 385 else /* SCLK is _very_ slow */ 386 usleep_range(delay, delay + 10); 387 388 /* 389 * Configure the DMA register: setup the watermark 390 * and enable DMA request. 391 */ 392 if (spi_imx->dma_is_inited) { 393 dma = readl(spi_imx->base + MX51_ECSPI_DMA); 394 395 rx_wml_cfg = spi_imx->wml << MX51_ECSPI_DMA_RX_WML_OFFSET; 396 tx_wml_cfg = spi_imx->wml << MX51_ECSPI_DMA_TX_WML_OFFSET; 397 rxt_wml_cfg = spi_imx->wml << MX51_ECSPI_DMA_RXT_WML_OFFSET; 398 dma = (dma & ~MX51_ECSPI_DMA_TX_WML_MASK 399 & ~MX51_ECSPI_DMA_RX_WML_MASK 400 & ~MX51_ECSPI_DMA_RXT_WML_MASK) 401 | rx_wml_cfg | tx_wml_cfg | rxt_wml_cfg 402 |(1 << MX51_ECSPI_DMA_TEDEN_OFFSET) 403 |(1 << MX51_ECSPI_DMA_RXDEN_OFFSET) 404 |(1 << MX51_ECSPI_DMA_RXTDEN_OFFSET); 405 406 writel(dma, spi_imx->base + MX51_ECSPI_DMA); 407 } 408 409 return 0; 410 } 411 412 static int __maybe_unused mx51_ecspi_rx_available(struct spi_imx_data *spi_imx) 413 { 414 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR; 415 } 416 417 static void __maybe_unused mx51_ecspi_reset(struct spi_imx_data *spi_imx) 418 { 419 /* drain receive buffer */ 420 while (mx51_ecspi_rx_available(spi_imx)) 421 readl(spi_imx->base + MXC_CSPIRXDATA); 422 } 423 424 #define MX31_INTREG_TEEN (1 << 0) 425 #define MX31_INTREG_RREN (1 << 3) 426 427 #define MX31_CSPICTRL_ENABLE (1 << 0) 428 #define MX31_CSPICTRL_MASTER (1 << 1) 429 #define MX31_CSPICTRL_XCH (1 << 2) 430 #define MX31_CSPICTRL_POL (1 << 4) 431 #define MX31_CSPICTRL_PHA (1 << 5) 432 #define MX31_CSPICTRL_SSCTL (1 << 6) 433 #define MX31_CSPICTRL_SSPOL (1 << 7) 434 #define MX31_CSPICTRL_BC_SHIFT 8 435 #define MX35_CSPICTRL_BL_SHIFT 20 436 #define MX31_CSPICTRL_CS_SHIFT 24 437 #define MX35_CSPICTRL_CS_SHIFT 12 438 #define MX31_CSPICTRL_DR_SHIFT 16 439 440 #define MX31_CSPISTATUS 0x14 441 #define MX31_STATUS_RR (1 << 3) 442 443 /* These functions also work for the i.MX35, but be aware that 444 * the i.MX35 has a slightly different register layout for bits 445 * we do not use here. 446 */ 447 static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable) 448 { 449 unsigned int val = 0; 450 451 if (enable & MXC_INT_TE) 452 val |= MX31_INTREG_TEEN; 453 if (enable & MXC_INT_RR) 454 val |= MX31_INTREG_RREN; 455 456 writel(val, spi_imx->base + MXC_CSPIINT); 457 } 458 459 static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx) 460 { 461 unsigned int reg; 462 463 reg = readl(spi_imx->base + MXC_CSPICTRL); 464 reg |= MX31_CSPICTRL_XCH; 465 writel(reg, spi_imx->base + MXC_CSPICTRL); 466 } 467 468 static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx, 469 struct spi_imx_config *config) 470 { 471 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER; 472 int cs = spi_imx->chipselect[config->cs]; 473 474 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) << 475 MX31_CSPICTRL_DR_SHIFT; 476 477 if (is_imx35_cspi(spi_imx)) { 478 reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT; 479 reg |= MX31_CSPICTRL_SSCTL; 480 } else { 481 reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT; 482 } 483 484 if (config->mode & SPI_CPHA) 485 reg |= MX31_CSPICTRL_PHA; 486 if (config->mode & SPI_CPOL) 487 reg |= MX31_CSPICTRL_POL; 488 if (config->mode & SPI_CS_HIGH) 489 reg |= MX31_CSPICTRL_SSPOL; 490 if (cs < 0) 491 reg |= (cs + 32) << 492 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT : 493 MX31_CSPICTRL_CS_SHIFT); 494 495 writel(reg, spi_imx->base + MXC_CSPICTRL); 496 497 return 0; 498 } 499 500 static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx) 501 { 502 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; 503 } 504 505 static void __maybe_unused mx31_reset(struct spi_imx_data *spi_imx) 506 { 507 /* drain receive buffer */ 508 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR) 509 readl(spi_imx->base + MXC_CSPIRXDATA); 510 } 511 512 #define MX21_INTREG_RR (1 << 4) 513 #define MX21_INTREG_TEEN (1 << 9) 514 #define MX21_INTREG_RREN (1 << 13) 515 516 #define MX21_CSPICTRL_POL (1 << 5) 517 #define MX21_CSPICTRL_PHA (1 << 6) 518 #define MX21_CSPICTRL_SSPOL (1 << 8) 519 #define MX21_CSPICTRL_XCH (1 << 9) 520 #define MX21_CSPICTRL_ENABLE (1 << 10) 521 #define MX21_CSPICTRL_MASTER (1 << 11) 522 #define MX21_CSPICTRL_DR_SHIFT 14 523 #define MX21_CSPICTRL_CS_SHIFT 19 524 525 static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable) 526 { 527 unsigned int val = 0; 528 529 if (enable & MXC_INT_TE) 530 val |= MX21_INTREG_TEEN; 531 if (enable & MXC_INT_RR) 532 val |= MX21_INTREG_RREN; 533 534 writel(val, spi_imx->base + MXC_CSPIINT); 535 } 536 537 static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx) 538 { 539 unsigned int reg; 540 541 reg = readl(spi_imx->base + MXC_CSPICTRL); 542 reg |= MX21_CSPICTRL_XCH; 543 writel(reg, spi_imx->base + MXC_CSPICTRL); 544 } 545 546 static int __maybe_unused mx21_config(struct spi_imx_data *spi_imx, 547 struct spi_imx_config *config) 548 { 549 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER; 550 int cs = spi_imx->chipselect[config->cs]; 551 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18; 552 553 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max) << 554 MX21_CSPICTRL_DR_SHIFT; 555 reg |= config->bpw - 1; 556 557 if (config->mode & SPI_CPHA) 558 reg |= MX21_CSPICTRL_PHA; 559 if (config->mode & SPI_CPOL) 560 reg |= MX21_CSPICTRL_POL; 561 if (config->mode & SPI_CS_HIGH) 562 reg |= MX21_CSPICTRL_SSPOL; 563 if (cs < 0) 564 reg |= (cs + 32) << MX21_CSPICTRL_CS_SHIFT; 565 566 writel(reg, spi_imx->base + MXC_CSPICTRL); 567 568 return 0; 569 } 570 571 static int __maybe_unused mx21_rx_available(struct spi_imx_data *spi_imx) 572 { 573 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR; 574 } 575 576 static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx) 577 { 578 writel(1, spi_imx->base + MXC_RESET); 579 } 580 581 #define MX1_INTREG_RR (1 << 3) 582 #define MX1_INTREG_TEEN (1 << 8) 583 #define MX1_INTREG_RREN (1 << 11) 584 585 #define MX1_CSPICTRL_POL (1 << 4) 586 #define MX1_CSPICTRL_PHA (1 << 5) 587 #define MX1_CSPICTRL_XCH (1 << 8) 588 #define MX1_CSPICTRL_ENABLE (1 << 9) 589 #define MX1_CSPICTRL_MASTER (1 << 10) 590 #define MX1_CSPICTRL_DR_SHIFT 13 591 592 static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable) 593 { 594 unsigned int val = 0; 595 596 if (enable & MXC_INT_TE) 597 val |= MX1_INTREG_TEEN; 598 if (enable & MXC_INT_RR) 599 val |= MX1_INTREG_RREN; 600 601 writel(val, spi_imx->base + MXC_CSPIINT); 602 } 603 604 static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx) 605 { 606 unsigned int reg; 607 608 reg = readl(spi_imx->base + MXC_CSPICTRL); 609 reg |= MX1_CSPICTRL_XCH; 610 writel(reg, spi_imx->base + MXC_CSPICTRL); 611 } 612 613 static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx, 614 struct spi_imx_config *config) 615 { 616 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER; 617 618 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) << 619 MX1_CSPICTRL_DR_SHIFT; 620 reg |= config->bpw - 1; 621 622 if (config->mode & SPI_CPHA) 623 reg |= MX1_CSPICTRL_PHA; 624 if (config->mode & SPI_CPOL) 625 reg |= MX1_CSPICTRL_POL; 626 627 writel(reg, spi_imx->base + MXC_CSPICTRL); 628 629 return 0; 630 } 631 632 static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx) 633 { 634 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; 635 } 636 637 static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx) 638 { 639 writel(1, spi_imx->base + MXC_RESET); 640 } 641 642 static struct spi_imx_devtype_data imx1_cspi_devtype_data = { 643 .intctrl = mx1_intctrl, 644 .config = mx1_config, 645 .trigger = mx1_trigger, 646 .rx_available = mx1_rx_available, 647 .reset = mx1_reset, 648 .devtype = IMX1_CSPI, 649 }; 650 651 static struct spi_imx_devtype_data imx21_cspi_devtype_data = { 652 .intctrl = mx21_intctrl, 653 .config = mx21_config, 654 .trigger = mx21_trigger, 655 .rx_available = mx21_rx_available, 656 .reset = mx21_reset, 657 .devtype = IMX21_CSPI, 658 }; 659 660 static struct spi_imx_devtype_data imx27_cspi_devtype_data = { 661 /* i.mx27 cspi shares the functions with i.mx21 one */ 662 .intctrl = mx21_intctrl, 663 .config = mx21_config, 664 .trigger = mx21_trigger, 665 .rx_available = mx21_rx_available, 666 .reset = mx21_reset, 667 .devtype = IMX27_CSPI, 668 }; 669 670 static struct spi_imx_devtype_data imx31_cspi_devtype_data = { 671 .intctrl = mx31_intctrl, 672 .config = mx31_config, 673 .trigger = mx31_trigger, 674 .rx_available = mx31_rx_available, 675 .reset = mx31_reset, 676 .devtype = IMX31_CSPI, 677 }; 678 679 static struct spi_imx_devtype_data imx35_cspi_devtype_data = { 680 /* i.mx35 and later cspi shares the functions with i.mx31 one */ 681 .intctrl = mx31_intctrl, 682 .config = mx31_config, 683 .trigger = mx31_trigger, 684 .rx_available = mx31_rx_available, 685 .reset = mx31_reset, 686 .devtype = IMX35_CSPI, 687 }; 688 689 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = { 690 .intctrl = mx51_ecspi_intctrl, 691 .config = mx51_ecspi_config, 692 .trigger = mx51_ecspi_trigger, 693 .rx_available = mx51_ecspi_rx_available, 694 .reset = mx51_ecspi_reset, 695 .devtype = IMX51_ECSPI, 696 }; 697 698 static const struct platform_device_id spi_imx_devtype[] = { 699 { 700 .name = "imx1-cspi", 701 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data, 702 }, { 703 .name = "imx21-cspi", 704 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data, 705 }, { 706 .name = "imx27-cspi", 707 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data, 708 }, { 709 .name = "imx31-cspi", 710 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data, 711 }, { 712 .name = "imx35-cspi", 713 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data, 714 }, { 715 .name = "imx51-ecspi", 716 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data, 717 }, { 718 /* sentinel */ 719 } 720 }; 721 722 static const struct of_device_id spi_imx_dt_ids[] = { 723 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, }, 724 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, }, 725 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, }, 726 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, }, 727 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, }, 728 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, }, 729 { /* sentinel */ } 730 }; 731 MODULE_DEVICE_TABLE(of, spi_imx_dt_ids); 732 733 static void spi_imx_chipselect(struct spi_device *spi, int is_active) 734 { 735 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 736 int gpio = spi_imx->chipselect[spi->chip_select]; 737 int active = is_active != BITBANG_CS_INACTIVE; 738 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH); 739 740 if (!gpio_is_valid(gpio)) 741 return; 742 743 gpio_set_value(gpio, dev_is_lowactive ^ active); 744 } 745 746 static void spi_imx_push(struct spi_imx_data *spi_imx) 747 { 748 while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) { 749 if (!spi_imx->count) 750 break; 751 spi_imx->tx(spi_imx); 752 spi_imx->txfifo++; 753 } 754 755 spi_imx->devtype_data->trigger(spi_imx); 756 } 757 758 static irqreturn_t spi_imx_isr(int irq, void *dev_id) 759 { 760 struct spi_imx_data *spi_imx = dev_id; 761 762 while (spi_imx->devtype_data->rx_available(spi_imx)) { 763 spi_imx->rx(spi_imx); 764 spi_imx->txfifo--; 765 } 766 767 if (spi_imx->count) { 768 spi_imx_push(spi_imx); 769 return IRQ_HANDLED; 770 } 771 772 if (spi_imx->txfifo) { 773 /* No data left to push, but still waiting for rx data, 774 * enable receive data available interrupt. 775 */ 776 spi_imx->devtype_data->intctrl( 777 spi_imx, MXC_INT_RR); 778 return IRQ_HANDLED; 779 } 780 781 spi_imx->devtype_data->intctrl(spi_imx, 0); 782 complete(&spi_imx->xfer_done); 783 784 return IRQ_HANDLED; 785 } 786 787 static int spi_imx_setupxfer(struct spi_device *spi, 788 struct spi_transfer *t) 789 { 790 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 791 struct spi_imx_config config; 792 793 config.bpw = t ? t->bits_per_word : spi->bits_per_word; 794 config.speed_hz = t ? t->speed_hz : spi->max_speed_hz; 795 config.mode = spi->mode; 796 config.cs = spi->chip_select; 797 798 if (!config.speed_hz) 799 config.speed_hz = spi->max_speed_hz; 800 if (!config.bpw) 801 config.bpw = spi->bits_per_word; 802 803 /* Initialize the functions for transfer */ 804 if (config.bpw <= 8) { 805 spi_imx->rx = spi_imx_buf_rx_u8; 806 spi_imx->tx = spi_imx_buf_tx_u8; 807 } else if (config.bpw <= 16) { 808 spi_imx->rx = spi_imx_buf_rx_u16; 809 spi_imx->tx = spi_imx_buf_tx_u16; 810 } else { 811 spi_imx->rx = spi_imx_buf_rx_u32; 812 spi_imx->tx = spi_imx_buf_tx_u32; 813 } 814 815 spi_imx->devtype_data->config(spi_imx, &config); 816 817 return 0; 818 } 819 820 static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx) 821 { 822 struct spi_master *master = spi_imx->bitbang.master; 823 824 if (master->dma_rx) { 825 dma_release_channel(master->dma_rx); 826 master->dma_rx = NULL; 827 } 828 829 if (master->dma_tx) { 830 dma_release_channel(master->dma_tx); 831 master->dma_tx = NULL; 832 } 833 834 spi_imx->dma_is_inited = 0; 835 } 836 837 static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx, 838 struct spi_master *master, 839 const struct resource *res) 840 { 841 struct dma_slave_config slave_config = {}; 842 int ret; 843 844 /* use pio mode for i.mx6dl chip TKT238285 */ 845 if (of_machine_is_compatible("fsl,imx6dl")) 846 return 0; 847 848 spi_imx->wml = spi_imx_get_fifosize(spi_imx) / 2; 849 850 /* Prepare for TX DMA: */ 851 master->dma_tx = dma_request_slave_channel_reason(dev, "tx"); 852 if (IS_ERR(master->dma_tx)) { 853 ret = PTR_ERR(master->dma_tx); 854 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret); 855 master->dma_tx = NULL; 856 goto err; 857 } 858 859 slave_config.direction = DMA_MEM_TO_DEV; 860 slave_config.dst_addr = res->start + MXC_CSPITXDATA; 861 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 862 slave_config.dst_maxburst = spi_imx->wml; 863 ret = dmaengine_slave_config(master->dma_tx, &slave_config); 864 if (ret) { 865 dev_err(dev, "error in TX dma configuration.\n"); 866 goto err; 867 } 868 869 /* Prepare for RX : */ 870 master->dma_rx = dma_request_slave_channel_reason(dev, "rx"); 871 if (IS_ERR(master->dma_rx)) { 872 ret = PTR_ERR(master->dma_rx); 873 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret); 874 master->dma_rx = NULL; 875 goto err; 876 } 877 878 slave_config.direction = DMA_DEV_TO_MEM; 879 slave_config.src_addr = res->start + MXC_CSPIRXDATA; 880 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 881 slave_config.src_maxburst = spi_imx->wml; 882 ret = dmaengine_slave_config(master->dma_rx, &slave_config); 883 if (ret) { 884 dev_err(dev, "error in RX dma configuration.\n"); 885 goto err; 886 } 887 888 init_completion(&spi_imx->dma_rx_completion); 889 init_completion(&spi_imx->dma_tx_completion); 890 master->can_dma = spi_imx_can_dma; 891 master->max_dma_len = MAX_SDMA_BD_BYTES; 892 spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX | 893 SPI_MASTER_MUST_TX; 894 spi_imx->dma_is_inited = 1; 895 896 return 0; 897 err: 898 spi_imx_sdma_exit(spi_imx); 899 return ret; 900 } 901 902 static void spi_imx_dma_rx_callback(void *cookie) 903 { 904 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie; 905 906 complete(&spi_imx->dma_rx_completion); 907 } 908 909 static void spi_imx_dma_tx_callback(void *cookie) 910 { 911 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie; 912 913 complete(&spi_imx->dma_tx_completion); 914 } 915 916 static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx, 917 struct spi_transfer *transfer) 918 { 919 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL; 920 int ret; 921 unsigned long timeout; 922 u32 dma; 923 int left; 924 struct spi_master *master = spi_imx->bitbang.master; 925 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg; 926 927 if (tx) { 928 desc_tx = dmaengine_prep_slave_sg(master->dma_tx, 929 tx->sgl, tx->nents, DMA_MEM_TO_DEV, 930 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 931 if (!desc_tx) 932 goto no_dma; 933 934 desc_tx->callback = spi_imx_dma_tx_callback; 935 desc_tx->callback_param = (void *)spi_imx; 936 dmaengine_submit(desc_tx); 937 } 938 939 if (rx) { 940 desc_rx = dmaengine_prep_slave_sg(master->dma_rx, 941 rx->sgl, rx->nents, DMA_DEV_TO_MEM, 942 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 943 if (!desc_rx) 944 goto no_dma; 945 946 desc_rx->callback = spi_imx_dma_rx_callback; 947 desc_rx->callback_param = (void *)spi_imx; 948 dmaengine_submit(desc_rx); 949 } 950 951 reinit_completion(&spi_imx->dma_rx_completion); 952 reinit_completion(&spi_imx->dma_tx_completion); 953 954 /* Trigger the cspi module. */ 955 spi_imx->dma_finished = 0; 956 957 dma = readl(spi_imx->base + MX51_ECSPI_DMA); 958 dma = dma & (~MX51_ECSPI_DMA_RXT_WML_MASK); 959 /* Change RX_DMA_LENGTH trigger dma fetch tail data */ 960 left = transfer->len % spi_imx->wml; 961 if (left) 962 writel(dma | (left << MX51_ECSPI_DMA_RXT_WML_OFFSET), 963 spi_imx->base + MX51_ECSPI_DMA); 964 /* 965 * Set these order to avoid potential RX overflow. The overflow may 966 * happen if we enable SPI HW before starting RX DMA due to rescheduling 967 * for another task and/or interrupt. 968 * So RX DMA enabled first to make sure data would be read out from FIFO 969 * ASAP. TX DMA enabled next to start filling TX FIFO with new data. 970 * And finaly SPI HW enabled to start actual data transfer. 971 */ 972 dma_async_issue_pending(master->dma_rx); 973 dma_async_issue_pending(master->dma_tx); 974 spi_imx->devtype_data->trigger(spi_imx); 975 976 /* Wait SDMA to finish the data transfer.*/ 977 timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion, 978 IMX_DMA_TIMEOUT); 979 if (!timeout) { 980 pr_warn("%s %s: I/O Error in DMA TX\n", 981 dev_driver_string(&master->dev), 982 dev_name(&master->dev)); 983 dmaengine_terminate_all(master->dma_tx); 984 dmaengine_terminate_all(master->dma_rx); 985 } else { 986 timeout = wait_for_completion_timeout( 987 &spi_imx->dma_rx_completion, IMX_DMA_TIMEOUT); 988 if (!timeout) { 989 pr_warn("%s %s: I/O Error in DMA RX\n", 990 dev_driver_string(&master->dev), 991 dev_name(&master->dev)); 992 spi_imx->devtype_data->reset(spi_imx); 993 dmaengine_terminate_all(master->dma_rx); 994 } 995 dma &= ~MX51_ECSPI_DMA_RXT_WML_MASK; 996 writel(dma | 997 spi_imx->wml << MX51_ECSPI_DMA_RXT_WML_OFFSET, 998 spi_imx->base + MX51_ECSPI_DMA); 999 } 1000 1001 spi_imx->dma_finished = 1; 1002 spi_imx->devtype_data->trigger(spi_imx); 1003 1004 if (!timeout) 1005 ret = -ETIMEDOUT; 1006 else 1007 ret = transfer->len; 1008 1009 return ret; 1010 1011 no_dma: 1012 pr_warn_once("%s %s: DMA not available, falling back to PIO\n", 1013 dev_driver_string(&master->dev), 1014 dev_name(&master->dev)); 1015 return -EAGAIN; 1016 } 1017 1018 static int spi_imx_pio_transfer(struct spi_device *spi, 1019 struct spi_transfer *transfer) 1020 { 1021 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 1022 1023 spi_imx->tx_buf = transfer->tx_buf; 1024 spi_imx->rx_buf = transfer->rx_buf; 1025 spi_imx->count = transfer->len; 1026 spi_imx->txfifo = 0; 1027 1028 reinit_completion(&spi_imx->xfer_done); 1029 1030 spi_imx_push(spi_imx); 1031 1032 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE); 1033 1034 wait_for_completion(&spi_imx->xfer_done); 1035 1036 return transfer->len; 1037 } 1038 1039 static int spi_imx_transfer(struct spi_device *spi, 1040 struct spi_transfer *transfer) 1041 { 1042 int ret; 1043 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 1044 1045 if (spi_imx->bitbang.master->can_dma && 1046 spi_imx_can_dma(spi_imx->bitbang.master, spi, transfer)) { 1047 spi_imx->usedma = true; 1048 ret = spi_imx_dma_transfer(spi_imx, transfer); 1049 if (ret != -EAGAIN) 1050 return ret; 1051 } 1052 spi_imx->usedma = false; 1053 1054 return spi_imx_pio_transfer(spi, transfer); 1055 } 1056 1057 static int spi_imx_setup(struct spi_device *spi) 1058 { 1059 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 1060 int gpio = spi_imx->chipselect[spi->chip_select]; 1061 1062 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__, 1063 spi->mode, spi->bits_per_word, spi->max_speed_hz); 1064 1065 if (gpio_is_valid(gpio)) 1066 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1); 1067 1068 spi_imx_chipselect(spi, BITBANG_CS_INACTIVE); 1069 1070 return 0; 1071 } 1072 1073 static void spi_imx_cleanup(struct spi_device *spi) 1074 { 1075 } 1076 1077 static int 1078 spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg) 1079 { 1080 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 1081 int ret; 1082 1083 ret = clk_enable(spi_imx->clk_per); 1084 if (ret) 1085 return ret; 1086 1087 ret = clk_enable(spi_imx->clk_ipg); 1088 if (ret) { 1089 clk_disable(spi_imx->clk_per); 1090 return ret; 1091 } 1092 1093 return 0; 1094 } 1095 1096 static int 1097 spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg) 1098 { 1099 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 1100 1101 clk_disable(spi_imx->clk_ipg); 1102 clk_disable(spi_imx->clk_per); 1103 return 0; 1104 } 1105 1106 static int spi_imx_probe(struct platform_device *pdev) 1107 { 1108 struct device_node *np = pdev->dev.of_node; 1109 const struct of_device_id *of_id = 1110 of_match_device(spi_imx_dt_ids, &pdev->dev); 1111 struct spi_imx_master *mxc_platform_info = 1112 dev_get_platdata(&pdev->dev); 1113 struct spi_master *master; 1114 struct spi_imx_data *spi_imx; 1115 struct resource *res; 1116 int i, ret, num_cs, irq; 1117 1118 if (!np && !mxc_platform_info) { 1119 dev_err(&pdev->dev, "can't get the platform data\n"); 1120 return -EINVAL; 1121 } 1122 1123 ret = of_property_read_u32(np, "fsl,spi-num-chipselects", &num_cs); 1124 if (ret < 0) { 1125 if (mxc_platform_info) 1126 num_cs = mxc_platform_info->num_chipselect; 1127 else 1128 return ret; 1129 } 1130 1131 master = spi_alloc_master(&pdev->dev, 1132 sizeof(struct spi_imx_data) + sizeof(int) * num_cs); 1133 if (!master) 1134 return -ENOMEM; 1135 1136 platform_set_drvdata(pdev, master); 1137 1138 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); 1139 master->bus_num = pdev->id; 1140 master->num_chipselect = num_cs; 1141 1142 spi_imx = spi_master_get_devdata(master); 1143 spi_imx->bitbang.master = master; 1144 1145 spi_imx->devtype_data = of_id ? of_id->data : 1146 (struct spi_imx_devtype_data *)pdev->id_entry->driver_data; 1147 1148 for (i = 0; i < master->num_chipselect; i++) { 1149 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i); 1150 if (!gpio_is_valid(cs_gpio) && mxc_platform_info) 1151 cs_gpio = mxc_platform_info->chipselect[i]; 1152 1153 spi_imx->chipselect[i] = cs_gpio; 1154 if (!gpio_is_valid(cs_gpio)) 1155 continue; 1156 1157 ret = devm_gpio_request(&pdev->dev, spi_imx->chipselect[i], 1158 DRIVER_NAME); 1159 if (ret) { 1160 dev_err(&pdev->dev, "can't get cs gpios\n"); 1161 goto out_master_put; 1162 } 1163 } 1164 1165 spi_imx->bitbang.chipselect = spi_imx_chipselect; 1166 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer; 1167 spi_imx->bitbang.txrx_bufs = spi_imx_transfer; 1168 spi_imx->bitbang.master->setup = spi_imx_setup; 1169 spi_imx->bitbang.master->cleanup = spi_imx_cleanup; 1170 spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message; 1171 spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message; 1172 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1173 if (is_imx51_ecspi(spi_imx)) 1174 spi_imx->bitbang.master->mode_bits |= SPI_LOOP; 1175 1176 init_completion(&spi_imx->xfer_done); 1177 1178 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1179 spi_imx->base = devm_ioremap_resource(&pdev->dev, res); 1180 if (IS_ERR(spi_imx->base)) { 1181 ret = PTR_ERR(spi_imx->base); 1182 goto out_master_put; 1183 } 1184 1185 irq = platform_get_irq(pdev, 0); 1186 if (irq < 0) { 1187 ret = irq; 1188 goto out_master_put; 1189 } 1190 1191 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0, 1192 dev_name(&pdev->dev), spi_imx); 1193 if (ret) { 1194 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret); 1195 goto out_master_put; 1196 } 1197 1198 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1199 if (IS_ERR(spi_imx->clk_ipg)) { 1200 ret = PTR_ERR(spi_imx->clk_ipg); 1201 goto out_master_put; 1202 } 1203 1204 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per"); 1205 if (IS_ERR(spi_imx->clk_per)) { 1206 ret = PTR_ERR(spi_imx->clk_per); 1207 goto out_master_put; 1208 } 1209 1210 ret = clk_prepare_enable(spi_imx->clk_per); 1211 if (ret) 1212 goto out_master_put; 1213 1214 ret = clk_prepare_enable(spi_imx->clk_ipg); 1215 if (ret) 1216 goto out_put_per; 1217 1218 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per); 1219 /* 1220 * Only validated on i.mx6 now, can remove the constrain if validated on 1221 * other chips. 1222 */ 1223 if (is_imx51_ecspi(spi_imx)) { 1224 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master, res); 1225 if (ret == -EPROBE_DEFER) 1226 goto out_clk_put; 1227 1228 if (ret < 0) 1229 dev_err(&pdev->dev, "dma setup error %d, use pio\n", 1230 ret); 1231 } 1232 1233 spi_imx->devtype_data->reset(spi_imx); 1234 1235 spi_imx->devtype_data->intctrl(spi_imx, 0); 1236 1237 master->dev.of_node = pdev->dev.of_node; 1238 ret = spi_bitbang_start(&spi_imx->bitbang); 1239 if (ret) { 1240 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret); 1241 goto out_clk_put; 1242 } 1243 1244 dev_info(&pdev->dev, "probed\n"); 1245 1246 clk_disable(spi_imx->clk_ipg); 1247 clk_disable(spi_imx->clk_per); 1248 return ret; 1249 1250 out_clk_put: 1251 clk_disable_unprepare(spi_imx->clk_ipg); 1252 out_put_per: 1253 clk_disable_unprepare(spi_imx->clk_per); 1254 out_master_put: 1255 spi_master_put(master); 1256 1257 return ret; 1258 } 1259 1260 static int spi_imx_remove(struct platform_device *pdev) 1261 { 1262 struct spi_master *master = platform_get_drvdata(pdev); 1263 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 1264 1265 spi_bitbang_stop(&spi_imx->bitbang); 1266 1267 writel(0, spi_imx->base + MXC_CSPICTRL); 1268 clk_unprepare(spi_imx->clk_ipg); 1269 clk_unprepare(spi_imx->clk_per); 1270 spi_imx_sdma_exit(spi_imx); 1271 spi_master_put(master); 1272 1273 return 0; 1274 } 1275 1276 static struct platform_driver spi_imx_driver = { 1277 .driver = { 1278 .name = DRIVER_NAME, 1279 .of_match_table = spi_imx_dt_ids, 1280 }, 1281 .id_table = spi_imx_devtype, 1282 .probe = spi_imx_probe, 1283 .remove = spi_imx_remove, 1284 }; 1285 module_platform_driver(spi_imx_driver); 1286 1287 MODULE_DESCRIPTION("SPI Master Controller driver"); 1288 MODULE_AUTHOR("Sascha Hauer, Pengutronix"); 1289 MODULE_LICENSE("GPL"); 1290 MODULE_ALIAS("platform:" DRIVER_NAME); 1291