1 /* 2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 3 * Copyright (C) 2008 Juergen Beisert 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 2 8 * of the License, or (at your option) any later version. 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the 16 * Free Software Foundation 17 * 51 Franklin Street, Fifth Floor 18 * Boston, MA 02110-1301, USA. 19 */ 20 21 #include <linux/clk.h> 22 #include <linux/completion.h> 23 #include <linux/delay.h> 24 #include <linux/dmaengine.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/err.h> 27 #include <linux/gpio.h> 28 #include <linux/interrupt.h> 29 #include <linux/io.h> 30 #include <linux/irq.h> 31 #include <linux/kernel.h> 32 #include <linux/module.h> 33 #include <linux/platform_device.h> 34 #include <linux/slab.h> 35 #include <linux/spi/spi.h> 36 #include <linux/spi/spi_bitbang.h> 37 #include <linux/types.h> 38 #include <linux/of.h> 39 #include <linux/of_device.h> 40 #include <linux/of_gpio.h> 41 42 #include <linux/platform_data/dma-imx.h> 43 #include <linux/platform_data/spi-imx.h> 44 45 #define DRIVER_NAME "spi_imx" 46 47 #define MXC_CSPIRXDATA 0x00 48 #define MXC_CSPITXDATA 0x04 49 #define MXC_CSPICTRL 0x08 50 #define MXC_CSPIINT 0x0c 51 #define MXC_RESET 0x1c 52 53 /* generic defines to abstract from the different register layouts */ 54 #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */ 55 #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */ 56 57 /* The maximum bytes that a sdma BD can transfer.*/ 58 #define MAX_SDMA_BD_BYTES (1 << 15) 59 struct spi_imx_config { 60 unsigned int speed_hz; 61 unsigned int bpw; 62 }; 63 64 enum spi_imx_devtype { 65 IMX1_CSPI, 66 IMX21_CSPI, 67 IMX27_CSPI, 68 IMX31_CSPI, 69 IMX35_CSPI, /* CSPI on all i.mx except above */ 70 IMX51_ECSPI, /* ECSPI on i.mx51 and later */ 71 }; 72 73 struct spi_imx_data; 74 75 struct spi_imx_devtype_data { 76 void (*intctrl)(struct spi_imx_data *, int); 77 int (*config)(struct spi_device *, struct spi_imx_config *); 78 void (*trigger)(struct spi_imx_data *); 79 int (*rx_available)(struct spi_imx_data *); 80 void (*reset)(struct spi_imx_data *); 81 enum spi_imx_devtype devtype; 82 }; 83 84 struct spi_imx_data { 85 struct spi_bitbang bitbang; 86 struct device *dev; 87 88 struct completion xfer_done; 89 void __iomem *base; 90 unsigned long base_phys; 91 92 struct clk *clk_per; 93 struct clk *clk_ipg; 94 unsigned long spi_clk; 95 unsigned int spi_bus_clk; 96 97 unsigned int bytes_per_word; 98 99 unsigned int count; 100 void (*tx)(struct spi_imx_data *); 101 void (*rx)(struct spi_imx_data *); 102 void *rx_buf; 103 const void *tx_buf; 104 unsigned int txfifo; /* number of words pushed in tx FIFO */ 105 106 /* DMA */ 107 bool usedma; 108 u32 wml; 109 struct completion dma_rx_completion; 110 struct completion dma_tx_completion; 111 112 const struct spi_imx_devtype_data *devtype_data; 113 }; 114 115 static inline int is_imx27_cspi(struct spi_imx_data *d) 116 { 117 return d->devtype_data->devtype == IMX27_CSPI; 118 } 119 120 static inline int is_imx35_cspi(struct spi_imx_data *d) 121 { 122 return d->devtype_data->devtype == IMX35_CSPI; 123 } 124 125 static inline int is_imx51_ecspi(struct spi_imx_data *d) 126 { 127 return d->devtype_data->devtype == IMX51_ECSPI; 128 } 129 130 static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d) 131 { 132 return is_imx51_ecspi(d) ? 64 : 8; 133 } 134 135 #define MXC_SPI_BUF_RX(type) \ 136 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \ 137 { \ 138 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \ 139 \ 140 if (spi_imx->rx_buf) { \ 141 *(type *)spi_imx->rx_buf = val; \ 142 spi_imx->rx_buf += sizeof(type); \ 143 } \ 144 } 145 146 #define MXC_SPI_BUF_TX(type) \ 147 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \ 148 { \ 149 type val = 0; \ 150 \ 151 if (spi_imx->tx_buf) { \ 152 val = *(type *)spi_imx->tx_buf; \ 153 spi_imx->tx_buf += sizeof(type); \ 154 } \ 155 \ 156 spi_imx->count -= sizeof(type); \ 157 \ 158 writel(val, spi_imx->base + MXC_CSPITXDATA); \ 159 } 160 161 MXC_SPI_BUF_RX(u8) 162 MXC_SPI_BUF_TX(u8) 163 MXC_SPI_BUF_RX(u16) 164 MXC_SPI_BUF_TX(u16) 165 MXC_SPI_BUF_RX(u32) 166 MXC_SPI_BUF_TX(u32) 167 168 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set 169 * (which is currently not the case in this driver) 170 */ 171 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192, 172 256, 384, 512, 768, 1024}; 173 174 /* MX21, MX27 */ 175 static unsigned int spi_imx_clkdiv_1(unsigned int fin, 176 unsigned int fspi, unsigned int max, unsigned int *fres) 177 { 178 int i; 179 180 for (i = 2; i < max; i++) 181 if (fspi * mxc_clkdivs[i] >= fin) 182 break; 183 184 *fres = fin / mxc_clkdivs[i]; 185 return i; 186 } 187 188 /* MX1, MX31, MX35, MX51 CSPI */ 189 static unsigned int spi_imx_clkdiv_2(unsigned int fin, 190 unsigned int fspi, unsigned int *fres) 191 { 192 int i, div = 4; 193 194 for (i = 0; i < 7; i++) { 195 if (fspi * div >= fin) 196 goto out; 197 div <<= 1; 198 } 199 200 out: 201 *fres = fin / div; 202 return i; 203 } 204 205 static int spi_imx_bytes_per_word(const int bpw) 206 { 207 return DIV_ROUND_UP(bpw, BITS_PER_BYTE); 208 } 209 210 static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi, 211 struct spi_transfer *transfer) 212 { 213 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 214 unsigned int bpw, i; 215 216 if (!master->dma_rx) 217 return false; 218 219 if (!transfer) 220 return false; 221 222 bpw = transfer->bits_per_word; 223 if (!bpw) 224 bpw = spi->bits_per_word; 225 226 bpw = spi_imx_bytes_per_word(bpw); 227 228 if (bpw != 1 && bpw != 2 && bpw != 4) 229 return false; 230 231 for (i = spi_imx_get_fifosize(spi_imx) / 2; i > 0; i--) { 232 if (!(transfer->len % (i * bpw))) 233 break; 234 } 235 236 if (i == 0) 237 return false; 238 239 spi_imx->wml = i; 240 241 return true; 242 } 243 244 #define MX51_ECSPI_CTRL 0x08 245 #define MX51_ECSPI_CTRL_ENABLE (1 << 0) 246 #define MX51_ECSPI_CTRL_XCH (1 << 2) 247 #define MX51_ECSPI_CTRL_SMC (1 << 3) 248 #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4) 249 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8 250 #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12 251 #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18) 252 #define MX51_ECSPI_CTRL_BL_OFFSET 20 253 254 #define MX51_ECSPI_CONFIG 0x0c 255 #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0)) 256 #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4)) 257 #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8)) 258 #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12)) 259 #define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20)) 260 261 #define MX51_ECSPI_INT 0x10 262 #define MX51_ECSPI_INT_TEEN (1 << 0) 263 #define MX51_ECSPI_INT_RREN (1 << 3) 264 265 #define MX51_ECSPI_DMA 0x14 266 #define MX51_ECSPI_DMA_TX_WML(wml) ((wml) & 0x3f) 267 #define MX51_ECSPI_DMA_RX_WML(wml) (((wml) & 0x3f) << 16) 268 #define MX51_ECSPI_DMA_RXT_WML(wml) (((wml) & 0x3f) << 24) 269 270 #define MX51_ECSPI_DMA_TEDEN (1 << 7) 271 #define MX51_ECSPI_DMA_RXDEN (1 << 23) 272 #define MX51_ECSPI_DMA_RXTDEN (1 << 31) 273 274 #define MX51_ECSPI_STAT 0x18 275 #define MX51_ECSPI_STAT_RR (1 << 3) 276 277 #define MX51_ECSPI_TESTREG 0x20 278 #define MX51_ECSPI_TESTREG_LBC BIT(31) 279 280 /* MX51 eCSPI */ 281 static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx, 282 unsigned int fspi, unsigned int *fres) 283 { 284 /* 285 * there are two 4-bit dividers, the pre-divider divides by 286 * $pre, the post-divider by 2^$post 287 */ 288 unsigned int pre, post; 289 unsigned int fin = spi_imx->spi_clk; 290 291 if (unlikely(fspi > fin)) 292 return 0; 293 294 post = fls(fin) - fls(fspi); 295 if (fin > fspi << post) 296 post++; 297 298 /* now we have: (fin <= fspi << post) with post being minimal */ 299 300 post = max(4U, post) - 4; 301 if (unlikely(post > 0xf)) { 302 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n", 303 fspi, fin); 304 return 0xff; 305 } 306 307 pre = DIV_ROUND_UP(fin, fspi << post) - 1; 308 309 dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n", 310 __func__, fin, fspi, post, pre); 311 312 /* Resulting frequency for the SCLK line. */ 313 *fres = (fin / (pre + 1)) >> post; 314 315 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) | 316 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET); 317 } 318 319 static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable) 320 { 321 unsigned val = 0; 322 323 if (enable & MXC_INT_TE) 324 val |= MX51_ECSPI_INT_TEEN; 325 326 if (enable & MXC_INT_RR) 327 val |= MX51_ECSPI_INT_RREN; 328 329 writel(val, spi_imx->base + MX51_ECSPI_INT); 330 } 331 332 static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx) 333 { 334 u32 reg; 335 336 reg = readl(spi_imx->base + MX51_ECSPI_CTRL); 337 reg |= MX51_ECSPI_CTRL_XCH; 338 writel(reg, spi_imx->base + MX51_ECSPI_CTRL); 339 } 340 341 static int mx51_ecspi_config(struct spi_device *spi, 342 struct spi_imx_config *config) 343 { 344 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 345 u32 ctrl = MX51_ECSPI_CTRL_ENABLE; 346 u32 clk = config->speed_hz, delay, reg; 347 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG); 348 349 /* 350 * The hardware seems to have a race condition when changing modes. The 351 * current assumption is that the selection of the channel arrives 352 * earlier in the hardware than the mode bits when they are written at 353 * the same time. 354 * So set master mode for all channels as we do not support slave mode. 355 */ 356 ctrl |= MX51_ECSPI_CTRL_MODE_MASK; 357 358 /* set clock speed */ 359 ctrl |= mx51_ecspi_clkdiv(spi_imx, config->speed_hz, &clk); 360 spi_imx->spi_bus_clk = clk; 361 362 /* set chip select to use */ 363 ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select); 364 365 ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET; 366 367 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select); 368 369 if (spi->mode & SPI_CPHA) 370 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); 371 else 372 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); 373 374 if (spi->mode & SPI_CPOL) { 375 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); 376 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); 377 } else { 378 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); 379 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); 380 } 381 if (spi->mode & SPI_CS_HIGH) 382 cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select); 383 else 384 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select); 385 386 if (spi_imx->usedma) 387 ctrl |= MX51_ECSPI_CTRL_SMC; 388 389 /* CTRL register always go first to bring out controller from reset */ 390 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); 391 392 reg = readl(spi_imx->base + MX51_ECSPI_TESTREG); 393 if (spi->mode & SPI_LOOP) 394 reg |= MX51_ECSPI_TESTREG_LBC; 395 else 396 reg &= ~MX51_ECSPI_TESTREG_LBC; 397 writel(reg, spi_imx->base + MX51_ECSPI_TESTREG); 398 399 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); 400 401 /* 402 * Wait until the changes in the configuration register CONFIGREG 403 * propagate into the hardware. It takes exactly one tick of the 404 * SCLK clock, but we will wait two SCLK clock just to be sure. The 405 * effect of the delay it takes for the hardware to apply changes 406 * is noticable if the SCLK clock run very slow. In such a case, if 407 * the polarity of SCLK should be inverted, the GPIO ChipSelect might 408 * be asserted before the SCLK polarity changes, which would disrupt 409 * the SPI communication as the device on the other end would consider 410 * the change of SCLK polarity as a clock tick already. 411 */ 412 delay = (2 * 1000000) / clk; 413 if (likely(delay < 10)) /* SCLK is faster than 100 kHz */ 414 udelay(delay); 415 else /* SCLK is _very_ slow */ 416 usleep_range(delay, delay + 10); 417 418 /* 419 * Configure the DMA register: setup the watermark 420 * and enable DMA request. 421 */ 422 423 writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml) | 424 MX51_ECSPI_DMA_TX_WML(spi_imx->wml) | 425 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) | 426 MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN | 427 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA); 428 429 return 0; 430 } 431 432 static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx) 433 { 434 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR; 435 } 436 437 static void mx51_ecspi_reset(struct spi_imx_data *spi_imx) 438 { 439 /* drain receive buffer */ 440 while (mx51_ecspi_rx_available(spi_imx)) 441 readl(spi_imx->base + MXC_CSPIRXDATA); 442 } 443 444 #define MX31_INTREG_TEEN (1 << 0) 445 #define MX31_INTREG_RREN (1 << 3) 446 447 #define MX31_CSPICTRL_ENABLE (1 << 0) 448 #define MX31_CSPICTRL_MASTER (1 << 1) 449 #define MX31_CSPICTRL_XCH (1 << 2) 450 #define MX31_CSPICTRL_SMC (1 << 3) 451 #define MX31_CSPICTRL_POL (1 << 4) 452 #define MX31_CSPICTRL_PHA (1 << 5) 453 #define MX31_CSPICTRL_SSCTL (1 << 6) 454 #define MX31_CSPICTRL_SSPOL (1 << 7) 455 #define MX31_CSPICTRL_BC_SHIFT 8 456 #define MX35_CSPICTRL_BL_SHIFT 20 457 #define MX31_CSPICTRL_CS_SHIFT 24 458 #define MX35_CSPICTRL_CS_SHIFT 12 459 #define MX31_CSPICTRL_DR_SHIFT 16 460 461 #define MX31_CSPI_DMAREG 0x10 462 #define MX31_DMAREG_RH_DEN (1<<4) 463 #define MX31_DMAREG_TH_DEN (1<<1) 464 465 #define MX31_CSPISTATUS 0x14 466 #define MX31_STATUS_RR (1 << 3) 467 468 #define MX31_CSPI_TESTREG 0x1C 469 #define MX31_TEST_LBC (1 << 14) 470 471 /* These functions also work for the i.MX35, but be aware that 472 * the i.MX35 has a slightly different register layout for bits 473 * we do not use here. 474 */ 475 static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable) 476 { 477 unsigned int val = 0; 478 479 if (enable & MXC_INT_TE) 480 val |= MX31_INTREG_TEEN; 481 if (enable & MXC_INT_RR) 482 val |= MX31_INTREG_RREN; 483 484 writel(val, spi_imx->base + MXC_CSPIINT); 485 } 486 487 static void mx31_trigger(struct spi_imx_data *spi_imx) 488 { 489 unsigned int reg; 490 491 reg = readl(spi_imx->base + MXC_CSPICTRL); 492 reg |= MX31_CSPICTRL_XCH; 493 writel(reg, spi_imx->base + MXC_CSPICTRL); 494 } 495 496 static int mx31_config(struct spi_device *spi, struct spi_imx_config *config) 497 { 498 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 499 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER; 500 unsigned int clk; 501 502 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz, &clk) << 503 MX31_CSPICTRL_DR_SHIFT; 504 spi_imx->spi_bus_clk = clk; 505 506 if (is_imx35_cspi(spi_imx)) { 507 reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT; 508 reg |= MX31_CSPICTRL_SSCTL; 509 } else { 510 reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT; 511 } 512 513 if (spi->mode & SPI_CPHA) 514 reg |= MX31_CSPICTRL_PHA; 515 if (spi->mode & SPI_CPOL) 516 reg |= MX31_CSPICTRL_POL; 517 if (spi->mode & SPI_CS_HIGH) 518 reg |= MX31_CSPICTRL_SSPOL; 519 if (spi->cs_gpio < 0) 520 reg |= (spi->cs_gpio + 32) << 521 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT : 522 MX31_CSPICTRL_CS_SHIFT); 523 524 if (spi_imx->usedma) 525 reg |= MX31_CSPICTRL_SMC; 526 527 writel(reg, spi_imx->base + MXC_CSPICTRL); 528 529 reg = readl(spi_imx->base + MX31_CSPI_TESTREG); 530 if (spi->mode & SPI_LOOP) 531 reg |= MX31_TEST_LBC; 532 else 533 reg &= ~MX31_TEST_LBC; 534 writel(reg, spi_imx->base + MX31_CSPI_TESTREG); 535 536 if (spi_imx->usedma) { 537 /* configure DMA requests when RXFIFO is half full and 538 when TXFIFO is half empty */ 539 writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN, 540 spi_imx->base + MX31_CSPI_DMAREG); 541 } 542 543 return 0; 544 } 545 546 static int mx31_rx_available(struct spi_imx_data *spi_imx) 547 { 548 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; 549 } 550 551 static void mx31_reset(struct spi_imx_data *spi_imx) 552 { 553 /* drain receive buffer */ 554 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR) 555 readl(spi_imx->base + MXC_CSPIRXDATA); 556 } 557 558 #define MX21_INTREG_RR (1 << 4) 559 #define MX21_INTREG_TEEN (1 << 9) 560 #define MX21_INTREG_RREN (1 << 13) 561 562 #define MX21_CSPICTRL_POL (1 << 5) 563 #define MX21_CSPICTRL_PHA (1 << 6) 564 #define MX21_CSPICTRL_SSPOL (1 << 8) 565 #define MX21_CSPICTRL_XCH (1 << 9) 566 #define MX21_CSPICTRL_ENABLE (1 << 10) 567 #define MX21_CSPICTRL_MASTER (1 << 11) 568 #define MX21_CSPICTRL_DR_SHIFT 14 569 #define MX21_CSPICTRL_CS_SHIFT 19 570 571 static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable) 572 { 573 unsigned int val = 0; 574 575 if (enable & MXC_INT_TE) 576 val |= MX21_INTREG_TEEN; 577 if (enable & MXC_INT_RR) 578 val |= MX21_INTREG_RREN; 579 580 writel(val, spi_imx->base + MXC_CSPIINT); 581 } 582 583 static void mx21_trigger(struct spi_imx_data *spi_imx) 584 { 585 unsigned int reg; 586 587 reg = readl(spi_imx->base + MXC_CSPICTRL); 588 reg |= MX21_CSPICTRL_XCH; 589 writel(reg, spi_imx->base + MXC_CSPICTRL); 590 } 591 592 static int mx21_config(struct spi_device *spi, struct spi_imx_config *config) 593 { 594 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 595 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER; 596 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18; 597 unsigned int clk; 598 599 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max, &clk) 600 << MX21_CSPICTRL_DR_SHIFT; 601 spi_imx->spi_bus_clk = clk; 602 603 reg |= config->bpw - 1; 604 605 if (spi->mode & SPI_CPHA) 606 reg |= MX21_CSPICTRL_PHA; 607 if (spi->mode & SPI_CPOL) 608 reg |= MX21_CSPICTRL_POL; 609 if (spi->mode & SPI_CS_HIGH) 610 reg |= MX21_CSPICTRL_SSPOL; 611 if (spi->cs_gpio < 0) 612 reg |= (spi->cs_gpio + 32) << MX21_CSPICTRL_CS_SHIFT; 613 614 writel(reg, spi_imx->base + MXC_CSPICTRL); 615 616 return 0; 617 } 618 619 static int mx21_rx_available(struct spi_imx_data *spi_imx) 620 { 621 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR; 622 } 623 624 static void mx21_reset(struct spi_imx_data *spi_imx) 625 { 626 writel(1, spi_imx->base + MXC_RESET); 627 } 628 629 #define MX1_INTREG_RR (1 << 3) 630 #define MX1_INTREG_TEEN (1 << 8) 631 #define MX1_INTREG_RREN (1 << 11) 632 633 #define MX1_CSPICTRL_POL (1 << 4) 634 #define MX1_CSPICTRL_PHA (1 << 5) 635 #define MX1_CSPICTRL_XCH (1 << 8) 636 #define MX1_CSPICTRL_ENABLE (1 << 9) 637 #define MX1_CSPICTRL_MASTER (1 << 10) 638 #define MX1_CSPICTRL_DR_SHIFT 13 639 640 static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable) 641 { 642 unsigned int val = 0; 643 644 if (enable & MXC_INT_TE) 645 val |= MX1_INTREG_TEEN; 646 if (enable & MXC_INT_RR) 647 val |= MX1_INTREG_RREN; 648 649 writel(val, spi_imx->base + MXC_CSPIINT); 650 } 651 652 static void mx1_trigger(struct spi_imx_data *spi_imx) 653 { 654 unsigned int reg; 655 656 reg = readl(spi_imx->base + MXC_CSPICTRL); 657 reg |= MX1_CSPICTRL_XCH; 658 writel(reg, spi_imx->base + MXC_CSPICTRL); 659 } 660 661 static int mx1_config(struct spi_device *spi, struct spi_imx_config *config) 662 { 663 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 664 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER; 665 unsigned int clk; 666 667 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz, &clk) << 668 MX1_CSPICTRL_DR_SHIFT; 669 spi_imx->spi_bus_clk = clk; 670 671 reg |= config->bpw - 1; 672 673 if (spi->mode & SPI_CPHA) 674 reg |= MX1_CSPICTRL_PHA; 675 if (spi->mode & SPI_CPOL) 676 reg |= MX1_CSPICTRL_POL; 677 678 writel(reg, spi_imx->base + MXC_CSPICTRL); 679 680 return 0; 681 } 682 683 static int mx1_rx_available(struct spi_imx_data *spi_imx) 684 { 685 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; 686 } 687 688 static void mx1_reset(struct spi_imx_data *spi_imx) 689 { 690 writel(1, spi_imx->base + MXC_RESET); 691 } 692 693 static struct spi_imx_devtype_data imx1_cspi_devtype_data = { 694 .intctrl = mx1_intctrl, 695 .config = mx1_config, 696 .trigger = mx1_trigger, 697 .rx_available = mx1_rx_available, 698 .reset = mx1_reset, 699 .devtype = IMX1_CSPI, 700 }; 701 702 static struct spi_imx_devtype_data imx21_cspi_devtype_data = { 703 .intctrl = mx21_intctrl, 704 .config = mx21_config, 705 .trigger = mx21_trigger, 706 .rx_available = mx21_rx_available, 707 .reset = mx21_reset, 708 .devtype = IMX21_CSPI, 709 }; 710 711 static struct spi_imx_devtype_data imx27_cspi_devtype_data = { 712 /* i.mx27 cspi shares the functions with i.mx21 one */ 713 .intctrl = mx21_intctrl, 714 .config = mx21_config, 715 .trigger = mx21_trigger, 716 .rx_available = mx21_rx_available, 717 .reset = mx21_reset, 718 .devtype = IMX27_CSPI, 719 }; 720 721 static struct spi_imx_devtype_data imx31_cspi_devtype_data = { 722 .intctrl = mx31_intctrl, 723 .config = mx31_config, 724 .trigger = mx31_trigger, 725 .rx_available = mx31_rx_available, 726 .reset = mx31_reset, 727 .devtype = IMX31_CSPI, 728 }; 729 730 static struct spi_imx_devtype_data imx35_cspi_devtype_data = { 731 /* i.mx35 and later cspi shares the functions with i.mx31 one */ 732 .intctrl = mx31_intctrl, 733 .config = mx31_config, 734 .trigger = mx31_trigger, 735 .rx_available = mx31_rx_available, 736 .reset = mx31_reset, 737 .devtype = IMX35_CSPI, 738 }; 739 740 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = { 741 .intctrl = mx51_ecspi_intctrl, 742 .config = mx51_ecspi_config, 743 .trigger = mx51_ecspi_trigger, 744 .rx_available = mx51_ecspi_rx_available, 745 .reset = mx51_ecspi_reset, 746 .devtype = IMX51_ECSPI, 747 }; 748 749 static const struct platform_device_id spi_imx_devtype[] = { 750 { 751 .name = "imx1-cspi", 752 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data, 753 }, { 754 .name = "imx21-cspi", 755 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data, 756 }, { 757 .name = "imx27-cspi", 758 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data, 759 }, { 760 .name = "imx31-cspi", 761 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data, 762 }, { 763 .name = "imx35-cspi", 764 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data, 765 }, { 766 .name = "imx51-ecspi", 767 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data, 768 }, { 769 /* sentinel */ 770 } 771 }; 772 773 static const struct of_device_id spi_imx_dt_ids[] = { 774 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, }, 775 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, }, 776 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, }, 777 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, }, 778 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, }, 779 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, }, 780 { /* sentinel */ } 781 }; 782 MODULE_DEVICE_TABLE(of, spi_imx_dt_ids); 783 784 static void spi_imx_chipselect(struct spi_device *spi, int is_active) 785 { 786 int active = is_active != BITBANG_CS_INACTIVE; 787 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH); 788 789 if (!gpio_is_valid(spi->cs_gpio)) 790 return; 791 792 gpio_set_value(spi->cs_gpio, dev_is_lowactive ^ active); 793 } 794 795 static void spi_imx_push(struct spi_imx_data *spi_imx) 796 { 797 while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) { 798 if (!spi_imx->count) 799 break; 800 spi_imx->tx(spi_imx); 801 spi_imx->txfifo++; 802 } 803 804 spi_imx->devtype_data->trigger(spi_imx); 805 } 806 807 static irqreturn_t spi_imx_isr(int irq, void *dev_id) 808 { 809 struct spi_imx_data *spi_imx = dev_id; 810 811 while (spi_imx->devtype_data->rx_available(spi_imx)) { 812 spi_imx->rx(spi_imx); 813 spi_imx->txfifo--; 814 } 815 816 if (spi_imx->count) { 817 spi_imx_push(spi_imx); 818 return IRQ_HANDLED; 819 } 820 821 if (spi_imx->txfifo) { 822 /* No data left to push, but still waiting for rx data, 823 * enable receive data available interrupt. 824 */ 825 spi_imx->devtype_data->intctrl( 826 spi_imx, MXC_INT_RR); 827 return IRQ_HANDLED; 828 } 829 830 spi_imx->devtype_data->intctrl(spi_imx, 0); 831 complete(&spi_imx->xfer_done); 832 833 return IRQ_HANDLED; 834 } 835 836 static int spi_imx_dma_configure(struct spi_master *master, 837 int bytes_per_word) 838 { 839 int ret; 840 enum dma_slave_buswidth buswidth; 841 struct dma_slave_config rx = {}, tx = {}; 842 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 843 844 switch (bytes_per_word) { 845 case 4: 846 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES; 847 break; 848 case 2: 849 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES; 850 break; 851 case 1: 852 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE; 853 break; 854 default: 855 return -EINVAL; 856 } 857 858 tx.direction = DMA_MEM_TO_DEV; 859 tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA; 860 tx.dst_addr_width = buswidth; 861 tx.dst_maxburst = spi_imx->wml; 862 ret = dmaengine_slave_config(master->dma_tx, &tx); 863 if (ret) { 864 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret); 865 return ret; 866 } 867 868 rx.direction = DMA_DEV_TO_MEM; 869 rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA; 870 rx.src_addr_width = buswidth; 871 rx.src_maxburst = spi_imx->wml; 872 ret = dmaengine_slave_config(master->dma_rx, &rx); 873 if (ret) { 874 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret); 875 return ret; 876 } 877 878 spi_imx->bytes_per_word = bytes_per_word; 879 880 return 0; 881 } 882 883 static int spi_imx_setupxfer(struct spi_device *spi, 884 struct spi_transfer *t) 885 { 886 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 887 struct spi_imx_config config; 888 int ret; 889 890 config.bpw = t ? t->bits_per_word : spi->bits_per_word; 891 config.speed_hz = t ? t->speed_hz : spi->max_speed_hz; 892 893 if (!config.speed_hz) 894 config.speed_hz = spi->max_speed_hz; 895 if (!config.bpw) 896 config.bpw = spi->bits_per_word; 897 898 /* Initialize the functions for transfer */ 899 if (config.bpw <= 8) { 900 spi_imx->rx = spi_imx_buf_rx_u8; 901 spi_imx->tx = spi_imx_buf_tx_u8; 902 } else if (config.bpw <= 16) { 903 spi_imx->rx = spi_imx_buf_rx_u16; 904 spi_imx->tx = spi_imx_buf_tx_u16; 905 } else { 906 spi_imx->rx = spi_imx_buf_rx_u32; 907 spi_imx->tx = spi_imx_buf_tx_u32; 908 } 909 910 if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t)) 911 spi_imx->usedma = 1; 912 else 913 spi_imx->usedma = 0; 914 915 if (spi_imx->usedma) { 916 ret = spi_imx_dma_configure(spi->master, 917 spi_imx_bytes_per_word(config.bpw)); 918 if (ret) 919 return ret; 920 } 921 922 spi_imx->devtype_data->config(spi, &config); 923 924 return 0; 925 } 926 927 static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx) 928 { 929 struct spi_master *master = spi_imx->bitbang.master; 930 931 if (master->dma_rx) { 932 dma_release_channel(master->dma_rx); 933 master->dma_rx = NULL; 934 } 935 936 if (master->dma_tx) { 937 dma_release_channel(master->dma_tx); 938 master->dma_tx = NULL; 939 } 940 } 941 942 static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx, 943 struct spi_master *master) 944 { 945 int ret; 946 947 /* use pio mode for i.mx6dl chip TKT238285 */ 948 if (of_machine_is_compatible("fsl,imx6dl")) 949 return 0; 950 951 spi_imx->wml = spi_imx_get_fifosize(spi_imx) / 2; 952 953 /* Prepare for TX DMA: */ 954 master->dma_tx = dma_request_slave_channel_reason(dev, "tx"); 955 if (IS_ERR(master->dma_tx)) { 956 ret = PTR_ERR(master->dma_tx); 957 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret); 958 master->dma_tx = NULL; 959 goto err; 960 } 961 962 /* Prepare for RX : */ 963 master->dma_rx = dma_request_slave_channel_reason(dev, "rx"); 964 if (IS_ERR(master->dma_rx)) { 965 ret = PTR_ERR(master->dma_rx); 966 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret); 967 master->dma_rx = NULL; 968 goto err; 969 } 970 971 spi_imx_dma_configure(master, 1); 972 973 init_completion(&spi_imx->dma_rx_completion); 974 init_completion(&spi_imx->dma_tx_completion); 975 master->can_dma = spi_imx_can_dma; 976 master->max_dma_len = MAX_SDMA_BD_BYTES; 977 spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX | 978 SPI_MASTER_MUST_TX; 979 980 return 0; 981 err: 982 spi_imx_sdma_exit(spi_imx); 983 return ret; 984 } 985 986 static void spi_imx_dma_rx_callback(void *cookie) 987 { 988 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie; 989 990 complete(&spi_imx->dma_rx_completion); 991 } 992 993 static void spi_imx_dma_tx_callback(void *cookie) 994 { 995 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie; 996 997 complete(&spi_imx->dma_tx_completion); 998 } 999 1000 static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size) 1001 { 1002 unsigned long timeout = 0; 1003 1004 /* Time with actual data transfer and CS change delay related to HW */ 1005 timeout = (8 + 4) * size / spi_imx->spi_bus_clk; 1006 1007 /* Add extra second for scheduler related activities */ 1008 timeout += 1; 1009 1010 /* Double calculated timeout */ 1011 return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC); 1012 } 1013 1014 static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx, 1015 struct spi_transfer *transfer) 1016 { 1017 struct dma_async_tx_descriptor *desc_tx, *desc_rx; 1018 unsigned long transfer_timeout; 1019 unsigned long timeout; 1020 struct spi_master *master = spi_imx->bitbang.master; 1021 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg; 1022 1023 /* 1024 * The TX DMA setup starts the transfer, so make sure RX is configured 1025 * before TX. 1026 */ 1027 desc_rx = dmaengine_prep_slave_sg(master->dma_rx, 1028 rx->sgl, rx->nents, DMA_DEV_TO_MEM, 1029 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1030 if (!desc_rx) 1031 return -EINVAL; 1032 1033 desc_rx->callback = spi_imx_dma_rx_callback; 1034 desc_rx->callback_param = (void *)spi_imx; 1035 dmaengine_submit(desc_rx); 1036 reinit_completion(&spi_imx->dma_rx_completion); 1037 dma_async_issue_pending(master->dma_rx); 1038 1039 desc_tx = dmaengine_prep_slave_sg(master->dma_tx, 1040 tx->sgl, tx->nents, DMA_MEM_TO_DEV, 1041 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1042 if (!desc_tx) { 1043 dmaengine_terminate_all(master->dma_tx); 1044 return -EINVAL; 1045 } 1046 1047 desc_tx->callback = spi_imx_dma_tx_callback; 1048 desc_tx->callback_param = (void *)spi_imx; 1049 dmaengine_submit(desc_tx); 1050 reinit_completion(&spi_imx->dma_tx_completion); 1051 dma_async_issue_pending(master->dma_tx); 1052 1053 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); 1054 1055 /* Wait SDMA to finish the data transfer.*/ 1056 timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion, 1057 transfer_timeout); 1058 if (!timeout) { 1059 dev_err(spi_imx->dev, "I/O Error in DMA TX\n"); 1060 dmaengine_terminate_all(master->dma_tx); 1061 dmaengine_terminate_all(master->dma_rx); 1062 return -ETIMEDOUT; 1063 } 1064 1065 timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion, 1066 transfer_timeout); 1067 if (!timeout) { 1068 dev_err(&master->dev, "I/O Error in DMA RX\n"); 1069 spi_imx->devtype_data->reset(spi_imx); 1070 dmaengine_terminate_all(master->dma_rx); 1071 return -ETIMEDOUT; 1072 } 1073 1074 return transfer->len; 1075 } 1076 1077 static int spi_imx_pio_transfer(struct spi_device *spi, 1078 struct spi_transfer *transfer) 1079 { 1080 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 1081 unsigned long transfer_timeout; 1082 unsigned long timeout; 1083 1084 spi_imx->tx_buf = transfer->tx_buf; 1085 spi_imx->rx_buf = transfer->rx_buf; 1086 spi_imx->count = transfer->len; 1087 spi_imx->txfifo = 0; 1088 1089 reinit_completion(&spi_imx->xfer_done); 1090 1091 spi_imx_push(spi_imx); 1092 1093 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE); 1094 1095 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); 1096 1097 timeout = wait_for_completion_timeout(&spi_imx->xfer_done, 1098 transfer_timeout); 1099 if (!timeout) { 1100 dev_err(&spi->dev, "I/O Error in PIO\n"); 1101 spi_imx->devtype_data->reset(spi_imx); 1102 return -ETIMEDOUT; 1103 } 1104 1105 return transfer->len; 1106 } 1107 1108 static int spi_imx_transfer(struct spi_device *spi, 1109 struct spi_transfer *transfer) 1110 { 1111 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 1112 1113 if (spi_imx->usedma) 1114 return spi_imx_dma_transfer(spi_imx, transfer); 1115 else 1116 return spi_imx_pio_transfer(spi, transfer); 1117 } 1118 1119 static int spi_imx_setup(struct spi_device *spi) 1120 { 1121 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__, 1122 spi->mode, spi->bits_per_word, spi->max_speed_hz); 1123 1124 if (gpio_is_valid(spi->cs_gpio)) 1125 gpio_direction_output(spi->cs_gpio, 1126 spi->mode & SPI_CS_HIGH ? 0 : 1); 1127 1128 spi_imx_chipselect(spi, BITBANG_CS_INACTIVE); 1129 1130 return 0; 1131 } 1132 1133 static void spi_imx_cleanup(struct spi_device *spi) 1134 { 1135 } 1136 1137 static int 1138 spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg) 1139 { 1140 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 1141 int ret; 1142 1143 ret = clk_enable(spi_imx->clk_per); 1144 if (ret) 1145 return ret; 1146 1147 ret = clk_enable(spi_imx->clk_ipg); 1148 if (ret) { 1149 clk_disable(spi_imx->clk_per); 1150 return ret; 1151 } 1152 1153 return 0; 1154 } 1155 1156 static int 1157 spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg) 1158 { 1159 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 1160 1161 clk_disable(spi_imx->clk_ipg); 1162 clk_disable(spi_imx->clk_per); 1163 return 0; 1164 } 1165 1166 static int spi_imx_probe(struct platform_device *pdev) 1167 { 1168 struct device_node *np = pdev->dev.of_node; 1169 const struct of_device_id *of_id = 1170 of_match_device(spi_imx_dt_ids, &pdev->dev); 1171 struct spi_imx_master *mxc_platform_info = 1172 dev_get_platdata(&pdev->dev); 1173 struct spi_master *master; 1174 struct spi_imx_data *spi_imx; 1175 struct resource *res; 1176 int i, ret, irq; 1177 1178 if (!np && !mxc_platform_info) { 1179 dev_err(&pdev->dev, "can't get the platform data\n"); 1180 return -EINVAL; 1181 } 1182 1183 master = spi_alloc_master(&pdev->dev, sizeof(struct spi_imx_data)); 1184 if (!master) 1185 return -ENOMEM; 1186 1187 platform_set_drvdata(pdev, master); 1188 1189 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); 1190 master->bus_num = np ? -1 : pdev->id; 1191 1192 spi_imx = spi_master_get_devdata(master); 1193 spi_imx->bitbang.master = master; 1194 spi_imx->dev = &pdev->dev; 1195 1196 spi_imx->devtype_data = of_id ? of_id->data : 1197 (struct spi_imx_devtype_data *)pdev->id_entry->driver_data; 1198 1199 if (mxc_platform_info) { 1200 master->num_chipselect = mxc_platform_info->num_chipselect; 1201 master->cs_gpios = devm_kzalloc(&master->dev, 1202 sizeof(int) * master->num_chipselect, GFP_KERNEL); 1203 if (!master->cs_gpios) 1204 return -ENOMEM; 1205 1206 for (i = 0; i < master->num_chipselect; i++) 1207 master->cs_gpios[i] = mxc_platform_info->chipselect[i]; 1208 } 1209 1210 spi_imx->bitbang.chipselect = spi_imx_chipselect; 1211 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer; 1212 spi_imx->bitbang.txrx_bufs = spi_imx_transfer; 1213 spi_imx->bitbang.master->setup = spi_imx_setup; 1214 spi_imx->bitbang.master->cleanup = spi_imx_cleanup; 1215 spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message; 1216 spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message; 1217 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1218 if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx)) 1219 spi_imx->bitbang.master->mode_bits |= SPI_LOOP; 1220 1221 init_completion(&spi_imx->xfer_done); 1222 1223 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1224 spi_imx->base = devm_ioremap_resource(&pdev->dev, res); 1225 if (IS_ERR(spi_imx->base)) { 1226 ret = PTR_ERR(spi_imx->base); 1227 goto out_master_put; 1228 } 1229 spi_imx->base_phys = res->start; 1230 1231 irq = platform_get_irq(pdev, 0); 1232 if (irq < 0) { 1233 ret = irq; 1234 goto out_master_put; 1235 } 1236 1237 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0, 1238 dev_name(&pdev->dev), spi_imx); 1239 if (ret) { 1240 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret); 1241 goto out_master_put; 1242 } 1243 1244 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1245 if (IS_ERR(spi_imx->clk_ipg)) { 1246 ret = PTR_ERR(spi_imx->clk_ipg); 1247 goto out_master_put; 1248 } 1249 1250 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per"); 1251 if (IS_ERR(spi_imx->clk_per)) { 1252 ret = PTR_ERR(spi_imx->clk_per); 1253 goto out_master_put; 1254 } 1255 1256 ret = clk_prepare_enable(spi_imx->clk_per); 1257 if (ret) 1258 goto out_master_put; 1259 1260 ret = clk_prepare_enable(spi_imx->clk_ipg); 1261 if (ret) 1262 goto out_put_per; 1263 1264 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per); 1265 /* 1266 * Only validated on i.mx35 and i.mx6 now, can remove the constraint 1267 * if validated on other chips. 1268 */ 1269 if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx)) { 1270 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master); 1271 if (ret == -EPROBE_DEFER) 1272 goto out_clk_put; 1273 1274 if (ret < 0) 1275 dev_err(&pdev->dev, "dma setup error %d, use pio\n", 1276 ret); 1277 } 1278 1279 spi_imx->devtype_data->reset(spi_imx); 1280 1281 spi_imx->devtype_data->intctrl(spi_imx, 0); 1282 1283 master->dev.of_node = pdev->dev.of_node; 1284 ret = spi_bitbang_start(&spi_imx->bitbang); 1285 if (ret) { 1286 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret); 1287 goto out_clk_put; 1288 } 1289 1290 if (!master->cs_gpios) { 1291 dev_err(&pdev->dev, "No CS GPIOs available\n"); 1292 ret = -EINVAL; 1293 goto out_clk_put; 1294 } 1295 1296 for (i = 0; i < master->num_chipselect; i++) { 1297 if (!gpio_is_valid(master->cs_gpios[i])) 1298 continue; 1299 1300 ret = devm_gpio_request(&pdev->dev, master->cs_gpios[i], 1301 DRIVER_NAME); 1302 if (ret) { 1303 dev_err(&pdev->dev, "Can't get CS GPIO %i\n", 1304 master->cs_gpios[i]); 1305 goto out_clk_put; 1306 } 1307 } 1308 1309 dev_info(&pdev->dev, "probed\n"); 1310 1311 clk_disable(spi_imx->clk_ipg); 1312 clk_disable(spi_imx->clk_per); 1313 return ret; 1314 1315 out_clk_put: 1316 clk_disable_unprepare(spi_imx->clk_ipg); 1317 out_put_per: 1318 clk_disable_unprepare(spi_imx->clk_per); 1319 out_master_put: 1320 spi_master_put(master); 1321 1322 return ret; 1323 } 1324 1325 static int spi_imx_remove(struct platform_device *pdev) 1326 { 1327 struct spi_master *master = platform_get_drvdata(pdev); 1328 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 1329 1330 spi_bitbang_stop(&spi_imx->bitbang); 1331 1332 writel(0, spi_imx->base + MXC_CSPICTRL); 1333 clk_unprepare(spi_imx->clk_ipg); 1334 clk_unprepare(spi_imx->clk_per); 1335 spi_imx_sdma_exit(spi_imx); 1336 spi_master_put(master); 1337 1338 return 0; 1339 } 1340 1341 static struct platform_driver spi_imx_driver = { 1342 .driver = { 1343 .name = DRIVER_NAME, 1344 .of_match_table = spi_imx_dt_ids, 1345 }, 1346 .id_table = spi_imx_devtype, 1347 .probe = spi_imx_probe, 1348 .remove = spi_imx_remove, 1349 }; 1350 module_platform_driver(spi_imx_driver); 1351 1352 MODULE_DESCRIPTION("SPI Master Controller driver"); 1353 MODULE_AUTHOR("Sascha Hauer, Pengutronix"); 1354 MODULE_LICENSE("GPL"); 1355 MODULE_ALIAS("platform:" DRIVER_NAME); 1356