1 /* 2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 3 * Copyright (C) 2008 Juergen Beisert 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 2 8 * of the License, or (at your option) any later version. 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the 16 * Free Software Foundation 17 * 51 Franklin Street, Fifth Floor 18 * Boston, MA 02110-1301, USA. 19 */ 20 21 #include <linux/clk.h> 22 #include <linux/completion.h> 23 #include <linux/delay.h> 24 #include <linux/dmaengine.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/err.h> 27 #include <linux/gpio.h> 28 #include <linux/interrupt.h> 29 #include <linux/io.h> 30 #include <linux/irq.h> 31 #include <linux/kernel.h> 32 #include <linux/module.h> 33 #include <linux/platform_device.h> 34 #include <linux/slab.h> 35 #include <linux/spi/spi.h> 36 #include <linux/spi/spi_bitbang.h> 37 #include <linux/types.h> 38 #include <linux/of.h> 39 #include <linux/of_device.h> 40 #include <linux/of_gpio.h> 41 42 #include <linux/platform_data/dma-imx.h> 43 #include <linux/platform_data/spi-imx.h> 44 45 #define DRIVER_NAME "spi_imx" 46 47 #define MXC_CSPIRXDATA 0x00 48 #define MXC_CSPITXDATA 0x04 49 #define MXC_CSPICTRL 0x08 50 #define MXC_CSPIINT 0x0c 51 #define MXC_RESET 0x1c 52 53 /* generic defines to abstract from the different register layouts */ 54 #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */ 55 #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */ 56 57 /* The maximum bytes that a sdma BD can transfer.*/ 58 #define MAX_SDMA_BD_BYTES (1 << 15) 59 struct spi_imx_config { 60 unsigned int speed_hz; 61 unsigned int bpw; 62 unsigned int mode; 63 u8 cs; 64 }; 65 66 enum spi_imx_devtype { 67 IMX1_CSPI, 68 IMX21_CSPI, 69 IMX27_CSPI, 70 IMX31_CSPI, 71 IMX35_CSPI, /* CSPI on all i.mx except above */ 72 IMX51_ECSPI, /* ECSPI on i.mx51 and later */ 73 }; 74 75 struct spi_imx_data; 76 77 struct spi_imx_devtype_data { 78 void (*intctrl)(struct spi_imx_data *, int); 79 int (*config)(struct spi_imx_data *, struct spi_imx_config *); 80 void (*trigger)(struct spi_imx_data *); 81 int (*rx_available)(struct spi_imx_data *); 82 void (*reset)(struct spi_imx_data *); 83 enum spi_imx_devtype devtype; 84 }; 85 86 struct spi_imx_data { 87 struct spi_bitbang bitbang; 88 struct device *dev; 89 90 struct completion xfer_done; 91 void __iomem *base; 92 unsigned long base_phys; 93 94 struct clk *clk_per; 95 struct clk *clk_ipg; 96 unsigned long spi_clk; 97 unsigned int spi_bus_clk; 98 99 unsigned int bytes_per_word; 100 101 unsigned int count; 102 void (*tx)(struct spi_imx_data *); 103 void (*rx)(struct spi_imx_data *); 104 void *rx_buf; 105 const void *tx_buf; 106 unsigned int txfifo; /* number of words pushed in tx FIFO */ 107 108 /* DMA */ 109 bool usedma; 110 u32 wml; 111 struct completion dma_rx_completion; 112 struct completion dma_tx_completion; 113 114 const struct spi_imx_devtype_data *devtype_data; 115 int chipselect[0]; 116 }; 117 118 static inline int is_imx27_cspi(struct spi_imx_data *d) 119 { 120 return d->devtype_data->devtype == IMX27_CSPI; 121 } 122 123 static inline int is_imx35_cspi(struct spi_imx_data *d) 124 { 125 return d->devtype_data->devtype == IMX35_CSPI; 126 } 127 128 static inline int is_imx51_ecspi(struct spi_imx_data *d) 129 { 130 return d->devtype_data->devtype == IMX51_ECSPI; 131 } 132 133 static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d) 134 { 135 return is_imx51_ecspi(d) ? 64 : 8; 136 } 137 138 #define MXC_SPI_BUF_RX(type) \ 139 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \ 140 { \ 141 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \ 142 \ 143 if (spi_imx->rx_buf) { \ 144 *(type *)spi_imx->rx_buf = val; \ 145 spi_imx->rx_buf += sizeof(type); \ 146 } \ 147 } 148 149 #define MXC_SPI_BUF_TX(type) \ 150 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \ 151 { \ 152 type val = 0; \ 153 \ 154 if (spi_imx->tx_buf) { \ 155 val = *(type *)spi_imx->tx_buf; \ 156 spi_imx->tx_buf += sizeof(type); \ 157 } \ 158 \ 159 spi_imx->count -= sizeof(type); \ 160 \ 161 writel(val, spi_imx->base + MXC_CSPITXDATA); \ 162 } 163 164 MXC_SPI_BUF_RX(u8) 165 MXC_SPI_BUF_TX(u8) 166 MXC_SPI_BUF_RX(u16) 167 MXC_SPI_BUF_TX(u16) 168 MXC_SPI_BUF_RX(u32) 169 MXC_SPI_BUF_TX(u32) 170 171 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set 172 * (which is currently not the case in this driver) 173 */ 174 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192, 175 256, 384, 512, 768, 1024}; 176 177 /* MX21, MX27 */ 178 static unsigned int spi_imx_clkdiv_1(unsigned int fin, 179 unsigned int fspi, unsigned int max) 180 { 181 int i; 182 183 for (i = 2; i < max; i++) 184 if (fspi * mxc_clkdivs[i] >= fin) 185 return i; 186 187 return max; 188 } 189 190 /* MX1, MX31, MX35, MX51 CSPI */ 191 static unsigned int spi_imx_clkdiv_2(unsigned int fin, 192 unsigned int fspi) 193 { 194 int i, div = 4; 195 196 for (i = 0; i < 7; i++) { 197 if (fspi * div >= fin) 198 return i; 199 div <<= 1; 200 } 201 202 return 7; 203 } 204 205 static int spi_imx_bytes_per_word(const int bpw) 206 { 207 return DIV_ROUND_UP(bpw, BITS_PER_BYTE); 208 } 209 210 static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi, 211 struct spi_transfer *transfer) 212 { 213 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 214 unsigned int bpw = transfer->bits_per_word; 215 216 if (!master->dma_rx) 217 return false; 218 219 if (!bpw) 220 bpw = spi->bits_per_word; 221 222 bpw = spi_imx_bytes_per_word(bpw); 223 224 if (bpw != 1 && bpw != 2 && bpw != 4) 225 return false; 226 227 if (transfer->len < spi_imx->wml * bpw) 228 return false; 229 230 if (transfer->len % (spi_imx->wml * bpw)) 231 return false; 232 233 return true; 234 } 235 236 #define MX51_ECSPI_CTRL 0x08 237 #define MX51_ECSPI_CTRL_ENABLE (1 << 0) 238 #define MX51_ECSPI_CTRL_XCH (1 << 2) 239 #define MX51_ECSPI_CTRL_SMC (1 << 3) 240 #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4) 241 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8 242 #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12 243 #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18) 244 #define MX51_ECSPI_CTRL_BL_OFFSET 20 245 246 #define MX51_ECSPI_CONFIG 0x0c 247 #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0)) 248 #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4)) 249 #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8)) 250 #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12)) 251 #define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20)) 252 253 #define MX51_ECSPI_INT 0x10 254 #define MX51_ECSPI_INT_TEEN (1 << 0) 255 #define MX51_ECSPI_INT_RREN (1 << 3) 256 257 #define MX51_ECSPI_DMA 0x14 258 #define MX51_ECSPI_DMA_TX_WML(wml) ((wml) & 0x3f) 259 #define MX51_ECSPI_DMA_RX_WML(wml) (((wml) & 0x3f) << 16) 260 #define MX51_ECSPI_DMA_RXT_WML(wml) (((wml) & 0x3f) << 24) 261 262 #define MX51_ECSPI_DMA_TEDEN (1 << 7) 263 #define MX51_ECSPI_DMA_RXDEN (1 << 23) 264 #define MX51_ECSPI_DMA_RXTDEN (1 << 31) 265 266 #define MX51_ECSPI_STAT 0x18 267 #define MX51_ECSPI_STAT_RR (1 << 3) 268 269 #define MX51_ECSPI_TESTREG 0x20 270 #define MX51_ECSPI_TESTREG_LBC BIT(31) 271 272 /* MX51 eCSPI */ 273 static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx, 274 unsigned int fspi, unsigned int *fres) 275 { 276 /* 277 * there are two 4-bit dividers, the pre-divider divides by 278 * $pre, the post-divider by 2^$post 279 */ 280 unsigned int pre, post; 281 unsigned int fin = spi_imx->spi_clk; 282 283 if (unlikely(fspi > fin)) 284 return 0; 285 286 post = fls(fin) - fls(fspi); 287 if (fin > fspi << post) 288 post++; 289 290 /* now we have: (fin <= fspi << post) with post being minimal */ 291 292 post = max(4U, post) - 4; 293 if (unlikely(post > 0xf)) { 294 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n", 295 fspi, fin); 296 return 0xff; 297 } 298 299 pre = DIV_ROUND_UP(fin, fspi << post) - 1; 300 301 dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n", 302 __func__, fin, fspi, post, pre); 303 304 /* Resulting frequency for the SCLK line. */ 305 *fres = (fin / (pre + 1)) >> post; 306 307 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) | 308 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET); 309 } 310 311 static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable) 312 { 313 unsigned val = 0; 314 315 if (enable & MXC_INT_TE) 316 val |= MX51_ECSPI_INT_TEEN; 317 318 if (enable & MXC_INT_RR) 319 val |= MX51_ECSPI_INT_RREN; 320 321 writel(val, spi_imx->base + MX51_ECSPI_INT); 322 } 323 324 static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx) 325 { 326 u32 reg; 327 328 reg = readl(spi_imx->base + MX51_ECSPI_CTRL); 329 reg |= MX51_ECSPI_CTRL_XCH; 330 writel(reg, spi_imx->base + MX51_ECSPI_CTRL); 331 } 332 333 static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx, 334 struct spi_imx_config *config) 335 { 336 u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0; 337 u32 clk = config->speed_hz, delay, reg; 338 339 /* 340 * The hardware seems to have a race condition when changing modes. The 341 * current assumption is that the selection of the channel arrives 342 * earlier in the hardware than the mode bits when they are written at 343 * the same time. 344 * So set master mode for all channels as we do not support slave mode. 345 */ 346 ctrl |= MX51_ECSPI_CTRL_MODE_MASK; 347 348 /* set clock speed */ 349 ctrl |= mx51_ecspi_clkdiv(spi_imx, config->speed_hz, &clk); 350 spi_imx->spi_bus_clk = clk; 351 352 /* set chip select to use */ 353 ctrl |= MX51_ECSPI_CTRL_CS(config->cs); 354 355 ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET; 356 357 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(config->cs); 358 359 if (config->mode & SPI_CPHA) 360 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs); 361 362 if (config->mode & SPI_CPOL) { 363 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs); 364 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(config->cs); 365 } 366 if (config->mode & SPI_CS_HIGH) 367 cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs); 368 369 if (spi_imx->usedma) 370 ctrl |= MX51_ECSPI_CTRL_SMC; 371 372 /* CTRL register always go first to bring out controller from reset */ 373 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); 374 375 reg = readl(spi_imx->base + MX51_ECSPI_TESTREG); 376 if (config->mode & SPI_LOOP) 377 reg |= MX51_ECSPI_TESTREG_LBC; 378 else 379 reg &= ~MX51_ECSPI_TESTREG_LBC; 380 writel(reg, spi_imx->base + MX51_ECSPI_TESTREG); 381 382 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); 383 384 /* 385 * Wait until the changes in the configuration register CONFIGREG 386 * propagate into the hardware. It takes exactly one tick of the 387 * SCLK clock, but we will wait two SCLK clock just to be sure. The 388 * effect of the delay it takes for the hardware to apply changes 389 * is noticable if the SCLK clock run very slow. In such a case, if 390 * the polarity of SCLK should be inverted, the GPIO ChipSelect might 391 * be asserted before the SCLK polarity changes, which would disrupt 392 * the SPI communication as the device on the other end would consider 393 * the change of SCLK polarity as a clock tick already. 394 */ 395 delay = (2 * 1000000) / clk; 396 if (likely(delay < 10)) /* SCLK is faster than 100 kHz */ 397 udelay(delay); 398 else /* SCLK is _very_ slow */ 399 usleep_range(delay, delay + 10); 400 401 /* 402 * Configure the DMA register: setup the watermark 403 * and enable DMA request. 404 */ 405 406 writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml) | 407 MX51_ECSPI_DMA_TX_WML(spi_imx->wml) | 408 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) | 409 MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN | 410 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA); 411 412 return 0; 413 } 414 415 static int __maybe_unused mx51_ecspi_rx_available(struct spi_imx_data *spi_imx) 416 { 417 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR; 418 } 419 420 static void __maybe_unused mx51_ecspi_reset(struct spi_imx_data *spi_imx) 421 { 422 /* drain receive buffer */ 423 while (mx51_ecspi_rx_available(spi_imx)) 424 readl(spi_imx->base + MXC_CSPIRXDATA); 425 } 426 427 #define MX31_INTREG_TEEN (1 << 0) 428 #define MX31_INTREG_RREN (1 << 3) 429 430 #define MX31_CSPICTRL_ENABLE (1 << 0) 431 #define MX31_CSPICTRL_MASTER (1 << 1) 432 #define MX31_CSPICTRL_XCH (1 << 2) 433 #define MX31_CSPICTRL_POL (1 << 4) 434 #define MX31_CSPICTRL_PHA (1 << 5) 435 #define MX31_CSPICTRL_SSCTL (1 << 6) 436 #define MX31_CSPICTRL_SSPOL (1 << 7) 437 #define MX31_CSPICTRL_BC_SHIFT 8 438 #define MX35_CSPICTRL_BL_SHIFT 20 439 #define MX31_CSPICTRL_CS_SHIFT 24 440 #define MX35_CSPICTRL_CS_SHIFT 12 441 #define MX31_CSPICTRL_DR_SHIFT 16 442 443 #define MX31_CSPISTATUS 0x14 444 #define MX31_STATUS_RR (1 << 3) 445 446 /* These functions also work for the i.MX35, but be aware that 447 * the i.MX35 has a slightly different register layout for bits 448 * we do not use here. 449 */ 450 static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable) 451 { 452 unsigned int val = 0; 453 454 if (enable & MXC_INT_TE) 455 val |= MX31_INTREG_TEEN; 456 if (enable & MXC_INT_RR) 457 val |= MX31_INTREG_RREN; 458 459 writel(val, spi_imx->base + MXC_CSPIINT); 460 } 461 462 static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx) 463 { 464 unsigned int reg; 465 466 reg = readl(spi_imx->base + MXC_CSPICTRL); 467 reg |= MX31_CSPICTRL_XCH; 468 writel(reg, spi_imx->base + MXC_CSPICTRL); 469 } 470 471 static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx, 472 struct spi_imx_config *config) 473 { 474 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER; 475 int cs = spi_imx->chipselect[config->cs]; 476 477 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) << 478 MX31_CSPICTRL_DR_SHIFT; 479 480 if (is_imx35_cspi(spi_imx)) { 481 reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT; 482 reg |= MX31_CSPICTRL_SSCTL; 483 } else { 484 reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT; 485 } 486 487 if (config->mode & SPI_CPHA) 488 reg |= MX31_CSPICTRL_PHA; 489 if (config->mode & SPI_CPOL) 490 reg |= MX31_CSPICTRL_POL; 491 if (config->mode & SPI_CS_HIGH) 492 reg |= MX31_CSPICTRL_SSPOL; 493 if (cs < 0) 494 reg |= (cs + 32) << 495 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT : 496 MX31_CSPICTRL_CS_SHIFT); 497 498 writel(reg, spi_imx->base + MXC_CSPICTRL); 499 500 return 0; 501 } 502 503 static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx) 504 { 505 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; 506 } 507 508 static void __maybe_unused mx31_reset(struct spi_imx_data *spi_imx) 509 { 510 /* drain receive buffer */ 511 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR) 512 readl(spi_imx->base + MXC_CSPIRXDATA); 513 } 514 515 #define MX21_INTREG_RR (1 << 4) 516 #define MX21_INTREG_TEEN (1 << 9) 517 #define MX21_INTREG_RREN (1 << 13) 518 519 #define MX21_CSPICTRL_POL (1 << 5) 520 #define MX21_CSPICTRL_PHA (1 << 6) 521 #define MX21_CSPICTRL_SSPOL (1 << 8) 522 #define MX21_CSPICTRL_XCH (1 << 9) 523 #define MX21_CSPICTRL_ENABLE (1 << 10) 524 #define MX21_CSPICTRL_MASTER (1 << 11) 525 #define MX21_CSPICTRL_DR_SHIFT 14 526 #define MX21_CSPICTRL_CS_SHIFT 19 527 528 static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable) 529 { 530 unsigned int val = 0; 531 532 if (enable & MXC_INT_TE) 533 val |= MX21_INTREG_TEEN; 534 if (enable & MXC_INT_RR) 535 val |= MX21_INTREG_RREN; 536 537 writel(val, spi_imx->base + MXC_CSPIINT); 538 } 539 540 static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx) 541 { 542 unsigned int reg; 543 544 reg = readl(spi_imx->base + MXC_CSPICTRL); 545 reg |= MX21_CSPICTRL_XCH; 546 writel(reg, spi_imx->base + MXC_CSPICTRL); 547 } 548 549 static int __maybe_unused mx21_config(struct spi_imx_data *spi_imx, 550 struct spi_imx_config *config) 551 { 552 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER; 553 int cs = spi_imx->chipselect[config->cs]; 554 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18; 555 556 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max) << 557 MX21_CSPICTRL_DR_SHIFT; 558 reg |= config->bpw - 1; 559 560 if (config->mode & SPI_CPHA) 561 reg |= MX21_CSPICTRL_PHA; 562 if (config->mode & SPI_CPOL) 563 reg |= MX21_CSPICTRL_POL; 564 if (config->mode & SPI_CS_HIGH) 565 reg |= MX21_CSPICTRL_SSPOL; 566 if (cs < 0) 567 reg |= (cs + 32) << MX21_CSPICTRL_CS_SHIFT; 568 569 writel(reg, spi_imx->base + MXC_CSPICTRL); 570 571 return 0; 572 } 573 574 static int __maybe_unused mx21_rx_available(struct spi_imx_data *spi_imx) 575 { 576 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR; 577 } 578 579 static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx) 580 { 581 writel(1, spi_imx->base + MXC_RESET); 582 } 583 584 #define MX1_INTREG_RR (1 << 3) 585 #define MX1_INTREG_TEEN (1 << 8) 586 #define MX1_INTREG_RREN (1 << 11) 587 588 #define MX1_CSPICTRL_POL (1 << 4) 589 #define MX1_CSPICTRL_PHA (1 << 5) 590 #define MX1_CSPICTRL_XCH (1 << 8) 591 #define MX1_CSPICTRL_ENABLE (1 << 9) 592 #define MX1_CSPICTRL_MASTER (1 << 10) 593 #define MX1_CSPICTRL_DR_SHIFT 13 594 595 static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable) 596 { 597 unsigned int val = 0; 598 599 if (enable & MXC_INT_TE) 600 val |= MX1_INTREG_TEEN; 601 if (enable & MXC_INT_RR) 602 val |= MX1_INTREG_RREN; 603 604 writel(val, spi_imx->base + MXC_CSPIINT); 605 } 606 607 static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx) 608 { 609 unsigned int reg; 610 611 reg = readl(spi_imx->base + MXC_CSPICTRL); 612 reg |= MX1_CSPICTRL_XCH; 613 writel(reg, spi_imx->base + MXC_CSPICTRL); 614 } 615 616 static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx, 617 struct spi_imx_config *config) 618 { 619 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER; 620 621 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) << 622 MX1_CSPICTRL_DR_SHIFT; 623 reg |= config->bpw - 1; 624 625 if (config->mode & SPI_CPHA) 626 reg |= MX1_CSPICTRL_PHA; 627 if (config->mode & SPI_CPOL) 628 reg |= MX1_CSPICTRL_POL; 629 630 writel(reg, spi_imx->base + MXC_CSPICTRL); 631 632 return 0; 633 } 634 635 static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx) 636 { 637 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; 638 } 639 640 static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx) 641 { 642 writel(1, spi_imx->base + MXC_RESET); 643 } 644 645 static struct spi_imx_devtype_data imx1_cspi_devtype_data = { 646 .intctrl = mx1_intctrl, 647 .config = mx1_config, 648 .trigger = mx1_trigger, 649 .rx_available = mx1_rx_available, 650 .reset = mx1_reset, 651 .devtype = IMX1_CSPI, 652 }; 653 654 static struct spi_imx_devtype_data imx21_cspi_devtype_data = { 655 .intctrl = mx21_intctrl, 656 .config = mx21_config, 657 .trigger = mx21_trigger, 658 .rx_available = mx21_rx_available, 659 .reset = mx21_reset, 660 .devtype = IMX21_CSPI, 661 }; 662 663 static struct spi_imx_devtype_data imx27_cspi_devtype_data = { 664 /* i.mx27 cspi shares the functions with i.mx21 one */ 665 .intctrl = mx21_intctrl, 666 .config = mx21_config, 667 .trigger = mx21_trigger, 668 .rx_available = mx21_rx_available, 669 .reset = mx21_reset, 670 .devtype = IMX27_CSPI, 671 }; 672 673 static struct spi_imx_devtype_data imx31_cspi_devtype_data = { 674 .intctrl = mx31_intctrl, 675 .config = mx31_config, 676 .trigger = mx31_trigger, 677 .rx_available = mx31_rx_available, 678 .reset = mx31_reset, 679 .devtype = IMX31_CSPI, 680 }; 681 682 static struct spi_imx_devtype_data imx35_cspi_devtype_data = { 683 /* i.mx35 and later cspi shares the functions with i.mx31 one */ 684 .intctrl = mx31_intctrl, 685 .config = mx31_config, 686 .trigger = mx31_trigger, 687 .rx_available = mx31_rx_available, 688 .reset = mx31_reset, 689 .devtype = IMX35_CSPI, 690 }; 691 692 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = { 693 .intctrl = mx51_ecspi_intctrl, 694 .config = mx51_ecspi_config, 695 .trigger = mx51_ecspi_trigger, 696 .rx_available = mx51_ecspi_rx_available, 697 .reset = mx51_ecspi_reset, 698 .devtype = IMX51_ECSPI, 699 }; 700 701 static const struct platform_device_id spi_imx_devtype[] = { 702 { 703 .name = "imx1-cspi", 704 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data, 705 }, { 706 .name = "imx21-cspi", 707 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data, 708 }, { 709 .name = "imx27-cspi", 710 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data, 711 }, { 712 .name = "imx31-cspi", 713 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data, 714 }, { 715 .name = "imx35-cspi", 716 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data, 717 }, { 718 .name = "imx51-ecspi", 719 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data, 720 }, { 721 /* sentinel */ 722 } 723 }; 724 725 static const struct of_device_id spi_imx_dt_ids[] = { 726 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, }, 727 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, }, 728 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, }, 729 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, }, 730 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, }, 731 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, }, 732 { /* sentinel */ } 733 }; 734 MODULE_DEVICE_TABLE(of, spi_imx_dt_ids); 735 736 static void spi_imx_chipselect(struct spi_device *spi, int is_active) 737 { 738 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 739 int gpio = spi_imx->chipselect[spi->chip_select]; 740 int active = is_active != BITBANG_CS_INACTIVE; 741 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH); 742 743 if (!gpio_is_valid(gpio)) 744 return; 745 746 gpio_set_value(gpio, dev_is_lowactive ^ active); 747 } 748 749 static void spi_imx_push(struct spi_imx_data *spi_imx) 750 { 751 while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) { 752 if (!spi_imx->count) 753 break; 754 spi_imx->tx(spi_imx); 755 spi_imx->txfifo++; 756 } 757 758 spi_imx->devtype_data->trigger(spi_imx); 759 } 760 761 static irqreturn_t spi_imx_isr(int irq, void *dev_id) 762 { 763 struct spi_imx_data *spi_imx = dev_id; 764 765 while (spi_imx->devtype_data->rx_available(spi_imx)) { 766 spi_imx->rx(spi_imx); 767 spi_imx->txfifo--; 768 } 769 770 if (spi_imx->count) { 771 spi_imx_push(spi_imx); 772 return IRQ_HANDLED; 773 } 774 775 if (spi_imx->txfifo) { 776 /* No data left to push, but still waiting for rx data, 777 * enable receive data available interrupt. 778 */ 779 spi_imx->devtype_data->intctrl( 780 spi_imx, MXC_INT_RR); 781 return IRQ_HANDLED; 782 } 783 784 spi_imx->devtype_data->intctrl(spi_imx, 0); 785 complete(&spi_imx->xfer_done); 786 787 return IRQ_HANDLED; 788 } 789 790 static int spi_imx_dma_configure(struct spi_master *master, 791 int bytes_per_word) 792 { 793 int ret; 794 enum dma_slave_buswidth buswidth; 795 struct dma_slave_config rx = {}, tx = {}; 796 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 797 798 if (bytes_per_word == spi_imx->bytes_per_word) 799 /* Same as last time */ 800 return 0; 801 802 switch (bytes_per_word) { 803 case 4: 804 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES; 805 break; 806 case 2: 807 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES; 808 break; 809 case 1: 810 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE; 811 break; 812 default: 813 return -EINVAL; 814 } 815 816 tx.direction = DMA_MEM_TO_DEV; 817 tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA; 818 tx.dst_addr_width = buswidth; 819 tx.dst_maxburst = spi_imx->wml; 820 ret = dmaengine_slave_config(master->dma_tx, &tx); 821 if (ret) { 822 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret); 823 return ret; 824 } 825 826 rx.direction = DMA_DEV_TO_MEM; 827 rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA; 828 rx.src_addr_width = buswidth; 829 rx.src_maxburst = spi_imx->wml; 830 ret = dmaengine_slave_config(master->dma_rx, &rx); 831 if (ret) { 832 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret); 833 return ret; 834 } 835 836 spi_imx->bytes_per_word = bytes_per_word; 837 838 return 0; 839 } 840 841 static int spi_imx_setupxfer(struct spi_device *spi, 842 struct spi_transfer *t) 843 { 844 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 845 struct spi_imx_config config; 846 int ret; 847 848 config.bpw = t ? t->bits_per_word : spi->bits_per_word; 849 config.speed_hz = t ? t->speed_hz : spi->max_speed_hz; 850 config.mode = spi->mode; 851 config.cs = spi->chip_select; 852 853 if (!config.speed_hz) 854 config.speed_hz = spi->max_speed_hz; 855 if (!config.bpw) 856 config.bpw = spi->bits_per_word; 857 858 /* Initialize the functions for transfer */ 859 if (config.bpw <= 8) { 860 spi_imx->rx = spi_imx_buf_rx_u8; 861 spi_imx->tx = spi_imx_buf_tx_u8; 862 } else if (config.bpw <= 16) { 863 spi_imx->rx = spi_imx_buf_rx_u16; 864 spi_imx->tx = spi_imx_buf_tx_u16; 865 } else { 866 spi_imx->rx = spi_imx_buf_rx_u32; 867 spi_imx->tx = spi_imx_buf_tx_u32; 868 } 869 870 if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t)) 871 spi_imx->usedma = 1; 872 else 873 spi_imx->usedma = 0; 874 875 if (spi_imx->usedma) { 876 ret = spi_imx_dma_configure(spi->master, 877 spi_imx_bytes_per_word(config.bpw)); 878 if (ret) 879 return ret; 880 } 881 882 spi_imx->devtype_data->config(spi_imx, &config); 883 884 return 0; 885 } 886 887 static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx) 888 { 889 struct spi_master *master = spi_imx->bitbang.master; 890 891 if (master->dma_rx) { 892 dma_release_channel(master->dma_rx); 893 master->dma_rx = NULL; 894 } 895 896 if (master->dma_tx) { 897 dma_release_channel(master->dma_tx); 898 master->dma_tx = NULL; 899 } 900 } 901 902 static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx, 903 struct spi_master *master) 904 { 905 int ret; 906 907 /* use pio mode for i.mx6dl chip TKT238285 */ 908 if (of_machine_is_compatible("fsl,imx6dl")) 909 return 0; 910 911 spi_imx->wml = spi_imx_get_fifosize(spi_imx) / 2; 912 913 /* Prepare for TX DMA: */ 914 master->dma_tx = dma_request_slave_channel_reason(dev, "tx"); 915 if (IS_ERR(master->dma_tx)) { 916 ret = PTR_ERR(master->dma_tx); 917 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret); 918 master->dma_tx = NULL; 919 goto err; 920 } 921 922 /* Prepare for RX : */ 923 master->dma_rx = dma_request_slave_channel_reason(dev, "rx"); 924 if (IS_ERR(master->dma_rx)) { 925 ret = PTR_ERR(master->dma_rx); 926 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret); 927 master->dma_rx = NULL; 928 goto err; 929 } 930 931 spi_imx_dma_configure(master, 1); 932 933 init_completion(&spi_imx->dma_rx_completion); 934 init_completion(&spi_imx->dma_tx_completion); 935 master->can_dma = spi_imx_can_dma; 936 master->max_dma_len = MAX_SDMA_BD_BYTES; 937 spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX | 938 SPI_MASTER_MUST_TX; 939 940 return 0; 941 err: 942 spi_imx_sdma_exit(spi_imx); 943 return ret; 944 } 945 946 static void spi_imx_dma_rx_callback(void *cookie) 947 { 948 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie; 949 950 complete(&spi_imx->dma_rx_completion); 951 } 952 953 static void spi_imx_dma_tx_callback(void *cookie) 954 { 955 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie; 956 957 complete(&spi_imx->dma_tx_completion); 958 } 959 960 static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size) 961 { 962 unsigned long timeout = 0; 963 964 /* Time with actual data transfer and CS change delay related to HW */ 965 timeout = (8 + 4) * size / spi_imx->spi_bus_clk; 966 967 /* Add extra second for scheduler related activities */ 968 timeout += 1; 969 970 /* Double calculated timeout */ 971 return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC); 972 } 973 974 static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx, 975 struct spi_transfer *transfer) 976 { 977 struct dma_async_tx_descriptor *desc_tx, *desc_rx; 978 unsigned long transfer_timeout; 979 unsigned long timeout; 980 struct spi_master *master = spi_imx->bitbang.master; 981 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg; 982 983 /* 984 * The TX DMA setup starts the transfer, so make sure RX is configured 985 * before TX. 986 */ 987 desc_rx = dmaengine_prep_slave_sg(master->dma_rx, 988 rx->sgl, rx->nents, DMA_DEV_TO_MEM, 989 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 990 if (!desc_rx) 991 return -EINVAL; 992 993 desc_rx->callback = spi_imx_dma_rx_callback; 994 desc_rx->callback_param = (void *)spi_imx; 995 dmaengine_submit(desc_rx); 996 reinit_completion(&spi_imx->dma_rx_completion); 997 dma_async_issue_pending(master->dma_rx); 998 999 desc_tx = dmaengine_prep_slave_sg(master->dma_tx, 1000 tx->sgl, tx->nents, DMA_MEM_TO_DEV, 1001 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1002 if (!desc_tx) { 1003 dmaengine_terminate_all(master->dma_tx); 1004 return -EINVAL; 1005 } 1006 1007 desc_tx->callback = spi_imx_dma_tx_callback; 1008 desc_tx->callback_param = (void *)spi_imx; 1009 dmaengine_submit(desc_tx); 1010 reinit_completion(&spi_imx->dma_tx_completion); 1011 dma_async_issue_pending(master->dma_tx); 1012 1013 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); 1014 1015 /* Wait SDMA to finish the data transfer.*/ 1016 timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion, 1017 transfer_timeout); 1018 if (!timeout) { 1019 dev_err(spi_imx->dev, "I/O Error in DMA TX\n"); 1020 dmaengine_terminate_all(master->dma_tx); 1021 dmaengine_terminate_all(master->dma_rx); 1022 return -ETIMEDOUT; 1023 } 1024 1025 timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion, 1026 transfer_timeout); 1027 if (!timeout) { 1028 dev_err(&master->dev, "I/O Error in DMA RX\n"); 1029 spi_imx->devtype_data->reset(spi_imx); 1030 dmaengine_terminate_all(master->dma_rx); 1031 return -ETIMEDOUT; 1032 } 1033 1034 return transfer->len; 1035 } 1036 1037 static int spi_imx_pio_transfer(struct spi_device *spi, 1038 struct spi_transfer *transfer) 1039 { 1040 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 1041 1042 spi_imx->tx_buf = transfer->tx_buf; 1043 spi_imx->rx_buf = transfer->rx_buf; 1044 spi_imx->count = transfer->len; 1045 spi_imx->txfifo = 0; 1046 1047 reinit_completion(&spi_imx->xfer_done); 1048 1049 spi_imx_push(spi_imx); 1050 1051 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE); 1052 1053 wait_for_completion(&spi_imx->xfer_done); 1054 1055 return transfer->len; 1056 } 1057 1058 static int spi_imx_transfer(struct spi_device *spi, 1059 struct spi_transfer *transfer) 1060 { 1061 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 1062 1063 if (spi_imx->usedma) 1064 return spi_imx_dma_transfer(spi_imx, transfer); 1065 else 1066 return spi_imx_pio_transfer(spi, transfer); 1067 } 1068 1069 static int spi_imx_setup(struct spi_device *spi) 1070 { 1071 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 1072 int gpio = spi_imx->chipselect[spi->chip_select]; 1073 1074 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__, 1075 spi->mode, spi->bits_per_word, spi->max_speed_hz); 1076 1077 if (gpio_is_valid(gpio)) 1078 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1); 1079 1080 spi_imx_chipselect(spi, BITBANG_CS_INACTIVE); 1081 1082 return 0; 1083 } 1084 1085 static void spi_imx_cleanup(struct spi_device *spi) 1086 { 1087 } 1088 1089 static int 1090 spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg) 1091 { 1092 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 1093 int ret; 1094 1095 ret = clk_enable(spi_imx->clk_per); 1096 if (ret) 1097 return ret; 1098 1099 ret = clk_enable(spi_imx->clk_ipg); 1100 if (ret) { 1101 clk_disable(spi_imx->clk_per); 1102 return ret; 1103 } 1104 1105 return 0; 1106 } 1107 1108 static int 1109 spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg) 1110 { 1111 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 1112 1113 clk_disable(spi_imx->clk_ipg); 1114 clk_disable(spi_imx->clk_per); 1115 return 0; 1116 } 1117 1118 static int spi_imx_probe(struct platform_device *pdev) 1119 { 1120 struct device_node *np = pdev->dev.of_node; 1121 const struct of_device_id *of_id = 1122 of_match_device(spi_imx_dt_ids, &pdev->dev); 1123 struct spi_imx_master *mxc_platform_info = 1124 dev_get_platdata(&pdev->dev); 1125 struct spi_master *master; 1126 struct spi_imx_data *spi_imx; 1127 struct resource *res; 1128 int i, ret, num_cs, irq; 1129 1130 if (!np && !mxc_platform_info) { 1131 dev_err(&pdev->dev, "can't get the platform data\n"); 1132 return -EINVAL; 1133 } 1134 1135 ret = of_property_read_u32(np, "fsl,spi-num-chipselects", &num_cs); 1136 if (ret < 0) { 1137 if (mxc_platform_info) 1138 num_cs = mxc_platform_info->num_chipselect; 1139 else 1140 return ret; 1141 } 1142 1143 master = spi_alloc_master(&pdev->dev, 1144 sizeof(struct spi_imx_data) + sizeof(int) * num_cs); 1145 if (!master) 1146 return -ENOMEM; 1147 1148 platform_set_drvdata(pdev, master); 1149 1150 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); 1151 master->bus_num = pdev->id; 1152 master->num_chipselect = num_cs; 1153 1154 spi_imx = spi_master_get_devdata(master); 1155 spi_imx->bitbang.master = master; 1156 spi_imx->dev = &pdev->dev; 1157 1158 spi_imx->devtype_data = of_id ? of_id->data : 1159 (struct spi_imx_devtype_data *)pdev->id_entry->driver_data; 1160 1161 for (i = 0; i < master->num_chipselect; i++) { 1162 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i); 1163 if (!gpio_is_valid(cs_gpio) && mxc_platform_info) 1164 cs_gpio = mxc_platform_info->chipselect[i]; 1165 1166 spi_imx->chipselect[i] = cs_gpio; 1167 if (!gpio_is_valid(cs_gpio)) 1168 continue; 1169 1170 ret = devm_gpio_request(&pdev->dev, spi_imx->chipselect[i], 1171 DRIVER_NAME); 1172 if (ret) { 1173 dev_err(&pdev->dev, "can't get cs gpios\n"); 1174 goto out_master_put; 1175 } 1176 } 1177 1178 spi_imx->bitbang.chipselect = spi_imx_chipselect; 1179 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer; 1180 spi_imx->bitbang.txrx_bufs = spi_imx_transfer; 1181 spi_imx->bitbang.master->setup = spi_imx_setup; 1182 spi_imx->bitbang.master->cleanup = spi_imx_cleanup; 1183 spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message; 1184 spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message; 1185 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1186 if (is_imx51_ecspi(spi_imx)) 1187 spi_imx->bitbang.master->mode_bits |= SPI_LOOP; 1188 1189 init_completion(&spi_imx->xfer_done); 1190 1191 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1192 spi_imx->base = devm_ioremap_resource(&pdev->dev, res); 1193 if (IS_ERR(spi_imx->base)) { 1194 ret = PTR_ERR(spi_imx->base); 1195 goto out_master_put; 1196 } 1197 spi_imx->base_phys = res->start; 1198 1199 irq = platform_get_irq(pdev, 0); 1200 if (irq < 0) { 1201 ret = irq; 1202 goto out_master_put; 1203 } 1204 1205 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0, 1206 dev_name(&pdev->dev), spi_imx); 1207 if (ret) { 1208 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret); 1209 goto out_master_put; 1210 } 1211 1212 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1213 if (IS_ERR(spi_imx->clk_ipg)) { 1214 ret = PTR_ERR(spi_imx->clk_ipg); 1215 goto out_master_put; 1216 } 1217 1218 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per"); 1219 if (IS_ERR(spi_imx->clk_per)) { 1220 ret = PTR_ERR(spi_imx->clk_per); 1221 goto out_master_put; 1222 } 1223 1224 ret = clk_prepare_enable(spi_imx->clk_per); 1225 if (ret) 1226 goto out_master_put; 1227 1228 ret = clk_prepare_enable(spi_imx->clk_ipg); 1229 if (ret) 1230 goto out_put_per; 1231 1232 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per); 1233 /* 1234 * Only validated on i.mx6 now, can remove the constrain if validated on 1235 * other chips. 1236 */ 1237 if (is_imx51_ecspi(spi_imx)) { 1238 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master); 1239 if (ret == -EPROBE_DEFER) 1240 goto out_clk_put; 1241 1242 if (ret < 0) 1243 dev_err(&pdev->dev, "dma setup error %d, use pio\n", 1244 ret); 1245 } 1246 1247 spi_imx->devtype_data->reset(spi_imx); 1248 1249 spi_imx->devtype_data->intctrl(spi_imx, 0); 1250 1251 master->dev.of_node = pdev->dev.of_node; 1252 ret = spi_bitbang_start(&spi_imx->bitbang); 1253 if (ret) { 1254 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret); 1255 goto out_clk_put; 1256 } 1257 1258 dev_info(&pdev->dev, "probed\n"); 1259 1260 clk_disable(spi_imx->clk_ipg); 1261 clk_disable(spi_imx->clk_per); 1262 return ret; 1263 1264 out_clk_put: 1265 clk_disable_unprepare(spi_imx->clk_ipg); 1266 out_put_per: 1267 clk_disable_unprepare(spi_imx->clk_per); 1268 out_master_put: 1269 spi_master_put(master); 1270 1271 return ret; 1272 } 1273 1274 static int spi_imx_remove(struct platform_device *pdev) 1275 { 1276 struct spi_master *master = platform_get_drvdata(pdev); 1277 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 1278 1279 spi_bitbang_stop(&spi_imx->bitbang); 1280 1281 writel(0, spi_imx->base + MXC_CSPICTRL); 1282 clk_unprepare(spi_imx->clk_ipg); 1283 clk_unprepare(spi_imx->clk_per); 1284 spi_imx_sdma_exit(spi_imx); 1285 spi_master_put(master); 1286 1287 return 0; 1288 } 1289 1290 static struct platform_driver spi_imx_driver = { 1291 .driver = { 1292 .name = DRIVER_NAME, 1293 .of_match_table = spi_imx_dt_ids, 1294 }, 1295 .id_table = spi_imx_devtype, 1296 .probe = spi_imx_probe, 1297 .remove = spi_imx_remove, 1298 }; 1299 module_platform_driver(spi_imx_driver); 1300 1301 MODULE_DESCRIPTION("SPI Master Controller driver"); 1302 MODULE_AUTHOR("Sascha Hauer, Pengutronix"); 1303 MODULE_LICENSE("GPL"); 1304 MODULE_ALIAS("platform:" DRIVER_NAME); 1305