xref: /openbmc/linux/drivers/spi/spi-imx.c (revision 110e6f26) 
1 /*
2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3  * Copyright (C) 2008 Juergen Beisert
4  *
5  * This program is free software; you can redistribute it and/or
6  * modify it under the terms of the GNU General Public License
7  * as published by the Free Software Foundation; either version 2
8  * of the License, or (at your option) any later version.
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the
16  * Free Software Foundation
17  * 51 Franklin Street, Fifth Floor
18  * Boston, MA  02110-1301, USA.
19  */
20 
21 #include <linux/clk.h>
22 #include <linux/completion.h>
23 #include <linux/delay.h>
24 #include <linux/dmaengine.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/err.h>
27 #include <linux/gpio.h>
28 #include <linux/interrupt.h>
29 #include <linux/io.h>
30 #include <linux/irq.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/platform_device.h>
34 #include <linux/slab.h>
35 #include <linux/spi/spi.h>
36 #include <linux/spi/spi_bitbang.h>
37 #include <linux/types.h>
38 #include <linux/of.h>
39 #include <linux/of_device.h>
40 #include <linux/of_gpio.h>
41 
42 #include <linux/platform_data/dma-imx.h>
43 #include <linux/platform_data/spi-imx.h>
44 
45 #define DRIVER_NAME "spi_imx"
46 
47 #define MXC_CSPIRXDATA		0x00
48 #define MXC_CSPITXDATA		0x04
49 #define MXC_CSPICTRL		0x08
50 #define MXC_CSPIINT		0x0c
51 #define MXC_RESET		0x1c
52 
53 /* generic defines to abstract from the different register layouts */
54 #define MXC_INT_RR	(1 << 0) /* Receive data ready interrupt */
55 #define MXC_INT_TE	(1 << 1) /* Transmit FIFO empty interrupt */
56 
57 /* The maximum  bytes that a sdma BD can transfer.*/
58 #define MAX_SDMA_BD_BYTES  (1 << 15)
59 struct spi_imx_config {
60 	unsigned int speed_hz;
61 	unsigned int bpw;
62 	unsigned int mode;
63 	u8 cs;
64 };
65 
66 enum spi_imx_devtype {
67 	IMX1_CSPI,
68 	IMX21_CSPI,
69 	IMX27_CSPI,
70 	IMX31_CSPI,
71 	IMX35_CSPI,	/* CSPI on all i.mx except above */
72 	IMX51_ECSPI,	/* ECSPI on i.mx51 and later */
73 };
74 
75 struct spi_imx_data;
76 
77 struct spi_imx_devtype_data {
78 	void (*intctrl)(struct spi_imx_data *, int);
79 	int (*config)(struct spi_imx_data *, struct spi_imx_config *);
80 	void (*trigger)(struct spi_imx_data *);
81 	int (*rx_available)(struct spi_imx_data *);
82 	void (*reset)(struct spi_imx_data *);
83 	enum spi_imx_devtype devtype;
84 };
85 
86 struct spi_imx_data {
87 	struct spi_bitbang bitbang;
88 	struct device *dev;
89 
90 	struct completion xfer_done;
91 	void __iomem *base;
92 	unsigned long base_phys;
93 
94 	struct clk *clk_per;
95 	struct clk *clk_ipg;
96 	unsigned long spi_clk;
97 	unsigned int spi_bus_clk;
98 
99 	unsigned int bytes_per_word;
100 
101 	unsigned int count;
102 	void (*tx)(struct spi_imx_data *);
103 	void (*rx)(struct spi_imx_data *);
104 	void *rx_buf;
105 	const void *tx_buf;
106 	unsigned int txfifo; /* number of words pushed in tx FIFO */
107 
108 	/* DMA */
109 	bool usedma;
110 	u32 wml;
111 	struct completion dma_rx_completion;
112 	struct completion dma_tx_completion;
113 
114 	const struct spi_imx_devtype_data *devtype_data;
115 	int chipselect[0];
116 };
117 
118 static inline int is_imx27_cspi(struct spi_imx_data *d)
119 {
120 	return d->devtype_data->devtype == IMX27_CSPI;
121 }
122 
123 static inline int is_imx35_cspi(struct spi_imx_data *d)
124 {
125 	return d->devtype_data->devtype == IMX35_CSPI;
126 }
127 
128 static inline int is_imx51_ecspi(struct spi_imx_data *d)
129 {
130 	return d->devtype_data->devtype == IMX51_ECSPI;
131 }
132 
133 static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d)
134 {
135 	return is_imx51_ecspi(d) ? 64 : 8;
136 }
137 
138 #define MXC_SPI_BUF_RX(type)						\
139 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx)		\
140 {									\
141 	unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);	\
142 									\
143 	if (spi_imx->rx_buf) {						\
144 		*(type *)spi_imx->rx_buf = val;				\
145 		spi_imx->rx_buf += sizeof(type);			\
146 	}								\
147 }
148 
149 #define MXC_SPI_BUF_TX(type)						\
150 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx)		\
151 {									\
152 	type val = 0;							\
153 									\
154 	if (spi_imx->tx_buf) {						\
155 		val = *(type *)spi_imx->tx_buf;				\
156 		spi_imx->tx_buf += sizeof(type);			\
157 	}								\
158 									\
159 	spi_imx->count -= sizeof(type);					\
160 									\
161 	writel(val, spi_imx->base + MXC_CSPITXDATA);			\
162 }
163 
164 MXC_SPI_BUF_RX(u8)
165 MXC_SPI_BUF_TX(u8)
166 MXC_SPI_BUF_RX(u16)
167 MXC_SPI_BUF_TX(u16)
168 MXC_SPI_BUF_RX(u32)
169 MXC_SPI_BUF_TX(u32)
170 
171 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
172  * (which is currently not the case in this driver)
173  */
174 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
175 	256, 384, 512, 768, 1024};
176 
177 /* MX21, MX27 */
178 static unsigned int spi_imx_clkdiv_1(unsigned int fin,
179 		unsigned int fspi, unsigned int max)
180 {
181 	int i;
182 
183 	for (i = 2; i < max; i++)
184 		if (fspi * mxc_clkdivs[i] >= fin)
185 			return i;
186 
187 	return max;
188 }
189 
190 /* MX1, MX31, MX35, MX51 CSPI */
191 static unsigned int spi_imx_clkdiv_2(unsigned int fin,
192 		unsigned int fspi)
193 {
194 	int i, div = 4;
195 
196 	for (i = 0; i < 7; i++) {
197 		if (fspi * div >= fin)
198 			return i;
199 		div <<= 1;
200 	}
201 
202 	return 7;
203 }
204 
205 static int spi_imx_bytes_per_word(const int bpw)
206 {
207 	return DIV_ROUND_UP(bpw, BITS_PER_BYTE);
208 }
209 
210 static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
211 			 struct spi_transfer *transfer)
212 {
213 	struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
214 	unsigned int bpw;
215 
216 	if (!master->dma_rx)
217 		return false;
218 
219 	if (!transfer)
220 		return false;
221 
222 	bpw = transfer->bits_per_word;
223 	if (!bpw)
224 		bpw = spi->bits_per_word;
225 
226 	bpw = spi_imx_bytes_per_word(bpw);
227 
228 	if (bpw != 1 && bpw != 2 && bpw != 4)
229 		return false;
230 
231 	if (transfer->len < spi_imx->wml * bpw)
232 		return false;
233 
234 	if (transfer->len % (spi_imx->wml * bpw))
235 		return false;
236 
237 	return true;
238 }
239 
240 #define MX51_ECSPI_CTRL		0x08
241 #define MX51_ECSPI_CTRL_ENABLE		(1 <<  0)
242 #define MX51_ECSPI_CTRL_XCH		(1 <<  2)
243 #define MX51_ECSPI_CTRL_SMC		(1 << 3)
244 #define MX51_ECSPI_CTRL_MODE_MASK	(0xf << 4)
245 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET	8
246 #define MX51_ECSPI_CTRL_PREDIV_OFFSET	12
247 #define MX51_ECSPI_CTRL_CS(cs)		((cs) << 18)
248 #define MX51_ECSPI_CTRL_BL_OFFSET	20
249 
250 #define MX51_ECSPI_CONFIG	0x0c
251 #define MX51_ECSPI_CONFIG_SCLKPHA(cs)	(1 << ((cs) +  0))
252 #define MX51_ECSPI_CONFIG_SCLKPOL(cs)	(1 << ((cs) +  4))
253 #define MX51_ECSPI_CONFIG_SBBCTRL(cs)	(1 << ((cs) +  8))
254 #define MX51_ECSPI_CONFIG_SSBPOL(cs)	(1 << ((cs) + 12))
255 #define MX51_ECSPI_CONFIG_SCLKCTL(cs)	(1 << ((cs) + 20))
256 
257 #define MX51_ECSPI_INT		0x10
258 #define MX51_ECSPI_INT_TEEN		(1 <<  0)
259 #define MX51_ECSPI_INT_RREN		(1 <<  3)
260 
261 #define MX51_ECSPI_DMA      0x14
262 #define MX51_ECSPI_DMA_TX_WML(wml)	((wml) & 0x3f)
263 #define MX51_ECSPI_DMA_RX_WML(wml)	(((wml) & 0x3f) << 16)
264 #define MX51_ECSPI_DMA_RXT_WML(wml)	(((wml) & 0x3f) << 24)
265 
266 #define MX51_ECSPI_DMA_TEDEN		(1 << 7)
267 #define MX51_ECSPI_DMA_RXDEN		(1 << 23)
268 #define MX51_ECSPI_DMA_RXTDEN		(1 << 31)
269 
270 #define MX51_ECSPI_STAT		0x18
271 #define MX51_ECSPI_STAT_RR		(1 <<  3)
272 
273 #define MX51_ECSPI_TESTREG	0x20
274 #define MX51_ECSPI_TESTREG_LBC	BIT(31)
275 
276 /* MX51 eCSPI */
277 static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx,
278 				      unsigned int fspi, unsigned int *fres)
279 {
280 	/*
281 	 * there are two 4-bit dividers, the pre-divider divides by
282 	 * $pre, the post-divider by 2^$post
283 	 */
284 	unsigned int pre, post;
285 	unsigned int fin = spi_imx->spi_clk;
286 
287 	if (unlikely(fspi > fin))
288 		return 0;
289 
290 	post = fls(fin) - fls(fspi);
291 	if (fin > fspi << post)
292 		post++;
293 
294 	/* now we have: (fin <= fspi << post) with post being minimal */
295 
296 	post = max(4U, post) - 4;
297 	if (unlikely(post > 0xf)) {
298 		dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n",
299 				fspi, fin);
300 		return 0xff;
301 	}
302 
303 	pre = DIV_ROUND_UP(fin, fspi << post) - 1;
304 
305 	dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
306 			__func__, fin, fspi, post, pre);
307 
308 	/* Resulting frequency for the SCLK line. */
309 	*fres = (fin / (pre + 1)) >> post;
310 
311 	return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
312 		(post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
313 }
314 
315 static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
316 {
317 	unsigned val = 0;
318 
319 	if (enable & MXC_INT_TE)
320 		val |= MX51_ECSPI_INT_TEEN;
321 
322 	if (enable & MXC_INT_RR)
323 		val |= MX51_ECSPI_INT_RREN;
324 
325 	writel(val, spi_imx->base + MX51_ECSPI_INT);
326 }
327 
328 static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
329 {
330 	u32 reg;
331 
332 	reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
333 	reg |= MX51_ECSPI_CTRL_XCH;
334 	writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
335 }
336 
337 static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
338 		struct spi_imx_config *config)
339 {
340 	u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
341 	u32 clk = config->speed_hz, delay, reg;
342 	u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
343 
344 	/*
345 	 * The hardware seems to have a race condition when changing modes. The
346 	 * current assumption is that the selection of the channel arrives
347 	 * earlier in the hardware than the mode bits when they are written at
348 	 * the same time.
349 	 * So set master mode for all channels as we do not support slave mode.
350 	 */
351 	ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
352 
353 	/* set clock speed */
354 	ctrl |= mx51_ecspi_clkdiv(spi_imx, config->speed_hz, &clk);
355 	spi_imx->spi_bus_clk = clk;
356 
357 	/* set chip select to use */
358 	ctrl |= MX51_ECSPI_CTRL_CS(config->cs);
359 
360 	ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET;
361 
362 	cfg |= MX51_ECSPI_CONFIG_SBBCTRL(config->cs);
363 
364 	if (config->mode & SPI_CPHA)
365 		cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs);
366 	else
367 		cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(config->cs);
368 
369 	if (config->mode & SPI_CPOL) {
370 		cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs);
371 		cfg |= MX51_ECSPI_CONFIG_SCLKCTL(config->cs);
372 	} else {
373 		cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(config->cs);
374 		cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(config->cs);
375 	}
376 	if (config->mode & SPI_CS_HIGH)
377 		cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs);
378 	else
379 		cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(config->cs);
380 
381 	if (spi_imx->usedma)
382 		ctrl |= MX51_ECSPI_CTRL_SMC;
383 
384 	/* CTRL register always go first to bring out controller from reset */
385 	writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
386 
387 	reg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
388 	if (config->mode & SPI_LOOP)
389 		reg |= MX51_ECSPI_TESTREG_LBC;
390 	else
391 		reg &= ~MX51_ECSPI_TESTREG_LBC;
392 	writel(reg, spi_imx->base + MX51_ECSPI_TESTREG);
393 
394 	writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
395 
396 	/*
397 	 * Wait until the changes in the configuration register CONFIGREG
398 	 * propagate into the hardware. It takes exactly one tick of the
399 	 * SCLK clock, but we will wait two SCLK clock just to be sure. The
400 	 * effect of the delay it takes for the hardware to apply changes
401 	 * is noticable if the SCLK clock run very slow. In such a case, if
402 	 * the polarity of SCLK should be inverted, the GPIO ChipSelect might
403 	 * be asserted before the SCLK polarity changes, which would disrupt
404 	 * the SPI communication as the device on the other end would consider
405 	 * the change of SCLK polarity as a clock tick already.
406 	 */
407 	delay = (2 * 1000000) / clk;
408 	if (likely(delay < 10))	/* SCLK is faster than 100 kHz */
409 		udelay(delay);
410 	else			/* SCLK is _very_ slow */
411 		usleep_range(delay, delay + 10);
412 
413 	/*
414 	 * Configure the DMA register: setup the watermark
415 	 * and enable DMA request.
416 	 */
417 
418 	writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml) |
419 		MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
420 		MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
421 		MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
422 		MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
423 
424 	return 0;
425 }
426 
427 static int __maybe_unused mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
428 {
429 	return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
430 }
431 
432 static void __maybe_unused mx51_ecspi_reset(struct spi_imx_data *spi_imx)
433 {
434 	/* drain receive buffer */
435 	while (mx51_ecspi_rx_available(spi_imx))
436 		readl(spi_imx->base + MXC_CSPIRXDATA);
437 }
438 
439 #define MX31_INTREG_TEEN	(1 << 0)
440 #define MX31_INTREG_RREN	(1 << 3)
441 
442 #define MX31_CSPICTRL_ENABLE	(1 << 0)
443 #define MX31_CSPICTRL_MASTER	(1 << 1)
444 #define MX31_CSPICTRL_XCH	(1 << 2)
445 #define MX31_CSPICTRL_POL	(1 << 4)
446 #define MX31_CSPICTRL_PHA	(1 << 5)
447 #define MX31_CSPICTRL_SSCTL	(1 << 6)
448 #define MX31_CSPICTRL_SSPOL	(1 << 7)
449 #define MX31_CSPICTRL_BC_SHIFT	8
450 #define MX35_CSPICTRL_BL_SHIFT	20
451 #define MX31_CSPICTRL_CS_SHIFT	24
452 #define MX35_CSPICTRL_CS_SHIFT	12
453 #define MX31_CSPICTRL_DR_SHIFT	16
454 
455 #define MX31_CSPISTATUS		0x14
456 #define MX31_STATUS_RR		(1 << 3)
457 
458 /* These functions also work for the i.MX35, but be aware that
459  * the i.MX35 has a slightly different register layout for bits
460  * we do not use here.
461  */
462 static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
463 {
464 	unsigned int val = 0;
465 
466 	if (enable & MXC_INT_TE)
467 		val |= MX31_INTREG_TEEN;
468 	if (enable & MXC_INT_RR)
469 		val |= MX31_INTREG_RREN;
470 
471 	writel(val, spi_imx->base + MXC_CSPIINT);
472 }
473 
474 static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx)
475 {
476 	unsigned int reg;
477 
478 	reg = readl(spi_imx->base + MXC_CSPICTRL);
479 	reg |= MX31_CSPICTRL_XCH;
480 	writel(reg, spi_imx->base + MXC_CSPICTRL);
481 }
482 
483 static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx,
484 		struct spi_imx_config *config)
485 {
486 	unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
487 	int cs = spi_imx->chipselect[config->cs];
488 
489 	reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
490 		MX31_CSPICTRL_DR_SHIFT;
491 
492 	if (is_imx35_cspi(spi_imx)) {
493 		reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
494 		reg |= MX31_CSPICTRL_SSCTL;
495 	} else {
496 		reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
497 	}
498 
499 	if (config->mode & SPI_CPHA)
500 		reg |= MX31_CSPICTRL_PHA;
501 	if (config->mode & SPI_CPOL)
502 		reg |= MX31_CSPICTRL_POL;
503 	if (config->mode & SPI_CS_HIGH)
504 		reg |= MX31_CSPICTRL_SSPOL;
505 	if (cs < 0)
506 		reg |= (cs + 32) <<
507 			(is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
508 						  MX31_CSPICTRL_CS_SHIFT);
509 
510 	writel(reg, spi_imx->base + MXC_CSPICTRL);
511 
512 	return 0;
513 }
514 
515 static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx)
516 {
517 	return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
518 }
519 
520 static void __maybe_unused mx31_reset(struct spi_imx_data *spi_imx)
521 {
522 	/* drain receive buffer */
523 	while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
524 		readl(spi_imx->base + MXC_CSPIRXDATA);
525 }
526 
527 #define MX21_INTREG_RR		(1 << 4)
528 #define MX21_INTREG_TEEN	(1 << 9)
529 #define MX21_INTREG_RREN	(1 << 13)
530 
531 #define MX21_CSPICTRL_POL	(1 << 5)
532 #define MX21_CSPICTRL_PHA	(1 << 6)
533 #define MX21_CSPICTRL_SSPOL	(1 << 8)
534 #define MX21_CSPICTRL_XCH	(1 << 9)
535 #define MX21_CSPICTRL_ENABLE	(1 << 10)
536 #define MX21_CSPICTRL_MASTER	(1 << 11)
537 #define MX21_CSPICTRL_DR_SHIFT	14
538 #define MX21_CSPICTRL_CS_SHIFT	19
539 
540 static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
541 {
542 	unsigned int val = 0;
543 
544 	if (enable & MXC_INT_TE)
545 		val |= MX21_INTREG_TEEN;
546 	if (enable & MXC_INT_RR)
547 		val |= MX21_INTREG_RREN;
548 
549 	writel(val, spi_imx->base + MXC_CSPIINT);
550 }
551 
552 static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx)
553 {
554 	unsigned int reg;
555 
556 	reg = readl(spi_imx->base + MXC_CSPICTRL);
557 	reg |= MX21_CSPICTRL_XCH;
558 	writel(reg, spi_imx->base + MXC_CSPICTRL);
559 }
560 
561 static int __maybe_unused mx21_config(struct spi_imx_data *spi_imx,
562 		struct spi_imx_config *config)
563 {
564 	unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
565 	int cs = spi_imx->chipselect[config->cs];
566 	unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
567 
568 	reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max) <<
569 		MX21_CSPICTRL_DR_SHIFT;
570 	reg |= config->bpw - 1;
571 
572 	if (config->mode & SPI_CPHA)
573 		reg |= MX21_CSPICTRL_PHA;
574 	if (config->mode & SPI_CPOL)
575 		reg |= MX21_CSPICTRL_POL;
576 	if (config->mode & SPI_CS_HIGH)
577 		reg |= MX21_CSPICTRL_SSPOL;
578 	if (cs < 0)
579 		reg |= (cs + 32) << MX21_CSPICTRL_CS_SHIFT;
580 
581 	writel(reg, spi_imx->base + MXC_CSPICTRL);
582 
583 	return 0;
584 }
585 
586 static int __maybe_unused mx21_rx_available(struct spi_imx_data *spi_imx)
587 {
588 	return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
589 }
590 
591 static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx)
592 {
593 	writel(1, spi_imx->base + MXC_RESET);
594 }
595 
596 #define MX1_INTREG_RR		(1 << 3)
597 #define MX1_INTREG_TEEN		(1 << 8)
598 #define MX1_INTREG_RREN		(1 << 11)
599 
600 #define MX1_CSPICTRL_POL	(1 << 4)
601 #define MX1_CSPICTRL_PHA	(1 << 5)
602 #define MX1_CSPICTRL_XCH	(1 << 8)
603 #define MX1_CSPICTRL_ENABLE	(1 << 9)
604 #define MX1_CSPICTRL_MASTER	(1 << 10)
605 #define MX1_CSPICTRL_DR_SHIFT	13
606 
607 static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
608 {
609 	unsigned int val = 0;
610 
611 	if (enable & MXC_INT_TE)
612 		val |= MX1_INTREG_TEEN;
613 	if (enable & MXC_INT_RR)
614 		val |= MX1_INTREG_RREN;
615 
616 	writel(val, spi_imx->base + MXC_CSPIINT);
617 }
618 
619 static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx)
620 {
621 	unsigned int reg;
622 
623 	reg = readl(spi_imx->base + MXC_CSPICTRL);
624 	reg |= MX1_CSPICTRL_XCH;
625 	writel(reg, spi_imx->base + MXC_CSPICTRL);
626 }
627 
628 static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx,
629 		struct spi_imx_config *config)
630 {
631 	unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
632 
633 	reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
634 		MX1_CSPICTRL_DR_SHIFT;
635 	reg |= config->bpw - 1;
636 
637 	if (config->mode & SPI_CPHA)
638 		reg |= MX1_CSPICTRL_PHA;
639 	if (config->mode & SPI_CPOL)
640 		reg |= MX1_CSPICTRL_POL;
641 
642 	writel(reg, spi_imx->base + MXC_CSPICTRL);
643 
644 	return 0;
645 }
646 
647 static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx)
648 {
649 	return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
650 }
651 
652 static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx)
653 {
654 	writel(1, spi_imx->base + MXC_RESET);
655 }
656 
657 static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
658 	.intctrl = mx1_intctrl,
659 	.config = mx1_config,
660 	.trigger = mx1_trigger,
661 	.rx_available = mx1_rx_available,
662 	.reset = mx1_reset,
663 	.devtype = IMX1_CSPI,
664 };
665 
666 static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
667 	.intctrl = mx21_intctrl,
668 	.config = mx21_config,
669 	.trigger = mx21_trigger,
670 	.rx_available = mx21_rx_available,
671 	.reset = mx21_reset,
672 	.devtype = IMX21_CSPI,
673 };
674 
675 static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
676 	/* i.mx27 cspi shares the functions with i.mx21 one */
677 	.intctrl = mx21_intctrl,
678 	.config = mx21_config,
679 	.trigger = mx21_trigger,
680 	.rx_available = mx21_rx_available,
681 	.reset = mx21_reset,
682 	.devtype = IMX27_CSPI,
683 };
684 
685 static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
686 	.intctrl = mx31_intctrl,
687 	.config = mx31_config,
688 	.trigger = mx31_trigger,
689 	.rx_available = mx31_rx_available,
690 	.reset = mx31_reset,
691 	.devtype = IMX31_CSPI,
692 };
693 
694 static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
695 	/* i.mx35 and later cspi shares the functions with i.mx31 one */
696 	.intctrl = mx31_intctrl,
697 	.config = mx31_config,
698 	.trigger = mx31_trigger,
699 	.rx_available = mx31_rx_available,
700 	.reset = mx31_reset,
701 	.devtype = IMX35_CSPI,
702 };
703 
704 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
705 	.intctrl = mx51_ecspi_intctrl,
706 	.config = mx51_ecspi_config,
707 	.trigger = mx51_ecspi_trigger,
708 	.rx_available = mx51_ecspi_rx_available,
709 	.reset = mx51_ecspi_reset,
710 	.devtype = IMX51_ECSPI,
711 };
712 
713 static const struct platform_device_id spi_imx_devtype[] = {
714 	{
715 		.name = "imx1-cspi",
716 		.driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
717 	}, {
718 		.name = "imx21-cspi",
719 		.driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
720 	}, {
721 		.name = "imx27-cspi",
722 		.driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
723 	}, {
724 		.name = "imx31-cspi",
725 		.driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
726 	}, {
727 		.name = "imx35-cspi",
728 		.driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
729 	}, {
730 		.name = "imx51-ecspi",
731 		.driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
732 	}, {
733 		/* sentinel */
734 	}
735 };
736 
737 static const struct of_device_id spi_imx_dt_ids[] = {
738 	{ .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
739 	{ .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
740 	{ .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
741 	{ .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
742 	{ .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
743 	{ .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
744 	{ /* sentinel */ }
745 };
746 MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
747 
748 static void spi_imx_chipselect(struct spi_device *spi, int is_active)
749 {
750 	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
751 	int gpio = spi_imx->chipselect[spi->chip_select];
752 	int active = is_active != BITBANG_CS_INACTIVE;
753 	int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
754 
755 	if (!gpio_is_valid(gpio))
756 		return;
757 
758 	gpio_set_value(gpio, dev_is_lowactive ^ active);
759 }
760 
761 static void spi_imx_push(struct spi_imx_data *spi_imx)
762 {
763 	while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) {
764 		if (!spi_imx->count)
765 			break;
766 		spi_imx->tx(spi_imx);
767 		spi_imx->txfifo++;
768 	}
769 
770 	spi_imx->devtype_data->trigger(spi_imx);
771 }
772 
773 static irqreturn_t spi_imx_isr(int irq, void *dev_id)
774 {
775 	struct spi_imx_data *spi_imx = dev_id;
776 
777 	while (spi_imx->devtype_data->rx_available(spi_imx)) {
778 		spi_imx->rx(spi_imx);
779 		spi_imx->txfifo--;
780 	}
781 
782 	if (spi_imx->count) {
783 		spi_imx_push(spi_imx);
784 		return IRQ_HANDLED;
785 	}
786 
787 	if (spi_imx->txfifo) {
788 		/* No data left to push, but still waiting for rx data,
789 		 * enable receive data available interrupt.
790 		 */
791 		spi_imx->devtype_data->intctrl(
792 				spi_imx, MXC_INT_RR);
793 		return IRQ_HANDLED;
794 	}
795 
796 	spi_imx->devtype_data->intctrl(spi_imx, 0);
797 	complete(&spi_imx->xfer_done);
798 
799 	return IRQ_HANDLED;
800 }
801 
802 static int spi_imx_dma_configure(struct spi_master *master,
803 				 int bytes_per_word)
804 {
805 	int ret;
806 	enum dma_slave_buswidth buswidth;
807 	struct dma_slave_config rx = {}, tx = {};
808 	struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
809 
810 	if (bytes_per_word == spi_imx->bytes_per_word)
811 		/* Same as last time */
812 		return 0;
813 
814 	switch (bytes_per_word) {
815 	case 4:
816 		buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
817 		break;
818 	case 2:
819 		buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
820 		break;
821 	case 1:
822 		buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
823 		break;
824 	default:
825 		return -EINVAL;
826 	}
827 
828 	tx.direction = DMA_MEM_TO_DEV;
829 	tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
830 	tx.dst_addr_width = buswidth;
831 	tx.dst_maxburst = spi_imx->wml;
832 	ret = dmaengine_slave_config(master->dma_tx, &tx);
833 	if (ret) {
834 		dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret);
835 		return ret;
836 	}
837 
838 	rx.direction = DMA_DEV_TO_MEM;
839 	rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA;
840 	rx.src_addr_width = buswidth;
841 	rx.src_maxburst = spi_imx->wml;
842 	ret = dmaengine_slave_config(master->dma_rx, &rx);
843 	if (ret) {
844 		dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret);
845 		return ret;
846 	}
847 
848 	spi_imx->bytes_per_word = bytes_per_word;
849 
850 	return 0;
851 }
852 
853 static int spi_imx_setupxfer(struct spi_device *spi,
854 				 struct spi_transfer *t)
855 {
856 	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
857 	struct spi_imx_config config;
858 	int ret;
859 
860 	config.bpw = t ? t->bits_per_word : spi->bits_per_word;
861 	config.speed_hz  = t ? t->speed_hz : spi->max_speed_hz;
862 	config.mode = spi->mode;
863 	config.cs = spi->chip_select;
864 
865 	if (!config.speed_hz)
866 		config.speed_hz = spi->max_speed_hz;
867 	if (!config.bpw)
868 		config.bpw = spi->bits_per_word;
869 
870 	/* Initialize the functions for transfer */
871 	if (config.bpw <= 8) {
872 		spi_imx->rx = spi_imx_buf_rx_u8;
873 		spi_imx->tx = spi_imx_buf_tx_u8;
874 	} else if (config.bpw <= 16) {
875 		spi_imx->rx = spi_imx_buf_rx_u16;
876 		spi_imx->tx = spi_imx_buf_tx_u16;
877 	} else {
878 		spi_imx->rx = spi_imx_buf_rx_u32;
879 		spi_imx->tx = spi_imx_buf_tx_u32;
880 	}
881 
882 	if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t))
883 		spi_imx->usedma = 1;
884 	else
885 		spi_imx->usedma = 0;
886 
887 	if (spi_imx->usedma) {
888 		ret = spi_imx_dma_configure(spi->master,
889 					    spi_imx_bytes_per_word(config.bpw));
890 		if (ret)
891 			return ret;
892 	}
893 
894 	spi_imx->devtype_data->config(spi_imx, &config);
895 
896 	return 0;
897 }
898 
899 static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
900 {
901 	struct spi_master *master = spi_imx->bitbang.master;
902 
903 	if (master->dma_rx) {
904 		dma_release_channel(master->dma_rx);
905 		master->dma_rx = NULL;
906 	}
907 
908 	if (master->dma_tx) {
909 		dma_release_channel(master->dma_tx);
910 		master->dma_tx = NULL;
911 	}
912 }
913 
914 static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
915 			     struct spi_master *master)
916 {
917 	int ret;
918 
919 	/* use pio mode for i.mx6dl chip TKT238285 */
920 	if (of_machine_is_compatible("fsl,imx6dl"))
921 		return 0;
922 
923 	spi_imx->wml = spi_imx_get_fifosize(spi_imx) / 2;
924 
925 	/* Prepare for TX DMA: */
926 	master->dma_tx = dma_request_slave_channel_reason(dev, "tx");
927 	if (IS_ERR(master->dma_tx)) {
928 		ret = PTR_ERR(master->dma_tx);
929 		dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
930 		master->dma_tx = NULL;
931 		goto err;
932 	}
933 
934 	/* Prepare for RX : */
935 	master->dma_rx = dma_request_slave_channel_reason(dev, "rx");
936 	if (IS_ERR(master->dma_rx)) {
937 		ret = PTR_ERR(master->dma_rx);
938 		dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
939 		master->dma_rx = NULL;
940 		goto err;
941 	}
942 
943 	spi_imx_dma_configure(master, 1);
944 
945 	init_completion(&spi_imx->dma_rx_completion);
946 	init_completion(&spi_imx->dma_tx_completion);
947 	master->can_dma = spi_imx_can_dma;
948 	master->max_dma_len = MAX_SDMA_BD_BYTES;
949 	spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX |
950 					 SPI_MASTER_MUST_TX;
951 
952 	return 0;
953 err:
954 	spi_imx_sdma_exit(spi_imx);
955 	return ret;
956 }
957 
958 static void spi_imx_dma_rx_callback(void *cookie)
959 {
960 	struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
961 
962 	complete(&spi_imx->dma_rx_completion);
963 }
964 
965 static void spi_imx_dma_tx_callback(void *cookie)
966 {
967 	struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
968 
969 	complete(&spi_imx->dma_tx_completion);
970 }
971 
972 static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size)
973 {
974 	unsigned long timeout = 0;
975 
976 	/* Time with actual data transfer and CS change delay related to HW */
977 	timeout = (8 + 4) * size / spi_imx->spi_bus_clk;
978 
979 	/* Add extra second for scheduler related activities */
980 	timeout += 1;
981 
982 	/* Double calculated timeout */
983 	return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
984 }
985 
986 static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
987 				struct spi_transfer *transfer)
988 {
989 	struct dma_async_tx_descriptor *desc_tx, *desc_rx;
990 	unsigned long transfer_timeout;
991 	unsigned long timeout;
992 	struct spi_master *master = spi_imx->bitbang.master;
993 	struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
994 
995 	/*
996 	 * The TX DMA setup starts the transfer, so make sure RX is configured
997 	 * before TX.
998 	 */
999 	desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
1000 				rx->sgl, rx->nents, DMA_DEV_TO_MEM,
1001 				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1002 	if (!desc_rx)
1003 		return -EINVAL;
1004 
1005 	desc_rx->callback = spi_imx_dma_rx_callback;
1006 	desc_rx->callback_param = (void *)spi_imx;
1007 	dmaengine_submit(desc_rx);
1008 	reinit_completion(&spi_imx->dma_rx_completion);
1009 	dma_async_issue_pending(master->dma_rx);
1010 
1011 	desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
1012 				tx->sgl, tx->nents, DMA_MEM_TO_DEV,
1013 				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1014 	if (!desc_tx) {
1015 		dmaengine_terminate_all(master->dma_tx);
1016 		return -EINVAL;
1017 	}
1018 
1019 	desc_tx->callback = spi_imx_dma_tx_callback;
1020 	desc_tx->callback_param = (void *)spi_imx;
1021 	dmaengine_submit(desc_tx);
1022 	reinit_completion(&spi_imx->dma_tx_completion);
1023 	dma_async_issue_pending(master->dma_tx);
1024 
1025 	transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1026 
1027 	/* Wait SDMA to finish the data transfer.*/
1028 	timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
1029 						transfer_timeout);
1030 	if (!timeout) {
1031 		dev_err(spi_imx->dev, "I/O Error in DMA TX\n");
1032 		dmaengine_terminate_all(master->dma_tx);
1033 		dmaengine_terminate_all(master->dma_rx);
1034 		return -ETIMEDOUT;
1035 	}
1036 
1037 	timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion,
1038 					      transfer_timeout);
1039 	if (!timeout) {
1040 		dev_err(&master->dev, "I/O Error in DMA RX\n");
1041 		spi_imx->devtype_data->reset(spi_imx);
1042 		dmaengine_terminate_all(master->dma_rx);
1043 		return -ETIMEDOUT;
1044 	}
1045 
1046 	return transfer->len;
1047 }
1048 
1049 static int spi_imx_pio_transfer(struct spi_device *spi,
1050 				struct spi_transfer *transfer)
1051 {
1052 	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1053 
1054 	spi_imx->tx_buf = transfer->tx_buf;
1055 	spi_imx->rx_buf = transfer->rx_buf;
1056 	spi_imx->count = transfer->len;
1057 	spi_imx->txfifo = 0;
1058 
1059 	reinit_completion(&spi_imx->xfer_done);
1060 
1061 	spi_imx_push(spi_imx);
1062 
1063 	spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
1064 
1065 	wait_for_completion(&spi_imx->xfer_done);
1066 
1067 	return transfer->len;
1068 }
1069 
1070 static int spi_imx_transfer(struct spi_device *spi,
1071 				struct spi_transfer *transfer)
1072 {
1073 	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1074 
1075 	if (spi_imx->usedma)
1076 		return spi_imx_dma_transfer(spi_imx, transfer);
1077 	else
1078 		return spi_imx_pio_transfer(spi, transfer);
1079 }
1080 
1081 static int spi_imx_setup(struct spi_device *spi)
1082 {
1083 	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1084 	int gpio = spi_imx->chipselect[spi->chip_select];
1085 
1086 	dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
1087 		 spi->mode, spi->bits_per_word, spi->max_speed_hz);
1088 
1089 	if (gpio_is_valid(gpio))
1090 		gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
1091 
1092 	spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
1093 
1094 	return 0;
1095 }
1096 
1097 static void spi_imx_cleanup(struct spi_device *spi)
1098 {
1099 }
1100 
1101 static int
1102 spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg)
1103 {
1104 	struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1105 	int ret;
1106 
1107 	ret = clk_enable(spi_imx->clk_per);
1108 	if (ret)
1109 		return ret;
1110 
1111 	ret = clk_enable(spi_imx->clk_ipg);
1112 	if (ret) {
1113 		clk_disable(spi_imx->clk_per);
1114 		return ret;
1115 	}
1116 
1117 	return 0;
1118 }
1119 
1120 static int
1121 spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
1122 {
1123 	struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1124 
1125 	clk_disable(spi_imx->clk_ipg);
1126 	clk_disable(spi_imx->clk_per);
1127 	return 0;
1128 }
1129 
1130 static int spi_imx_probe(struct platform_device *pdev)
1131 {
1132 	struct device_node *np = pdev->dev.of_node;
1133 	const struct of_device_id *of_id =
1134 			of_match_device(spi_imx_dt_ids, &pdev->dev);
1135 	struct spi_imx_master *mxc_platform_info =
1136 			dev_get_platdata(&pdev->dev);
1137 	struct spi_master *master;
1138 	struct spi_imx_data *spi_imx;
1139 	struct resource *res;
1140 	int i, ret, num_cs, irq;
1141 
1142 	if (!np && !mxc_platform_info) {
1143 		dev_err(&pdev->dev, "can't get the platform data\n");
1144 		return -EINVAL;
1145 	}
1146 
1147 	ret = of_property_read_u32(np, "fsl,spi-num-chipselects", &num_cs);
1148 	if (ret < 0) {
1149 		if (mxc_platform_info)
1150 			num_cs = mxc_platform_info->num_chipselect;
1151 		else
1152 			return ret;
1153 	}
1154 
1155 	master = spi_alloc_master(&pdev->dev,
1156 			sizeof(struct spi_imx_data) + sizeof(int) * num_cs);
1157 	if (!master)
1158 		return -ENOMEM;
1159 
1160 	platform_set_drvdata(pdev, master);
1161 
1162 	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
1163 	master->bus_num = pdev->id;
1164 	master->num_chipselect = num_cs;
1165 
1166 	spi_imx = spi_master_get_devdata(master);
1167 	spi_imx->bitbang.master = master;
1168 	spi_imx->dev = &pdev->dev;
1169 
1170 	spi_imx->devtype_data = of_id ? of_id->data :
1171 		(struct spi_imx_devtype_data *)pdev->id_entry->driver_data;
1172 
1173 	for (i = 0; i < master->num_chipselect; i++) {
1174 		int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
1175 		if (!gpio_is_valid(cs_gpio) && mxc_platform_info)
1176 			cs_gpio = mxc_platform_info->chipselect[i];
1177 
1178 		spi_imx->chipselect[i] = cs_gpio;
1179 		if (!gpio_is_valid(cs_gpio))
1180 			continue;
1181 
1182 		ret = devm_gpio_request(&pdev->dev, spi_imx->chipselect[i],
1183 					DRIVER_NAME);
1184 		if (ret) {
1185 			dev_err(&pdev->dev, "can't get cs gpios\n");
1186 			goto out_master_put;
1187 		}
1188 	}
1189 
1190 	spi_imx->bitbang.chipselect = spi_imx_chipselect;
1191 	spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
1192 	spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
1193 	spi_imx->bitbang.master->setup = spi_imx_setup;
1194 	spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
1195 	spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
1196 	spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
1197 	spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1198 	if (is_imx51_ecspi(spi_imx))
1199 		spi_imx->bitbang.master->mode_bits |= SPI_LOOP;
1200 
1201 	init_completion(&spi_imx->xfer_done);
1202 
1203 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1204 	spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
1205 	if (IS_ERR(spi_imx->base)) {
1206 		ret = PTR_ERR(spi_imx->base);
1207 		goto out_master_put;
1208 	}
1209 	spi_imx->base_phys = res->start;
1210 
1211 	irq = platform_get_irq(pdev, 0);
1212 	if (irq < 0) {
1213 		ret = irq;
1214 		goto out_master_put;
1215 	}
1216 
1217 	ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
1218 			       dev_name(&pdev->dev), spi_imx);
1219 	if (ret) {
1220 		dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
1221 		goto out_master_put;
1222 	}
1223 
1224 	spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1225 	if (IS_ERR(spi_imx->clk_ipg)) {
1226 		ret = PTR_ERR(spi_imx->clk_ipg);
1227 		goto out_master_put;
1228 	}
1229 
1230 	spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
1231 	if (IS_ERR(spi_imx->clk_per)) {
1232 		ret = PTR_ERR(spi_imx->clk_per);
1233 		goto out_master_put;
1234 	}
1235 
1236 	ret = clk_prepare_enable(spi_imx->clk_per);
1237 	if (ret)
1238 		goto out_master_put;
1239 
1240 	ret = clk_prepare_enable(spi_imx->clk_ipg);
1241 	if (ret)
1242 		goto out_put_per;
1243 
1244 	spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
1245 	/*
1246 	 * Only validated on i.mx6 now, can remove the constrain if validated on
1247 	 * other chips.
1248 	 */
1249 	if (is_imx51_ecspi(spi_imx)) {
1250 		ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master);
1251 		if (ret == -EPROBE_DEFER)
1252 			goto out_clk_put;
1253 
1254 		if (ret < 0)
1255 			dev_err(&pdev->dev, "dma setup error %d, use pio\n",
1256 				ret);
1257 	}
1258 
1259 	spi_imx->devtype_data->reset(spi_imx);
1260 
1261 	spi_imx->devtype_data->intctrl(spi_imx, 0);
1262 
1263 	master->dev.of_node = pdev->dev.of_node;
1264 	ret = spi_bitbang_start(&spi_imx->bitbang);
1265 	if (ret) {
1266 		dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
1267 		goto out_clk_put;
1268 	}
1269 
1270 	dev_info(&pdev->dev, "probed\n");
1271 
1272 	clk_disable(spi_imx->clk_ipg);
1273 	clk_disable(spi_imx->clk_per);
1274 	return ret;
1275 
1276 out_clk_put:
1277 	clk_disable_unprepare(spi_imx->clk_ipg);
1278 out_put_per:
1279 	clk_disable_unprepare(spi_imx->clk_per);
1280 out_master_put:
1281 	spi_master_put(master);
1282 
1283 	return ret;
1284 }
1285 
1286 static int spi_imx_remove(struct platform_device *pdev)
1287 {
1288 	struct spi_master *master = platform_get_drvdata(pdev);
1289 	struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1290 
1291 	spi_bitbang_stop(&spi_imx->bitbang);
1292 
1293 	writel(0, spi_imx->base + MXC_CSPICTRL);
1294 	clk_unprepare(spi_imx->clk_ipg);
1295 	clk_unprepare(spi_imx->clk_per);
1296 	spi_imx_sdma_exit(spi_imx);
1297 	spi_master_put(master);
1298 
1299 	return 0;
1300 }
1301 
1302 static struct platform_driver spi_imx_driver = {
1303 	.driver = {
1304 		   .name = DRIVER_NAME,
1305 		   .of_match_table = spi_imx_dt_ids,
1306 		   },
1307 	.id_table = spi_imx_devtype,
1308 	.probe = spi_imx_probe,
1309 	.remove = spi_imx_remove,
1310 };
1311 module_platform_driver(spi_imx_driver);
1312 
1313 MODULE_DESCRIPTION("SPI Master Controller driver");
1314 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1315 MODULE_LICENSE("GPL");
1316 MODULE_ALIAS("platform:" DRIVER_NAME);
1317