1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved. 3 4 #include <linux/clk.h> 5 #include <linux/interrupt.h> 6 #include <linux/io.h> 7 #include <linux/log2.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/pm_opp.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/qcom-geni-se.h> 13 #include <linux/spi/spi.h> 14 #include <linux/spinlock.h> 15 16 /* SPI SE specific registers and respective register fields */ 17 #define SE_SPI_CPHA 0x224 18 #define CPHA BIT(0) 19 20 #define SE_SPI_LOOPBACK 0x22c 21 #define LOOPBACK_ENABLE 0x1 22 #define NORMAL_MODE 0x0 23 #define LOOPBACK_MSK GENMASK(1, 0) 24 25 #define SE_SPI_CPOL 0x230 26 #define CPOL BIT(2) 27 28 #define SE_SPI_DEMUX_OUTPUT_INV 0x24c 29 #define CS_DEMUX_OUTPUT_INV_MSK GENMASK(3, 0) 30 31 #define SE_SPI_DEMUX_SEL 0x250 32 #define CS_DEMUX_OUTPUT_SEL GENMASK(3, 0) 33 34 #define SE_SPI_TRANS_CFG 0x25c 35 #define CS_TOGGLE BIT(0) 36 37 #define SE_SPI_WORD_LEN 0x268 38 #define WORD_LEN_MSK GENMASK(9, 0) 39 #define MIN_WORD_LEN 4 40 41 #define SE_SPI_TX_TRANS_LEN 0x26c 42 #define SE_SPI_RX_TRANS_LEN 0x270 43 #define TRANS_LEN_MSK GENMASK(23, 0) 44 45 #define SE_SPI_PRE_POST_CMD_DLY 0x274 46 47 #define SE_SPI_DELAY_COUNTERS 0x278 48 #define SPI_INTER_WORDS_DELAY_MSK GENMASK(9, 0) 49 #define SPI_CS_CLK_DELAY_MSK GENMASK(19, 10) 50 #define SPI_CS_CLK_DELAY_SHFT 10 51 52 /* M_CMD OP codes for SPI */ 53 #define SPI_TX_ONLY 1 54 #define SPI_RX_ONLY 2 55 #define SPI_TX_RX 7 56 #define SPI_CS_ASSERT 8 57 #define SPI_CS_DEASSERT 9 58 #define SPI_SCK_ONLY 10 59 /* M_CMD params for SPI */ 60 #define SPI_PRE_CMD_DELAY BIT(0) 61 #define TIMESTAMP_BEFORE BIT(1) 62 #define FRAGMENTATION BIT(2) 63 #define TIMESTAMP_AFTER BIT(3) 64 #define POST_CMD_DELAY BIT(4) 65 66 struct spi_geni_master { 67 struct geni_se se; 68 struct device *dev; 69 u32 tx_fifo_depth; 70 u32 fifo_width_bits; 71 u32 tx_wm; 72 u32 last_mode; 73 unsigned long cur_speed_hz; 74 unsigned long cur_sclk_hz; 75 unsigned int cur_bits_per_word; 76 unsigned int tx_rem_bytes; 77 unsigned int rx_rem_bytes; 78 const struct spi_transfer *cur_xfer; 79 struct completion cs_done; 80 struct completion cancel_done; 81 struct completion abort_done; 82 unsigned int oversampling; 83 spinlock_t lock; 84 int irq; 85 bool cs_flag; 86 }; 87 88 static int get_spi_clk_cfg(unsigned int speed_hz, 89 struct spi_geni_master *mas, 90 unsigned int *clk_idx, 91 unsigned int *clk_div) 92 { 93 unsigned long sclk_freq; 94 unsigned int actual_hz; 95 int ret; 96 97 ret = geni_se_clk_freq_match(&mas->se, 98 speed_hz * mas->oversampling, 99 clk_idx, &sclk_freq, false); 100 if (ret) { 101 dev_err(mas->dev, "Failed(%d) to find src clk for %dHz\n", 102 ret, speed_hz); 103 return ret; 104 } 105 106 *clk_div = DIV_ROUND_UP(sclk_freq, mas->oversampling * speed_hz); 107 actual_hz = sclk_freq / (mas->oversampling * *clk_div); 108 109 dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz, 110 actual_hz, sclk_freq, *clk_idx, *clk_div); 111 ret = dev_pm_opp_set_rate(mas->dev, sclk_freq); 112 if (ret) 113 dev_err(mas->dev, "dev_pm_opp_set_rate failed %d\n", ret); 114 else 115 mas->cur_sclk_hz = sclk_freq; 116 117 return ret; 118 } 119 120 static void handle_fifo_timeout(struct spi_master *spi, 121 struct spi_message *msg) 122 { 123 struct spi_geni_master *mas = spi_master_get_devdata(spi); 124 unsigned long time_left; 125 struct geni_se *se = &mas->se; 126 127 spin_lock_irq(&mas->lock); 128 reinit_completion(&mas->cancel_done); 129 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 130 mas->cur_xfer = NULL; 131 geni_se_cancel_m_cmd(se); 132 spin_unlock_irq(&mas->lock); 133 134 time_left = wait_for_completion_timeout(&mas->cancel_done, HZ); 135 if (time_left) 136 return; 137 138 spin_lock_irq(&mas->lock); 139 reinit_completion(&mas->abort_done); 140 geni_se_abort_m_cmd(se); 141 spin_unlock_irq(&mas->lock); 142 143 time_left = wait_for_completion_timeout(&mas->abort_done, HZ); 144 if (!time_left) 145 dev_err(mas->dev, "Failed to cancel/abort m_cmd\n"); 146 } 147 148 static void spi_geni_set_cs(struct spi_device *slv, bool set_flag) 149 { 150 struct spi_geni_master *mas = spi_master_get_devdata(slv->master); 151 struct spi_master *spi = dev_get_drvdata(mas->dev); 152 struct geni_se *se = &mas->se; 153 unsigned long time_left; 154 155 if (!(slv->mode & SPI_CS_HIGH)) 156 set_flag = !set_flag; 157 158 if (set_flag == mas->cs_flag) 159 return; 160 161 mas->cs_flag = set_flag; 162 163 pm_runtime_get_sync(mas->dev); 164 spin_lock_irq(&mas->lock); 165 reinit_completion(&mas->cs_done); 166 if (set_flag) 167 geni_se_setup_m_cmd(se, SPI_CS_ASSERT, 0); 168 else 169 geni_se_setup_m_cmd(se, SPI_CS_DEASSERT, 0); 170 spin_unlock_irq(&mas->lock); 171 172 time_left = wait_for_completion_timeout(&mas->cs_done, HZ); 173 if (!time_left) 174 handle_fifo_timeout(spi, NULL); 175 176 pm_runtime_put(mas->dev); 177 } 178 179 static void spi_setup_word_len(struct spi_geni_master *mas, u16 mode, 180 unsigned int bits_per_word) 181 { 182 unsigned int pack_words; 183 bool msb_first = (mode & SPI_LSB_FIRST) ? false : true; 184 struct geni_se *se = &mas->se; 185 u32 word_len; 186 187 /* 188 * If bits_per_word isn't a byte aligned value, set the packing to be 189 * 1 SPI word per FIFO word. 190 */ 191 if (!(mas->fifo_width_bits % bits_per_word)) 192 pack_words = mas->fifo_width_bits / bits_per_word; 193 else 194 pack_words = 1; 195 geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first, 196 true, true); 197 word_len = (bits_per_word - MIN_WORD_LEN) & WORD_LEN_MSK; 198 writel(word_len, se->base + SE_SPI_WORD_LEN); 199 } 200 201 static int geni_spi_set_clock_and_bw(struct spi_geni_master *mas, 202 unsigned long clk_hz) 203 { 204 u32 clk_sel, m_clk_cfg, idx, div; 205 struct geni_se *se = &mas->se; 206 int ret; 207 208 if (clk_hz == mas->cur_speed_hz) 209 return 0; 210 211 ret = get_spi_clk_cfg(clk_hz, mas, &idx, &div); 212 if (ret) { 213 dev_err(mas->dev, "Err setting clk to %lu: %d\n", clk_hz, ret); 214 return ret; 215 } 216 217 /* 218 * SPI core clock gets configured with the requested frequency 219 * or the frequency closer to the requested frequency. 220 * For that reason requested frequency is stored in the 221 * cur_speed_hz and referred in the consecutive transfer instead 222 * of calling clk_get_rate() API. 223 */ 224 mas->cur_speed_hz = clk_hz; 225 226 clk_sel = idx & CLK_SEL_MSK; 227 m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN; 228 writel(clk_sel, se->base + SE_GENI_CLK_SEL); 229 writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG); 230 231 /* Set BW quota for CPU as driver supports FIFO mode only. */ 232 se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz); 233 ret = geni_icc_set_bw(se); 234 if (ret) 235 return ret; 236 237 return 0; 238 } 239 240 static int setup_fifo_params(struct spi_device *spi_slv, 241 struct spi_master *spi) 242 { 243 struct spi_geni_master *mas = spi_master_get_devdata(spi); 244 struct geni_se *se = &mas->se; 245 u32 loopback_cfg = 0, cpol = 0, cpha = 0, demux_output_inv = 0; 246 u32 demux_sel; 247 248 if (mas->last_mode != spi_slv->mode) { 249 if (spi_slv->mode & SPI_LOOP) 250 loopback_cfg = LOOPBACK_ENABLE; 251 252 if (spi_slv->mode & SPI_CPOL) 253 cpol = CPOL; 254 255 if (spi_slv->mode & SPI_CPHA) 256 cpha = CPHA; 257 258 if (spi_slv->mode & SPI_CS_HIGH) 259 demux_output_inv = BIT(spi_slv->chip_select); 260 261 demux_sel = spi_slv->chip_select; 262 mas->cur_bits_per_word = spi_slv->bits_per_word; 263 264 spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word); 265 writel(loopback_cfg, se->base + SE_SPI_LOOPBACK); 266 writel(demux_sel, se->base + SE_SPI_DEMUX_SEL); 267 writel(cpha, se->base + SE_SPI_CPHA); 268 writel(cpol, se->base + SE_SPI_CPOL); 269 writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV); 270 271 mas->last_mode = spi_slv->mode; 272 } 273 274 return geni_spi_set_clock_and_bw(mas, spi_slv->max_speed_hz); 275 } 276 277 static int spi_geni_prepare_message(struct spi_master *spi, 278 struct spi_message *spi_msg) 279 { 280 int ret; 281 struct spi_geni_master *mas = spi_master_get_devdata(spi); 282 283 ret = setup_fifo_params(spi_msg->spi, spi); 284 if (ret) 285 dev_err(mas->dev, "Couldn't select mode %d\n", ret); 286 return ret; 287 } 288 289 static int spi_geni_init(struct spi_geni_master *mas) 290 { 291 struct geni_se *se = &mas->se; 292 unsigned int proto, major, minor, ver; 293 294 pm_runtime_get_sync(mas->dev); 295 296 proto = geni_se_read_proto(se); 297 if (proto != GENI_SE_SPI) { 298 dev_err(mas->dev, "Invalid proto %d\n", proto); 299 pm_runtime_put(mas->dev); 300 return -ENXIO; 301 } 302 mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se); 303 304 /* Width of Tx and Rx FIFO is same */ 305 mas->fifo_width_bits = geni_se_get_tx_fifo_width(se); 306 307 /* 308 * Hardware programming guide suggests to configure 309 * RX FIFO RFR level to fifo_depth-2. 310 */ 311 geni_se_init(se, mas->tx_fifo_depth / 2, mas->tx_fifo_depth - 2); 312 /* Transmit an entire FIFO worth of data per IRQ */ 313 mas->tx_wm = 1; 314 ver = geni_se_get_qup_hw_version(se); 315 major = GENI_SE_VERSION_MAJOR(ver); 316 minor = GENI_SE_VERSION_MINOR(ver); 317 318 if (major == 1 && minor == 0) 319 mas->oversampling = 2; 320 else 321 mas->oversampling = 1; 322 323 geni_se_select_mode(se, GENI_SE_FIFO); 324 325 pm_runtime_put(mas->dev); 326 return 0; 327 } 328 329 static void setup_fifo_xfer(struct spi_transfer *xfer, 330 struct spi_geni_master *mas, 331 u16 mode, struct spi_master *spi) 332 { 333 u32 m_cmd = 0; 334 u32 spi_tx_cfg, len; 335 struct geni_se *se = &mas->se; 336 int ret; 337 338 /* 339 * Ensure that our interrupt handler isn't still running from some 340 * prior command before we start messing with the hardware behind 341 * its back. We don't need to _keep_ the lock here since we're only 342 * worried about racing with out interrupt handler. The SPI core 343 * already handles making sure that we're not trying to do two 344 * transfers at once or setting a chip select and doing a transfer 345 * concurrently. 346 * 347 * NOTE: we actually _can't_ hold the lock here because possibly we 348 * might call clk_set_rate() which needs to be able to sleep. 349 */ 350 spin_lock_irq(&mas->lock); 351 spin_unlock_irq(&mas->lock); 352 353 spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG); 354 if (xfer->bits_per_word != mas->cur_bits_per_word) { 355 spi_setup_word_len(mas, mode, xfer->bits_per_word); 356 mas->cur_bits_per_word = xfer->bits_per_word; 357 } 358 359 /* Speed and bits per word can be overridden per transfer */ 360 ret = geni_spi_set_clock_and_bw(mas, xfer->speed_hz); 361 if (ret) 362 return; 363 364 mas->tx_rem_bytes = 0; 365 mas->rx_rem_bytes = 0; 366 367 spi_tx_cfg &= ~CS_TOGGLE; 368 369 if (!(mas->cur_bits_per_word % MIN_WORD_LEN)) 370 len = xfer->len * BITS_PER_BYTE / mas->cur_bits_per_word; 371 else 372 len = xfer->len / (mas->cur_bits_per_word / BITS_PER_BYTE + 1); 373 len &= TRANS_LEN_MSK; 374 375 mas->cur_xfer = xfer; 376 if (xfer->tx_buf) { 377 m_cmd |= SPI_TX_ONLY; 378 mas->tx_rem_bytes = xfer->len; 379 writel(len, se->base + SE_SPI_TX_TRANS_LEN); 380 } 381 382 if (xfer->rx_buf) { 383 m_cmd |= SPI_RX_ONLY; 384 writel(len, se->base + SE_SPI_RX_TRANS_LEN); 385 mas->rx_rem_bytes = xfer->len; 386 } 387 writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG); 388 389 /* 390 * Lock around right before we start the transfer since our 391 * interrupt could come in at any time now. 392 */ 393 spin_lock_irq(&mas->lock); 394 geni_se_setup_m_cmd(se, m_cmd, FRAGMENTATION); 395 396 /* 397 * TX_WATERMARK_REG should be set after SPI configuration and 398 * setting up GENI SE engine, as driver starts data transfer 399 * for the watermark interrupt. 400 */ 401 if (m_cmd & SPI_TX_ONLY) 402 writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG); 403 spin_unlock_irq(&mas->lock); 404 } 405 406 static int spi_geni_transfer_one(struct spi_master *spi, 407 struct spi_device *slv, 408 struct spi_transfer *xfer) 409 { 410 struct spi_geni_master *mas = spi_master_get_devdata(spi); 411 412 /* Terminate and return success for 0 byte length transfer */ 413 if (!xfer->len) 414 return 0; 415 416 setup_fifo_xfer(xfer, mas, slv->mode, spi); 417 return 1; 418 } 419 420 static unsigned int geni_byte_per_fifo_word(struct spi_geni_master *mas) 421 { 422 /* 423 * Calculate how many bytes we'll put in each FIFO word. If the 424 * transfer words don't pack cleanly into a FIFO word we'll just put 425 * one transfer word in each FIFO word. If they do pack we'll pack 'em. 426 */ 427 if (mas->fifo_width_bits % mas->cur_bits_per_word) 428 return roundup_pow_of_two(DIV_ROUND_UP(mas->cur_bits_per_word, 429 BITS_PER_BYTE)); 430 431 return mas->fifo_width_bits / BITS_PER_BYTE; 432 } 433 434 static void geni_spi_handle_tx(struct spi_geni_master *mas) 435 { 436 struct geni_se *se = &mas->se; 437 unsigned int max_bytes; 438 const u8 *tx_buf; 439 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas); 440 unsigned int i = 0; 441 442 max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * bytes_per_fifo_word; 443 if (mas->tx_rem_bytes < max_bytes) 444 max_bytes = mas->tx_rem_bytes; 445 446 tx_buf = mas->cur_xfer->tx_buf + mas->cur_xfer->len - mas->tx_rem_bytes; 447 while (i < max_bytes) { 448 unsigned int j; 449 unsigned int bytes_to_write; 450 u32 fifo_word = 0; 451 u8 *fifo_byte = (u8 *)&fifo_word; 452 453 bytes_to_write = min(bytes_per_fifo_word, max_bytes - i); 454 for (j = 0; j < bytes_to_write; j++) 455 fifo_byte[j] = tx_buf[i++]; 456 iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1); 457 } 458 mas->tx_rem_bytes -= max_bytes; 459 if (!mas->tx_rem_bytes) 460 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 461 } 462 463 static void geni_spi_handle_rx(struct spi_geni_master *mas) 464 { 465 struct geni_se *se = &mas->se; 466 u32 rx_fifo_status; 467 unsigned int rx_bytes; 468 unsigned int rx_last_byte_valid; 469 u8 *rx_buf; 470 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas); 471 unsigned int i = 0; 472 473 rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS); 474 rx_bytes = (rx_fifo_status & RX_FIFO_WC_MSK) * bytes_per_fifo_word; 475 if (rx_fifo_status & RX_LAST) { 476 rx_last_byte_valid = rx_fifo_status & RX_LAST_BYTE_VALID_MSK; 477 rx_last_byte_valid >>= RX_LAST_BYTE_VALID_SHFT; 478 if (rx_last_byte_valid && rx_last_byte_valid < 4) 479 rx_bytes -= bytes_per_fifo_word - rx_last_byte_valid; 480 } 481 if (mas->rx_rem_bytes < rx_bytes) 482 rx_bytes = mas->rx_rem_bytes; 483 484 rx_buf = mas->cur_xfer->rx_buf + mas->cur_xfer->len - mas->rx_rem_bytes; 485 while (i < rx_bytes) { 486 u32 fifo_word = 0; 487 u8 *fifo_byte = (u8 *)&fifo_word; 488 unsigned int bytes_to_read; 489 unsigned int j; 490 491 bytes_to_read = min(bytes_per_fifo_word, rx_bytes - i); 492 ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1); 493 for (j = 0; j < bytes_to_read; j++) 494 rx_buf[i++] = fifo_byte[j]; 495 } 496 mas->rx_rem_bytes -= rx_bytes; 497 } 498 499 static irqreturn_t geni_spi_isr(int irq, void *data) 500 { 501 struct spi_master *spi = data; 502 struct spi_geni_master *mas = spi_master_get_devdata(spi); 503 struct geni_se *se = &mas->se; 504 u32 m_irq; 505 506 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); 507 if (!m_irq) 508 return IRQ_NONE; 509 510 if (m_irq & (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN | 511 M_RX_FIFO_RD_ERR_EN | M_RX_FIFO_WR_ERR_EN | 512 M_TX_FIFO_RD_ERR_EN | M_TX_FIFO_WR_ERR_EN)) 513 dev_warn(mas->dev, "Unexpected IRQ err status %#010x\n", m_irq); 514 515 spin_lock(&mas->lock); 516 517 if ((m_irq & M_RX_FIFO_WATERMARK_EN) || (m_irq & M_RX_FIFO_LAST_EN)) 518 geni_spi_handle_rx(mas); 519 520 if (m_irq & M_TX_FIFO_WATERMARK_EN) 521 geni_spi_handle_tx(mas); 522 523 if (m_irq & M_CMD_DONE_EN) { 524 if (mas->cur_xfer) { 525 spi_finalize_current_transfer(spi); 526 mas->cur_xfer = NULL; 527 /* 528 * If this happens, then a CMD_DONE came before all the 529 * Tx buffer bytes were sent out. This is unusual, log 530 * this condition and disable the WM interrupt to 531 * prevent the system from stalling due an interrupt 532 * storm. 533 * 534 * If this happens when all Rx bytes haven't been 535 * received, log the condition. The only known time 536 * this can happen is if bits_per_word != 8 and some 537 * registers that expect xfer lengths in num spi_words 538 * weren't written correctly. 539 */ 540 if (mas->tx_rem_bytes) { 541 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 542 dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n", 543 mas->tx_rem_bytes, mas->cur_bits_per_word); 544 } 545 if (mas->rx_rem_bytes) 546 dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n", 547 mas->rx_rem_bytes, mas->cur_bits_per_word); 548 } else { 549 complete(&mas->cs_done); 550 } 551 } 552 553 if (m_irq & M_CMD_CANCEL_EN) 554 complete(&mas->cancel_done); 555 if (m_irq & M_CMD_ABORT_EN) 556 complete(&mas->abort_done); 557 558 /* 559 * It's safe or a good idea to Ack all of our our interrupts at the 560 * end of the function. Specifically: 561 * - M_CMD_DONE_EN / M_RX_FIFO_LAST_EN: Edge triggered interrupts and 562 * clearing Acks. Clearing at the end relies on nobody else having 563 * started a new transfer yet or else we could be clearing _their_ 564 * done bit, but everyone grabs the spinlock before starting a new 565 * transfer. 566 * - M_RX_FIFO_WATERMARK_EN / M_TX_FIFO_WATERMARK_EN: These appear 567 * to be "latched level" interrupts so it's important to clear them 568 * _after_ you've handled the condition and always safe to do so 569 * since they'll re-assert if they're still happening. 570 */ 571 writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR); 572 573 spin_unlock(&mas->lock); 574 575 return IRQ_HANDLED; 576 } 577 578 static int spi_geni_probe(struct platform_device *pdev) 579 { 580 int ret, irq; 581 struct spi_master *spi; 582 struct spi_geni_master *mas; 583 void __iomem *base; 584 struct clk *clk; 585 struct device *dev = &pdev->dev; 586 587 irq = platform_get_irq(pdev, 0); 588 if (irq < 0) 589 return irq; 590 591 base = devm_platform_ioremap_resource(pdev, 0); 592 if (IS_ERR(base)) 593 return PTR_ERR(base); 594 595 clk = devm_clk_get(dev, "se"); 596 if (IS_ERR(clk)) 597 return PTR_ERR(clk); 598 599 spi = spi_alloc_master(dev, sizeof(*mas)); 600 if (!spi) 601 return -ENOMEM; 602 603 platform_set_drvdata(pdev, spi); 604 mas = spi_master_get_devdata(spi); 605 mas->irq = irq; 606 mas->dev = dev; 607 mas->se.dev = dev; 608 mas->se.wrapper = dev_get_drvdata(dev->parent); 609 mas->se.base = base; 610 mas->se.clk = clk; 611 mas->se.opp_table = dev_pm_opp_set_clkname(&pdev->dev, "se"); 612 if (IS_ERR(mas->se.opp_table)) 613 return PTR_ERR(mas->se.opp_table); 614 /* OPP table is optional */ 615 ret = dev_pm_opp_of_add_table(&pdev->dev); 616 if (!ret) { 617 mas->se.has_opp_table = true; 618 } else if (ret != -ENODEV) { 619 dev_err(&pdev->dev, "invalid OPP table in device tree\n"); 620 return ret; 621 } 622 623 spi->bus_num = -1; 624 spi->dev.of_node = dev->of_node; 625 spi->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH; 626 spi->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 627 spi->num_chipselect = 4; 628 spi->max_speed_hz = 50000000; 629 spi->prepare_message = spi_geni_prepare_message; 630 spi->transfer_one = spi_geni_transfer_one; 631 spi->auto_runtime_pm = true; 632 spi->handle_err = handle_fifo_timeout; 633 spi->set_cs = spi_geni_set_cs; 634 635 init_completion(&mas->cs_done); 636 init_completion(&mas->cancel_done); 637 init_completion(&mas->abort_done); 638 spin_lock_init(&mas->lock); 639 pm_runtime_use_autosuspend(&pdev->dev); 640 pm_runtime_set_autosuspend_delay(&pdev->dev, 250); 641 pm_runtime_enable(dev); 642 643 ret = geni_icc_get(&mas->se, NULL); 644 if (ret) 645 goto spi_geni_probe_runtime_disable; 646 /* Set the bus quota to a reasonable value for register access */ 647 mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ); 648 mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; 649 650 ret = geni_icc_set_bw(&mas->se); 651 if (ret) 652 goto spi_geni_probe_runtime_disable; 653 654 ret = spi_geni_init(mas); 655 if (ret) 656 goto spi_geni_probe_runtime_disable; 657 658 ret = request_irq(mas->irq, geni_spi_isr, 0, dev_name(dev), spi); 659 if (ret) 660 goto spi_geni_probe_runtime_disable; 661 662 ret = spi_register_master(spi); 663 if (ret) 664 goto spi_geni_probe_free_irq; 665 666 return 0; 667 spi_geni_probe_free_irq: 668 free_irq(mas->irq, spi); 669 spi_geni_probe_runtime_disable: 670 pm_runtime_disable(dev); 671 spi_master_put(spi); 672 if (mas->se.has_opp_table) 673 dev_pm_opp_of_remove_table(&pdev->dev); 674 dev_pm_opp_put_clkname(mas->se.opp_table); 675 return ret; 676 } 677 678 static int spi_geni_remove(struct platform_device *pdev) 679 { 680 struct spi_master *spi = platform_get_drvdata(pdev); 681 struct spi_geni_master *mas = spi_master_get_devdata(spi); 682 683 /* Unregister _before_ disabling pm_runtime() so we stop transfers */ 684 spi_unregister_master(spi); 685 686 free_irq(mas->irq, spi); 687 pm_runtime_disable(&pdev->dev); 688 if (mas->se.has_opp_table) 689 dev_pm_opp_of_remove_table(&pdev->dev); 690 dev_pm_opp_put_clkname(mas->se.opp_table); 691 return 0; 692 } 693 694 static int __maybe_unused spi_geni_runtime_suspend(struct device *dev) 695 { 696 struct spi_master *spi = dev_get_drvdata(dev); 697 struct spi_geni_master *mas = spi_master_get_devdata(spi); 698 int ret; 699 700 /* Drop the performance state vote */ 701 dev_pm_opp_set_rate(dev, 0); 702 703 ret = geni_se_resources_off(&mas->se); 704 if (ret) 705 return ret; 706 707 return geni_icc_disable(&mas->se); 708 } 709 710 static int __maybe_unused spi_geni_runtime_resume(struct device *dev) 711 { 712 struct spi_master *spi = dev_get_drvdata(dev); 713 struct spi_geni_master *mas = spi_master_get_devdata(spi); 714 int ret; 715 716 ret = geni_icc_enable(&mas->se); 717 if (ret) 718 return ret; 719 720 ret = geni_se_resources_on(&mas->se); 721 if (ret) 722 return ret; 723 724 return dev_pm_opp_set_rate(mas->dev, mas->cur_sclk_hz); 725 } 726 727 static int __maybe_unused spi_geni_suspend(struct device *dev) 728 { 729 struct spi_master *spi = dev_get_drvdata(dev); 730 int ret; 731 732 ret = spi_master_suspend(spi); 733 if (ret) 734 return ret; 735 736 ret = pm_runtime_force_suspend(dev); 737 if (ret) 738 spi_master_resume(spi); 739 740 return ret; 741 } 742 743 static int __maybe_unused spi_geni_resume(struct device *dev) 744 { 745 struct spi_master *spi = dev_get_drvdata(dev); 746 int ret; 747 748 ret = pm_runtime_force_resume(dev); 749 if (ret) 750 return ret; 751 752 ret = spi_master_resume(spi); 753 if (ret) 754 pm_runtime_force_suspend(dev); 755 756 return ret; 757 } 758 759 static const struct dev_pm_ops spi_geni_pm_ops = { 760 SET_RUNTIME_PM_OPS(spi_geni_runtime_suspend, 761 spi_geni_runtime_resume, NULL) 762 SET_SYSTEM_SLEEP_PM_OPS(spi_geni_suspend, spi_geni_resume) 763 }; 764 765 static const struct of_device_id spi_geni_dt_match[] = { 766 { .compatible = "qcom,geni-spi" }, 767 {} 768 }; 769 MODULE_DEVICE_TABLE(of, spi_geni_dt_match); 770 771 static struct platform_driver spi_geni_driver = { 772 .probe = spi_geni_probe, 773 .remove = spi_geni_remove, 774 .driver = { 775 .name = "geni_spi", 776 .pm = &spi_geni_pm_ops, 777 .of_match_table = spi_geni_dt_match, 778 }, 779 }; 780 module_platform_driver(spi_geni_driver); 781 782 MODULE_DESCRIPTION("SPI driver for GENI based QUP cores"); 783 MODULE_LICENSE("GPL v2"); 784