1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved. 3 4 #include <linux/clk.h> 5 #include <linux/dmaengine.h> 6 #include <linux/dma-mapping.h> 7 #include <linux/dma/qcom-gpi-dma.h> 8 #include <linux/interrupt.h> 9 #include <linux/io.h> 10 #include <linux/log2.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm_opp.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/soc/qcom/geni-se.h> 16 #include <linux/spi/spi.h> 17 #include <linux/spinlock.h> 18 19 /* SPI SE specific registers and respective register fields */ 20 #define SE_SPI_CPHA 0x224 21 #define CPHA BIT(0) 22 23 #define SE_SPI_LOOPBACK 0x22c 24 #define LOOPBACK_ENABLE 0x1 25 #define NORMAL_MODE 0x0 26 #define LOOPBACK_MSK GENMASK(1, 0) 27 28 #define SE_SPI_CPOL 0x230 29 #define CPOL BIT(2) 30 31 #define SE_SPI_DEMUX_OUTPUT_INV 0x24c 32 #define CS_DEMUX_OUTPUT_INV_MSK GENMASK(3, 0) 33 34 #define SE_SPI_DEMUX_SEL 0x250 35 #define CS_DEMUX_OUTPUT_SEL GENMASK(3, 0) 36 37 #define SE_SPI_TRANS_CFG 0x25c 38 #define CS_TOGGLE BIT(1) 39 40 #define SE_SPI_WORD_LEN 0x268 41 #define WORD_LEN_MSK GENMASK(9, 0) 42 #define MIN_WORD_LEN 4 43 44 #define SE_SPI_TX_TRANS_LEN 0x26c 45 #define SE_SPI_RX_TRANS_LEN 0x270 46 #define TRANS_LEN_MSK GENMASK(23, 0) 47 48 #define SE_SPI_PRE_POST_CMD_DLY 0x274 49 50 #define SE_SPI_DELAY_COUNTERS 0x278 51 #define SPI_INTER_WORDS_DELAY_MSK GENMASK(9, 0) 52 #define SPI_CS_CLK_DELAY_MSK GENMASK(19, 10) 53 #define SPI_CS_CLK_DELAY_SHFT 10 54 55 /* M_CMD OP codes for SPI */ 56 #define SPI_TX_ONLY 1 57 #define SPI_RX_ONLY 2 58 #define SPI_TX_RX 7 59 #define SPI_CS_ASSERT 8 60 #define SPI_CS_DEASSERT 9 61 #define SPI_SCK_ONLY 10 62 /* M_CMD params for SPI */ 63 #define SPI_PRE_CMD_DELAY BIT(0) 64 #define TIMESTAMP_BEFORE BIT(1) 65 #define FRAGMENTATION BIT(2) 66 #define TIMESTAMP_AFTER BIT(3) 67 #define POST_CMD_DELAY BIT(4) 68 69 #define GSI_LOOPBACK_EN BIT(0) 70 #define GSI_CS_TOGGLE BIT(3) 71 #define GSI_CPHA BIT(4) 72 #define GSI_CPOL BIT(5) 73 74 struct spi_geni_master { 75 struct geni_se se; 76 struct device *dev; 77 u32 tx_fifo_depth; 78 u32 fifo_width_bits; 79 u32 tx_wm; 80 u32 last_mode; 81 unsigned long cur_speed_hz; 82 unsigned long cur_sclk_hz; 83 unsigned int cur_bits_per_word; 84 unsigned int tx_rem_bytes; 85 unsigned int rx_rem_bytes; 86 const struct spi_transfer *cur_xfer; 87 struct completion cs_done; 88 struct completion cancel_done; 89 struct completion abort_done; 90 struct completion tx_reset_done; 91 struct completion rx_reset_done; 92 unsigned int oversampling; 93 spinlock_t lock; 94 int irq; 95 bool cs_flag; 96 bool abort_failed; 97 struct dma_chan *tx; 98 struct dma_chan *rx; 99 int cur_xfer_mode; 100 }; 101 102 static int get_spi_clk_cfg(unsigned int speed_hz, 103 struct spi_geni_master *mas, 104 unsigned int *clk_idx, 105 unsigned int *clk_div) 106 { 107 unsigned long sclk_freq; 108 unsigned int actual_hz; 109 int ret; 110 111 ret = geni_se_clk_freq_match(&mas->se, 112 speed_hz * mas->oversampling, 113 clk_idx, &sclk_freq, false); 114 if (ret) { 115 dev_err(mas->dev, "Failed(%d) to find src clk for %dHz\n", 116 ret, speed_hz); 117 return ret; 118 } 119 120 *clk_div = DIV_ROUND_UP(sclk_freq, mas->oversampling * speed_hz); 121 actual_hz = sclk_freq / (mas->oversampling * *clk_div); 122 123 dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz, 124 actual_hz, sclk_freq, *clk_idx, *clk_div); 125 ret = dev_pm_opp_set_rate(mas->dev, sclk_freq); 126 if (ret) 127 dev_err(mas->dev, "dev_pm_opp_set_rate failed %d\n", ret); 128 else 129 mas->cur_sclk_hz = sclk_freq; 130 131 return ret; 132 } 133 134 static void handle_se_timeout(struct spi_master *spi, 135 struct spi_message *msg) 136 { 137 struct spi_geni_master *mas = spi_master_get_devdata(spi); 138 unsigned long time_left; 139 struct geni_se *se = &mas->se; 140 const struct spi_transfer *xfer; 141 142 spin_lock_irq(&mas->lock); 143 reinit_completion(&mas->cancel_done); 144 if (mas->cur_xfer_mode == GENI_SE_FIFO) 145 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 146 147 xfer = mas->cur_xfer; 148 mas->cur_xfer = NULL; 149 geni_se_cancel_m_cmd(se); 150 spin_unlock_irq(&mas->lock); 151 152 time_left = wait_for_completion_timeout(&mas->cancel_done, HZ); 153 if (time_left) 154 goto unmap_if_dma; 155 156 spin_lock_irq(&mas->lock); 157 reinit_completion(&mas->abort_done); 158 geni_se_abort_m_cmd(se); 159 spin_unlock_irq(&mas->lock); 160 161 time_left = wait_for_completion_timeout(&mas->abort_done, HZ); 162 if (!time_left) { 163 dev_err(mas->dev, "Failed to cancel/abort m_cmd\n"); 164 165 /* 166 * No need for a lock since SPI core has a lock and we never 167 * access this from an interrupt. 168 */ 169 mas->abort_failed = true; 170 } 171 172 unmap_if_dma: 173 if (mas->cur_xfer_mode == GENI_SE_DMA) { 174 if (xfer) { 175 if (xfer->tx_buf) { 176 spin_lock_irq(&mas->lock); 177 reinit_completion(&mas->tx_reset_done); 178 writel(1, se->base + SE_DMA_TX_FSM_RST); 179 spin_unlock_irq(&mas->lock); 180 time_left = wait_for_completion_timeout(&mas->tx_reset_done, HZ); 181 if (!time_left) 182 dev_err(mas->dev, "DMA TX RESET failed\n"); 183 } 184 if (xfer->rx_buf) { 185 spin_lock_irq(&mas->lock); 186 reinit_completion(&mas->rx_reset_done); 187 writel(1, se->base + SE_DMA_RX_FSM_RST); 188 spin_unlock_irq(&mas->lock); 189 time_left = wait_for_completion_timeout(&mas->rx_reset_done, HZ); 190 if (!time_left) 191 dev_err(mas->dev, "DMA RX RESET failed\n"); 192 } 193 } else { 194 /* 195 * This can happen if a timeout happened and we had to wait 196 * for lock in this function because isr was holding the lock 197 * and handling transfer completion at that time. 198 */ 199 dev_warn(mas->dev, "Cancel/Abort on completed SPI transfer\n"); 200 } 201 } 202 } 203 204 static void handle_gpi_timeout(struct spi_master *spi, struct spi_message *msg) 205 { 206 struct spi_geni_master *mas = spi_master_get_devdata(spi); 207 208 dmaengine_terminate_sync(mas->tx); 209 dmaengine_terminate_sync(mas->rx); 210 } 211 212 static void spi_geni_handle_err(struct spi_master *spi, struct spi_message *msg) 213 { 214 struct spi_geni_master *mas = spi_master_get_devdata(spi); 215 216 switch (mas->cur_xfer_mode) { 217 case GENI_SE_FIFO: 218 case GENI_SE_DMA: 219 handle_se_timeout(spi, msg); 220 break; 221 case GENI_GPI_DMA: 222 handle_gpi_timeout(spi, msg); 223 break; 224 default: 225 dev_err(mas->dev, "Abort on Mode:%d not supported", mas->cur_xfer_mode); 226 } 227 } 228 229 static bool spi_geni_is_abort_still_pending(struct spi_geni_master *mas) 230 { 231 struct geni_se *se = &mas->se; 232 u32 m_irq, m_irq_en; 233 234 if (!mas->abort_failed) 235 return false; 236 237 /* 238 * The only known case where a transfer times out and then a cancel 239 * times out then an abort times out is if something is blocking our 240 * interrupt handler from running. Avoid starting any new transfers 241 * until that sorts itself out. 242 */ 243 spin_lock_irq(&mas->lock); 244 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); 245 m_irq_en = readl(se->base + SE_GENI_M_IRQ_EN); 246 spin_unlock_irq(&mas->lock); 247 248 if (m_irq & m_irq_en) { 249 dev_err(mas->dev, "Interrupts pending after abort: %#010x\n", 250 m_irq & m_irq_en); 251 return true; 252 } 253 254 /* 255 * If we're here the problem resolved itself so no need to check more 256 * on future transfers. 257 */ 258 mas->abort_failed = false; 259 260 return false; 261 } 262 263 static void spi_geni_set_cs(struct spi_device *slv, bool set_flag) 264 { 265 struct spi_geni_master *mas = spi_master_get_devdata(slv->master); 266 struct spi_master *spi = dev_get_drvdata(mas->dev); 267 struct geni_se *se = &mas->se; 268 unsigned long time_left; 269 270 if (!(slv->mode & SPI_CS_HIGH)) 271 set_flag = !set_flag; 272 273 if (set_flag == mas->cs_flag) 274 return; 275 276 pm_runtime_get_sync(mas->dev); 277 278 if (spi_geni_is_abort_still_pending(mas)) { 279 dev_err(mas->dev, "Can't set chip select\n"); 280 goto exit; 281 } 282 283 spin_lock_irq(&mas->lock); 284 if (mas->cur_xfer) { 285 dev_err(mas->dev, "Can't set CS when prev xfer running\n"); 286 spin_unlock_irq(&mas->lock); 287 goto exit; 288 } 289 290 mas->cs_flag = set_flag; 291 /* set xfer_mode to FIFO to complete cs_done in isr */ 292 mas->cur_xfer_mode = GENI_SE_FIFO; 293 geni_se_select_mode(se, mas->cur_xfer_mode); 294 295 reinit_completion(&mas->cs_done); 296 if (set_flag) 297 geni_se_setup_m_cmd(se, SPI_CS_ASSERT, 0); 298 else 299 geni_se_setup_m_cmd(se, SPI_CS_DEASSERT, 0); 300 spin_unlock_irq(&mas->lock); 301 302 time_left = wait_for_completion_timeout(&mas->cs_done, HZ); 303 if (!time_left) { 304 dev_warn(mas->dev, "Timeout setting chip select\n"); 305 handle_se_timeout(spi, NULL); 306 } 307 308 exit: 309 pm_runtime_put(mas->dev); 310 } 311 312 static void spi_setup_word_len(struct spi_geni_master *mas, u16 mode, 313 unsigned int bits_per_word) 314 { 315 unsigned int pack_words; 316 bool msb_first = (mode & SPI_LSB_FIRST) ? false : true; 317 struct geni_se *se = &mas->se; 318 u32 word_len; 319 320 /* 321 * If bits_per_word isn't a byte aligned value, set the packing to be 322 * 1 SPI word per FIFO word. 323 */ 324 if (!(mas->fifo_width_bits % bits_per_word)) 325 pack_words = mas->fifo_width_bits / bits_per_word; 326 else 327 pack_words = 1; 328 geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first, 329 true, true); 330 word_len = (bits_per_word - MIN_WORD_LEN) & WORD_LEN_MSK; 331 writel(word_len, se->base + SE_SPI_WORD_LEN); 332 } 333 334 static int geni_spi_set_clock_and_bw(struct spi_geni_master *mas, 335 unsigned long clk_hz) 336 { 337 u32 clk_sel, m_clk_cfg, idx, div; 338 struct geni_se *se = &mas->se; 339 int ret; 340 341 if (clk_hz == mas->cur_speed_hz) 342 return 0; 343 344 ret = get_spi_clk_cfg(clk_hz, mas, &idx, &div); 345 if (ret) { 346 dev_err(mas->dev, "Err setting clk to %lu: %d\n", clk_hz, ret); 347 return ret; 348 } 349 350 /* 351 * SPI core clock gets configured with the requested frequency 352 * or the frequency closer to the requested frequency. 353 * For that reason requested frequency is stored in the 354 * cur_speed_hz and referred in the consecutive transfer instead 355 * of calling clk_get_rate() API. 356 */ 357 mas->cur_speed_hz = clk_hz; 358 359 clk_sel = idx & CLK_SEL_MSK; 360 m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN; 361 writel(clk_sel, se->base + SE_GENI_CLK_SEL); 362 writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG); 363 364 /* Set BW quota for CPU as driver supports FIFO mode only. */ 365 se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz); 366 ret = geni_icc_set_bw(se); 367 if (ret) 368 return ret; 369 370 return 0; 371 } 372 373 static int setup_fifo_params(struct spi_device *spi_slv, 374 struct spi_master *spi) 375 { 376 struct spi_geni_master *mas = spi_master_get_devdata(spi); 377 struct geni_se *se = &mas->se; 378 u32 loopback_cfg = 0, cpol = 0, cpha = 0, demux_output_inv = 0; 379 u32 demux_sel; 380 381 if (mas->last_mode != spi_slv->mode) { 382 if (spi_slv->mode & SPI_LOOP) 383 loopback_cfg = LOOPBACK_ENABLE; 384 385 if (spi_slv->mode & SPI_CPOL) 386 cpol = CPOL; 387 388 if (spi_slv->mode & SPI_CPHA) 389 cpha = CPHA; 390 391 if (spi_slv->mode & SPI_CS_HIGH) 392 demux_output_inv = BIT(spi_get_chipselect(spi_slv, 0)); 393 394 demux_sel = spi_get_chipselect(spi_slv, 0); 395 mas->cur_bits_per_word = spi_slv->bits_per_word; 396 397 spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word); 398 writel(loopback_cfg, se->base + SE_SPI_LOOPBACK); 399 writel(demux_sel, se->base + SE_SPI_DEMUX_SEL); 400 writel(cpha, se->base + SE_SPI_CPHA); 401 writel(cpol, se->base + SE_SPI_CPOL); 402 writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV); 403 404 mas->last_mode = spi_slv->mode; 405 } 406 407 return geni_spi_set_clock_and_bw(mas, spi_slv->max_speed_hz); 408 } 409 410 static void 411 spi_gsi_callback_result(void *cb, const struct dmaengine_result *result) 412 { 413 struct spi_master *spi = cb; 414 415 spi->cur_msg->status = -EIO; 416 if (result->result != DMA_TRANS_NOERROR) { 417 dev_err(&spi->dev, "DMA txn failed: %d\n", result->result); 418 spi_finalize_current_transfer(spi); 419 return; 420 } 421 422 if (!result->residue) { 423 spi->cur_msg->status = 0; 424 dev_dbg(&spi->dev, "DMA txn completed\n"); 425 } else { 426 dev_err(&spi->dev, "DMA xfer has pending: %d\n", result->residue); 427 } 428 429 spi_finalize_current_transfer(spi); 430 } 431 432 static int setup_gsi_xfer(struct spi_transfer *xfer, struct spi_geni_master *mas, 433 struct spi_device *spi_slv, struct spi_master *spi) 434 { 435 unsigned long flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK; 436 struct dma_slave_config config = {}; 437 struct gpi_spi_config peripheral = {}; 438 struct dma_async_tx_descriptor *tx_desc, *rx_desc; 439 int ret; 440 441 config.peripheral_config = &peripheral; 442 config.peripheral_size = sizeof(peripheral); 443 peripheral.set_config = true; 444 445 if (xfer->bits_per_word != mas->cur_bits_per_word || 446 xfer->speed_hz != mas->cur_speed_hz) { 447 mas->cur_bits_per_word = xfer->bits_per_word; 448 mas->cur_speed_hz = xfer->speed_hz; 449 } 450 451 if (xfer->tx_buf && xfer->rx_buf) { 452 peripheral.cmd = SPI_DUPLEX; 453 } else if (xfer->tx_buf) { 454 peripheral.cmd = SPI_TX; 455 peripheral.rx_len = 0; 456 } else if (xfer->rx_buf) { 457 peripheral.cmd = SPI_RX; 458 if (!(mas->cur_bits_per_word % MIN_WORD_LEN)) { 459 peripheral.rx_len = ((xfer->len << 3) / mas->cur_bits_per_word); 460 } else { 461 int bytes_per_word = (mas->cur_bits_per_word / BITS_PER_BYTE) + 1; 462 463 peripheral.rx_len = (xfer->len / bytes_per_word); 464 } 465 } 466 467 peripheral.loopback_en = !!(spi_slv->mode & SPI_LOOP); 468 peripheral.clock_pol_high = !!(spi_slv->mode & SPI_CPOL); 469 peripheral.data_pol_high = !!(spi_slv->mode & SPI_CPHA); 470 peripheral.cs = spi_get_chipselect(spi_slv, 0); 471 peripheral.pack_en = true; 472 peripheral.word_len = xfer->bits_per_word - MIN_WORD_LEN; 473 474 ret = get_spi_clk_cfg(mas->cur_speed_hz, mas, 475 &peripheral.clk_src, &peripheral.clk_div); 476 if (ret) { 477 dev_err(mas->dev, "Err in get_spi_clk_cfg() :%d\n", ret); 478 return ret; 479 } 480 481 if (!xfer->cs_change) { 482 if (!list_is_last(&xfer->transfer_list, &spi->cur_msg->transfers)) 483 peripheral.fragmentation = FRAGMENTATION; 484 } 485 486 if (peripheral.cmd & SPI_RX) { 487 dmaengine_slave_config(mas->rx, &config); 488 rx_desc = dmaengine_prep_slave_sg(mas->rx, xfer->rx_sg.sgl, xfer->rx_sg.nents, 489 DMA_DEV_TO_MEM, flags); 490 if (!rx_desc) { 491 dev_err(mas->dev, "Err setting up rx desc\n"); 492 return -EIO; 493 } 494 } 495 496 /* 497 * Prepare the TX always, even for RX or tx_buf being null, we would 498 * need TX to be prepared per GSI spec 499 */ 500 dmaengine_slave_config(mas->tx, &config); 501 tx_desc = dmaengine_prep_slave_sg(mas->tx, xfer->tx_sg.sgl, xfer->tx_sg.nents, 502 DMA_MEM_TO_DEV, flags); 503 if (!tx_desc) { 504 dev_err(mas->dev, "Err setting up tx desc\n"); 505 return -EIO; 506 } 507 508 tx_desc->callback_result = spi_gsi_callback_result; 509 tx_desc->callback_param = spi; 510 511 if (peripheral.cmd & SPI_RX) 512 dmaengine_submit(rx_desc); 513 dmaengine_submit(tx_desc); 514 515 if (peripheral.cmd & SPI_RX) 516 dma_async_issue_pending(mas->rx); 517 518 dma_async_issue_pending(mas->tx); 519 return 1; 520 } 521 522 static u32 get_xfer_len_in_words(struct spi_transfer *xfer, 523 struct spi_geni_master *mas) 524 { 525 u32 len; 526 527 if (!(mas->cur_bits_per_word % MIN_WORD_LEN)) 528 len = xfer->len * BITS_PER_BYTE / mas->cur_bits_per_word; 529 else 530 len = xfer->len / (mas->cur_bits_per_word / BITS_PER_BYTE + 1); 531 len &= TRANS_LEN_MSK; 532 533 return len; 534 } 535 536 static bool geni_can_dma(struct spi_controller *ctlr, 537 struct spi_device *slv, struct spi_transfer *xfer) 538 { 539 struct spi_geni_master *mas = spi_master_get_devdata(slv->master); 540 u32 len, fifo_size; 541 542 if (mas->cur_xfer_mode == GENI_GPI_DMA) 543 return true; 544 545 len = get_xfer_len_in_words(xfer, mas); 546 fifo_size = mas->tx_fifo_depth * mas->fifo_width_bits / mas->cur_bits_per_word; 547 548 if (len > fifo_size) 549 return true; 550 else 551 return false; 552 } 553 554 static int spi_geni_prepare_message(struct spi_master *spi, 555 struct spi_message *spi_msg) 556 { 557 struct spi_geni_master *mas = spi_master_get_devdata(spi); 558 int ret; 559 560 switch (mas->cur_xfer_mode) { 561 case GENI_SE_FIFO: 562 case GENI_SE_DMA: 563 if (spi_geni_is_abort_still_pending(mas)) 564 return -EBUSY; 565 ret = setup_fifo_params(spi_msg->spi, spi); 566 if (ret) 567 dev_err(mas->dev, "Couldn't select mode %d\n", ret); 568 return ret; 569 570 case GENI_GPI_DMA: 571 /* nothing to do for GPI DMA */ 572 return 0; 573 } 574 575 dev_err(mas->dev, "Mode not supported %d", mas->cur_xfer_mode); 576 return -EINVAL; 577 } 578 579 static int spi_geni_grab_gpi_chan(struct spi_geni_master *mas) 580 { 581 int ret; 582 583 mas->tx = dma_request_chan(mas->dev, "tx"); 584 if (IS_ERR(mas->tx)) { 585 ret = dev_err_probe(mas->dev, PTR_ERR(mas->tx), 586 "Failed to get tx DMA ch\n"); 587 goto err_tx; 588 } 589 590 mas->rx = dma_request_chan(mas->dev, "rx"); 591 if (IS_ERR(mas->rx)) { 592 ret = dev_err_probe(mas->dev, PTR_ERR(mas->rx), 593 "Failed to get rx DMA ch\n"); 594 goto err_rx; 595 } 596 597 return 0; 598 599 err_rx: 600 mas->rx = NULL; 601 dma_release_channel(mas->tx); 602 err_tx: 603 mas->tx = NULL; 604 return ret; 605 } 606 607 static void spi_geni_release_dma_chan(struct spi_geni_master *mas) 608 { 609 if (mas->rx) { 610 dma_release_channel(mas->rx); 611 mas->rx = NULL; 612 } 613 614 if (mas->tx) { 615 dma_release_channel(mas->tx); 616 mas->tx = NULL; 617 } 618 } 619 620 static int spi_geni_init(struct spi_geni_master *mas) 621 { 622 struct geni_se *se = &mas->se; 623 unsigned int proto, major, minor, ver; 624 u32 spi_tx_cfg, fifo_disable; 625 int ret = -ENXIO; 626 627 pm_runtime_get_sync(mas->dev); 628 629 proto = geni_se_read_proto(se); 630 if (proto != GENI_SE_SPI) { 631 dev_err(mas->dev, "Invalid proto %d\n", proto); 632 goto out_pm; 633 } 634 mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se); 635 636 /* Width of Tx and Rx FIFO is same */ 637 mas->fifo_width_bits = geni_se_get_tx_fifo_width(se); 638 639 /* 640 * Hardware programming guide suggests to configure 641 * RX FIFO RFR level to fifo_depth-2. 642 */ 643 geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2); 644 /* Transmit an entire FIFO worth of data per IRQ */ 645 mas->tx_wm = 1; 646 ver = geni_se_get_qup_hw_version(se); 647 major = GENI_SE_VERSION_MAJOR(ver); 648 minor = GENI_SE_VERSION_MINOR(ver); 649 650 if (major == 1 && minor == 0) 651 mas->oversampling = 2; 652 else 653 mas->oversampling = 1; 654 655 fifo_disable = readl(se->base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE; 656 switch (fifo_disable) { 657 case 1: 658 ret = spi_geni_grab_gpi_chan(mas); 659 if (!ret) { /* success case */ 660 mas->cur_xfer_mode = GENI_GPI_DMA; 661 geni_se_select_mode(se, GENI_GPI_DMA); 662 dev_dbg(mas->dev, "Using GPI DMA mode for SPI\n"); 663 break; 664 } else if (ret == -EPROBE_DEFER) { 665 goto out_pm; 666 } 667 /* 668 * in case of failure to get gpi dma channel, we can still do the 669 * FIFO mode, so fallthrough 670 */ 671 dev_warn(mas->dev, "FIFO mode disabled, but couldn't get DMA, fall back to FIFO mode\n"); 672 fallthrough; 673 674 case 0: 675 mas->cur_xfer_mode = GENI_SE_FIFO; 676 geni_se_select_mode(se, GENI_SE_FIFO); 677 ret = 0; 678 break; 679 } 680 681 /* We always control CS manually */ 682 spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG); 683 spi_tx_cfg &= ~CS_TOGGLE; 684 writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG); 685 686 out_pm: 687 pm_runtime_put(mas->dev); 688 return ret; 689 } 690 691 static unsigned int geni_byte_per_fifo_word(struct spi_geni_master *mas) 692 { 693 /* 694 * Calculate how many bytes we'll put in each FIFO word. If the 695 * transfer words don't pack cleanly into a FIFO word we'll just put 696 * one transfer word in each FIFO word. If they do pack we'll pack 'em. 697 */ 698 if (mas->fifo_width_bits % mas->cur_bits_per_word) 699 return roundup_pow_of_two(DIV_ROUND_UP(mas->cur_bits_per_word, 700 BITS_PER_BYTE)); 701 702 return mas->fifo_width_bits / BITS_PER_BYTE; 703 } 704 705 static bool geni_spi_handle_tx(struct spi_geni_master *mas) 706 { 707 struct geni_se *se = &mas->se; 708 unsigned int max_bytes; 709 const u8 *tx_buf; 710 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas); 711 unsigned int i = 0; 712 713 /* Stop the watermark IRQ if nothing to send */ 714 if (!mas->cur_xfer) { 715 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 716 return false; 717 } 718 719 max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * bytes_per_fifo_word; 720 if (mas->tx_rem_bytes < max_bytes) 721 max_bytes = mas->tx_rem_bytes; 722 723 tx_buf = mas->cur_xfer->tx_buf + mas->cur_xfer->len - mas->tx_rem_bytes; 724 while (i < max_bytes) { 725 unsigned int j; 726 unsigned int bytes_to_write; 727 u32 fifo_word = 0; 728 u8 *fifo_byte = (u8 *)&fifo_word; 729 730 bytes_to_write = min(bytes_per_fifo_word, max_bytes - i); 731 for (j = 0; j < bytes_to_write; j++) 732 fifo_byte[j] = tx_buf[i++]; 733 iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1); 734 } 735 mas->tx_rem_bytes -= max_bytes; 736 if (!mas->tx_rem_bytes) { 737 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 738 return false; 739 } 740 return true; 741 } 742 743 static void geni_spi_handle_rx(struct spi_geni_master *mas) 744 { 745 struct geni_se *se = &mas->se; 746 u32 rx_fifo_status; 747 unsigned int rx_bytes; 748 unsigned int rx_last_byte_valid; 749 u8 *rx_buf; 750 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas); 751 unsigned int i = 0; 752 753 rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS); 754 rx_bytes = (rx_fifo_status & RX_FIFO_WC_MSK) * bytes_per_fifo_word; 755 if (rx_fifo_status & RX_LAST) { 756 rx_last_byte_valid = rx_fifo_status & RX_LAST_BYTE_VALID_MSK; 757 rx_last_byte_valid >>= RX_LAST_BYTE_VALID_SHFT; 758 if (rx_last_byte_valid && rx_last_byte_valid < 4) 759 rx_bytes -= bytes_per_fifo_word - rx_last_byte_valid; 760 } 761 762 /* Clear out the FIFO and bail if nowhere to put it */ 763 if (!mas->cur_xfer) { 764 for (i = 0; i < DIV_ROUND_UP(rx_bytes, bytes_per_fifo_word); i++) 765 readl(se->base + SE_GENI_RX_FIFOn); 766 return; 767 } 768 769 if (mas->rx_rem_bytes < rx_bytes) 770 rx_bytes = mas->rx_rem_bytes; 771 772 rx_buf = mas->cur_xfer->rx_buf + mas->cur_xfer->len - mas->rx_rem_bytes; 773 while (i < rx_bytes) { 774 u32 fifo_word = 0; 775 u8 *fifo_byte = (u8 *)&fifo_word; 776 unsigned int bytes_to_read; 777 unsigned int j; 778 779 bytes_to_read = min(bytes_per_fifo_word, rx_bytes - i); 780 ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1); 781 for (j = 0; j < bytes_to_read; j++) 782 rx_buf[i++] = fifo_byte[j]; 783 } 784 mas->rx_rem_bytes -= rx_bytes; 785 } 786 787 static int setup_se_xfer(struct spi_transfer *xfer, 788 struct spi_geni_master *mas, 789 u16 mode, struct spi_master *spi) 790 { 791 u32 m_cmd = 0; 792 u32 len; 793 struct geni_se *se = &mas->se; 794 int ret; 795 796 /* 797 * Ensure that our interrupt handler isn't still running from some 798 * prior command before we start messing with the hardware behind 799 * its back. We don't need to _keep_ the lock here since we're only 800 * worried about racing with out interrupt handler. The SPI core 801 * already handles making sure that we're not trying to do two 802 * transfers at once or setting a chip select and doing a transfer 803 * concurrently. 804 * 805 * NOTE: we actually _can't_ hold the lock here because possibly we 806 * might call clk_set_rate() which needs to be able to sleep. 807 */ 808 spin_lock_irq(&mas->lock); 809 spin_unlock_irq(&mas->lock); 810 811 if (xfer->bits_per_word != mas->cur_bits_per_word) { 812 spi_setup_word_len(mas, mode, xfer->bits_per_word); 813 mas->cur_bits_per_word = xfer->bits_per_word; 814 } 815 816 /* Speed and bits per word can be overridden per transfer */ 817 ret = geni_spi_set_clock_and_bw(mas, xfer->speed_hz); 818 if (ret) 819 return ret; 820 821 mas->tx_rem_bytes = 0; 822 mas->rx_rem_bytes = 0; 823 824 len = get_xfer_len_in_words(xfer, mas); 825 826 mas->cur_xfer = xfer; 827 if (xfer->tx_buf) { 828 m_cmd |= SPI_TX_ONLY; 829 mas->tx_rem_bytes = xfer->len; 830 writel(len, se->base + SE_SPI_TX_TRANS_LEN); 831 } 832 833 if (xfer->rx_buf) { 834 m_cmd |= SPI_RX_ONLY; 835 writel(len, se->base + SE_SPI_RX_TRANS_LEN); 836 mas->rx_rem_bytes = xfer->len; 837 } 838 839 /* 840 * Select DMA mode if sgt are present; and with only 1 entry 841 * This is not a serious limitation because the xfer buffers are 842 * expected to fit into in 1 entry almost always, and if any 843 * doesn't for any reason we fall back to FIFO mode anyway 844 */ 845 if (!xfer->tx_sg.nents && !xfer->rx_sg.nents) 846 mas->cur_xfer_mode = GENI_SE_FIFO; 847 else if (xfer->tx_sg.nents > 1 || xfer->rx_sg.nents > 1) { 848 dev_warn_once(mas->dev, "Doing FIFO, cannot handle tx_nents-%d, rx_nents-%d\n", 849 xfer->tx_sg.nents, xfer->rx_sg.nents); 850 mas->cur_xfer_mode = GENI_SE_FIFO; 851 } else 852 mas->cur_xfer_mode = GENI_SE_DMA; 853 geni_se_select_mode(se, mas->cur_xfer_mode); 854 855 /* 856 * Lock around right before we start the transfer since our 857 * interrupt could come in at any time now. 858 */ 859 spin_lock_irq(&mas->lock); 860 geni_se_setup_m_cmd(se, m_cmd, FRAGMENTATION); 861 862 if (mas->cur_xfer_mode == GENI_SE_DMA) { 863 if (m_cmd & SPI_RX_ONLY) 864 geni_se_rx_init_dma(se, sg_dma_address(xfer->rx_sg.sgl), 865 sg_dma_len(xfer->rx_sg.sgl)); 866 if (m_cmd & SPI_TX_ONLY) 867 geni_se_tx_init_dma(se, sg_dma_address(xfer->tx_sg.sgl), 868 sg_dma_len(xfer->tx_sg.sgl)); 869 } else if (m_cmd & SPI_TX_ONLY) { 870 if (geni_spi_handle_tx(mas)) 871 writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG); 872 } 873 874 spin_unlock_irq(&mas->lock); 875 return ret; 876 } 877 878 static int spi_geni_transfer_one(struct spi_master *spi, 879 struct spi_device *slv, 880 struct spi_transfer *xfer) 881 { 882 struct spi_geni_master *mas = spi_master_get_devdata(spi); 883 int ret; 884 885 if (spi_geni_is_abort_still_pending(mas)) 886 return -EBUSY; 887 888 /* Terminate and return success for 0 byte length transfer */ 889 if (!xfer->len) 890 return 0; 891 892 if (mas->cur_xfer_mode == GENI_SE_FIFO || mas->cur_xfer_mode == GENI_SE_DMA) { 893 ret = setup_se_xfer(xfer, mas, slv->mode, spi); 894 /* SPI framework expects +ve ret code to wait for transfer complete */ 895 if (!ret) 896 ret = 1; 897 return ret; 898 } 899 return setup_gsi_xfer(xfer, mas, slv, spi); 900 } 901 902 static irqreturn_t geni_spi_isr(int irq, void *data) 903 { 904 struct spi_master *spi = data; 905 struct spi_geni_master *mas = spi_master_get_devdata(spi); 906 struct geni_se *se = &mas->se; 907 u32 m_irq; 908 909 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); 910 if (!m_irq) 911 return IRQ_NONE; 912 913 if (m_irq & (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN | 914 M_RX_FIFO_RD_ERR_EN | M_RX_FIFO_WR_ERR_EN | 915 M_TX_FIFO_RD_ERR_EN | M_TX_FIFO_WR_ERR_EN)) 916 dev_warn(mas->dev, "Unexpected IRQ err status %#010x\n", m_irq); 917 918 spin_lock(&mas->lock); 919 920 if (mas->cur_xfer_mode == GENI_SE_FIFO) { 921 if ((m_irq & M_RX_FIFO_WATERMARK_EN) || (m_irq & M_RX_FIFO_LAST_EN)) 922 geni_spi_handle_rx(mas); 923 924 if (m_irq & M_TX_FIFO_WATERMARK_EN) 925 geni_spi_handle_tx(mas); 926 927 if (m_irq & M_CMD_DONE_EN) { 928 if (mas->cur_xfer) { 929 spi_finalize_current_transfer(spi); 930 mas->cur_xfer = NULL; 931 /* 932 * If this happens, then a CMD_DONE came before all the 933 * Tx buffer bytes were sent out. This is unusual, log 934 * this condition and disable the WM interrupt to 935 * prevent the system from stalling due an interrupt 936 * storm. 937 * 938 * If this happens when all Rx bytes haven't been 939 * received, log the condition. The only known time 940 * this can happen is if bits_per_word != 8 and some 941 * registers that expect xfer lengths in num spi_words 942 * weren't written correctly. 943 */ 944 if (mas->tx_rem_bytes) { 945 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 946 dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n", 947 mas->tx_rem_bytes, mas->cur_bits_per_word); 948 } 949 if (mas->rx_rem_bytes) 950 dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n", 951 mas->rx_rem_bytes, mas->cur_bits_per_word); 952 } else { 953 complete(&mas->cs_done); 954 } 955 } 956 } else if (mas->cur_xfer_mode == GENI_SE_DMA) { 957 const struct spi_transfer *xfer = mas->cur_xfer; 958 u32 dma_tx_status = readl_relaxed(se->base + SE_DMA_TX_IRQ_STAT); 959 u32 dma_rx_status = readl_relaxed(se->base + SE_DMA_RX_IRQ_STAT); 960 961 if (dma_tx_status) 962 writel(dma_tx_status, se->base + SE_DMA_TX_IRQ_CLR); 963 if (dma_rx_status) 964 writel(dma_rx_status, se->base + SE_DMA_RX_IRQ_CLR); 965 if (dma_tx_status & TX_DMA_DONE) 966 mas->tx_rem_bytes = 0; 967 if (dma_rx_status & RX_DMA_DONE) 968 mas->rx_rem_bytes = 0; 969 if (dma_tx_status & TX_RESET_DONE) 970 complete(&mas->tx_reset_done); 971 if (dma_rx_status & RX_RESET_DONE) 972 complete(&mas->rx_reset_done); 973 if (!mas->tx_rem_bytes && !mas->rx_rem_bytes && xfer) { 974 spi_finalize_current_transfer(spi); 975 mas->cur_xfer = NULL; 976 } 977 } 978 979 if (m_irq & M_CMD_CANCEL_EN) 980 complete(&mas->cancel_done); 981 if (m_irq & M_CMD_ABORT_EN) 982 complete(&mas->abort_done); 983 984 /* 985 * It's safe or a good idea to Ack all of our interrupts at the end 986 * of the function. Specifically: 987 * - M_CMD_DONE_EN / M_RX_FIFO_LAST_EN: Edge triggered interrupts and 988 * clearing Acks. Clearing at the end relies on nobody else having 989 * started a new transfer yet or else we could be clearing _their_ 990 * done bit, but everyone grabs the spinlock before starting a new 991 * transfer. 992 * - M_RX_FIFO_WATERMARK_EN / M_TX_FIFO_WATERMARK_EN: These appear 993 * to be "latched level" interrupts so it's important to clear them 994 * _after_ you've handled the condition and always safe to do so 995 * since they'll re-assert if they're still happening. 996 */ 997 writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR); 998 999 spin_unlock(&mas->lock); 1000 1001 return IRQ_HANDLED; 1002 } 1003 1004 static int spi_geni_probe(struct platform_device *pdev) 1005 { 1006 int ret, irq; 1007 struct spi_master *spi; 1008 struct spi_geni_master *mas; 1009 void __iomem *base; 1010 struct clk *clk; 1011 struct device *dev = &pdev->dev; 1012 1013 irq = platform_get_irq(pdev, 0); 1014 if (irq < 0) 1015 return irq; 1016 1017 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); 1018 if (ret) 1019 return dev_err_probe(dev, ret, "could not set DMA mask\n"); 1020 1021 base = devm_platform_ioremap_resource(pdev, 0); 1022 if (IS_ERR(base)) 1023 return PTR_ERR(base); 1024 1025 clk = devm_clk_get(dev, "se"); 1026 if (IS_ERR(clk)) 1027 return PTR_ERR(clk); 1028 1029 spi = devm_spi_alloc_master(dev, sizeof(*mas)); 1030 if (!spi) 1031 return -ENOMEM; 1032 1033 platform_set_drvdata(pdev, spi); 1034 mas = spi_master_get_devdata(spi); 1035 mas->irq = irq; 1036 mas->dev = dev; 1037 mas->se.dev = dev; 1038 mas->se.wrapper = dev_get_drvdata(dev->parent); 1039 mas->se.base = base; 1040 mas->se.clk = clk; 1041 1042 ret = devm_pm_opp_set_clkname(&pdev->dev, "se"); 1043 if (ret) 1044 return ret; 1045 /* OPP table is optional */ 1046 ret = devm_pm_opp_of_add_table(&pdev->dev); 1047 if (ret && ret != -ENODEV) { 1048 dev_err(&pdev->dev, "invalid OPP table in device tree\n"); 1049 return ret; 1050 } 1051 1052 spi->bus_num = -1; 1053 spi->dev.of_node = dev->of_node; 1054 spi->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH; 1055 spi->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1056 spi->num_chipselect = 4; 1057 spi->max_speed_hz = 50000000; 1058 spi->max_dma_len = 0xffff0; /* 24 bits for tx/rx dma length */ 1059 spi->prepare_message = spi_geni_prepare_message; 1060 spi->transfer_one = spi_geni_transfer_one; 1061 spi->can_dma = geni_can_dma; 1062 spi->dma_map_dev = dev->parent; 1063 spi->auto_runtime_pm = true; 1064 spi->handle_err = spi_geni_handle_err; 1065 spi->use_gpio_descriptors = true; 1066 1067 init_completion(&mas->cs_done); 1068 init_completion(&mas->cancel_done); 1069 init_completion(&mas->abort_done); 1070 init_completion(&mas->tx_reset_done); 1071 init_completion(&mas->rx_reset_done); 1072 spin_lock_init(&mas->lock); 1073 pm_runtime_use_autosuspend(&pdev->dev); 1074 pm_runtime_set_autosuspend_delay(&pdev->dev, 250); 1075 pm_runtime_enable(dev); 1076 1077 ret = geni_icc_get(&mas->se, NULL); 1078 if (ret) 1079 goto spi_geni_probe_runtime_disable; 1080 /* Set the bus quota to a reasonable value for register access */ 1081 mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ); 1082 mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; 1083 1084 ret = geni_icc_set_bw(&mas->se); 1085 if (ret) 1086 goto spi_geni_probe_runtime_disable; 1087 1088 ret = spi_geni_init(mas); 1089 if (ret) 1090 goto spi_geni_probe_runtime_disable; 1091 1092 /* 1093 * check the mode supported and set_cs for fifo mode only 1094 * for dma (gsi) mode, the gsi will set cs based on params passed in 1095 * TRE 1096 */ 1097 if (mas->cur_xfer_mode == GENI_SE_FIFO) 1098 spi->set_cs = spi_geni_set_cs; 1099 1100 /* 1101 * TX is required per GSI spec, see setup_gsi_xfer(). 1102 */ 1103 if (mas->cur_xfer_mode == GENI_GPI_DMA) 1104 spi->flags = SPI_CONTROLLER_MUST_TX; 1105 1106 ret = request_irq(mas->irq, geni_spi_isr, 0, dev_name(dev), spi); 1107 if (ret) 1108 goto spi_geni_release_dma; 1109 1110 ret = spi_register_master(spi); 1111 if (ret) 1112 goto spi_geni_probe_free_irq; 1113 1114 return 0; 1115 spi_geni_probe_free_irq: 1116 free_irq(mas->irq, spi); 1117 spi_geni_release_dma: 1118 spi_geni_release_dma_chan(mas); 1119 spi_geni_probe_runtime_disable: 1120 pm_runtime_disable(dev); 1121 return ret; 1122 } 1123 1124 static void spi_geni_remove(struct platform_device *pdev) 1125 { 1126 struct spi_master *spi = platform_get_drvdata(pdev); 1127 struct spi_geni_master *mas = spi_master_get_devdata(spi); 1128 1129 /* Unregister _before_ disabling pm_runtime() so we stop transfers */ 1130 spi_unregister_master(spi); 1131 1132 spi_geni_release_dma_chan(mas); 1133 1134 free_irq(mas->irq, spi); 1135 pm_runtime_disable(&pdev->dev); 1136 } 1137 1138 static int __maybe_unused spi_geni_runtime_suspend(struct device *dev) 1139 { 1140 struct spi_master *spi = dev_get_drvdata(dev); 1141 struct spi_geni_master *mas = spi_master_get_devdata(spi); 1142 int ret; 1143 1144 /* Drop the performance state vote */ 1145 dev_pm_opp_set_rate(dev, 0); 1146 1147 ret = geni_se_resources_off(&mas->se); 1148 if (ret) 1149 return ret; 1150 1151 return geni_icc_disable(&mas->se); 1152 } 1153 1154 static int __maybe_unused spi_geni_runtime_resume(struct device *dev) 1155 { 1156 struct spi_master *spi = dev_get_drvdata(dev); 1157 struct spi_geni_master *mas = spi_master_get_devdata(spi); 1158 int ret; 1159 1160 ret = geni_icc_enable(&mas->se); 1161 if (ret) 1162 return ret; 1163 1164 ret = geni_se_resources_on(&mas->se); 1165 if (ret) 1166 return ret; 1167 1168 return dev_pm_opp_set_rate(mas->dev, mas->cur_sclk_hz); 1169 } 1170 1171 static int __maybe_unused spi_geni_suspend(struct device *dev) 1172 { 1173 struct spi_master *spi = dev_get_drvdata(dev); 1174 int ret; 1175 1176 ret = spi_master_suspend(spi); 1177 if (ret) 1178 return ret; 1179 1180 ret = pm_runtime_force_suspend(dev); 1181 if (ret) 1182 spi_master_resume(spi); 1183 1184 return ret; 1185 } 1186 1187 static int __maybe_unused spi_geni_resume(struct device *dev) 1188 { 1189 struct spi_master *spi = dev_get_drvdata(dev); 1190 int ret; 1191 1192 ret = pm_runtime_force_resume(dev); 1193 if (ret) 1194 return ret; 1195 1196 ret = spi_master_resume(spi); 1197 if (ret) 1198 pm_runtime_force_suspend(dev); 1199 1200 return ret; 1201 } 1202 1203 static const struct dev_pm_ops spi_geni_pm_ops = { 1204 SET_RUNTIME_PM_OPS(spi_geni_runtime_suspend, 1205 spi_geni_runtime_resume, NULL) 1206 SET_SYSTEM_SLEEP_PM_OPS(spi_geni_suspend, spi_geni_resume) 1207 }; 1208 1209 static const struct of_device_id spi_geni_dt_match[] = { 1210 { .compatible = "qcom,geni-spi" }, 1211 {} 1212 }; 1213 MODULE_DEVICE_TABLE(of, spi_geni_dt_match); 1214 1215 static struct platform_driver spi_geni_driver = { 1216 .probe = spi_geni_probe, 1217 .remove_new = spi_geni_remove, 1218 .driver = { 1219 .name = "geni_spi", 1220 .pm = &spi_geni_pm_ops, 1221 .of_match_table = spi_geni_dt_match, 1222 }, 1223 }; 1224 module_platform_driver(spi_geni_driver); 1225 1226 MODULE_DESCRIPTION("SPI driver for GENI based QUP cores"); 1227 MODULE_LICENSE("GPL v2"); 1228