1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved. 3 4 #include <linux/clk.h> 5 #include <linux/dmaengine.h> 6 #include <linux/dma-mapping.h> 7 #include <linux/dma/qcom-gpi-dma.h> 8 #include <linux/interrupt.h> 9 #include <linux/io.h> 10 #include <linux/log2.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm_opp.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/soc/qcom/geni-se.h> 16 #include <linux/spi/spi.h> 17 #include <linux/spinlock.h> 18 19 /* SPI SE specific registers and respective register fields */ 20 #define SE_SPI_CPHA 0x224 21 #define CPHA BIT(0) 22 23 #define SE_SPI_LOOPBACK 0x22c 24 #define LOOPBACK_ENABLE 0x1 25 #define NORMAL_MODE 0x0 26 #define LOOPBACK_MSK GENMASK(1, 0) 27 28 #define SE_SPI_CPOL 0x230 29 #define CPOL BIT(2) 30 31 #define SE_SPI_DEMUX_OUTPUT_INV 0x24c 32 #define CS_DEMUX_OUTPUT_INV_MSK GENMASK(3, 0) 33 34 #define SE_SPI_DEMUX_SEL 0x250 35 #define CS_DEMUX_OUTPUT_SEL GENMASK(3, 0) 36 37 #define SE_SPI_TRANS_CFG 0x25c 38 #define CS_TOGGLE BIT(0) 39 40 #define SE_SPI_WORD_LEN 0x268 41 #define WORD_LEN_MSK GENMASK(9, 0) 42 #define MIN_WORD_LEN 4 43 44 #define SE_SPI_TX_TRANS_LEN 0x26c 45 #define SE_SPI_RX_TRANS_LEN 0x270 46 #define TRANS_LEN_MSK GENMASK(23, 0) 47 48 #define SE_SPI_PRE_POST_CMD_DLY 0x274 49 50 #define SE_SPI_DELAY_COUNTERS 0x278 51 #define SPI_INTER_WORDS_DELAY_MSK GENMASK(9, 0) 52 #define SPI_CS_CLK_DELAY_MSK GENMASK(19, 10) 53 #define SPI_CS_CLK_DELAY_SHFT 10 54 55 /* M_CMD OP codes for SPI */ 56 #define SPI_TX_ONLY 1 57 #define SPI_RX_ONLY 2 58 #define SPI_TX_RX 7 59 #define SPI_CS_ASSERT 8 60 #define SPI_CS_DEASSERT 9 61 #define SPI_SCK_ONLY 10 62 /* M_CMD params for SPI */ 63 #define SPI_PRE_CMD_DELAY BIT(0) 64 #define TIMESTAMP_BEFORE BIT(1) 65 #define FRAGMENTATION BIT(2) 66 #define TIMESTAMP_AFTER BIT(3) 67 #define POST_CMD_DELAY BIT(4) 68 69 #define GSI_LOOPBACK_EN BIT(0) 70 #define GSI_CS_TOGGLE BIT(3) 71 #define GSI_CPHA BIT(4) 72 #define GSI_CPOL BIT(5) 73 74 struct spi_geni_master { 75 struct geni_se se; 76 struct device *dev; 77 u32 tx_fifo_depth; 78 u32 fifo_width_bits; 79 u32 tx_wm; 80 u32 last_mode; 81 unsigned long cur_speed_hz; 82 unsigned long cur_sclk_hz; 83 unsigned int cur_bits_per_word; 84 unsigned int tx_rem_bytes; 85 unsigned int rx_rem_bytes; 86 const struct spi_transfer *cur_xfer; 87 struct completion cs_done; 88 struct completion cancel_done; 89 struct completion abort_done; 90 struct completion tx_reset_done; 91 struct completion rx_reset_done; 92 unsigned int oversampling; 93 spinlock_t lock; 94 int irq; 95 bool cs_flag; 96 bool abort_failed; 97 struct dma_chan *tx; 98 struct dma_chan *rx; 99 int cur_xfer_mode; 100 dma_addr_t tx_se_dma; 101 dma_addr_t rx_se_dma; 102 }; 103 104 static int get_spi_clk_cfg(unsigned int speed_hz, 105 struct spi_geni_master *mas, 106 unsigned int *clk_idx, 107 unsigned int *clk_div) 108 { 109 unsigned long sclk_freq; 110 unsigned int actual_hz; 111 int ret; 112 113 ret = geni_se_clk_freq_match(&mas->se, 114 speed_hz * mas->oversampling, 115 clk_idx, &sclk_freq, false); 116 if (ret) { 117 dev_err(mas->dev, "Failed(%d) to find src clk for %dHz\n", 118 ret, speed_hz); 119 return ret; 120 } 121 122 *clk_div = DIV_ROUND_UP(sclk_freq, mas->oversampling * speed_hz); 123 actual_hz = sclk_freq / (mas->oversampling * *clk_div); 124 125 dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz, 126 actual_hz, sclk_freq, *clk_idx, *clk_div); 127 ret = dev_pm_opp_set_rate(mas->dev, sclk_freq); 128 if (ret) 129 dev_err(mas->dev, "dev_pm_opp_set_rate failed %d\n", ret); 130 else 131 mas->cur_sclk_hz = sclk_freq; 132 133 return ret; 134 } 135 136 static void handle_se_timeout(struct spi_master *spi, 137 struct spi_message *msg) 138 { 139 struct spi_geni_master *mas = spi_master_get_devdata(spi); 140 unsigned long time_left; 141 struct geni_se *se = &mas->se; 142 const struct spi_transfer *xfer; 143 144 spin_lock_irq(&mas->lock); 145 reinit_completion(&mas->cancel_done); 146 if (mas->cur_xfer_mode == GENI_SE_FIFO) 147 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 148 149 xfer = mas->cur_xfer; 150 mas->cur_xfer = NULL; 151 geni_se_cancel_m_cmd(se); 152 spin_unlock_irq(&mas->lock); 153 154 time_left = wait_for_completion_timeout(&mas->cancel_done, HZ); 155 if (time_left) 156 goto unmap_if_dma; 157 158 spin_lock_irq(&mas->lock); 159 reinit_completion(&mas->abort_done); 160 geni_se_abort_m_cmd(se); 161 spin_unlock_irq(&mas->lock); 162 163 time_left = wait_for_completion_timeout(&mas->abort_done, HZ); 164 if (!time_left) { 165 dev_err(mas->dev, "Failed to cancel/abort m_cmd\n"); 166 167 /* 168 * No need for a lock since SPI core has a lock and we never 169 * access this from an interrupt. 170 */ 171 mas->abort_failed = true; 172 } 173 174 unmap_if_dma: 175 if (mas->cur_xfer_mode == GENI_SE_DMA) { 176 if (xfer) { 177 if (xfer->tx_buf && mas->tx_se_dma) { 178 spin_lock_irq(&mas->lock); 179 reinit_completion(&mas->tx_reset_done); 180 writel(1, se->base + SE_DMA_TX_FSM_RST); 181 spin_unlock_irq(&mas->lock); 182 time_left = wait_for_completion_timeout(&mas->tx_reset_done, HZ); 183 if (!time_left) 184 dev_err(mas->dev, "DMA TX RESET failed\n"); 185 geni_se_tx_dma_unprep(se, mas->tx_se_dma, xfer->len); 186 } 187 if (xfer->rx_buf && mas->rx_se_dma) { 188 spin_lock_irq(&mas->lock); 189 reinit_completion(&mas->rx_reset_done); 190 writel(1, se->base + SE_DMA_RX_FSM_RST); 191 spin_unlock_irq(&mas->lock); 192 time_left = wait_for_completion_timeout(&mas->rx_reset_done, HZ); 193 if (!time_left) 194 dev_err(mas->dev, "DMA RX RESET failed\n"); 195 geni_se_rx_dma_unprep(se, mas->rx_se_dma, xfer->len); 196 } 197 } else { 198 /* 199 * This can happen if a timeout happened and we had to wait 200 * for lock in this function because isr was holding the lock 201 * and handling transfer completion at that time. 202 */ 203 dev_warn(mas->dev, "Cancel/Abort on completed SPI transfer\n"); 204 } 205 } 206 } 207 208 static void handle_gpi_timeout(struct spi_master *spi, struct spi_message *msg) 209 { 210 struct spi_geni_master *mas = spi_master_get_devdata(spi); 211 212 dmaengine_terminate_sync(mas->tx); 213 dmaengine_terminate_sync(mas->rx); 214 } 215 216 static void spi_geni_handle_err(struct spi_master *spi, struct spi_message *msg) 217 { 218 struct spi_geni_master *mas = spi_master_get_devdata(spi); 219 220 switch (mas->cur_xfer_mode) { 221 case GENI_SE_FIFO: 222 case GENI_SE_DMA: 223 handle_se_timeout(spi, msg); 224 break; 225 case GENI_GPI_DMA: 226 handle_gpi_timeout(spi, msg); 227 break; 228 default: 229 dev_err(mas->dev, "Abort on Mode:%d not supported", mas->cur_xfer_mode); 230 } 231 } 232 233 static bool spi_geni_is_abort_still_pending(struct spi_geni_master *mas) 234 { 235 struct geni_se *se = &mas->se; 236 u32 m_irq, m_irq_en; 237 238 if (!mas->abort_failed) 239 return false; 240 241 /* 242 * The only known case where a transfer times out and then a cancel 243 * times out then an abort times out is if something is blocking our 244 * interrupt handler from running. Avoid starting any new transfers 245 * until that sorts itself out. 246 */ 247 spin_lock_irq(&mas->lock); 248 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); 249 m_irq_en = readl(se->base + SE_GENI_M_IRQ_EN); 250 spin_unlock_irq(&mas->lock); 251 252 if (m_irq & m_irq_en) { 253 dev_err(mas->dev, "Interrupts pending after abort: %#010x\n", 254 m_irq & m_irq_en); 255 return true; 256 } 257 258 /* 259 * If we're here the problem resolved itself so no need to check more 260 * on future transfers. 261 */ 262 mas->abort_failed = false; 263 264 return false; 265 } 266 267 static void spi_geni_set_cs(struct spi_device *slv, bool set_flag) 268 { 269 struct spi_geni_master *mas = spi_master_get_devdata(slv->master); 270 struct spi_master *spi = dev_get_drvdata(mas->dev); 271 struct geni_se *se = &mas->se; 272 unsigned long time_left; 273 274 if (!(slv->mode & SPI_CS_HIGH)) 275 set_flag = !set_flag; 276 277 if (set_flag == mas->cs_flag) 278 return; 279 280 pm_runtime_get_sync(mas->dev); 281 282 if (spi_geni_is_abort_still_pending(mas)) { 283 dev_err(mas->dev, "Can't set chip select\n"); 284 goto exit; 285 } 286 287 spin_lock_irq(&mas->lock); 288 if (mas->cur_xfer) { 289 dev_err(mas->dev, "Can't set CS when prev xfer running\n"); 290 spin_unlock_irq(&mas->lock); 291 goto exit; 292 } 293 294 mas->cs_flag = set_flag; 295 /* set xfer_mode to FIFO to complete cs_done in isr */ 296 mas->cur_xfer_mode = GENI_SE_FIFO; 297 reinit_completion(&mas->cs_done); 298 if (set_flag) 299 geni_se_setup_m_cmd(se, SPI_CS_ASSERT, 0); 300 else 301 geni_se_setup_m_cmd(se, SPI_CS_DEASSERT, 0); 302 spin_unlock_irq(&mas->lock); 303 304 time_left = wait_for_completion_timeout(&mas->cs_done, HZ); 305 if (!time_left) { 306 dev_warn(mas->dev, "Timeout setting chip select\n"); 307 handle_se_timeout(spi, NULL); 308 } 309 310 exit: 311 pm_runtime_put(mas->dev); 312 } 313 314 static void spi_setup_word_len(struct spi_geni_master *mas, u16 mode, 315 unsigned int bits_per_word) 316 { 317 unsigned int pack_words; 318 bool msb_first = (mode & SPI_LSB_FIRST) ? false : true; 319 struct geni_se *se = &mas->se; 320 u32 word_len; 321 322 /* 323 * If bits_per_word isn't a byte aligned value, set the packing to be 324 * 1 SPI word per FIFO word. 325 */ 326 if (!(mas->fifo_width_bits % bits_per_word)) 327 pack_words = mas->fifo_width_bits / bits_per_word; 328 else 329 pack_words = 1; 330 geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first, 331 true, true); 332 word_len = (bits_per_word - MIN_WORD_LEN) & WORD_LEN_MSK; 333 writel(word_len, se->base + SE_SPI_WORD_LEN); 334 } 335 336 static int geni_spi_set_clock_and_bw(struct spi_geni_master *mas, 337 unsigned long clk_hz) 338 { 339 u32 clk_sel, m_clk_cfg, idx, div; 340 struct geni_se *se = &mas->se; 341 int ret; 342 343 if (clk_hz == mas->cur_speed_hz) 344 return 0; 345 346 ret = get_spi_clk_cfg(clk_hz, mas, &idx, &div); 347 if (ret) { 348 dev_err(mas->dev, "Err setting clk to %lu: %d\n", clk_hz, ret); 349 return ret; 350 } 351 352 /* 353 * SPI core clock gets configured with the requested frequency 354 * or the frequency closer to the requested frequency. 355 * For that reason requested frequency is stored in the 356 * cur_speed_hz and referred in the consecutive transfer instead 357 * of calling clk_get_rate() API. 358 */ 359 mas->cur_speed_hz = clk_hz; 360 361 clk_sel = idx & CLK_SEL_MSK; 362 m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN; 363 writel(clk_sel, se->base + SE_GENI_CLK_SEL); 364 writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG); 365 366 /* Set BW quota for CPU as driver supports FIFO mode only. */ 367 se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz); 368 ret = geni_icc_set_bw(se); 369 if (ret) 370 return ret; 371 372 return 0; 373 } 374 375 static int setup_fifo_params(struct spi_device *spi_slv, 376 struct spi_master *spi) 377 { 378 struct spi_geni_master *mas = spi_master_get_devdata(spi); 379 struct geni_se *se = &mas->se; 380 u32 loopback_cfg = 0, cpol = 0, cpha = 0, demux_output_inv = 0; 381 u32 demux_sel; 382 383 if (mas->last_mode != spi_slv->mode) { 384 if (spi_slv->mode & SPI_LOOP) 385 loopback_cfg = LOOPBACK_ENABLE; 386 387 if (spi_slv->mode & SPI_CPOL) 388 cpol = CPOL; 389 390 if (spi_slv->mode & SPI_CPHA) 391 cpha = CPHA; 392 393 if (spi_slv->mode & SPI_CS_HIGH) 394 demux_output_inv = BIT(spi_slv->chip_select); 395 396 demux_sel = spi_slv->chip_select; 397 mas->cur_bits_per_word = spi_slv->bits_per_word; 398 399 spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word); 400 writel(loopback_cfg, se->base + SE_SPI_LOOPBACK); 401 writel(demux_sel, se->base + SE_SPI_DEMUX_SEL); 402 writel(cpha, se->base + SE_SPI_CPHA); 403 writel(cpol, se->base + SE_SPI_CPOL); 404 writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV); 405 406 mas->last_mode = spi_slv->mode; 407 } 408 409 return geni_spi_set_clock_and_bw(mas, spi_slv->max_speed_hz); 410 } 411 412 static void 413 spi_gsi_callback_result(void *cb, const struct dmaengine_result *result) 414 { 415 struct spi_master *spi = cb; 416 417 spi->cur_msg->status = -EIO; 418 if (result->result != DMA_TRANS_NOERROR) { 419 dev_err(&spi->dev, "DMA txn failed: %d\n", result->result); 420 spi_finalize_current_transfer(spi); 421 return; 422 } 423 424 if (!result->residue) { 425 spi->cur_msg->status = 0; 426 dev_dbg(&spi->dev, "DMA txn completed\n"); 427 } else { 428 dev_err(&spi->dev, "DMA xfer has pending: %d\n", result->residue); 429 } 430 431 spi_finalize_current_transfer(spi); 432 } 433 434 static int setup_gsi_xfer(struct spi_transfer *xfer, struct spi_geni_master *mas, 435 struct spi_device *spi_slv, struct spi_master *spi) 436 { 437 unsigned long flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK; 438 struct dma_slave_config config = {}; 439 struct gpi_spi_config peripheral = {}; 440 struct dma_async_tx_descriptor *tx_desc, *rx_desc; 441 int ret; 442 443 config.peripheral_config = &peripheral; 444 config.peripheral_size = sizeof(peripheral); 445 peripheral.set_config = true; 446 447 if (xfer->bits_per_word != mas->cur_bits_per_word || 448 xfer->speed_hz != mas->cur_speed_hz) { 449 mas->cur_bits_per_word = xfer->bits_per_word; 450 mas->cur_speed_hz = xfer->speed_hz; 451 } 452 453 if (xfer->tx_buf && xfer->rx_buf) { 454 peripheral.cmd = SPI_DUPLEX; 455 } else if (xfer->tx_buf) { 456 peripheral.cmd = SPI_TX; 457 peripheral.rx_len = 0; 458 } else if (xfer->rx_buf) { 459 peripheral.cmd = SPI_RX; 460 if (!(mas->cur_bits_per_word % MIN_WORD_LEN)) { 461 peripheral.rx_len = ((xfer->len << 3) / mas->cur_bits_per_word); 462 } else { 463 int bytes_per_word = (mas->cur_bits_per_word / BITS_PER_BYTE) + 1; 464 465 peripheral.rx_len = (xfer->len / bytes_per_word); 466 } 467 } 468 469 peripheral.loopback_en = !!(spi_slv->mode & SPI_LOOP); 470 peripheral.clock_pol_high = !!(spi_slv->mode & SPI_CPOL); 471 peripheral.data_pol_high = !!(spi_slv->mode & SPI_CPHA); 472 peripheral.cs = spi_slv->chip_select; 473 peripheral.pack_en = true; 474 peripheral.word_len = xfer->bits_per_word - MIN_WORD_LEN; 475 476 ret = get_spi_clk_cfg(mas->cur_speed_hz, mas, 477 &peripheral.clk_src, &peripheral.clk_div); 478 if (ret) { 479 dev_err(mas->dev, "Err in get_spi_clk_cfg() :%d\n", ret); 480 return ret; 481 } 482 483 if (!xfer->cs_change) { 484 if (!list_is_last(&xfer->transfer_list, &spi->cur_msg->transfers)) 485 peripheral.fragmentation = FRAGMENTATION; 486 } 487 488 if (peripheral.cmd & SPI_RX) { 489 dmaengine_slave_config(mas->rx, &config); 490 rx_desc = dmaengine_prep_slave_sg(mas->rx, xfer->rx_sg.sgl, xfer->rx_sg.nents, 491 DMA_DEV_TO_MEM, flags); 492 if (!rx_desc) { 493 dev_err(mas->dev, "Err setting up rx desc\n"); 494 return -EIO; 495 } 496 } 497 498 /* 499 * Prepare the TX always, even for RX or tx_buf being null, we would 500 * need TX to be prepared per GSI spec 501 */ 502 dmaengine_slave_config(mas->tx, &config); 503 tx_desc = dmaengine_prep_slave_sg(mas->tx, xfer->tx_sg.sgl, xfer->tx_sg.nents, 504 DMA_MEM_TO_DEV, flags); 505 if (!tx_desc) { 506 dev_err(mas->dev, "Err setting up tx desc\n"); 507 return -EIO; 508 } 509 510 tx_desc->callback_result = spi_gsi_callback_result; 511 tx_desc->callback_param = spi; 512 513 if (peripheral.cmd & SPI_RX) 514 dmaengine_submit(rx_desc); 515 dmaengine_submit(tx_desc); 516 517 if (peripheral.cmd & SPI_RX) 518 dma_async_issue_pending(mas->rx); 519 520 dma_async_issue_pending(mas->tx); 521 return 1; 522 } 523 524 static bool geni_can_dma(struct spi_controller *ctlr, 525 struct spi_device *slv, struct spi_transfer *xfer) 526 { 527 struct spi_geni_master *mas = spi_master_get_devdata(slv->master); 528 529 /* 530 * Return true if transfer needs to be mapped prior to 531 * calling transfer_one which is the case only for GPI_DMA. 532 * For SE_DMA mode, map/unmap is done in geni_se_*x_dma_prep. 533 */ 534 return mas->cur_xfer_mode == GENI_GPI_DMA; 535 } 536 537 static int spi_geni_prepare_message(struct spi_master *spi, 538 struct spi_message *spi_msg) 539 { 540 struct spi_geni_master *mas = spi_master_get_devdata(spi); 541 int ret; 542 543 switch (mas->cur_xfer_mode) { 544 case GENI_SE_FIFO: 545 case GENI_SE_DMA: 546 if (spi_geni_is_abort_still_pending(mas)) 547 return -EBUSY; 548 ret = setup_fifo_params(spi_msg->spi, spi); 549 if (ret) 550 dev_err(mas->dev, "Couldn't select mode %d\n", ret); 551 return ret; 552 553 case GENI_GPI_DMA: 554 /* nothing to do for GPI DMA */ 555 return 0; 556 } 557 558 dev_err(mas->dev, "Mode not supported %d", mas->cur_xfer_mode); 559 return -EINVAL; 560 } 561 562 static int spi_geni_grab_gpi_chan(struct spi_geni_master *mas) 563 { 564 int ret; 565 566 mas->tx = dma_request_chan(mas->dev, "tx"); 567 if (IS_ERR(mas->tx)) { 568 ret = dev_err_probe(mas->dev, PTR_ERR(mas->tx), 569 "Failed to get tx DMA ch\n"); 570 goto err_tx; 571 } 572 573 mas->rx = dma_request_chan(mas->dev, "rx"); 574 if (IS_ERR(mas->rx)) { 575 ret = dev_err_probe(mas->dev, PTR_ERR(mas->rx), 576 "Failed to get rx DMA ch\n"); 577 goto err_rx; 578 } 579 580 return 0; 581 582 err_rx: 583 mas->rx = NULL; 584 dma_release_channel(mas->tx); 585 err_tx: 586 mas->tx = NULL; 587 return ret; 588 } 589 590 static void spi_geni_release_dma_chan(struct spi_geni_master *mas) 591 { 592 if (mas->rx) { 593 dma_release_channel(mas->rx); 594 mas->rx = NULL; 595 } 596 597 if (mas->tx) { 598 dma_release_channel(mas->tx); 599 mas->tx = NULL; 600 } 601 } 602 603 static int spi_geni_init(struct spi_geni_master *mas) 604 { 605 struct geni_se *se = &mas->se; 606 unsigned int proto, major, minor, ver; 607 u32 spi_tx_cfg, fifo_disable; 608 int ret = -ENXIO; 609 610 pm_runtime_get_sync(mas->dev); 611 612 proto = geni_se_read_proto(se); 613 if (proto != GENI_SE_SPI) { 614 dev_err(mas->dev, "Invalid proto %d\n", proto); 615 goto out_pm; 616 } 617 mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se); 618 619 /* Width of Tx and Rx FIFO is same */ 620 mas->fifo_width_bits = geni_se_get_tx_fifo_width(se); 621 622 /* 623 * Hardware programming guide suggests to configure 624 * RX FIFO RFR level to fifo_depth-2. 625 */ 626 geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2); 627 /* Transmit an entire FIFO worth of data per IRQ */ 628 mas->tx_wm = 1; 629 ver = geni_se_get_qup_hw_version(se); 630 major = GENI_SE_VERSION_MAJOR(ver); 631 minor = GENI_SE_VERSION_MINOR(ver); 632 633 if (major == 1 && minor == 0) 634 mas->oversampling = 2; 635 else 636 mas->oversampling = 1; 637 638 fifo_disable = readl(se->base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE; 639 switch (fifo_disable) { 640 case 1: 641 ret = spi_geni_grab_gpi_chan(mas); 642 if (!ret) { /* success case */ 643 mas->cur_xfer_mode = GENI_GPI_DMA; 644 geni_se_select_mode(se, GENI_GPI_DMA); 645 dev_dbg(mas->dev, "Using GPI DMA mode for SPI\n"); 646 break; 647 } 648 /* 649 * in case of failure to get gpi dma channel, we can still do the 650 * FIFO mode, so fallthrough 651 */ 652 dev_warn(mas->dev, "FIFO mode disabled, but couldn't get DMA, fall back to FIFO mode\n"); 653 fallthrough; 654 655 case 0: 656 mas->cur_xfer_mode = GENI_SE_FIFO; 657 geni_se_select_mode(se, GENI_SE_FIFO); 658 ret = 0; 659 break; 660 } 661 662 /* We always control CS manually */ 663 spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG); 664 spi_tx_cfg &= ~CS_TOGGLE; 665 writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG); 666 667 out_pm: 668 pm_runtime_put(mas->dev); 669 return ret; 670 } 671 672 static unsigned int geni_byte_per_fifo_word(struct spi_geni_master *mas) 673 { 674 /* 675 * Calculate how many bytes we'll put in each FIFO word. If the 676 * transfer words don't pack cleanly into a FIFO word we'll just put 677 * one transfer word in each FIFO word. If they do pack we'll pack 'em. 678 */ 679 if (mas->fifo_width_bits % mas->cur_bits_per_word) 680 return roundup_pow_of_two(DIV_ROUND_UP(mas->cur_bits_per_word, 681 BITS_PER_BYTE)); 682 683 return mas->fifo_width_bits / BITS_PER_BYTE; 684 } 685 686 static bool geni_spi_handle_tx(struct spi_geni_master *mas) 687 { 688 struct geni_se *se = &mas->se; 689 unsigned int max_bytes; 690 const u8 *tx_buf; 691 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas); 692 unsigned int i = 0; 693 694 /* Stop the watermark IRQ if nothing to send */ 695 if (!mas->cur_xfer) { 696 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 697 return false; 698 } 699 700 max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * bytes_per_fifo_word; 701 if (mas->tx_rem_bytes < max_bytes) 702 max_bytes = mas->tx_rem_bytes; 703 704 tx_buf = mas->cur_xfer->tx_buf + mas->cur_xfer->len - mas->tx_rem_bytes; 705 while (i < max_bytes) { 706 unsigned int j; 707 unsigned int bytes_to_write; 708 u32 fifo_word = 0; 709 u8 *fifo_byte = (u8 *)&fifo_word; 710 711 bytes_to_write = min(bytes_per_fifo_word, max_bytes - i); 712 for (j = 0; j < bytes_to_write; j++) 713 fifo_byte[j] = tx_buf[i++]; 714 iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1); 715 } 716 mas->tx_rem_bytes -= max_bytes; 717 if (!mas->tx_rem_bytes) { 718 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 719 return false; 720 } 721 return true; 722 } 723 724 static void geni_spi_handle_rx(struct spi_geni_master *mas) 725 { 726 struct geni_se *se = &mas->se; 727 u32 rx_fifo_status; 728 unsigned int rx_bytes; 729 unsigned int rx_last_byte_valid; 730 u8 *rx_buf; 731 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas); 732 unsigned int i = 0; 733 734 rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS); 735 rx_bytes = (rx_fifo_status & RX_FIFO_WC_MSK) * bytes_per_fifo_word; 736 if (rx_fifo_status & RX_LAST) { 737 rx_last_byte_valid = rx_fifo_status & RX_LAST_BYTE_VALID_MSK; 738 rx_last_byte_valid >>= RX_LAST_BYTE_VALID_SHFT; 739 if (rx_last_byte_valid && rx_last_byte_valid < 4) 740 rx_bytes -= bytes_per_fifo_word - rx_last_byte_valid; 741 } 742 743 /* Clear out the FIFO and bail if nowhere to put it */ 744 if (!mas->cur_xfer) { 745 for (i = 0; i < DIV_ROUND_UP(rx_bytes, bytes_per_fifo_word); i++) 746 readl(se->base + SE_GENI_RX_FIFOn); 747 return; 748 } 749 750 if (mas->rx_rem_bytes < rx_bytes) 751 rx_bytes = mas->rx_rem_bytes; 752 753 rx_buf = mas->cur_xfer->rx_buf + mas->cur_xfer->len - mas->rx_rem_bytes; 754 while (i < rx_bytes) { 755 u32 fifo_word = 0; 756 u8 *fifo_byte = (u8 *)&fifo_word; 757 unsigned int bytes_to_read; 758 unsigned int j; 759 760 bytes_to_read = min(bytes_per_fifo_word, rx_bytes - i); 761 ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1); 762 for (j = 0; j < bytes_to_read; j++) 763 rx_buf[i++] = fifo_byte[j]; 764 } 765 mas->rx_rem_bytes -= rx_bytes; 766 } 767 768 static int setup_se_xfer(struct spi_transfer *xfer, 769 struct spi_geni_master *mas, 770 u16 mode, struct spi_master *spi) 771 { 772 u32 m_cmd = 0; 773 u32 len, fifo_size; 774 struct geni_se *se = &mas->se; 775 int ret; 776 777 /* 778 * Ensure that our interrupt handler isn't still running from some 779 * prior command before we start messing with the hardware behind 780 * its back. We don't need to _keep_ the lock here since we're only 781 * worried about racing with out interrupt handler. The SPI core 782 * already handles making sure that we're not trying to do two 783 * transfers at once or setting a chip select and doing a transfer 784 * concurrently. 785 * 786 * NOTE: we actually _can't_ hold the lock here because possibly we 787 * might call clk_set_rate() which needs to be able to sleep. 788 */ 789 spin_lock_irq(&mas->lock); 790 spin_unlock_irq(&mas->lock); 791 792 if (xfer->bits_per_word != mas->cur_bits_per_word) { 793 spi_setup_word_len(mas, mode, xfer->bits_per_word); 794 mas->cur_bits_per_word = xfer->bits_per_word; 795 } 796 797 /* Speed and bits per word can be overridden per transfer */ 798 ret = geni_spi_set_clock_and_bw(mas, xfer->speed_hz); 799 if (ret) 800 return ret; 801 802 mas->tx_rem_bytes = 0; 803 mas->rx_rem_bytes = 0; 804 805 if (!(mas->cur_bits_per_word % MIN_WORD_LEN)) 806 len = xfer->len * BITS_PER_BYTE / mas->cur_bits_per_word; 807 else 808 len = xfer->len / (mas->cur_bits_per_word / BITS_PER_BYTE + 1); 809 len &= TRANS_LEN_MSK; 810 811 mas->cur_xfer = xfer; 812 if (xfer->tx_buf) { 813 m_cmd |= SPI_TX_ONLY; 814 mas->tx_rem_bytes = xfer->len; 815 writel(len, se->base + SE_SPI_TX_TRANS_LEN); 816 } 817 818 if (xfer->rx_buf) { 819 m_cmd |= SPI_RX_ONLY; 820 writel(len, se->base + SE_SPI_RX_TRANS_LEN); 821 mas->rx_rem_bytes = xfer->len; 822 } 823 824 /* Select transfer mode based on transfer length */ 825 fifo_size = mas->tx_fifo_depth * mas->fifo_width_bits / mas->cur_bits_per_word; 826 mas->cur_xfer_mode = (len <= fifo_size) ? GENI_SE_FIFO : GENI_SE_DMA; 827 geni_se_select_mode(se, mas->cur_xfer_mode); 828 829 /* 830 * Lock around right before we start the transfer since our 831 * interrupt could come in at any time now. 832 */ 833 spin_lock_irq(&mas->lock); 834 geni_se_setup_m_cmd(se, m_cmd, FRAGMENTATION); 835 836 if (mas->cur_xfer_mode == GENI_SE_DMA) { 837 if (m_cmd & SPI_RX_ONLY) { 838 ret = geni_se_rx_dma_prep(se, xfer->rx_buf, 839 xfer->len, &mas->rx_se_dma); 840 if (ret) { 841 dev_err(mas->dev, "Failed to setup Rx dma %d\n", ret); 842 mas->rx_se_dma = 0; 843 goto unlock_and_return; 844 } 845 } 846 if (m_cmd & SPI_TX_ONLY) { 847 ret = geni_se_tx_dma_prep(se, (void *)xfer->tx_buf, 848 xfer->len, &mas->tx_se_dma); 849 if (ret) { 850 dev_err(mas->dev, "Failed to setup Tx dma %d\n", ret); 851 mas->tx_se_dma = 0; 852 if (m_cmd & SPI_RX_ONLY) { 853 /* Unmap rx buffer if duplex transfer */ 854 geni_se_rx_dma_unprep(se, mas->rx_se_dma, xfer->len); 855 mas->rx_se_dma = 0; 856 } 857 goto unlock_and_return; 858 } 859 } 860 } else if (m_cmd & SPI_TX_ONLY) { 861 if (geni_spi_handle_tx(mas)) 862 writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG); 863 } 864 865 unlock_and_return: 866 spin_unlock_irq(&mas->lock); 867 return ret; 868 } 869 870 static int spi_geni_transfer_one(struct spi_master *spi, 871 struct spi_device *slv, 872 struct spi_transfer *xfer) 873 { 874 struct spi_geni_master *mas = spi_master_get_devdata(spi); 875 int ret; 876 877 if (spi_geni_is_abort_still_pending(mas)) 878 return -EBUSY; 879 880 /* Terminate and return success for 0 byte length transfer */ 881 if (!xfer->len) 882 return 0; 883 884 if (mas->cur_xfer_mode == GENI_SE_FIFO || mas->cur_xfer_mode == GENI_SE_DMA) { 885 ret = setup_se_xfer(xfer, mas, slv->mode, spi); 886 /* SPI framework expects +ve ret code to wait for transfer complete */ 887 if (!ret) 888 ret = 1; 889 return ret; 890 } 891 return setup_gsi_xfer(xfer, mas, slv, spi); 892 } 893 894 static irqreturn_t geni_spi_isr(int irq, void *data) 895 { 896 struct spi_master *spi = data; 897 struct spi_geni_master *mas = spi_master_get_devdata(spi); 898 struct geni_se *se = &mas->se; 899 u32 m_irq; 900 901 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); 902 if (!m_irq) 903 return IRQ_NONE; 904 905 if (m_irq & (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN | 906 M_RX_FIFO_RD_ERR_EN | M_RX_FIFO_WR_ERR_EN | 907 M_TX_FIFO_RD_ERR_EN | M_TX_FIFO_WR_ERR_EN)) 908 dev_warn(mas->dev, "Unexpected IRQ err status %#010x\n", m_irq); 909 910 spin_lock(&mas->lock); 911 912 if (mas->cur_xfer_mode == GENI_SE_FIFO) { 913 if ((m_irq & M_RX_FIFO_WATERMARK_EN) || (m_irq & M_RX_FIFO_LAST_EN)) 914 geni_spi_handle_rx(mas); 915 916 if (m_irq & M_TX_FIFO_WATERMARK_EN) 917 geni_spi_handle_tx(mas); 918 919 if (m_irq & M_CMD_DONE_EN) { 920 if (mas->cur_xfer) { 921 spi_finalize_current_transfer(spi); 922 mas->cur_xfer = NULL; 923 /* 924 * If this happens, then a CMD_DONE came before all the 925 * Tx buffer bytes were sent out. This is unusual, log 926 * this condition and disable the WM interrupt to 927 * prevent the system from stalling due an interrupt 928 * storm. 929 * 930 * If this happens when all Rx bytes haven't been 931 * received, log the condition. The only known time 932 * this can happen is if bits_per_word != 8 and some 933 * registers that expect xfer lengths in num spi_words 934 * weren't written correctly. 935 */ 936 if (mas->tx_rem_bytes) { 937 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 938 dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n", 939 mas->tx_rem_bytes, mas->cur_bits_per_word); 940 } 941 if (mas->rx_rem_bytes) 942 dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n", 943 mas->rx_rem_bytes, mas->cur_bits_per_word); 944 } else { 945 complete(&mas->cs_done); 946 } 947 } 948 } else if (mas->cur_xfer_mode == GENI_SE_DMA) { 949 const struct spi_transfer *xfer = mas->cur_xfer; 950 u32 dma_tx_status = readl_relaxed(se->base + SE_DMA_TX_IRQ_STAT); 951 u32 dma_rx_status = readl_relaxed(se->base + SE_DMA_RX_IRQ_STAT); 952 953 if (dma_tx_status) 954 writel(dma_tx_status, se->base + SE_DMA_TX_IRQ_CLR); 955 if (dma_rx_status) 956 writel(dma_rx_status, se->base + SE_DMA_RX_IRQ_CLR); 957 if (dma_tx_status & TX_DMA_DONE) 958 mas->tx_rem_bytes = 0; 959 if (dma_rx_status & RX_DMA_DONE) 960 mas->rx_rem_bytes = 0; 961 if (dma_tx_status & TX_RESET_DONE) 962 complete(&mas->tx_reset_done); 963 if (dma_rx_status & RX_RESET_DONE) 964 complete(&mas->rx_reset_done); 965 if (!mas->tx_rem_bytes && !mas->rx_rem_bytes && xfer) { 966 if (xfer->tx_buf && mas->tx_se_dma) { 967 geni_se_tx_dma_unprep(se, mas->tx_se_dma, xfer->len); 968 mas->tx_se_dma = 0; 969 } 970 if (xfer->rx_buf && mas->rx_se_dma) { 971 geni_se_rx_dma_unprep(se, mas->rx_se_dma, xfer->len); 972 mas->rx_se_dma = 0; 973 } 974 spi_finalize_current_transfer(spi); 975 mas->cur_xfer = NULL; 976 } 977 } 978 979 if (m_irq & M_CMD_CANCEL_EN) 980 complete(&mas->cancel_done); 981 if (m_irq & M_CMD_ABORT_EN) 982 complete(&mas->abort_done); 983 984 /* 985 * It's safe or a good idea to Ack all of our interrupts at the end 986 * of the function. Specifically: 987 * - M_CMD_DONE_EN / M_RX_FIFO_LAST_EN: Edge triggered interrupts and 988 * clearing Acks. Clearing at the end relies on nobody else having 989 * started a new transfer yet or else we could be clearing _their_ 990 * done bit, but everyone grabs the spinlock before starting a new 991 * transfer. 992 * - M_RX_FIFO_WATERMARK_EN / M_TX_FIFO_WATERMARK_EN: These appear 993 * to be "latched level" interrupts so it's important to clear them 994 * _after_ you've handled the condition and always safe to do so 995 * since they'll re-assert if they're still happening. 996 */ 997 writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR); 998 999 spin_unlock(&mas->lock); 1000 1001 return IRQ_HANDLED; 1002 } 1003 1004 static int spi_geni_probe(struct platform_device *pdev) 1005 { 1006 int ret, irq; 1007 struct spi_master *spi; 1008 struct spi_geni_master *mas; 1009 void __iomem *base; 1010 struct clk *clk; 1011 struct device *dev = &pdev->dev; 1012 1013 irq = platform_get_irq(pdev, 0); 1014 if (irq < 0) 1015 return irq; 1016 1017 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); 1018 if (ret) 1019 return dev_err_probe(dev, ret, "could not set DMA mask\n"); 1020 1021 base = devm_platform_ioremap_resource(pdev, 0); 1022 if (IS_ERR(base)) 1023 return PTR_ERR(base); 1024 1025 clk = devm_clk_get(dev, "se"); 1026 if (IS_ERR(clk)) 1027 return PTR_ERR(clk); 1028 1029 spi = devm_spi_alloc_master(dev, sizeof(*mas)); 1030 if (!spi) 1031 return -ENOMEM; 1032 1033 platform_set_drvdata(pdev, spi); 1034 mas = spi_master_get_devdata(spi); 1035 mas->irq = irq; 1036 mas->dev = dev; 1037 mas->se.dev = dev; 1038 mas->se.wrapper = dev_get_drvdata(dev->parent); 1039 mas->se.base = base; 1040 mas->se.clk = clk; 1041 1042 ret = devm_pm_opp_set_clkname(&pdev->dev, "se"); 1043 if (ret) 1044 return ret; 1045 /* OPP table is optional */ 1046 ret = devm_pm_opp_of_add_table(&pdev->dev); 1047 if (ret && ret != -ENODEV) { 1048 dev_err(&pdev->dev, "invalid OPP table in device tree\n"); 1049 return ret; 1050 } 1051 1052 spi->bus_num = -1; 1053 spi->dev.of_node = dev->of_node; 1054 spi->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH; 1055 spi->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1056 spi->num_chipselect = 4; 1057 spi->max_speed_hz = 50000000; 1058 spi->prepare_message = spi_geni_prepare_message; 1059 spi->transfer_one = spi_geni_transfer_one; 1060 spi->can_dma = geni_can_dma; 1061 spi->dma_map_dev = dev->parent; 1062 spi->auto_runtime_pm = true; 1063 spi->handle_err = spi_geni_handle_err; 1064 spi->use_gpio_descriptors = true; 1065 1066 init_completion(&mas->cs_done); 1067 init_completion(&mas->cancel_done); 1068 init_completion(&mas->abort_done); 1069 init_completion(&mas->tx_reset_done); 1070 init_completion(&mas->rx_reset_done); 1071 spin_lock_init(&mas->lock); 1072 pm_runtime_use_autosuspend(&pdev->dev); 1073 pm_runtime_set_autosuspend_delay(&pdev->dev, 250); 1074 pm_runtime_enable(dev); 1075 1076 ret = geni_icc_get(&mas->se, NULL); 1077 if (ret) 1078 goto spi_geni_probe_runtime_disable; 1079 /* Set the bus quota to a reasonable value for register access */ 1080 mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ); 1081 mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; 1082 1083 ret = geni_icc_set_bw(&mas->se); 1084 if (ret) 1085 goto spi_geni_probe_runtime_disable; 1086 1087 ret = spi_geni_init(mas); 1088 if (ret) 1089 goto spi_geni_probe_runtime_disable; 1090 1091 /* 1092 * check the mode supported and set_cs for fifo mode only 1093 * for dma (gsi) mode, the gsi will set cs based on params passed in 1094 * TRE 1095 */ 1096 if (mas->cur_xfer_mode == GENI_SE_FIFO) 1097 spi->set_cs = spi_geni_set_cs; 1098 1099 ret = request_irq(mas->irq, geni_spi_isr, 0, dev_name(dev), spi); 1100 if (ret) 1101 goto spi_geni_release_dma; 1102 1103 ret = spi_register_master(spi); 1104 if (ret) 1105 goto spi_geni_probe_free_irq; 1106 1107 return 0; 1108 spi_geni_probe_free_irq: 1109 free_irq(mas->irq, spi); 1110 spi_geni_release_dma: 1111 spi_geni_release_dma_chan(mas); 1112 spi_geni_probe_runtime_disable: 1113 pm_runtime_disable(dev); 1114 return ret; 1115 } 1116 1117 static int spi_geni_remove(struct platform_device *pdev) 1118 { 1119 struct spi_master *spi = platform_get_drvdata(pdev); 1120 struct spi_geni_master *mas = spi_master_get_devdata(spi); 1121 1122 /* Unregister _before_ disabling pm_runtime() so we stop transfers */ 1123 spi_unregister_master(spi); 1124 1125 spi_geni_release_dma_chan(mas); 1126 1127 free_irq(mas->irq, spi); 1128 pm_runtime_disable(&pdev->dev); 1129 return 0; 1130 } 1131 1132 static int __maybe_unused spi_geni_runtime_suspend(struct device *dev) 1133 { 1134 struct spi_master *spi = dev_get_drvdata(dev); 1135 struct spi_geni_master *mas = spi_master_get_devdata(spi); 1136 int ret; 1137 1138 /* Drop the performance state vote */ 1139 dev_pm_opp_set_rate(dev, 0); 1140 1141 ret = geni_se_resources_off(&mas->se); 1142 if (ret) 1143 return ret; 1144 1145 return geni_icc_disable(&mas->se); 1146 } 1147 1148 static int __maybe_unused spi_geni_runtime_resume(struct device *dev) 1149 { 1150 struct spi_master *spi = dev_get_drvdata(dev); 1151 struct spi_geni_master *mas = spi_master_get_devdata(spi); 1152 int ret; 1153 1154 ret = geni_icc_enable(&mas->se); 1155 if (ret) 1156 return ret; 1157 1158 ret = geni_se_resources_on(&mas->se); 1159 if (ret) 1160 return ret; 1161 1162 return dev_pm_opp_set_rate(mas->dev, mas->cur_sclk_hz); 1163 } 1164 1165 static int __maybe_unused spi_geni_suspend(struct device *dev) 1166 { 1167 struct spi_master *spi = dev_get_drvdata(dev); 1168 int ret; 1169 1170 ret = spi_master_suspend(spi); 1171 if (ret) 1172 return ret; 1173 1174 ret = pm_runtime_force_suspend(dev); 1175 if (ret) 1176 spi_master_resume(spi); 1177 1178 return ret; 1179 } 1180 1181 static int __maybe_unused spi_geni_resume(struct device *dev) 1182 { 1183 struct spi_master *spi = dev_get_drvdata(dev); 1184 int ret; 1185 1186 ret = pm_runtime_force_resume(dev); 1187 if (ret) 1188 return ret; 1189 1190 ret = spi_master_resume(spi); 1191 if (ret) 1192 pm_runtime_force_suspend(dev); 1193 1194 return ret; 1195 } 1196 1197 static const struct dev_pm_ops spi_geni_pm_ops = { 1198 SET_RUNTIME_PM_OPS(spi_geni_runtime_suspend, 1199 spi_geni_runtime_resume, NULL) 1200 SET_SYSTEM_SLEEP_PM_OPS(spi_geni_suspend, spi_geni_resume) 1201 }; 1202 1203 static const struct of_device_id spi_geni_dt_match[] = { 1204 { .compatible = "qcom,geni-spi" }, 1205 {} 1206 }; 1207 MODULE_DEVICE_TABLE(of, spi_geni_dt_match); 1208 1209 static struct platform_driver spi_geni_driver = { 1210 .probe = spi_geni_probe, 1211 .remove = spi_geni_remove, 1212 .driver = { 1213 .name = "geni_spi", 1214 .pm = &spi_geni_pm_ops, 1215 .of_match_table = spi_geni_dt_match, 1216 }, 1217 }; 1218 module_platform_driver(spi_geni_driver); 1219 1220 MODULE_DESCRIPTION("SPI driver for GENI based QUP cores"); 1221 MODULE_LICENSE("GPL v2"); 1222