1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved. 3 4 #include <linux/clk.h> 5 #include <linux/dmaengine.h> 6 #include <linux/dma-mapping.h> 7 #include <linux/dma/qcom-gpi-dma.h> 8 #include <linux/interrupt.h> 9 #include <linux/io.h> 10 #include <linux/log2.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm_opp.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/soc/qcom/geni-se.h> 16 #include <linux/spi/spi.h> 17 #include <linux/spinlock.h> 18 19 /* SPI SE specific registers and respective register fields */ 20 #define SE_SPI_CPHA 0x224 21 #define CPHA BIT(0) 22 23 #define SE_SPI_LOOPBACK 0x22c 24 #define LOOPBACK_ENABLE 0x1 25 #define NORMAL_MODE 0x0 26 #define LOOPBACK_MSK GENMASK(1, 0) 27 28 #define SE_SPI_CPOL 0x230 29 #define CPOL BIT(2) 30 31 #define SE_SPI_DEMUX_OUTPUT_INV 0x24c 32 #define CS_DEMUX_OUTPUT_INV_MSK GENMASK(3, 0) 33 34 #define SE_SPI_DEMUX_SEL 0x250 35 #define CS_DEMUX_OUTPUT_SEL GENMASK(3, 0) 36 37 #define SE_SPI_TRANS_CFG 0x25c 38 #define CS_TOGGLE BIT(0) 39 40 #define SE_SPI_WORD_LEN 0x268 41 #define WORD_LEN_MSK GENMASK(9, 0) 42 #define MIN_WORD_LEN 4 43 44 #define SE_SPI_TX_TRANS_LEN 0x26c 45 #define SE_SPI_RX_TRANS_LEN 0x270 46 #define TRANS_LEN_MSK GENMASK(23, 0) 47 48 #define SE_SPI_PRE_POST_CMD_DLY 0x274 49 50 #define SE_SPI_DELAY_COUNTERS 0x278 51 #define SPI_INTER_WORDS_DELAY_MSK GENMASK(9, 0) 52 #define SPI_CS_CLK_DELAY_MSK GENMASK(19, 10) 53 #define SPI_CS_CLK_DELAY_SHFT 10 54 55 /* M_CMD OP codes for SPI */ 56 #define SPI_TX_ONLY 1 57 #define SPI_RX_ONLY 2 58 #define SPI_TX_RX 7 59 #define SPI_CS_ASSERT 8 60 #define SPI_CS_DEASSERT 9 61 #define SPI_SCK_ONLY 10 62 /* M_CMD params for SPI */ 63 #define SPI_PRE_CMD_DELAY BIT(0) 64 #define TIMESTAMP_BEFORE BIT(1) 65 #define FRAGMENTATION BIT(2) 66 #define TIMESTAMP_AFTER BIT(3) 67 #define POST_CMD_DELAY BIT(4) 68 69 #define GSI_LOOPBACK_EN BIT(0) 70 #define GSI_CS_TOGGLE BIT(3) 71 #define GSI_CPHA BIT(4) 72 #define GSI_CPOL BIT(5) 73 74 struct spi_geni_master { 75 struct geni_se se; 76 struct device *dev; 77 u32 tx_fifo_depth; 78 u32 fifo_width_bits; 79 u32 tx_wm; 80 u32 last_mode; 81 unsigned long cur_speed_hz; 82 unsigned long cur_sclk_hz; 83 unsigned int cur_bits_per_word; 84 unsigned int tx_rem_bytes; 85 unsigned int rx_rem_bytes; 86 const struct spi_transfer *cur_xfer; 87 struct completion cs_done; 88 struct completion cancel_done; 89 struct completion abort_done; 90 struct completion tx_reset_done; 91 struct completion rx_reset_done; 92 unsigned int oversampling; 93 spinlock_t lock; 94 int irq; 95 bool cs_flag; 96 bool abort_failed; 97 struct dma_chan *tx; 98 struct dma_chan *rx; 99 int cur_xfer_mode; 100 dma_addr_t tx_se_dma; 101 dma_addr_t rx_se_dma; 102 }; 103 104 static int get_spi_clk_cfg(unsigned int speed_hz, 105 struct spi_geni_master *mas, 106 unsigned int *clk_idx, 107 unsigned int *clk_div) 108 { 109 unsigned long sclk_freq; 110 unsigned int actual_hz; 111 int ret; 112 113 ret = geni_se_clk_freq_match(&mas->se, 114 speed_hz * mas->oversampling, 115 clk_idx, &sclk_freq, false); 116 if (ret) { 117 dev_err(mas->dev, "Failed(%d) to find src clk for %dHz\n", 118 ret, speed_hz); 119 return ret; 120 } 121 122 *clk_div = DIV_ROUND_UP(sclk_freq, mas->oversampling * speed_hz); 123 actual_hz = sclk_freq / (mas->oversampling * *clk_div); 124 125 dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz, 126 actual_hz, sclk_freq, *clk_idx, *clk_div); 127 ret = dev_pm_opp_set_rate(mas->dev, sclk_freq); 128 if (ret) 129 dev_err(mas->dev, "dev_pm_opp_set_rate failed %d\n", ret); 130 else 131 mas->cur_sclk_hz = sclk_freq; 132 133 return ret; 134 } 135 136 static void handle_se_timeout(struct spi_master *spi, 137 struct spi_message *msg) 138 { 139 struct spi_geni_master *mas = spi_master_get_devdata(spi); 140 unsigned long time_left; 141 struct geni_se *se = &mas->se; 142 const struct spi_transfer *xfer; 143 144 spin_lock_irq(&mas->lock); 145 reinit_completion(&mas->cancel_done); 146 if (mas->cur_xfer_mode == GENI_SE_FIFO) 147 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 148 149 xfer = mas->cur_xfer; 150 mas->cur_xfer = NULL; 151 geni_se_cancel_m_cmd(se); 152 spin_unlock_irq(&mas->lock); 153 154 time_left = wait_for_completion_timeout(&mas->cancel_done, HZ); 155 if (time_left) 156 goto unmap_if_dma; 157 158 spin_lock_irq(&mas->lock); 159 reinit_completion(&mas->abort_done); 160 geni_se_abort_m_cmd(se); 161 spin_unlock_irq(&mas->lock); 162 163 time_left = wait_for_completion_timeout(&mas->abort_done, HZ); 164 if (!time_left) { 165 dev_err(mas->dev, "Failed to cancel/abort m_cmd\n"); 166 167 /* 168 * No need for a lock since SPI core has a lock and we never 169 * access this from an interrupt. 170 */ 171 mas->abort_failed = true; 172 } 173 174 unmap_if_dma: 175 if (mas->cur_xfer_mode == GENI_SE_DMA) { 176 if (xfer) { 177 if (xfer->tx_buf && mas->tx_se_dma) { 178 spin_lock_irq(&mas->lock); 179 reinit_completion(&mas->tx_reset_done); 180 writel(1, se->base + SE_DMA_TX_FSM_RST); 181 spin_unlock_irq(&mas->lock); 182 time_left = wait_for_completion_timeout(&mas->tx_reset_done, HZ); 183 if (!time_left) 184 dev_err(mas->dev, "DMA TX RESET failed\n"); 185 geni_se_tx_dma_unprep(se, mas->tx_se_dma, xfer->len); 186 } 187 if (xfer->rx_buf && mas->rx_se_dma) { 188 spin_lock_irq(&mas->lock); 189 reinit_completion(&mas->rx_reset_done); 190 writel(1, se->base + SE_DMA_RX_FSM_RST); 191 spin_unlock_irq(&mas->lock); 192 time_left = wait_for_completion_timeout(&mas->rx_reset_done, HZ); 193 if (!time_left) 194 dev_err(mas->dev, "DMA RX RESET failed\n"); 195 geni_se_rx_dma_unprep(se, mas->rx_se_dma, xfer->len); 196 } 197 } else { 198 /* 199 * This can happen if a timeout happened and we had to wait 200 * for lock in this function because isr was holding the lock 201 * and handling transfer completion at that time. 202 */ 203 dev_warn(mas->dev, "Cancel/Abort on completed SPI transfer\n"); 204 } 205 } 206 } 207 208 static void handle_gpi_timeout(struct spi_master *spi, struct spi_message *msg) 209 { 210 struct spi_geni_master *mas = spi_master_get_devdata(spi); 211 212 dmaengine_terminate_sync(mas->tx); 213 dmaengine_terminate_sync(mas->rx); 214 } 215 216 static void spi_geni_handle_err(struct spi_master *spi, struct spi_message *msg) 217 { 218 struct spi_geni_master *mas = spi_master_get_devdata(spi); 219 220 switch (mas->cur_xfer_mode) { 221 case GENI_SE_FIFO: 222 case GENI_SE_DMA: 223 handle_se_timeout(spi, msg); 224 break; 225 case GENI_GPI_DMA: 226 handle_gpi_timeout(spi, msg); 227 break; 228 default: 229 dev_err(mas->dev, "Abort on Mode:%d not supported", mas->cur_xfer_mode); 230 } 231 } 232 233 static bool spi_geni_is_abort_still_pending(struct spi_geni_master *mas) 234 { 235 struct geni_se *se = &mas->se; 236 u32 m_irq, m_irq_en; 237 238 if (!mas->abort_failed) 239 return false; 240 241 /* 242 * The only known case where a transfer times out and then a cancel 243 * times out then an abort times out is if something is blocking our 244 * interrupt handler from running. Avoid starting any new transfers 245 * until that sorts itself out. 246 */ 247 spin_lock_irq(&mas->lock); 248 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); 249 m_irq_en = readl(se->base + SE_GENI_M_IRQ_EN); 250 spin_unlock_irq(&mas->lock); 251 252 if (m_irq & m_irq_en) { 253 dev_err(mas->dev, "Interrupts pending after abort: %#010x\n", 254 m_irq & m_irq_en); 255 return true; 256 } 257 258 /* 259 * If we're here the problem resolved itself so no need to check more 260 * on future transfers. 261 */ 262 mas->abort_failed = false; 263 264 return false; 265 } 266 267 static void spi_geni_set_cs(struct spi_device *slv, bool set_flag) 268 { 269 struct spi_geni_master *mas = spi_master_get_devdata(slv->master); 270 struct spi_master *spi = dev_get_drvdata(mas->dev); 271 struct geni_se *se = &mas->se; 272 unsigned long time_left; 273 274 if (!(slv->mode & SPI_CS_HIGH)) 275 set_flag = !set_flag; 276 277 if (set_flag == mas->cs_flag) 278 return; 279 280 pm_runtime_get_sync(mas->dev); 281 282 if (spi_geni_is_abort_still_pending(mas)) { 283 dev_err(mas->dev, "Can't set chip select\n"); 284 goto exit; 285 } 286 287 spin_lock_irq(&mas->lock); 288 if (mas->cur_xfer) { 289 dev_err(mas->dev, "Can't set CS when prev xfer running\n"); 290 spin_unlock_irq(&mas->lock); 291 goto exit; 292 } 293 294 mas->cs_flag = set_flag; 295 /* set xfer_mode to FIFO to complete cs_done in isr */ 296 mas->cur_xfer_mode = GENI_SE_FIFO; 297 geni_se_select_mode(se, mas->cur_xfer_mode); 298 299 reinit_completion(&mas->cs_done); 300 if (set_flag) 301 geni_se_setup_m_cmd(se, SPI_CS_ASSERT, 0); 302 else 303 geni_se_setup_m_cmd(se, SPI_CS_DEASSERT, 0); 304 spin_unlock_irq(&mas->lock); 305 306 time_left = wait_for_completion_timeout(&mas->cs_done, HZ); 307 if (!time_left) { 308 dev_warn(mas->dev, "Timeout setting chip select\n"); 309 handle_se_timeout(spi, NULL); 310 } 311 312 exit: 313 pm_runtime_put(mas->dev); 314 } 315 316 static void spi_setup_word_len(struct spi_geni_master *mas, u16 mode, 317 unsigned int bits_per_word) 318 { 319 unsigned int pack_words; 320 bool msb_first = (mode & SPI_LSB_FIRST) ? false : true; 321 struct geni_se *se = &mas->se; 322 u32 word_len; 323 324 /* 325 * If bits_per_word isn't a byte aligned value, set the packing to be 326 * 1 SPI word per FIFO word. 327 */ 328 if (!(mas->fifo_width_bits % bits_per_word)) 329 pack_words = mas->fifo_width_bits / bits_per_word; 330 else 331 pack_words = 1; 332 geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first, 333 true, true); 334 word_len = (bits_per_word - MIN_WORD_LEN) & WORD_LEN_MSK; 335 writel(word_len, se->base + SE_SPI_WORD_LEN); 336 } 337 338 static int geni_spi_set_clock_and_bw(struct spi_geni_master *mas, 339 unsigned long clk_hz) 340 { 341 u32 clk_sel, m_clk_cfg, idx, div; 342 struct geni_se *se = &mas->se; 343 int ret; 344 345 if (clk_hz == mas->cur_speed_hz) 346 return 0; 347 348 ret = get_spi_clk_cfg(clk_hz, mas, &idx, &div); 349 if (ret) { 350 dev_err(mas->dev, "Err setting clk to %lu: %d\n", clk_hz, ret); 351 return ret; 352 } 353 354 /* 355 * SPI core clock gets configured with the requested frequency 356 * or the frequency closer to the requested frequency. 357 * For that reason requested frequency is stored in the 358 * cur_speed_hz and referred in the consecutive transfer instead 359 * of calling clk_get_rate() API. 360 */ 361 mas->cur_speed_hz = clk_hz; 362 363 clk_sel = idx & CLK_SEL_MSK; 364 m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN; 365 writel(clk_sel, se->base + SE_GENI_CLK_SEL); 366 writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG); 367 368 /* Set BW quota for CPU as driver supports FIFO mode only. */ 369 se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz); 370 ret = geni_icc_set_bw(se); 371 if (ret) 372 return ret; 373 374 return 0; 375 } 376 377 static int setup_fifo_params(struct spi_device *spi_slv, 378 struct spi_master *spi) 379 { 380 struct spi_geni_master *mas = spi_master_get_devdata(spi); 381 struct geni_se *se = &mas->se; 382 u32 loopback_cfg = 0, cpol = 0, cpha = 0, demux_output_inv = 0; 383 u32 demux_sel; 384 385 if (mas->last_mode != spi_slv->mode) { 386 if (spi_slv->mode & SPI_LOOP) 387 loopback_cfg = LOOPBACK_ENABLE; 388 389 if (spi_slv->mode & SPI_CPOL) 390 cpol = CPOL; 391 392 if (spi_slv->mode & SPI_CPHA) 393 cpha = CPHA; 394 395 if (spi_slv->mode & SPI_CS_HIGH) 396 demux_output_inv = BIT(spi_get_chipselect(spi_slv, 0)); 397 398 demux_sel = spi_get_chipselect(spi_slv, 0); 399 mas->cur_bits_per_word = spi_slv->bits_per_word; 400 401 spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word); 402 writel(loopback_cfg, se->base + SE_SPI_LOOPBACK); 403 writel(demux_sel, se->base + SE_SPI_DEMUX_SEL); 404 writel(cpha, se->base + SE_SPI_CPHA); 405 writel(cpol, se->base + SE_SPI_CPOL); 406 writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV); 407 408 mas->last_mode = spi_slv->mode; 409 } 410 411 return geni_spi_set_clock_and_bw(mas, spi_slv->max_speed_hz); 412 } 413 414 static void 415 spi_gsi_callback_result(void *cb, const struct dmaengine_result *result) 416 { 417 struct spi_master *spi = cb; 418 419 spi->cur_msg->status = -EIO; 420 if (result->result != DMA_TRANS_NOERROR) { 421 dev_err(&spi->dev, "DMA txn failed: %d\n", result->result); 422 spi_finalize_current_transfer(spi); 423 return; 424 } 425 426 if (!result->residue) { 427 spi->cur_msg->status = 0; 428 dev_dbg(&spi->dev, "DMA txn completed\n"); 429 } else { 430 dev_err(&spi->dev, "DMA xfer has pending: %d\n", result->residue); 431 } 432 433 spi_finalize_current_transfer(spi); 434 } 435 436 static int setup_gsi_xfer(struct spi_transfer *xfer, struct spi_geni_master *mas, 437 struct spi_device *spi_slv, struct spi_master *spi) 438 { 439 unsigned long flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK; 440 struct dma_slave_config config = {}; 441 struct gpi_spi_config peripheral = {}; 442 struct dma_async_tx_descriptor *tx_desc, *rx_desc; 443 int ret; 444 445 config.peripheral_config = &peripheral; 446 config.peripheral_size = sizeof(peripheral); 447 peripheral.set_config = true; 448 449 if (xfer->bits_per_word != mas->cur_bits_per_word || 450 xfer->speed_hz != mas->cur_speed_hz) { 451 mas->cur_bits_per_word = xfer->bits_per_word; 452 mas->cur_speed_hz = xfer->speed_hz; 453 } 454 455 if (xfer->tx_buf && xfer->rx_buf) { 456 peripheral.cmd = SPI_DUPLEX; 457 } else if (xfer->tx_buf) { 458 peripheral.cmd = SPI_TX; 459 peripheral.rx_len = 0; 460 } else if (xfer->rx_buf) { 461 peripheral.cmd = SPI_RX; 462 if (!(mas->cur_bits_per_word % MIN_WORD_LEN)) { 463 peripheral.rx_len = ((xfer->len << 3) / mas->cur_bits_per_word); 464 } else { 465 int bytes_per_word = (mas->cur_bits_per_word / BITS_PER_BYTE) + 1; 466 467 peripheral.rx_len = (xfer->len / bytes_per_word); 468 } 469 } 470 471 peripheral.loopback_en = !!(spi_slv->mode & SPI_LOOP); 472 peripheral.clock_pol_high = !!(spi_slv->mode & SPI_CPOL); 473 peripheral.data_pol_high = !!(spi_slv->mode & SPI_CPHA); 474 peripheral.cs = spi_get_chipselect(spi_slv, 0); 475 peripheral.pack_en = true; 476 peripheral.word_len = xfer->bits_per_word - MIN_WORD_LEN; 477 478 ret = get_spi_clk_cfg(mas->cur_speed_hz, mas, 479 &peripheral.clk_src, &peripheral.clk_div); 480 if (ret) { 481 dev_err(mas->dev, "Err in get_spi_clk_cfg() :%d\n", ret); 482 return ret; 483 } 484 485 if (!xfer->cs_change) { 486 if (!list_is_last(&xfer->transfer_list, &spi->cur_msg->transfers)) 487 peripheral.fragmentation = FRAGMENTATION; 488 } 489 490 if (peripheral.cmd & SPI_RX) { 491 dmaengine_slave_config(mas->rx, &config); 492 rx_desc = dmaengine_prep_slave_sg(mas->rx, xfer->rx_sg.sgl, xfer->rx_sg.nents, 493 DMA_DEV_TO_MEM, flags); 494 if (!rx_desc) { 495 dev_err(mas->dev, "Err setting up rx desc\n"); 496 return -EIO; 497 } 498 } 499 500 /* 501 * Prepare the TX always, even for RX or tx_buf being null, we would 502 * need TX to be prepared per GSI spec 503 */ 504 dmaengine_slave_config(mas->tx, &config); 505 tx_desc = dmaengine_prep_slave_sg(mas->tx, xfer->tx_sg.sgl, xfer->tx_sg.nents, 506 DMA_MEM_TO_DEV, flags); 507 if (!tx_desc) { 508 dev_err(mas->dev, "Err setting up tx desc\n"); 509 return -EIO; 510 } 511 512 tx_desc->callback_result = spi_gsi_callback_result; 513 tx_desc->callback_param = spi; 514 515 if (peripheral.cmd & SPI_RX) 516 dmaengine_submit(rx_desc); 517 dmaengine_submit(tx_desc); 518 519 if (peripheral.cmd & SPI_RX) 520 dma_async_issue_pending(mas->rx); 521 522 dma_async_issue_pending(mas->tx); 523 return 1; 524 } 525 526 static bool geni_can_dma(struct spi_controller *ctlr, 527 struct spi_device *slv, struct spi_transfer *xfer) 528 { 529 struct spi_geni_master *mas = spi_master_get_devdata(slv->master); 530 531 /* 532 * Return true if transfer needs to be mapped prior to 533 * calling transfer_one which is the case only for GPI_DMA. 534 * For SE_DMA mode, map/unmap is done in geni_se_*x_dma_prep. 535 */ 536 return mas->cur_xfer_mode == GENI_GPI_DMA; 537 } 538 539 static int spi_geni_prepare_message(struct spi_master *spi, 540 struct spi_message *spi_msg) 541 { 542 struct spi_geni_master *mas = spi_master_get_devdata(spi); 543 int ret; 544 545 switch (mas->cur_xfer_mode) { 546 case GENI_SE_FIFO: 547 case GENI_SE_DMA: 548 if (spi_geni_is_abort_still_pending(mas)) 549 return -EBUSY; 550 ret = setup_fifo_params(spi_msg->spi, spi); 551 if (ret) 552 dev_err(mas->dev, "Couldn't select mode %d\n", ret); 553 return ret; 554 555 case GENI_GPI_DMA: 556 /* nothing to do for GPI DMA */ 557 return 0; 558 } 559 560 dev_err(mas->dev, "Mode not supported %d", mas->cur_xfer_mode); 561 return -EINVAL; 562 } 563 564 static int spi_geni_grab_gpi_chan(struct spi_geni_master *mas) 565 { 566 int ret; 567 568 mas->tx = dma_request_chan(mas->dev, "tx"); 569 if (IS_ERR(mas->tx)) { 570 ret = dev_err_probe(mas->dev, PTR_ERR(mas->tx), 571 "Failed to get tx DMA ch\n"); 572 goto err_tx; 573 } 574 575 mas->rx = dma_request_chan(mas->dev, "rx"); 576 if (IS_ERR(mas->rx)) { 577 ret = dev_err_probe(mas->dev, PTR_ERR(mas->rx), 578 "Failed to get rx DMA ch\n"); 579 goto err_rx; 580 } 581 582 return 0; 583 584 err_rx: 585 mas->rx = NULL; 586 dma_release_channel(mas->tx); 587 err_tx: 588 mas->tx = NULL; 589 return ret; 590 } 591 592 static void spi_geni_release_dma_chan(struct spi_geni_master *mas) 593 { 594 if (mas->rx) { 595 dma_release_channel(mas->rx); 596 mas->rx = NULL; 597 } 598 599 if (mas->tx) { 600 dma_release_channel(mas->tx); 601 mas->tx = NULL; 602 } 603 } 604 605 static int spi_geni_init(struct spi_geni_master *mas) 606 { 607 struct geni_se *se = &mas->se; 608 unsigned int proto, major, minor, ver; 609 u32 spi_tx_cfg, fifo_disable; 610 int ret = -ENXIO; 611 612 pm_runtime_get_sync(mas->dev); 613 614 proto = geni_se_read_proto(se); 615 if (proto != GENI_SE_SPI) { 616 dev_err(mas->dev, "Invalid proto %d\n", proto); 617 goto out_pm; 618 } 619 mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se); 620 621 /* Width of Tx and Rx FIFO is same */ 622 mas->fifo_width_bits = geni_se_get_tx_fifo_width(se); 623 624 /* 625 * Hardware programming guide suggests to configure 626 * RX FIFO RFR level to fifo_depth-2. 627 */ 628 geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2); 629 /* Transmit an entire FIFO worth of data per IRQ */ 630 mas->tx_wm = 1; 631 ver = geni_se_get_qup_hw_version(se); 632 major = GENI_SE_VERSION_MAJOR(ver); 633 minor = GENI_SE_VERSION_MINOR(ver); 634 635 if (major == 1 && minor == 0) 636 mas->oversampling = 2; 637 else 638 mas->oversampling = 1; 639 640 fifo_disable = readl(se->base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE; 641 switch (fifo_disable) { 642 case 1: 643 ret = spi_geni_grab_gpi_chan(mas); 644 if (!ret) { /* success case */ 645 mas->cur_xfer_mode = GENI_GPI_DMA; 646 geni_se_select_mode(se, GENI_GPI_DMA); 647 dev_dbg(mas->dev, "Using GPI DMA mode for SPI\n"); 648 break; 649 } 650 /* 651 * in case of failure to get gpi dma channel, we can still do the 652 * FIFO mode, so fallthrough 653 */ 654 dev_warn(mas->dev, "FIFO mode disabled, but couldn't get DMA, fall back to FIFO mode\n"); 655 fallthrough; 656 657 case 0: 658 mas->cur_xfer_mode = GENI_SE_FIFO; 659 geni_se_select_mode(se, GENI_SE_FIFO); 660 ret = 0; 661 break; 662 } 663 664 /* We always control CS manually */ 665 spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG); 666 spi_tx_cfg &= ~CS_TOGGLE; 667 writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG); 668 669 out_pm: 670 pm_runtime_put(mas->dev); 671 return ret; 672 } 673 674 static unsigned int geni_byte_per_fifo_word(struct spi_geni_master *mas) 675 { 676 /* 677 * Calculate how many bytes we'll put in each FIFO word. If the 678 * transfer words don't pack cleanly into a FIFO word we'll just put 679 * one transfer word in each FIFO word. If they do pack we'll pack 'em. 680 */ 681 if (mas->fifo_width_bits % mas->cur_bits_per_word) 682 return roundup_pow_of_two(DIV_ROUND_UP(mas->cur_bits_per_word, 683 BITS_PER_BYTE)); 684 685 return mas->fifo_width_bits / BITS_PER_BYTE; 686 } 687 688 static bool geni_spi_handle_tx(struct spi_geni_master *mas) 689 { 690 struct geni_se *se = &mas->se; 691 unsigned int max_bytes; 692 const u8 *tx_buf; 693 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas); 694 unsigned int i = 0; 695 696 /* Stop the watermark IRQ if nothing to send */ 697 if (!mas->cur_xfer) { 698 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 699 return false; 700 } 701 702 max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * bytes_per_fifo_word; 703 if (mas->tx_rem_bytes < max_bytes) 704 max_bytes = mas->tx_rem_bytes; 705 706 tx_buf = mas->cur_xfer->tx_buf + mas->cur_xfer->len - mas->tx_rem_bytes; 707 while (i < max_bytes) { 708 unsigned int j; 709 unsigned int bytes_to_write; 710 u32 fifo_word = 0; 711 u8 *fifo_byte = (u8 *)&fifo_word; 712 713 bytes_to_write = min(bytes_per_fifo_word, max_bytes - i); 714 for (j = 0; j < bytes_to_write; j++) 715 fifo_byte[j] = tx_buf[i++]; 716 iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1); 717 } 718 mas->tx_rem_bytes -= max_bytes; 719 if (!mas->tx_rem_bytes) { 720 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 721 return false; 722 } 723 return true; 724 } 725 726 static void geni_spi_handle_rx(struct spi_geni_master *mas) 727 { 728 struct geni_se *se = &mas->se; 729 u32 rx_fifo_status; 730 unsigned int rx_bytes; 731 unsigned int rx_last_byte_valid; 732 u8 *rx_buf; 733 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas); 734 unsigned int i = 0; 735 736 rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS); 737 rx_bytes = (rx_fifo_status & RX_FIFO_WC_MSK) * bytes_per_fifo_word; 738 if (rx_fifo_status & RX_LAST) { 739 rx_last_byte_valid = rx_fifo_status & RX_LAST_BYTE_VALID_MSK; 740 rx_last_byte_valid >>= RX_LAST_BYTE_VALID_SHFT; 741 if (rx_last_byte_valid && rx_last_byte_valid < 4) 742 rx_bytes -= bytes_per_fifo_word - rx_last_byte_valid; 743 } 744 745 /* Clear out the FIFO and bail if nowhere to put it */ 746 if (!mas->cur_xfer) { 747 for (i = 0; i < DIV_ROUND_UP(rx_bytes, bytes_per_fifo_word); i++) 748 readl(se->base + SE_GENI_RX_FIFOn); 749 return; 750 } 751 752 if (mas->rx_rem_bytes < rx_bytes) 753 rx_bytes = mas->rx_rem_bytes; 754 755 rx_buf = mas->cur_xfer->rx_buf + mas->cur_xfer->len - mas->rx_rem_bytes; 756 while (i < rx_bytes) { 757 u32 fifo_word = 0; 758 u8 *fifo_byte = (u8 *)&fifo_word; 759 unsigned int bytes_to_read; 760 unsigned int j; 761 762 bytes_to_read = min(bytes_per_fifo_word, rx_bytes - i); 763 ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1); 764 for (j = 0; j < bytes_to_read; j++) 765 rx_buf[i++] = fifo_byte[j]; 766 } 767 mas->rx_rem_bytes -= rx_bytes; 768 } 769 770 static int setup_se_xfer(struct spi_transfer *xfer, 771 struct spi_geni_master *mas, 772 u16 mode, struct spi_master *spi) 773 { 774 u32 m_cmd = 0; 775 u32 len, fifo_size; 776 struct geni_se *se = &mas->se; 777 int ret; 778 779 /* 780 * Ensure that our interrupt handler isn't still running from some 781 * prior command before we start messing with the hardware behind 782 * its back. We don't need to _keep_ the lock here since we're only 783 * worried about racing with out interrupt handler. The SPI core 784 * already handles making sure that we're not trying to do two 785 * transfers at once or setting a chip select and doing a transfer 786 * concurrently. 787 * 788 * NOTE: we actually _can't_ hold the lock here because possibly we 789 * might call clk_set_rate() which needs to be able to sleep. 790 */ 791 spin_lock_irq(&mas->lock); 792 spin_unlock_irq(&mas->lock); 793 794 if (xfer->bits_per_word != mas->cur_bits_per_word) { 795 spi_setup_word_len(mas, mode, xfer->bits_per_word); 796 mas->cur_bits_per_word = xfer->bits_per_word; 797 } 798 799 /* Speed and bits per word can be overridden per transfer */ 800 ret = geni_spi_set_clock_and_bw(mas, xfer->speed_hz); 801 if (ret) 802 return ret; 803 804 mas->tx_rem_bytes = 0; 805 mas->rx_rem_bytes = 0; 806 807 if (!(mas->cur_bits_per_word % MIN_WORD_LEN)) 808 len = xfer->len * BITS_PER_BYTE / mas->cur_bits_per_word; 809 else 810 len = xfer->len / (mas->cur_bits_per_word / BITS_PER_BYTE + 1); 811 len &= TRANS_LEN_MSK; 812 813 mas->cur_xfer = xfer; 814 if (xfer->tx_buf) { 815 m_cmd |= SPI_TX_ONLY; 816 mas->tx_rem_bytes = xfer->len; 817 writel(len, se->base + SE_SPI_TX_TRANS_LEN); 818 } 819 820 if (xfer->rx_buf) { 821 m_cmd |= SPI_RX_ONLY; 822 writel(len, se->base + SE_SPI_RX_TRANS_LEN); 823 mas->rx_rem_bytes = xfer->len; 824 } 825 826 /* Select transfer mode based on transfer length */ 827 fifo_size = mas->tx_fifo_depth * mas->fifo_width_bits / mas->cur_bits_per_word; 828 mas->cur_xfer_mode = (len <= fifo_size) ? GENI_SE_FIFO : GENI_SE_DMA; 829 geni_se_select_mode(se, mas->cur_xfer_mode); 830 831 /* 832 * Lock around right before we start the transfer since our 833 * interrupt could come in at any time now. 834 */ 835 spin_lock_irq(&mas->lock); 836 geni_se_setup_m_cmd(se, m_cmd, FRAGMENTATION); 837 838 if (mas->cur_xfer_mode == GENI_SE_DMA) { 839 if (m_cmd & SPI_RX_ONLY) { 840 ret = geni_se_rx_dma_prep(se, xfer->rx_buf, 841 xfer->len, &mas->rx_se_dma); 842 if (ret) { 843 dev_err(mas->dev, "Failed to setup Rx dma %d\n", ret); 844 mas->rx_se_dma = 0; 845 goto unlock_and_return; 846 } 847 } 848 if (m_cmd & SPI_TX_ONLY) { 849 ret = geni_se_tx_dma_prep(se, (void *)xfer->tx_buf, 850 xfer->len, &mas->tx_se_dma); 851 if (ret) { 852 dev_err(mas->dev, "Failed to setup Tx dma %d\n", ret); 853 mas->tx_se_dma = 0; 854 if (m_cmd & SPI_RX_ONLY) { 855 /* Unmap rx buffer if duplex transfer */ 856 geni_se_rx_dma_unprep(se, mas->rx_se_dma, xfer->len); 857 mas->rx_se_dma = 0; 858 } 859 goto unlock_and_return; 860 } 861 } 862 } else if (m_cmd & SPI_TX_ONLY) { 863 if (geni_spi_handle_tx(mas)) 864 writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG); 865 } 866 867 unlock_and_return: 868 spin_unlock_irq(&mas->lock); 869 return ret; 870 } 871 872 static int spi_geni_transfer_one(struct spi_master *spi, 873 struct spi_device *slv, 874 struct spi_transfer *xfer) 875 { 876 struct spi_geni_master *mas = spi_master_get_devdata(spi); 877 int ret; 878 879 if (spi_geni_is_abort_still_pending(mas)) 880 return -EBUSY; 881 882 /* Terminate and return success for 0 byte length transfer */ 883 if (!xfer->len) 884 return 0; 885 886 if (mas->cur_xfer_mode == GENI_SE_FIFO || mas->cur_xfer_mode == GENI_SE_DMA) { 887 ret = setup_se_xfer(xfer, mas, slv->mode, spi); 888 /* SPI framework expects +ve ret code to wait for transfer complete */ 889 if (!ret) 890 ret = 1; 891 return ret; 892 } 893 return setup_gsi_xfer(xfer, mas, slv, spi); 894 } 895 896 static irqreturn_t geni_spi_isr(int irq, void *data) 897 { 898 struct spi_master *spi = data; 899 struct spi_geni_master *mas = spi_master_get_devdata(spi); 900 struct geni_se *se = &mas->se; 901 u32 m_irq; 902 903 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); 904 if (!m_irq) 905 return IRQ_NONE; 906 907 if (m_irq & (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN | 908 M_RX_FIFO_RD_ERR_EN | M_RX_FIFO_WR_ERR_EN | 909 M_TX_FIFO_RD_ERR_EN | M_TX_FIFO_WR_ERR_EN)) 910 dev_warn(mas->dev, "Unexpected IRQ err status %#010x\n", m_irq); 911 912 spin_lock(&mas->lock); 913 914 if (mas->cur_xfer_mode == GENI_SE_FIFO) { 915 if ((m_irq & M_RX_FIFO_WATERMARK_EN) || (m_irq & M_RX_FIFO_LAST_EN)) 916 geni_spi_handle_rx(mas); 917 918 if (m_irq & M_TX_FIFO_WATERMARK_EN) 919 geni_spi_handle_tx(mas); 920 921 if (m_irq & M_CMD_DONE_EN) { 922 if (mas->cur_xfer) { 923 spi_finalize_current_transfer(spi); 924 mas->cur_xfer = NULL; 925 /* 926 * If this happens, then a CMD_DONE came before all the 927 * Tx buffer bytes were sent out. This is unusual, log 928 * this condition and disable the WM interrupt to 929 * prevent the system from stalling due an interrupt 930 * storm. 931 * 932 * If this happens when all Rx bytes haven't been 933 * received, log the condition. The only known time 934 * this can happen is if bits_per_word != 8 and some 935 * registers that expect xfer lengths in num spi_words 936 * weren't written correctly. 937 */ 938 if (mas->tx_rem_bytes) { 939 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 940 dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n", 941 mas->tx_rem_bytes, mas->cur_bits_per_word); 942 } 943 if (mas->rx_rem_bytes) 944 dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n", 945 mas->rx_rem_bytes, mas->cur_bits_per_word); 946 } else { 947 complete(&mas->cs_done); 948 } 949 } 950 } else if (mas->cur_xfer_mode == GENI_SE_DMA) { 951 const struct spi_transfer *xfer = mas->cur_xfer; 952 u32 dma_tx_status = readl_relaxed(se->base + SE_DMA_TX_IRQ_STAT); 953 u32 dma_rx_status = readl_relaxed(se->base + SE_DMA_RX_IRQ_STAT); 954 955 if (dma_tx_status) 956 writel(dma_tx_status, se->base + SE_DMA_TX_IRQ_CLR); 957 if (dma_rx_status) 958 writel(dma_rx_status, se->base + SE_DMA_RX_IRQ_CLR); 959 if (dma_tx_status & TX_DMA_DONE) 960 mas->tx_rem_bytes = 0; 961 if (dma_rx_status & RX_DMA_DONE) 962 mas->rx_rem_bytes = 0; 963 if (dma_tx_status & TX_RESET_DONE) 964 complete(&mas->tx_reset_done); 965 if (dma_rx_status & RX_RESET_DONE) 966 complete(&mas->rx_reset_done); 967 if (!mas->tx_rem_bytes && !mas->rx_rem_bytes && xfer) { 968 if (xfer->tx_buf && mas->tx_se_dma) { 969 geni_se_tx_dma_unprep(se, mas->tx_se_dma, xfer->len); 970 mas->tx_se_dma = 0; 971 } 972 if (xfer->rx_buf && mas->rx_se_dma) { 973 geni_se_rx_dma_unprep(se, mas->rx_se_dma, xfer->len); 974 mas->rx_se_dma = 0; 975 } 976 spi_finalize_current_transfer(spi); 977 mas->cur_xfer = NULL; 978 } 979 } 980 981 if (m_irq & M_CMD_CANCEL_EN) 982 complete(&mas->cancel_done); 983 if (m_irq & M_CMD_ABORT_EN) 984 complete(&mas->abort_done); 985 986 /* 987 * It's safe or a good idea to Ack all of our interrupts at the end 988 * of the function. Specifically: 989 * - M_CMD_DONE_EN / M_RX_FIFO_LAST_EN: Edge triggered interrupts and 990 * clearing Acks. Clearing at the end relies on nobody else having 991 * started a new transfer yet or else we could be clearing _their_ 992 * done bit, but everyone grabs the spinlock before starting a new 993 * transfer. 994 * - M_RX_FIFO_WATERMARK_EN / M_TX_FIFO_WATERMARK_EN: These appear 995 * to be "latched level" interrupts so it's important to clear them 996 * _after_ you've handled the condition and always safe to do so 997 * since they'll re-assert if they're still happening. 998 */ 999 writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR); 1000 1001 spin_unlock(&mas->lock); 1002 1003 return IRQ_HANDLED; 1004 } 1005 1006 static int spi_geni_probe(struct platform_device *pdev) 1007 { 1008 int ret, irq; 1009 struct spi_master *spi; 1010 struct spi_geni_master *mas; 1011 void __iomem *base; 1012 struct clk *clk; 1013 struct device *dev = &pdev->dev; 1014 1015 irq = platform_get_irq(pdev, 0); 1016 if (irq < 0) 1017 return irq; 1018 1019 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); 1020 if (ret) 1021 return dev_err_probe(dev, ret, "could not set DMA mask\n"); 1022 1023 base = devm_platform_ioremap_resource(pdev, 0); 1024 if (IS_ERR(base)) 1025 return PTR_ERR(base); 1026 1027 clk = devm_clk_get(dev, "se"); 1028 if (IS_ERR(clk)) 1029 return PTR_ERR(clk); 1030 1031 spi = devm_spi_alloc_master(dev, sizeof(*mas)); 1032 if (!spi) 1033 return -ENOMEM; 1034 1035 platform_set_drvdata(pdev, spi); 1036 mas = spi_master_get_devdata(spi); 1037 mas->irq = irq; 1038 mas->dev = dev; 1039 mas->se.dev = dev; 1040 mas->se.wrapper = dev_get_drvdata(dev->parent); 1041 mas->se.base = base; 1042 mas->se.clk = clk; 1043 1044 ret = devm_pm_opp_set_clkname(&pdev->dev, "se"); 1045 if (ret) 1046 return ret; 1047 /* OPP table is optional */ 1048 ret = devm_pm_opp_of_add_table(&pdev->dev); 1049 if (ret && ret != -ENODEV) { 1050 dev_err(&pdev->dev, "invalid OPP table in device tree\n"); 1051 return ret; 1052 } 1053 1054 spi->bus_num = -1; 1055 spi->dev.of_node = dev->of_node; 1056 spi->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH; 1057 spi->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1058 spi->num_chipselect = 4; 1059 spi->max_speed_hz = 50000000; 1060 spi->prepare_message = spi_geni_prepare_message; 1061 spi->transfer_one = spi_geni_transfer_one; 1062 spi->can_dma = geni_can_dma; 1063 spi->dma_map_dev = dev->parent; 1064 spi->auto_runtime_pm = true; 1065 spi->handle_err = spi_geni_handle_err; 1066 spi->use_gpio_descriptors = true; 1067 1068 init_completion(&mas->cs_done); 1069 init_completion(&mas->cancel_done); 1070 init_completion(&mas->abort_done); 1071 init_completion(&mas->tx_reset_done); 1072 init_completion(&mas->rx_reset_done); 1073 spin_lock_init(&mas->lock); 1074 pm_runtime_use_autosuspend(&pdev->dev); 1075 pm_runtime_set_autosuspend_delay(&pdev->dev, 250); 1076 pm_runtime_enable(dev); 1077 1078 ret = geni_icc_get(&mas->se, NULL); 1079 if (ret) 1080 goto spi_geni_probe_runtime_disable; 1081 /* Set the bus quota to a reasonable value for register access */ 1082 mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ); 1083 mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; 1084 1085 ret = geni_icc_set_bw(&mas->se); 1086 if (ret) 1087 goto spi_geni_probe_runtime_disable; 1088 1089 ret = spi_geni_init(mas); 1090 if (ret) 1091 goto spi_geni_probe_runtime_disable; 1092 1093 /* 1094 * check the mode supported and set_cs for fifo mode only 1095 * for dma (gsi) mode, the gsi will set cs based on params passed in 1096 * TRE 1097 */ 1098 if (mas->cur_xfer_mode == GENI_SE_FIFO) 1099 spi->set_cs = spi_geni_set_cs; 1100 1101 ret = request_irq(mas->irq, geni_spi_isr, 0, dev_name(dev), spi); 1102 if (ret) 1103 goto spi_geni_release_dma; 1104 1105 ret = spi_register_master(spi); 1106 if (ret) 1107 goto spi_geni_probe_free_irq; 1108 1109 return 0; 1110 spi_geni_probe_free_irq: 1111 free_irq(mas->irq, spi); 1112 spi_geni_release_dma: 1113 spi_geni_release_dma_chan(mas); 1114 spi_geni_probe_runtime_disable: 1115 pm_runtime_disable(dev); 1116 return ret; 1117 } 1118 1119 static void spi_geni_remove(struct platform_device *pdev) 1120 { 1121 struct spi_master *spi = platform_get_drvdata(pdev); 1122 struct spi_geni_master *mas = spi_master_get_devdata(spi); 1123 1124 /* Unregister _before_ disabling pm_runtime() so we stop transfers */ 1125 spi_unregister_master(spi); 1126 1127 spi_geni_release_dma_chan(mas); 1128 1129 free_irq(mas->irq, spi); 1130 pm_runtime_disable(&pdev->dev); 1131 } 1132 1133 static int __maybe_unused spi_geni_runtime_suspend(struct device *dev) 1134 { 1135 struct spi_master *spi = dev_get_drvdata(dev); 1136 struct spi_geni_master *mas = spi_master_get_devdata(spi); 1137 int ret; 1138 1139 /* Drop the performance state vote */ 1140 dev_pm_opp_set_rate(dev, 0); 1141 1142 ret = geni_se_resources_off(&mas->se); 1143 if (ret) 1144 return ret; 1145 1146 return geni_icc_disable(&mas->se); 1147 } 1148 1149 static int __maybe_unused spi_geni_runtime_resume(struct device *dev) 1150 { 1151 struct spi_master *spi = dev_get_drvdata(dev); 1152 struct spi_geni_master *mas = spi_master_get_devdata(spi); 1153 int ret; 1154 1155 ret = geni_icc_enable(&mas->se); 1156 if (ret) 1157 return ret; 1158 1159 ret = geni_se_resources_on(&mas->se); 1160 if (ret) 1161 return ret; 1162 1163 return dev_pm_opp_set_rate(mas->dev, mas->cur_sclk_hz); 1164 } 1165 1166 static int __maybe_unused spi_geni_suspend(struct device *dev) 1167 { 1168 struct spi_master *spi = dev_get_drvdata(dev); 1169 int ret; 1170 1171 ret = spi_master_suspend(spi); 1172 if (ret) 1173 return ret; 1174 1175 ret = pm_runtime_force_suspend(dev); 1176 if (ret) 1177 spi_master_resume(spi); 1178 1179 return ret; 1180 } 1181 1182 static int __maybe_unused spi_geni_resume(struct device *dev) 1183 { 1184 struct spi_master *spi = dev_get_drvdata(dev); 1185 int ret; 1186 1187 ret = pm_runtime_force_resume(dev); 1188 if (ret) 1189 return ret; 1190 1191 ret = spi_master_resume(spi); 1192 if (ret) 1193 pm_runtime_force_suspend(dev); 1194 1195 return ret; 1196 } 1197 1198 static const struct dev_pm_ops spi_geni_pm_ops = { 1199 SET_RUNTIME_PM_OPS(spi_geni_runtime_suspend, 1200 spi_geni_runtime_resume, NULL) 1201 SET_SYSTEM_SLEEP_PM_OPS(spi_geni_suspend, spi_geni_resume) 1202 }; 1203 1204 static const struct of_device_id spi_geni_dt_match[] = { 1205 { .compatible = "qcom,geni-spi" }, 1206 {} 1207 }; 1208 MODULE_DEVICE_TABLE(of, spi_geni_dt_match); 1209 1210 static struct platform_driver spi_geni_driver = { 1211 .probe = spi_geni_probe, 1212 .remove_new = spi_geni_remove, 1213 .driver = { 1214 .name = "geni_spi", 1215 .pm = &spi_geni_pm_ops, 1216 .of_match_table = spi_geni_dt_match, 1217 }, 1218 }; 1219 module_platform_driver(spi_geni_driver); 1220 1221 MODULE_DESCRIPTION("SPI driver for GENI based QUP cores"); 1222 MODULE_LICENSE("GPL v2"); 1223