1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved. 3 4 #include <linux/clk.h> 5 #include <linux/dmaengine.h> 6 #include <linux/dma-mapping.h> 7 #include <linux/dma/qcom-gpi-dma.h> 8 #include <linux/interrupt.h> 9 #include <linux/io.h> 10 #include <linux/log2.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm_opp.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/qcom-geni-se.h> 16 #include <linux/spi/spi.h> 17 #include <linux/spinlock.h> 18 19 /* SPI SE specific registers and respective register fields */ 20 #define SE_SPI_CPHA 0x224 21 #define CPHA BIT(0) 22 23 #define SE_SPI_LOOPBACK 0x22c 24 #define LOOPBACK_ENABLE 0x1 25 #define NORMAL_MODE 0x0 26 #define LOOPBACK_MSK GENMASK(1, 0) 27 28 #define SE_SPI_CPOL 0x230 29 #define CPOL BIT(2) 30 31 #define SE_SPI_DEMUX_OUTPUT_INV 0x24c 32 #define CS_DEMUX_OUTPUT_INV_MSK GENMASK(3, 0) 33 34 #define SE_SPI_DEMUX_SEL 0x250 35 #define CS_DEMUX_OUTPUT_SEL GENMASK(3, 0) 36 37 #define SE_SPI_TRANS_CFG 0x25c 38 #define CS_TOGGLE BIT(0) 39 40 #define SE_SPI_WORD_LEN 0x268 41 #define WORD_LEN_MSK GENMASK(9, 0) 42 #define MIN_WORD_LEN 4 43 44 #define SE_SPI_TX_TRANS_LEN 0x26c 45 #define SE_SPI_RX_TRANS_LEN 0x270 46 #define TRANS_LEN_MSK GENMASK(23, 0) 47 48 #define SE_SPI_PRE_POST_CMD_DLY 0x274 49 50 #define SE_SPI_DELAY_COUNTERS 0x278 51 #define SPI_INTER_WORDS_DELAY_MSK GENMASK(9, 0) 52 #define SPI_CS_CLK_DELAY_MSK GENMASK(19, 10) 53 #define SPI_CS_CLK_DELAY_SHFT 10 54 55 /* M_CMD OP codes for SPI */ 56 #define SPI_TX_ONLY 1 57 #define SPI_RX_ONLY 2 58 #define SPI_TX_RX 7 59 #define SPI_CS_ASSERT 8 60 #define SPI_CS_DEASSERT 9 61 #define SPI_SCK_ONLY 10 62 /* M_CMD params for SPI */ 63 #define SPI_PRE_CMD_DELAY BIT(0) 64 #define TIMESTAMP_BEFORE BIT(1) 65 #define FRAGMENTATION BIT(2) 66 #define TIMESTAMP_AFTER BIT(3) 67 #define POST_CMD_DELAY BIT(4) 68 69 #define GSI_LOOPBACK_EN BIT(0) 70 #define GSI_CS_TOGGLE BIT(3) 71 #define GSI_CPHA BIT(4) 72 #define GSI_CPOL BIT(5) 73 74 #define MAX_TX_SG 3 75 #define NUM_SPI_XFER 8 76 #define SPI_XFER_TIMEOUT_MS 250 77 78 struct spi_geni_master { 79 struct geni_se se; 80 struct device *dev; 81 u32 tx_fifo_depth; 82 u32 fifo_width_bits; 83 u32 tx_wm; 84 u32 last_mode; 85 unsigned long cur_speed_hz; 86 unsigned long cur_sclk_hz; 87 unsigned int cur_bits_per_word; 88 unsigned int tx_rem_bytes; 89 unsigned int rx_rem_bytes; 90 const struct spi_transfer *cur_xfer; 91 struct completion cs_done; 92 struct completion cancel_done; 93 struct completion abort_done; 94 unsigned int oversampling; 95 spinlock_t lock; 96 int irq; 97 bool cs_flag; 98 bool abort_failed; 99 struct dma_chan *tx; 100 struct dma_chan *rx; 101 int cur_xfer_mode; 102 }; 103 104 static int get_spi_clk_cfg(unsigned int speed_hz, 105 struct spi_geni_master *mas, 106 unsigned int *clk_idx, 107 unsigned int *clk_div) 108 { 109 unsigned long sclk_freq; 110 unsigned int actual_hz; 111 int ret; 112 113 ret = geni_se_clk_freq_match(&mas->se, 114 speed_hz * mas->oversampling, 115 clk_idx, &sclk_freq, false); 116 if (ret) { 117 dev_err(mas->dev, "Failed(%d) to find src clk for %dHz\n", 118 ret, speed_hz); 119 return ret; 120 } 121 122 *clk_div = DIV_ROUND_UP(sclk_freq, mas->oversampling * speed_hz); 123 actual_hz = sclk_freq / (mas->oversampling * *clk_div); 124 125 dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz, 126 actual_hz, sclk_freq, *clk_idx, *clk_div); 127 ret = dev_pm_opp_set_rate(mas->dev, sclk_freq); 128 if (ret) 129 dev_err(mas->dev, "dev_pm_opp_set_rate failed %d\n", ret); 130 else 131 mas->cur_sclk_hz = sclk_freq; 132 133 return ret; 134 } 135 136 static void handle_fifo_timeout(struct spi_master *spi, 137 struct spi_message *msg) 138 { 139 struct spi_geni_master *mas = spi_master_get_devdata(spi); 140 unsigned long time_left; 141 struct geni_se *se = &mas->se; 142 143 spin_lock_irq(&mas->lock); 144 reinit_completion(&mas->cancel_done); 145 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 146 mas->cur_xfer = NULL; 147 geni_se_cancel_m_cmd(se); 148 spin_unlock_irq(&mas->lock); 149 150 time_left = wait_for_completion_timeout(&mas->cancel_done, HZ); 151 if (time_left) 152 return; 153 154 spin_lock_irq(&mas->lock); 155 reinit_completion(&mas->abort_done); 156 geni_se_abort_m_cmd(se); 157 spin_unlock_irq(&mas->lock); 158 159 time_left = wait_for_completion_timeout(&mas->abort_done, HZ); 160 if (!time_left) { 161 dev_err(mas->dev, "Failed to cancel/abort m_cmd\n"); 162 163 /* 164 * No need for a lock since SPI core has a lock and we never 165 * access this from an interrupt. 166 */ 167 mas->abort_failed = true; 168 } 169 } 170 171 static bool spi_geni_is_abort_still_pending(struct spi_geni_master *mas) 172 { 173 struct geni_se *se = &mas->se; 174 u32 m_irq, m_irq_en; 175 176 if (!mas->abort_failed) 177 return false; 178 179 /* 180 * The only known case where a transfer times out and then a cancel 181 * times out then an abort times out is if something is blocking our 182 * interrupt handler from running. Avoid starting any new transfers 183 * until that sorts itself out. 184 */ 185 spin_lock_irq(&mas->lock); 186 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); 187 m_irq_en = readl(se->base + SE_GENI_M_IRQ_EN); 188 spin_unlock_irq(&mas->lock); 189 190 if (m_irq & m_irq_en) { 191 dev_err(mas->dev, "Interrupts pending after abort: %#010x\n", 192 m_irq & m_irq_en); 193 return true; 194 } 195 196 /* 197 * If we're here the problem resolved itself so no need to check more 198 * on future transfers. 199 */ 200 mas->abort_failed = false; 201 202 return false; 203 } 204 205 static void spi_geni_set_cs(struct spi_device *slv, bool set_flag) 206 { 207 struct spi_geni_master *mas = spi_master_get_devdata(slv->master); 208 struct spi_master *spi = dev_get_drvdata(mas->dev); 209 struct geni_se *se = &mas->se; 210 unsigned long time_left; 211 212 if (!(slv->mode & SPI_CS_HIGH)) 213 set_flag = !set_flag; 214 215 if (set_flag == mas->cs_flag) 216 return; 217 218 pm_runtime_get_sync(mas->dev); 219 220 if (spi_geni_is_abort_still_pending(mas)) { 221 dev_err(mas->dev, "Can't set chip select\n"); 222 goto exit; 223 } 224 225 spin_lock_irq(&mas->lock); 226 if (mas->cur_xfer) { 227 dev_err(mas->dev, "Can't set CS when prev xfer running\n"); 228 spin_unlock_irq(&mas->lock); 229 goto exit; 230 } 231 232 mas->cs_flag = set_flag; 233 reinit_completion(&mas->cs_done); 234 if (set_flag) 235 geni_se_setup_m_cmd(se, SPI_CS_ASSERT, 0); 236 else 237 geni_se_setup_m_cmd(se, SPI_CS_DEASSERT, 0); 238 spin_unlock_irq(&mas->lock); 239 240 time_left = wait_for_completion_timeout(&mas->cs_done, HZ); 241 if (!time_left) { 242 dev_warn(mas->dev, "Timeout setting chip select\n"); 243 handle_fifo_timeout(spi, NULL); 244 } 245 246 exit: 247 pm_runtime_put(mas->dev); 248 } 249 250 static void spi_setup_word_len(struct spi_geni_master *mas, u16 mode, 251 unsigned int bits_per_word) 252 { 253 unsigned int pack_words; 254 bool msb_first = (mode & SPI_LSB_FIRST) ? false : true; 255 struct geni_se *se = &mas->se; 256 u32 word_len; 257 258 /* 259 * If bits_per_word isn't a byte aligned value, set the packing to be 260 * 1 SPI word per FIFO word. 261 */ 262 if (!(mas->fifo_width_bits % bits_per_word)) 263 pack_words = mas->fifo_width_bits / bits_per_word; 264 else 265 pack_words = 1; 266 geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first, 267 true, true); 268 word_len = (bits_per_word - MIN_WORD_LEN) & WORD_LEN_MSK; 269 writel(word_len, se->base + SE_SPI_WORD_LEN); 270 } 271 272 static int geni_spi_set_clock_and_bw(struct spi_geni_master *mas, 273 unsigned long clk_hz) 274 { 275 u32 clk_sel, m_clk_cfg, idx, div; 276 struct geni_se *se = &mas->se; 277 int ret; 278 279 if (clk_hz == mas->cur_speed_hz) 280 return 0; 281 282 ret = get_spi_clk_cfg(clk_hz, mas, &idx, &div); 283 if (ret) { 284 dev_err(mas->dev, "Err setting clk to %lu: %d\n", clk_hz, ret); 285 return ret; 286 } 287 288 /* 289 * SPI core clock gets configured with the requested frequency 290 * or the frequency closer to the requested frequency. 291 * For that reason requested frequency is stored in the 292 * cur_speed_hz and referred in the consecutive transfer instead 293 * of calling clk_get_rate() API. 294 */ 295 mas->cur_speed_hz = clk_hz; 296 297 clk_sel = idx & CLK_SEL_MSK; 298 m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN; 299 writel(clk_sel, se->base + SE_GENI_CLK_SEL); 300 writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG); 301 302 /* Set BW quota for CPU as driver supports FIFO mode only. */ 303 se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz); 304 ret = geni_icc_set_bw(se); 305 if (ret) 306 return ret; 307 308 return 0; 309 } 310 311 static int setup_fifo_params(struct spi_device *spi_slv, 312 struct spi_master *spi) 313 { 314 struct spi_geni_master *mas = spi_master_get_devdata(spi); 315 struct geni_se *se = &mas->se; 316 u32 loopback_cfg = 0, cpol = 0, cpha = 0, demux_output_inv = 0; 317 u32 demux_sel; 318 319 if (mas->last_mode != spi_slv->mode) { 320 if (spi_slv->mode & SPI_LOOP) 321 loopback_cfg = LOOPBACK_ENABLE; 322 323 if (spi_slv->mode & SPI_CPOL) 324 cpol = CPOL; 325 326 if (spi_slv->mode & SPI_CPHA) 327 cpha = CPHA; 328 329 if (spi_slv->mode & SPI_CS_HIGH) 330 demux_output_inv = BIT(spi_slv->chip_select); 331 332 demux_sel = spi_slv->chip_select; 333 mas->cur_bits_per_word = spi_slv->bits_per_word; 334 335 spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word); 336 writel(loopback_cfg, se->base + SE_SPI_LOOPBACK); 337 writel(demux_sel, se->base + SE_SPI_DEMUX_SEL); 338 writel(cpha, se->base + SE_SPI_CPHA); 339 writel(cpol, se->base + SE_SPI_CPOL); 340 writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV); 341 342 mas->last_mode = spi_slv->mode; 343 } 344 345 return geni_spi_set_clock_and_bw(mas, spi_slv->max_speed_hz); 346 } 347 348 static void 349 spi_gsi_callback_result(void *cb, const struct dmaengine_result *result) 350 { 351 struct spi_master *spi = cb; 352 353 if (result->result != DMA_TRANS_NOERROR) { 354 dev_err(&spi->dev, "DMA txn failed: %d\n", result->result); 355 return; 356 } 357 358 if (!result->residue) { 359 dev_dbg(&spi->dev, "DMA txn completed\n"); 360 spi_finalize_current_transfer(spi); 361 } else { 362 dev_err(&spi->dev, "DMA xfer has pending: %d\n", result->residue); 363 } 364 } 365 366 static int setup_gsi_xfer(struct spi_transfer *xfer, struct spi_geni_master *mas, 367 struct spi_device *spi_slv, struct spi_master *spi) 368 { 369 unsigned long flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK; 370 struct dma_slave_config config = {}; 371 struct gpi_spi_config peripheral = {}; 372 struct dma_async_tx_descriptor *tx_desc, *rx_desc; 373 int ret; 374 375 config.peripheral_config = &peripheral; 376 config.peripheral_size = sizeof(peripheral); 377 peripheral.set_config = true; 378 379 if (xfer->bits_per_word != mas->cur_bits_per_word || 380 xfer->speed_hz != mas->cur_speed_hz) { 381 mas->cur_bits_per_word = xfer->bits_per_word; 382 mas->cur_speed_hz = xfer->speed_hz; 383 } 384 385 if (xfer->tx_buf && xfer->rx_buf) { 386 peripheral.cmd = SPI_DUPLEX; 387 } else if (xfer->tx_buf) { 388 peripheral.cmd = SPI_TX; 389 peripheral.rx_len = 0; 390 } else if (xfer->rx_buf) { 391 peripheral.cmd = SPI_RX; 392 if (!(mas->cur_bits_per_word % MIN_WORD_LEN)) { 393 peripheral.rx_len = ((xfer->len << 3) / mas->cur_bits_per_word); 394 } else { 395 int bytes_per_word = (mas->cur_bits_per_word / BITS_PER_BYTE) + 1; 396 397 peripheral.rx_len = (xfer->len / bytes_per_word); 398 } 399 } 400 401 peripheral.loopback_en = !!(spi_slv->mode & SPI_LOOP); 402 peripheral.clock_pol_high = !!(spi_slv->mode & SPI_CPOL); 403 peripheral.data_pol_high = !!(spi_slv->mode & SPI_CPHA); 404 peripheral.cs = spi_slv->chip_select; 405 peripheral.pack_en = true; 406 peripheral.word_len = xfer->bits_per_word - MIN_WORD_LEN; 407 408 ret = get_spi_clk_cfg(mas->cur_speed_hz, mas, 409 &peripheral.clk_src, &peripheral.clk_div); 410 if (ret) { 411 dev_err(mas->dev, "Err in get_spi_clk_cfg() :%d\n", ret); 412 return ret; 413 } 414 415 if (!xfer->cs_change) { 416 if (!list_is_last(&xfer->transfer_list, &spi->cur_msg->transfers)) 417 peripheral.fragmentation = FRAGMENTATION; 418 } 419 420 if (peripheral.cmd & SPI_RX) { 421 dmaengine_slave_config(mas->rx, &config); 422 rx_desc = dmaengine_prep_slave_sg(mas->rx, xfer->rx_sg.sgl, xfer->rx_sg.nents, 423 DMA_DEV_TO_MEM, flags); 424 if (!rx_desc) { 425 dev_err(mas->dev, "Err setting up rx desc\n"); 426 return -EIO; 427 } 428 } 429 430 /* 431 * Prepare the TX always, even for RX or tx_buf being null, we would 432 * need TX to be prepared per GSI spec 433 */ 434 dmaengine_slave_config(mas->tx, &config); 435 tx_desc = dmaengine_prep_slave_sg(mas->tx, xfer->tx_sg.sgl, xfer->tx_sg.nents, 436 DMA_MEM_TO_DEV, flags); 437 if (!tx_desc) { 438 dev_err(mas->dev, "Err setting up tx desc\n"); 439 return -EIO; 440 } 441 442 tx_desc->callback_result = spi_gsi_callback_result; 443 tx_desc->callback_param = spi; 444 445 if (peripheral.cmd & SPI_RX) 446 dmaengine_submit(rx_desc); 447 dmaengine_submit(tx_desc); 448 449 if (peripheral.cmd & SPI_RX) 450 dma_async_issue_pending(mas->rx); 451 452 dma_async_issue_pending(mas->tx); 453 return 1; 454 } 455 456 static bool geni_can_dma(struct spi_controller *ctlr, 457 struct spi_device *slv, struct spi_transfer *xfer) 458 { 459 struct spi_geni_master *mas = spi_master_get_devdata(slv->master); 460 461 /* check if dma is supported */ 462 return mas->cur_xfer_mode != GENI_SE_FIFO; 463 } 464 465 static int spi_geni_prepare_message(struct spi_master *spi, 466 struct spi_message *spi_msg) 467 { 468 struct spi_geni_master *mas = spi_master_get_devdata(spi); 469 int ret; 470 471 switch (mas->cur_xfer_mode) { 472 case GENI_SE_FIFO: 473 if (spi_geni_is_abort_still_pending(mas)) 474 return -EBUSY; 475 ret = setup_fifo_params(spi_msg->spi, spi); 476 if (ret) 477 dev_err(mas->dev, "Couldn't select mode %d\n", ret); 478 return ret; 479 480 case GENI_GPI_DMA: 481 /* nothing to do for GPI DMA */ 482 return 0; 483 } 484 485 dev_err(mas->dev, "Mode not supported %d", mas->cur_xfer_mode); 486 return -EINVAL; 487 } 488 489 static int spi_geni_grab_gpi_chan(struct spi_geni_master *mas) 490 { 491 int ret; 492 493 mas->tx = dma_request_chan(mas->dev, "tx"); 494 ret = dev_err_probe(mas->dev, IS_ERR(mas->tx), "Failed to get tx DMA ch\n"); 495 if (ret < 0) 496 goto err_tx; 497 498 mas->rx = dma_request_chan(mas->dev, "rx"); 499 ret = dev_err_probe(mas->dev, IS_ERR(mas->rx), "Failed to get rx DMA ch\n"); 500 if (ret < 0) 501 goto err_rx; 502 503 return 0; 504 505 err_rx: 506 dma_release_channel(mas->tx); 507 mas->tx = NULL; 508 err_tx: 509 mas->rx = NULL; 510 return ret; 511 } 512 513 static void spi_geni_release_dma_chan(struct spi_geni_master *mas) 514 { 515 if (mas->rx) { 516 dma_release_channel(mas->rx); 517 mas->rx = NULL; 518 } 519 520 if (mas->tx) { 521 dma_release_channel(mas->tx); 522 mas->tx = NULL; 523 } 524 } 525 526 static int spi_geni_init(struct spi_geni_master *mas) 527 { 528 struct geni_se *se = &mas->se; 529 unsigned int proto, major, minor, ver; 530 u32 spi_tx_cfg, fifo_disable; 531 int ret = -ENXIO; 532 533 pm_runtime_get_sync(mas->dev); 534 535 proto = geni_se_read_proto(se); 536 if (proto != GENI_SE_SPI) { 537 dev_err(mas->dev, "Invalid proto %d\n", proto); 538 goto out_pm; 539 } 540 mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se); 541 542 /* Width of Tx and Rx FIFO is same */ 543 mas->fifo_width_bits = geni_se_get_tx_fifo_width(se); 544 545 /* 546 * Hardware programming guide suggests to configure 547 * RX FIFO RFR level to fifo_depth-2. 548 */ 549 geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2); 550 /* Transmit an entire FIFO worth of data per IRQ */ 551 mas->tx_wm = 1; 552 ver = geni_se_get_qup_hw_version(se); 553 major = GENI_SE_VERSION_MAJOR(ver); 554 minor = GENI_SE_VERSION_MINOR(ver); 555 556 if (major == 1 && minor == 0) 557 mas->oversampling = 2; 558 else 559 mas->oversampling = 1; 560 561 fifo_disable = readl(se->base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE; 562 switch (fifo_disable) { 563 case 1: 564 ret = spi_geni_grab_gpi_chan(mas); 565 if (!ret) { /* success case */ 566 mas->cur_xfer_mode = GENI_GPI_DMA; 567 geni_se_select_mode(se, GENI_GPI_DMA); 568 dev_dbg(mas->dev, "Using GPI DMA mode for SPI\n"); 569 break; 570 } 571 /* 572 * in case of failure to get dma channel, we can still do the 573 * FIFO mode, so fallthrough 574 */ 575 dev_warn(mas->dev, "FIFO mode disabled, but couldn't get DMA, fall back to FIFO mode\n"); 576 fallthrough; 577 578 case 0: 579 mas->cur_xfer_mode = GENI_SE_FIFO; 580 geni_se_select_mode(se, GENI_SE_FIFO); 581 ret = 0; 582 break; 583 } 584 585 /* We always control CS manually */ 586 spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG); 587 spi_tx_cfg &= ~CS_TOGGLE; 588 writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG); 589 590 out_pm: 591 pm_runtime_put(mas->dev); 592 return ret; 593 } 594 595 static unsigned int geni_byte_per_fifo_word(struct spi_geni_master *mas) 596 { 597 /* 598 * Calculate how many bytes we'll put in each FIFO word. If the 599 * transfer words don't pack cleanly into a FIFO word we'll just put 600 * one transfer word in each FIFO word. If they do pack we'll pack 'em. 601 */ 602 if (mas->fifo_width_bits % mas->cur_bits_per_word) 603 return roundup_pow_of_two(DIV_ROUND_UP(mas->cur_bits_per_word, 604 BITS_PER_BYTE)); 605 606 return mas->fifo_width_bits / BITS_PER_BYTE; 607 } 608 609 static bool geni_spi_handle_tx(struct spi_geni_master *mas) 610 { 611 struct geni_se *se = &mas->se; 612 unsigned int max_bytes; 613 const u8 *tx_buf; 614 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas); 615 unsigned int i = 0; 616 617 /* Stop the watermark IRQ if nothing to send */ 618 if (!mas->cur_xfer) { 619 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 620 return false; 621 } 622 623 max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * bytes_per_fifo_word; 624 if (mas->tx_rem_bytes < max_bytes) 625 max_bytes = mas->tx_rem_bytes; 626 627 tx_buf = mas->cur_xfer->tx_buf + mas->cur_xfer->len - mas->tx_rem_bytes; 628 while (i < max_bytes) { 629 unsigned int j; 630 unsigned int bytes_to_write; 631 u32 fifo_word = 0; 632 u8 *fifo_byte = (u8 *)&fifo_word; 633 634 bytes_to_write = min(bytes_per_fifo_word, max_bytes - i); 635 for (j = 0; j < bytes_to_write; j++) 636 fifo_byte[j] = tx_buf[i++]; 637 iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1); 638 } 639 mas->tx_rem_bytes -= max_bytes; 640 if (!mas->tx_rem_bytes) { 641 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 642 return false; 643 } 644 return true; 645 } 646 647 static void geni_spi_handle_rx(struct spi_geni_master *mas) 648 { 649 struct geni_se *se = &mas->se; 650 u32 rx_fifo_status; 651 unsigned int rx_bytes; 652 unsigned int rx_last_byte_valid; 653 u8 *rx_buf; 654 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas); 655 unsigned int i = 0; 656 657 rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS); 658 rx_bytes = (rx_fifo_status & RX_FIFO_WC_MSK) * bytes_per_fifo_word; 659 if (rx_fifo_status & RX_LAST) { 660 rx_last_byte_valid = rx_fifo_status & RX_LAST_BYTE_VALID_MSK; 661 rx_last_byte_valid >>= RX_LAST_BYTE_VALID_SHFT; 662 if (rx_last_byte_valid && rx_last_byte_valid < 4) 663 rx_bytes -= bytes_per_fifo_word - rx_last_byte_valid; 664 } 665 666 /* Clear out the FIFO and bail if nowhere to put it */ 667 if (!mas->cur_xfer) { 668 for (i = 0; i < DIV_ROUND_UP(rx_bytes, bytes_per_fifo_word); i++) 669 readl(se->base + SE_GENI_RX_FIFOn); 670 return; 671 } 672 673 if (mas->rx_rem_bytes < rx_bytes) 674 rx_bytes = mas->rx_rem_bytes; 675 676 rx_buf = mas->cur_xfer->rx_buf + mas->cur_xfer->len - mas->rx_rem_bytes; 677 while (i < rx_bytes) { 678 u32 fifo_word = 0; 679 u8 *fifo_byte = (u8 *)&fifo_word; 680 unsigned int bytes_to_read; 681 unsigned int j; 682 683 bytes_to_read = min(bytes_per_fifo_word, rx_bytes - i); 684 ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1); 685 for (j = 0; j < bytes_to_read; j++) 686 rx_buf[i++] = fifo_byte[j]; 687 } 688 mas->rx_rem_bytes -= rx_bytes; 689 } 690 691 static void setup_fifo_xfer(struct spi_transfer *xfer, 692 struct spi_geni_master *mas, 693 u16 mode, struct spi_master *spi) 694 { 695 u32 m_cmd = 0; 696 u32 len; 697 struct geni_se *se = &mas->se; 698 int ret; 699 700 /* 701 * Ensure that our interrupt handler isn't still running from some 702 * prior command before we start messing with the hardware behind 703 * its back. We don't need to _keep_ the lock here since we're only 704 * worried about racing with out interrupt handler. The SPI core 705 * already handles making sure that we're not trying to do two 706 * transfers at once or setting a chip select and doing a transfer 707 * concurrently. 708 * 709 * NOTE: we actually _can't_ hold the lock here because possibly we 710 * might call clk_set_rate() which needs to be able to sleep. 711 */ 712 spin_lock_irq(&mas->lock); 713 spin_unlock_irq(&mas->lock); 714 715 if (xfer->bits_per_word != mas->cur_bits_per_word) { 716 spi_setup_word_len(mas, mode, xfer->bits_per_word); 717 mas->cur_bits_per_word = xfer->bits_per_word; 718 } 719 720 /* Speed and bits per word can be overridden per transfer */ 721 ret = geni_spi_set_clock_and_bw(mas, xfer->speed_hz); 722 if (ret) 723 return; 724 725 mas->tx_rem_bytes = 0; 726 mas->rx_rem_bytes = 0; 727 728 if (!(mas->cur_bits_per_word % MIN_WORD_LEN)) 729 len = xfer->len * BITS_PER_BYTE / mas->cur_bits_per_word; 730 else 731 len = xfer->len / (mas->cur_bits_per_word / BITS_PER_BYTE + 1); 732 len &= TRANS_LEN_MSK; 733 734 mas->cur_xfer = xfer; 735 if (xfer->tx_buf) { 736 m_cmd |= SPI_TX_ONLY; 737 mas->tx_rem_bytes = xfer->len; 738 writel(len, se->base + SE_SPI_TX_TRANS_LEN); 739 } 740 741 if (xfer->rx_buf) { 742 m_cmd |= SPI_RX_ONLY; 743 writel(len, se->base + SE_SPI_RX_TRANS_LEN); 744 mas->rx_rem_bytes = xfer->len; 745 } 746 747 /* 748 * Lock around right before we start the transfer since our 749 * interrupt could come in at any time now. 750 */ 751 spin_lock_irq(&mas->lock); 752 geni_se_setup_m_cmd(se, m_cmd, FRAGMENTATION); 753 if (m_cmd & SPI_TX_ONLY) { 754 if (geni_spi_handle_tx(mas)) 755 writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG); 756 } 757 spin_unlock_irq(&mas->lock); 758 } 759 760 static int spi_geni_transfer_one(struct spi_master *spi, 761 struct spi_device *slv, 762 struct spi_transfer *xfer) 763 { 764 struct spi_geni_master *mas = spi_master_get_devdata(spi); 765 766 if (spi_geni_is_abort_still_pending(mas)) 767 return -EBUSY; 768 769 /* Terminate and return success for 0 byte length transfer */ 770 if (!xfer->len) 771 return 0; 772 773 if (mas->cur_xfer_mode == GENI_SE_FIFO) { 774 setup_fifo_xfer(xfer, mas, slv->mode, spi); 775 return 1; 776 } 777 return setup_gsi_xfer(xfer, mas, slv, spi); 778 } 779 780 static irqreturn_t geni_spi_isr(int irq, void *data) 781 { 782 struct spi_master *spi = data; 783 struct spi_geni_master *mas = spi_master_get_devdata(spi); 784 struct geni_se *se = &mas->se; 785 u32 m_irq; 786 787 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); 788 if (!m_irq) 789 return IRQ_NONE; 790 791 if (m_irq & (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN | 792 M_RX_FIFO_RD_ERR_EN | M_RX_FIFO_WR_ERR_EN | 793 M_TX_FIFO_RD_ERR_EN | M_TX_FIFO_WR_ERR_EN)) 794 dev_warn(mas->dev, "Unexpected IRQ err status %#010x\n", m_irq); 795 796 spin_lock(&mas->lock); 797 798 if ((m_irq & M_RX_FIFO_WATERMARK_EN) || (m_irq & M_RX_FIFO_LAST_EN)) 799 geni_spi_handle_rx(mas); 800 801 if (m_irq & M_TX_FIFO_WATERMARK_EN) 802 geni_spi_handle_tx(mas); 803 804 if (m_irq & M_CMD_DONE_EN) { 805 if (mas->cur_xfer) { 806 spi_finalize_current_transfer(spi); 807 mas->cur_xfer = NULL; 808 /* 809 * If this happens, then a CMD_DONE came before all the 810 * Tx buffer bytes were sent out. This is unusual, log 811 * this condition and disable the WM interrupt to 812 * prevent the system from stalling due an interrupt 813 * storm. 814 * 815 * If this happens when all Rx bytes haven't been 816 * received, log the condition. The only known time 817 * this can happen is if bits_per_word != 8 and some 818 * registers that expect xfer lengths in num spi_words 819 * weren't written correctly. 820 */ 821 if (mas->tx_rem_bytes) { 822 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 823 dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n", 824 mas->tx_rem_bytes, mas->cur_bits_per_word); 825 } 826 if (mas->rx_rem_bytes) 827 dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n", 828 mas->rx_rem_bytes, mas->cur_bits_per_word); 829 } else { 830 complete(&mas->cs_done); 831 } 832 } 833 834 if (m_irq & M_CMD_CANCEL_EN) 835 complete(&mas->cancel_done); 836 if (m_irq & M_CMD_ABORT_EN) 837 complete(&mas->abort_done); 838 839 /* 840 * It's safe or a good idea to Ack all of our interrupts at the end 841 * of the function. Specifically: 842 * - M_CMD_DONE_EN / M_RX_FIFO_LAST_EN: Edge triggered interrupts and 843 * clearing Acks. Clearing at the end relies on nobody else having 844 * started a new transfer yet or else we could be clearing _their_ 845 * done bit, but everyone grabs the spinlock before starting a new 846 * transfer. 847 * - M_RX_FIFO_WATERMARK_EN / M_TX_FIFO_WATERMARK_EN: These appear 848 * to be "latched level" interrupts so it's important to clear them 849 * _after_ you've handled the condition and always safe to do so 850 * since they'll re-assert if they're still happening. 851 */ 852 writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR); 853 854 spin_unlock(&mas->lock); 855 856 return IRQ_HANDLED; 857 } 858 859 static int spi_geni_probe(struct platform_device *pdev) 860 { 861 int ret, irq; 862 struct spi_master *spi; 863 struct spi_geni_master *mas; 864 void __iomem *base; 865 struct clk *clk; 866 struct device *dev = &pdev->dev; 867 868 irq = platform_get_irq(pdev, 0); 869 if (irq < 0) 870 return irq; 871 872 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); 873 if (ret) { 874 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 875 if (ret) 876 return dev_err_probe(dev, ret, "could not set DMA mask\n"); 877 } 878 879 base = devm_platform_ioremap_resource(pdev, 0); 880 if (IS_ERR(base)) 881 return PTR_ERR(base); 882 883 clk = devm_clk_get(dev, "se"); 884 if (IS_ERR(clk)) 885 return PTR_ERR(clk); 886 887 spi = devm_spi_alloc_master(dev, sizeof(*mas)); 888 if (!spi) 889 return -ENOMEM; 890 891 platform_set_drvdata(pdev, spi); 892 mas = spi_master_get_devdata(spi); 893 mas->irq = irq; 894 mas->dev = dev; 895 mas->se.dev = dev; 896 mas->se.wrapper = dev_get_drvdata(dev->parent); 897 mas->se.base = base; 898 mas->se.clk = clk; 899 900 ret = devm_pm_opp_set_clkname(&pdev->dev, "se"); 901 if (ret) 902 return ret; 903 /* OPP table is optional */ 904 ret = devm_pm_opp_of_add_table(&pdev->dev); 905 if (ret && ret != -ENODEV) { 906 dev_err(&pdev->dev, "invalid OPP table in device tree\n"); 907 return ret; 908 } 909 910 spi->bus_num = -1; 911 spi->dev.of_node = dev->of_node; 912 spi->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH; 913 spi->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 914 spi->num_chipselect = 4; 915 spi->max_speed_hz = 50000000; 916 spi->prepare_message = spi_geni_prepare_message; 917 spi->transfer_one = spi_geni_transfer_one; 918 spi->can_dma = geni_can_dma; 919 spi->dma_map_dev = dev->parent; 920 spi->auto_runtime_pm = true; 921 spi->handle_err = handle_fifo_timeout; 922 spi->use_gpio_descriptors = true; 923 924 init_completion(&mas->cs_done); 925 init_completion(&mas->cancel_done); 926 init_completion(&mas->abort_done); 927 spin_lock_init(&mas->lock); 928 pm_runtime_use_autosuspend(&pdev->dev); 929 pm_runtime_set_autosuspend_delay(&pdev->dev, 250); 930 pm_runtime_enable(dev); 931 932 ret = geni_icc_get(&mas->se, NULL); 933 if (ret) 934 goto spi_geni_probe_runtime_disable; 935 /* Set the bus quota to a reasonable value for register access */ 936 mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ); 937 mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; 938 939 ret = geni_icc_set_bw(&mas->se); 940 if (ret) 941 goto spi_geni_probe_runtime_disable; 942 943 ret = spi_geni_init(mas); 944 if (ret) 945 goto spi_geni_probe_runtime_disable; 946 947 /* 948 * check the mode supported and set_cs for fifo mode only 949 * for dma (gsi) mode, the gsi will set cs based on params passed in 950 * TRE 951 */ 952 if (mas->cur_xfer_mode == GENI_SE_FIFO) 953 spi->set_cs = spi_geni_set_cs; 954 955 ret = request_irq(mas->irq, geni_spi_isr, 0, dev_name(dev), spi); 956 if (ret) 957 goto spi_geni_release_dma; 958 959 ret = spi_register_master(spi); 960 if (ret) 961 goto spi_geni_probe_free_irq; 962 963 return 0; 964 spi_geni_probe_free_irq: 965 free_irq(mas->irq, spi); 966 spi_geni_release_dma: 967 spi_geni_release_dma_chan(mas); 968 spi_geni_probe_runtime_disable: 969 pm_runtime_disable(dev); 970 return ret; 971 } 972 973 static int spi_geni_remove(struct platform_device *pdev) 974 { 975 struct spi_master *spi = platform_get_drvdata(pdev); 976 struct spi_geni_master *mas = spi_master_get_devdata(spi); 977 978 /* Unregister _before_ disabling pm_runtime() so we stop transfers */ 979 spi_unregister_master(spi); 980 981 spi_geni_release_dma_chan(mas); 982 983 free_irq(mas->irq, spi); 984 pm_runtime_disable(&pdev->dev); 985 return 0; 986 } 987 988 static int __maybe_unused spi_geni_runtime_suspend(struct device *dev) 989 { 990 struct spi_master *spi = dev_get_drvdata(dev); 991 struct spi_geni_master *mas = spi_master_get_devdata(spi); 992 int ret; 993 994 /* Drop the performance state vote */ 995 dev_pm_opp_set_rate(dev, 0); 996 997 ret = geni_se_resources_off(&mas->se); 998 if (ret) 999 return ret; 1000 1001 return geni_icc_disable(&mas->se); 1002 } 1003 1004 static int __maybe_unused spi_geni_runtime_resume(struct device *dev) 1005 { 1006 struct spi_master *spi = dev_get_drvdata(dev); 1007 struct spi_geni_master *mas = spi_master_get_devdata(spi); 1008 int ret; 1009 1010 ret = geni_icc_enable(&mas->se); 1011 if (ret) 1012 return ret; 1013 1014 ret = geni_se_resources_on(&mas->se); 1015 if (ret) 1016 return ret; 1017 1018 return dev_pm_opp_set_rate(mas->dev, mas->cur_sclk_hz); 1019 } 1020 1021 static int __maybe_unused spi_geni_suspend(struct device *dev) 1022 { 1023 struct spi_master *spi = dev_get_drvdata(dev); 1024 int ret; 1025 1026 ret = spi_master_suspend(spi); 1027 if (ret) 1028 return ret; 1029 1030 ret = pm_runtime_force_suspend(dev); 1031 if (ret) 1032 spi_master_resume(spi); 1033 1034 return ret; 1035 } 1036 1037 static int __maybe_unused spi_geni_resume(struct device *dev) 1038 { 1039 struct spi_master *spi = dev_get_drvdata(dev); 1040 int ret; 1041 1042 ret = pm_runtime_force_resume(dev); 1043 if (ret) 1044 return ret; 1045 1046 ret = spi_master_resume(spi); 1047 if (ret) 1048 pm_runtime_force_suspend(dev); 1049 1050 return ret; 1051 } 1052 1053 static const struct dev_pm_ops spi_geni_pm_ops = { 1054 SET_RUNTIME_PM_OPS(spi_geni_runtime_suspend, 1055 spi_geni_runtime_resume, NULL) 1056 SET_SYSTEM_SLEEP_PM_OPS(spi_geni_suspend, spi_geni_resume) 1057 }; 1058 1059 static const struct of_device_id spi_geni_dt_match[] = { 1060 { .compatible = "qcom,geni-spi" }, 1061 {} 1062 }; 1063 MODULE_DEVICE_TABLE(of, spi_geni_dt_match); 1064 1065 static struct platform_driver spi_geni_driver = { 1066 .probe = spi_geni_probe, 1067 .remove = spi_geni_remove, 1068 .driver = { 1069 .name = "geni_spi", 1070 .pm = &spi_geni_pm_ops, 1071 .of_match_table = spi_geni_dt_match, 1072 }, 1073 }; 1074 module_platform_driver(spi_geni_driver); 1075 1076 MODULE_DESCRIPTION("SPI driver for GENI based QUP cores"); 1077 MODULE_LICENSE("GPL v2"); 1078