1561de45fSGirish Mahadevan // SPDX-License-Identifier: GPL-2.0 2561de45fSGirish Mahadevan // Copyright (c) 2017-2018, The Linux foundation. All rights reserved. 3561de45fSGirish Mahadevan 4561de45fSGirish Mahadevan #include <linux/clk.h> 5561de45fSGirish Mahadevan #include <linux/interrupt.h> 6561de45fSGirish Mahadevan #include <linux/io.h> 7561de45fSGirish Mahadevan #include <linux/log2.h> 8561de45fSGirish Mahadevan #include <linux/module.h> 9561de45fSGirish Mahadevan #include <linux/platform_device.h> 101a9e489eSRajendra Nayak #include <linux/pm_opp.h> 11561de45fSGirish Mahadevan #include <linux/pm_runtime.h> 12561de45fSGirish Mahadevan #include <linux/qcom-geni-se.h> 13561de45fSGirish Mahadevan #include <linux/spi/spi.h> 14561de45fSGirish Mahadevan #include <linux/spinlock.h> 15561de45fSGirish Mahadevan 16561de45fSGirish Mahadevan /* SPI SE specific registers and respective register fields */ 17561de45fSGirish Mahadevan #define SE_SPI_CPHA 0x224 18561de45fSGirish Mahadevan #define CPHA BIT(0) 19561de45fSGirish Mahadevan 20561de45fSGirish Mahadevan #define SE_SPI_LOOPBACK 0x22c 21561de45fSGirish Mahadevan #define LOOPBACK_ENABLE 0x1 22561de45fSGirish Mahadevan #define NORMAL_MODE 0x0 23561de45fSGirish Mahadevan #define LOOPBACK_MSK GENMASK(1, 0) 24561de45fSGirish Mahadevan 25561de45fSGirish Mahadevan #define SE_SPI_CPOL 0x230 26561de45fSGirish Mahadevan #define CPOL BIT(2) 27561de45fSGirish Mahadevan 28561de45fSGirish Mahadevan #define SE_SPI_DEMUX_OUTPUT_INV 0x24c 29561de45fSGirish Mahadevan #define CS_DEMUX_OUTPUT_INV_MSK GENMASK(3, 0) 30561de45fSGirish Mahadevan 31561de45fSGirish Mahadevan #define SE_SPI_DEMUX_SEL 0x250 32561de45fSGirish Mahadevan #define CS_DEMUX_OUTPUT_SEL GENMASK(3, 0) 33561de45fSGirish Mahadevan 34561de45fSGirish Mahadevan #define SE_SPI_TRANS_CFG 0x25c 35561de45fSGirish Mahadevan #define CS_TOGGLE BIT(0) 36561de45fSGirish Mahadevan 37561de45fSGirish Mahadevan #define SE_SPI_WORD_LEN 0x268 38561de45fSGirish Mahadevan #define WORD_LEN_MSK GENMASK(9, 0) 39561de45fSGirish Mahadevan #define MIN_WORD_LEN 4 40561de45fSGirish Mahadevan 41561de45fSGirish Mahadevan #define SE_SPI_TX_TRANS_LEN 0x26c 42561de45fSGirish Mahadevan #define SE_SPI_RX_TRANS_LEN 0x270 43561de45fSGirish Mahadevan #define TRANS_LEN_MSK GENMASK(23, 0) 44561de45fSGirish Mahadevan 45561de45fSGirish Mahadevan #define SE_SPI_PRE_POST_CMD_DLY 0x274 46561de45fSGirish Mahadevan 47561de45fSGirish Mahadevan #define SE_SPI_DELAY_COUNTERS 0x278 48561de45fSGirish Mahadevan #define SPI_INTER_WORDS_DELAY_MSK GENMASK(9, 0) 49561de45fSGirish Mahadevan #define SPI_CS_CLK_DELAY_MSK GENMASK(19, 10) 50561de45fSGirish Mahadevan #define SPI_CS_CLK_DELAY_SHFT 10 51561de45fSGirish Mahadevan 52561de45fSGirish Mahadevan /* M_CMD OP codes for SPI */ 53561de45fSGirish Mahadevan #define SPI_TX_ONLY 1 54561de45fSGirish Mahadevan #define SPI_RX_ONLY 2 55561de45fSGirish Mahadevan #define SPI_TX_RX 7 56561de45fSGirish Mahadevan #define SPI_CS_ASSERT 8 57561de45fSGirish Mahadevan #define SPI_CS_DEASSERT 9 58561de45fSGirish Mahadevan #define SPI_SCK_ONLY 10 59561de45fSGirish Mahadevan /* M_CMD params for SPI */ 60561de45fSGirish Mahadevan #define SPI_PRE_CMD_DELAY BIT(0) 61561de45fSGirish Mahadevan #define TIMESTAMP_BEFORE BIT(1) 62561de45fSGirish Mahadevan #define FRAGMENTATION BIT(2) 63561de45fSGirish Mahadevan #define TIMESTAMP_AFTER BIT(3) 64561de45fSGirish Mahadevan #define POST_CMD_DELAY BIT(4) 65561de45fSGirish Mahadevan 66561de45fSGirish Mahadevan struct spi_geni_master { 67561de45fSGirish Mahadevan struct geni_se se; 68561de45fSGirish Mahadevan struct device *dev; 69561de45fSGirish Mahadevan u32 tx_fifo_depth; 70561de45fSGirish Mahadevan u32 fifo_width_bits; 71561de45fSGirish Mahadevan u32 tx_wm; 72da48dc8cSDouglas Anderson u32 last_mode; 73561de45fSGirish Mahadevan unsigned long cur_speed_hz; 745f219524SDouglas Anderson unsigned long cur_sclk_hz; 75561de45fSGirish Mahadevan unsigned int cur_bits_per_word; 76561de45fSGirish Mahadevan unsigned int tx_rem_bytes; 77561de45fSGirish Mahadevan unsigned int rx_rem_bytes; 78561de45fSGirish Mahadevan const struct spi_transfer *cur_xfer; 797ba9bdcbSDouglas Anderson struct completion cs_done; 807ba9bdcbSDouglas Anderson struct completion cancel_done; 817ba9bdcbSDouglas Anderson struct completion abort_done; 82561de45fSGirish Mahadevan unsigned int oversampling; 83561de45fSGirish Mahadevan spinlock_t lock; 84561de45fSGirish Mahadevan int irq; 85638d8488SDouglas Anderson bool cs_flag; 86561de45fSGirish Mahadevan }; 87561de45fSGirish Mahadevan 88561de45fSGirish Mahadevan static int get_spi_clk_cfg(unsigned int speed_hz, 89561de45fSGirish Mahadevan struct spi_geni_master *mas, 90561de45fSGirish Mahadevan unsigned int *clk_idx, 91561de45fSGirish Mahadevan unsigned int *clk_div) 92561de45fSGirish Mahadevan { 93561de45fSGirish Mahadevan unsigned long sclk_freq; 94561de45fSGirish Mahadevan unsigned int actual_hz; 95561de45fSGirish Mahadevan int ret; 96561de45fSGirish Mahadevan 97561de45fSGirish Mahadevan ret = geni_se_clk_freq_match(&mas->se, 98561de45fSGirish Mahadevan speed_hz * mas->oversampling, 99561de45fSGirish Mahadevan clk_idx, &sclk_freq, false); 100561de45fSGirish Mahadevan if (ret) { 101561de45fSGirish Mahadevan dev_err(mas->dev, "Failed(%d) to find src clk for %dHz\n", 102561de45fSGirish Mahadevan ret, speed_hz); 103561de45fSGirish Mahadevan return ret; 104561de45fSGirish Mahadevan } 105561de45fSGirish Mahadevan 106561de45fSGirish Mahadevan *clk_div = DIV_ROUND_UP(sclk_freq, mas->oversampling * speed_hz); 107561de45fSGirish Mahadevan actual_hz = sclk_freq / (mas->oversampling * *clk_div); 108561de45fSGirish Mahadevan 109561de45fSGirish Mahadevan dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz, 110561de45fSGirish Mahadevan actual_hz, sclk_freq, *clk_idx, *clk_div); 1111a9e489eSRajendra Nayak ret = dev_pm_opp_set_rate(mas->dev, sclk_freq); 112561de45fSGirish Mahadevan if (ret) 1131a9e489eSRajendra Nayak dev_err(mas->dev, "dev_pm_opp_set_rate failed %d\n", ret); 1145f219524SDouglas Anderson else 1155f219524SDouglas Anderson mas->cur_sclk_hz = sclk_freq; 1165f219524SDouglas Anderson 117561de45fSGirish Mahadevan return ret; 118561de45fSGirish Mahadevan } 119561de45fSGirish Mahadevan 120de43affeSStephen Boyd static void handle_fifo_timeout(struct spi_master *spi, 121de43affeSStephen Boyd struct spi_message *msg) 122de43affeSStephen Boyd { 123de43affeSStephen Boyd struct spi_geni_master *mas = spi_master_get_devdata(spi); 124539afdf9SDouglas Anderson unsigned long time_left; 125de43affeSStephen Boyd struct geni_se *se = &mas->se; 126de43affeSStephen Boyd 127539afdf9SDouglas Anderson spin_lock_irq(&mas->lock); 1287ba9bdcbSDouglas Anderson reinit_completion(&mas->cancel_done); 129de43affeSStephen Boyd writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 1307ba9bdcbSDouglas Anderson mas->cur_xfer = NULL; 1317ba9bdcbSDouglas Anderson geni_se_cancel_m_cmd(se); 132539afdf9SDouglas Anderson spin_unlock_irq(&mas->lock); 1337ba9bdcbSDouglas Anderson 1347ba9bdcbSDouglas Anderson time_left = wait_for_completion_timeout(&mas->cancel_done, HZ); 135de43affeSStephen Boyd if (time_left) 136de43affeSStephen Boyd return; 137de43affeSStephen Boyd 138539afdf9SDouglas Anderson spin_lock_irq(&mas->lock); 1397ba9bdcbSDouglas Anderson reinit_completion(&mas->abort_done); 140de43affeSStephen Boyd geni_se_abort_m_cmd(se); 141539afdf9SDouglas Anderson spin_unlock_irq(&mas->lock); 1427ba9bdcbSDouglas Anderson 1437ba9bdcbSDouglas Anderson time_left = wait_for_completion_timeout(&mas->abort_done, HZ); 144de43affeSStephen Boyd if (!time_left) 145de43affeSStephen Boyd dev_err(mas->dev, "Failed to cancel/abort m_cmd\n"); 146de43affeSStephen Boyd } 147de43affeSStephen Boyd 148561de45fSGirish Mahadevan static void spi_geni_set_cs(struct spi_device *slv, bool set_flag) 149561de45fSGirish Mahadevan { 150561de45fSGirish Mahadevan struct spi_geni_master *mas = spi_master_get_devdata(slv->master); 151561de45fSGirish Mahadevan struct spi_master *spi = dev_get_drvdata(mas->dev); 152561de45fSGirish Mahadevan struct geni_se *se = &mas->se; 1530dccff3cSAlok Chauhan unsigned long time_left; 154561de45fSGirish Mahadevan 155561de45fSGirish Mahadevan if (!(slv->mode & SPI_CS_HIGH)) 156561de45fSGirish Mahadevan set_flag = !set_flag; 157561de45fSGirish Mahadevan 158638d8488SDouglas Anderson if (set_flag == mas->cs_flag) 159638d8488SDouglas Anderson return; 160638d8488SDouglas Anderson 161638d8488SDouglas Anderson mas->cs_flag = set_flag; 162638d8488SDouglas Anderson 163638d8488SDouglas Anderson pm_runtime_get_sync(mas->dev); 1642ee471a1SDouglas Anderson spin_lock_irq(&mas->lock); 1657ba9bdcbSDouglas Anderson reinit_completion(&mas->cs_done); 166561de45fSGirish Mahadevan if (set_flag) 167561de45fSGirish Mahadevan geni_se_setup_m_cmd(se, SPI_CS_ASSERT, 0); 168561de45fSGirish Mahadevan else 169561de45fSGirish Mahadevan geni_se_setup_m_cmd(se, SPI_CS_DEASSERT, 0); 1702ee471a1SDouglas Anderson spin_unlock_irq(&mas->lock); 171561de45fSGirish Mahadevan 1727ba9bdcbSDouglas Anderson time_left = wait_for_completion_timeout(&mas->cs_done, HZ); 1730dccff3cSAlok Chauhan if (!time_left) 174561de45fSGirish Mahadevan handle_fifo_timeout(spi, NULL); 175561de45fSGirish Mahadevan 176561de45fSGirish Mahadevan pm_runtime_put(mas->dev); 177561de45fSGirish Mahadevan } 178561de45fSGirish Mahadevan 179561de45fSGirish Mahadevan static void spi_setup_word_len(struct spi_geni_master *mas, u16 mode, 180561de45fSGirish Mahadevan unsigned int bits_per_word) 181561de45fSGirish Mahadevan { 182561de45fSGirish Mahadevan unsigned int pack_words; 183561de45fSGirish Mahadevan bool msb_first = (mode & SPI_LSB_FIRST) ? false : true; 184561de45fSGirish Mahadevan struct geni_se *se = &mas->se; 185561de45fSGirish Mahadevan u32 word_len; 186561de45fSGirish Mahadevan 187561de45fSGirish Mahadevan /* 188561de45fSGirish Mahadevan * If bits_per_word isn't a byte aligned value, set the packing to be 189561de45fSGirish Mahadevan * 1 SPI word per FIFO word. 190561de45fSGirish Mahadevan */ 191561de45fSGirish Mahadevan if (!(mas->fifo_width_bits % bits_per_word)) 192561de45fSGirish Mahadevan pack_words = mas->fifo_width_bits / bits_per_word; 193561de45fSGirish Mahadevan else 194561de45fSGirish Mahadevan pack_words = 1; 195561de45fSGirish Mahadevan geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first, 196561de45fSGirish Mahadevan true, true); 197da48dc8cSDouglas Anderson word_len = (bits_per_word - MIN_WORD_LEN) & WORD_LEN_MSK; 198561de45fSGirish Mahadevan writel(word_len, se->base + SE_SPI_WORD_LEN); 199561de45fSGirish Mahadevan } 200561de45fSGirish Mahadevan 2010e3b8a81SAkash Asthana static int geni_spi_set_clock_and_bw(struct spi_geni_master *mas, 2020e3b8a81SAkash Asthana unsigned long clk_hz) 203e68b6624SDouglas Anderson { 204e68b6624SDouglas Anderson u32 clk_sel, m_clk_cfg, idx, div; 205e68b6624SDouglas Anderson struct geni_se *se = &mas->se; 206e68b6624SDouglas Anderson int ret; 207e68b6624SDouglas Anderson 20868890e20SDouglas Anderson if (clk_hz == mas->cur_speed_hz) 20968890e20SDouglas Anderson return 0; 21068890e20SDouglas Anderson 211e68b6624SDouglas Anderson ret = get_spi_clk_cfg(clk_hz, mas, &idx, &div); 212e68b6624SDouglas Anderson if (ret) { 213e68b6624SDouglas Anderson dev_err(mas->dev, "Err setting clk to %lu: %d\n", clk_hz, ret); 214e68b6624SDouglas Anderson return ret; 215e68b6624SDouglas Anderson } 216e68b6624SDouglas Anderson 217e68b6624SDouglas Anderson /* 218e68b6624SDouglas Anderson * SPI core clock gets configured with the requested frequency 219e68b6624SDouglas Anderson * or the frequency closer to the requested frequency. 220e68b6624SDouglas Anderson * For that reason requested frequency is stored in the 221e68b6624SDouglas Anderson * cur_speed_hz and referred in the consecutive transfer instead 222e68b6624SDouglas Anderson * of calling clk_get_rate() API. 223e68b6624SDouglas Anderson */ 224e68b6624SDouglas Anderson mas->cur_speed_hz = clk_hz; 225e68b6624SDouglas Anderson 226e68b6624SDouglas Anderson clk_sel = idx & CLK_SEL_MSK; 227e68b6624SDouglas Anderson m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN; 228e68b6624SDouglas Anderson writel(clk_sel, se->base + SE_GENI_CLK_SEL); 229e68b6624SDouglas Anderson writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG); 230e68b6624SDouglas Anderson 2310e3b8a81SAkash Asthana /* Set BW quota for CPU as driver supports FIFO mode only. */ 2320e3b8a81SAkash Asthana se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz); 2330e3b8a81SAkash Asthana ret = geni_icc_set_bw(se); 2340e3b8a81SAkash Asthana if (ret) 2350e3b8a81SAkash Asthana return ret; 2360e3b8a81SAkash Asthana 237e68b6624SDouglas Anderson return 0; 238e68b6624SDouglas Anderson } 239e68b6624SDouglas Anderson 240561de45fSGirish Mahadevan static int setup_fifo_params(struct spi_device *spi_slv, 241561de45fSGirish Mahadevan struct spi_master *spi) 242561de45fSGirish Mahadevan { 243561de45fSGirish Mahadevan struct spi_geni_master *mas = spi_master_get_devdata(spi); 244561de45fSGirish Mahadevan struct geni_se *se = &mas->se; 245da48dc8cSDouglas Anderson u32 loopback_cfg = 0, cpol = 0, cpha = 0, demux_output_inv = 0; 246e68b6624SDouglas Anderson u32 demux_sel; 247561de45fSGirish Mahadevan 248da48dc8cSDouglas Anderson if (mas->last_mode != spi_slv->mode) { 249561de45fSGirish Mahadevan if (spi_slv->mode & SPI_LOOP) 250da48dc8cSDouglas Anderson loopback_cfg = LOOPBACK_ENABLE; 251561de45fSGirish Mahadevan 252561de45fSGirish Mahadevan if (spi_slv->mode & SPI_CPOL) 253da48dc8cSDouglas Anderson cpol = CPOL; 254561de45fSGirish Mahadevan 255561de45fSGirish Mahadevan if (spi_slv->mode & SPI_CPHA) 256da48dc8cSDouglas Anderson cpha = CPHA; 257561de45fSGirish Mahadevan 258561de45fSGirish Mahadevan if (spi_slv->mode & SPI_CS_HIGH) 259561de45fSGirish Mahadevan demux_output_inv = BIT(spi_slv->chip_select); 260561de45fSGirish Mahadevan 261561de45fSGirish Mahadevan demux_sel = spi_slv->chip_select; 262561de45fSGirish Mahadevan mas->cur_bits_per_word = spi_slv->bits_per_word; 263561de45fSGirish Mahadevan 264561de45fSGirish Mahadevan spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word); 265561de45fSGirish Mahadevan writel(loopback_cfg, se->base + SE_SPI_LOOPBACK); 266561de45fSGirish Mahadevan writel(demux_sel, se->base + SE_SPI_DEMUX_SEL); 267561de45fSGirish Mahadevan writel(cpha, se->base + SE_SPI_CPHA); 268561de45fSGirish Mahadevan writel(cpol, se->base + SE_SPI_CPOL); 269561de45fSGirish Mahadevan writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV); 270e68b6624SDouglas Anderson 271da48dc8cSDouglas Anderson mas->last_mode = spi_slv->mode; 272da48dc8cSDouglas Anderson } 273da48dc8cSDouglas Anderson 2740e3b8a81SAkash Asthana return geni_spi_set_clock_and_bw(mas, spi_slv->max_speed_hz); 275561de45fSGirish Mahadevan } 276561de45fSGirish Mahadevan 277561de45fSGirish Mahadevan static int spi_geni_prepare_message(struct spi_master *spi, 278561de45fSGirish Mahadevan struct spi_message *spi_msg) 279561de45fSGirish Mahadevan { 280561de45fSGirish Mahadevan int ret; 281561de45fSGirish Mahadevan struct spi_geni_master *mas = spi_master_get_devdata(spi); 282561de45fSGirish Mahadevan 283561de45fSGirish Mahadevan ret = setup_fifo_params(spi_msg->spi, spi); 284561de45fSGirish Mahadevan if (ret) 285561de45fSGirish Mahadevan dev_err(mas->dev, "Couldn't select mode %d\n", ret); 286561de45fSGirish Mahadevan return ret; 287561de45fSGirish Mahadevan } 288561de45fSGirish Mahadevan 289561de45fSGirish Mahadevan static int spi_geni_init(struct spi_geni_master *mas) 290561de45fSGirish Mahadevan { 291561de45fSGirish Mahadevan struct geni_se *se = &mas->se; 292561de45fSGirish Mahadevan unsigned int proto, major, minor, ver; 29314ac4e04SDouglas Anderson u32 spi_tx_cfg; 294561de45fSGirish Mahadevan 295561de45fSGirish Mahadevan pm_runtime_get_sync(mas->dev); 296561de45fSGirish Mahadevan 297561de45fSGirish Mahadevan proto = geni_se_read_proto(se); 298561de45fSGirish Mahadevan if (proto != GENI_SE_SPI) { 299561de45fSGirish Mahadevan dev_err(mas->dev, "Invalid proto %d\n", proto); 300561de45fSGirish Mahadevan pm_runtime_put(mas->dev); 301561de45fSGirish Mahadevan return -ENXIO; 302561de45fSGirish Mahadevan } 303561de45fSGirish Mahadevan mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se); 304561de45fSGirish Mahadevan 305561de45fSGirish Mahadevan /* Width of Tx and Rx FIFO is same */ 306561de45fSGirish Mahadevan mas->fifo_width_bits = geni_se_get_tx_fifo_width(se); 307561de45fSGirish Mahadevan 308561de45fSGirish Mahadevan /* 309561de45fSGirish Mahadevan * Hardware programming guide suggests to configure 310561de45fSGirish Mahadevan * RX FIFO RFR level to fifo_depth-2. 311561de45fSGirish Mahadevan */ 312fc129a43SDouglas Anderson geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2); 313561de45fSGirish Mahadevan /* Transmit an entire FIFO worth of data per IRQ */ 314561de45fSGirish Mahadevan mas->tx_wm = 1; 315561de45fSGirish Mahadevan ver = geni_se_get_qup_hw_version(se); 316561de45fSGirish Mahadevan major = GENI_SE_VERSION_MAJOR(ver); 317561de45fSGirish Mahadevan minor = GENI_SE_VERSION_MINOR(ver); 318561de45fSGirish Mahadevan 319561de45fSGirish Mahadevan if (major == 1 && minor == 0) 320561de45fSGirish Mahadevan mas->oversampling = 2; 321561de45fSGirish Mahadevan else 322561de45fSGirish Mahadevan mas->oversampling = 1; 323561de45fSGirish Mahadevan 324da48dc8cSDouglas Anderson geni_se_select_mode(se, GENI_SE_FIFO); 325da48dc8cSDouglas Anderson 32614ac4e04SDouglas Anderson /* We always control CS manually */ 32714ac4e04SDouglas Anderson spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG); 32814ac4e04SDouglas Anderson spi_tx_cfg &= ~CS_TOGGLE; 32914ac4e04SDouglas Anderson writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG); 33014ac4e04SDouglas Anderson 331561de45fSGirish Mahadevan pm_runtime_put(mas->dev); 332561de45fSGirish Mahadevan return 0; 333561de45fSGirish Mahadevan } 334561de45fSGirish Mahadevan 3356d66507dSDouglas Anderson static unsigned int geni_byte_per_fifo_word(struct spi_geni_master *mas) 3366d66507dSDouglas Anderson { 3376d66507dSDouglas Anderson /* 3386d66507dSDouglas Anderson * Calculate how many bytes we'll put in each FIFO word. If the 3396d66507dSDouglas Anderson * transfer words don't pack cleanly into a FIFO word we'll just put 3406d66507dSDouglas Anderson * one transfer word in each FIFO word. If they do pack we'll pack 'em. 3416d66507dSDouglas Anderson */ 3426d66507dSDouglas Anderson if (mas->fifo_width_bits % mas->cur_bits_per_word) 3436d66507dSDouglas Anderson return roundup_pow_of_two(DIV_ROUND_UP(mas->cur_bits_per_word, 3446d66507dSDouglas Anderson BITS_PER_BYTE)); 3456d66507dSDouglas Anderson 3466d66507dSDouglas Anderson return mas->fifo_width_bits / BITS_PER_BYTE; 3476d66507dSDouglas Anderson } 3486d66507dSDouglas Anderson 3496d66507dSDouglas Anderson static bool geni_spi_handle_tx(struct spi_geni_master *mas) 3506d66507dSDouglas Anderson { 3516d66507dSDouglas Anderson struct geni_se *se = &mas->se; 3526d66507dSDouglas Anderson unsigned int max_bytes; 3536d66507dSDouglas Anderson const u8 *tx_buf; 3546d66507dSDouglas Anderson unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas); 3556d66507dSDouglas Anderson unsigned int i = 0; 3566d66507dSDouglas Anderson 3576d66507dSDouglas Anderson max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * bytes_per_fifo_word; 3586d66507dSDouglas Anderson if (mas->tx_rem_bytes < max_bytes) 3596d66507dSDouglas Anderson max_bytes = mas->tx_rem_bytes; 3606d66507dSDouglas Anderson 3616d66507dSDouglas Anderson tx_buf = mas->cur_xfer->tx_buf + mas->cur_xfer->len - mas->tx_rem_bytes; 3626d66507dSDouglas Anderson while (i < max_bytes) { 3636d66507dSDouglas Anderson unsigned int j; 3646d66507dSDouglas Anderson unsigned int bytes_to_write; 3656d66507dSDouglas Anderson u32 fifo_word = 0; 3666d66507dSDouglas Anderson u8 *fifo_byte = (u8 *)&fifo_word; 3676d66507dSDouglas Anderson 3686d66507dSDouglas Anderson bytes_to_write = min(bytes_per_fifo_word, max_bytes - i); 3696d66507dSDouglas Anderson for (j = 0; j < bytes_to_write; j++) 3706d66507dSDouglas Anderson fifo_byte[j] = tx_buf[i++]; 3716d66507dSDouglas Anderson iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1); 3726d66507dSDouglas Anderson } 3736d66507dSDouglas Anderson mas->tx_rem_bytes -= max_bytes; 3746d66507dSDouglas Anderson if (!mas->tx_rem_bytes) { 3756d66507dSDouglas Anderson writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 3766d66507dSDouglas Anderson return false; 3776d66507dSDouglas Anderson } 3786d66507dSDouglas Anderson return true; 3796d66507dSDouglas Anderson } 3806d66507dSDouglas Anderson 3816d66507dSDouglas Anderson static void geni_spi_handle_rx(struct spi_geni_master *mas) 3826d66507dSDouglas Anderson { 3836d66507dSDouglas Anderson struct geni_se *se = &mas->se; 3846d66507dSDouglas Anderson u32 rx_fifo_status; 3856d66507dSDouglas Anderson unsigned int rx_bytes; 3866d66507dSDouglas Anderson unsigned int rx_last_byte_valid; 3876d66507dSDouglas Anderson u8 *rx_buf; 3886d66507dSDouglas Anderson unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas); 3896d66507dSDouglas Anderson unsigned int i = 0; 3906d66507dSDouglas Anderson 3916d66507dSDouglas Anderson rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS); 3926d66507dSDouglas Anderson rx_bytes = (rx_fifo_status & RX_FIFO_WC_MSK) * bytes_per_fifo_word; 3936d66507dSDouglas Anderson if (rx_fifo_status & RX_LAST) { 3946d66507dSDouglas Anderson rx_last_byte_valid = rx_fifo_status & RX_LAST_BYTE_VALID_MSK; 3956d66507dSDouglas Anderson rx_last_byte_valid >>= RX_LAST_BYTE_VALID_SHFT; 3966d66507dSDouglas Anderson if (rx_last_byte_valid && rx_last_byte_valid < 4) 3976d66507dSDouglas Anderson rx_bytes -= bytes_per_fifo_word - rx_last_byte_valid; 3986d66507dSDouglas Anderson } 3996d66507dSDouglas Anderson if (mas->rx_rem_bytes < rx_bytes) 4006d66507dSDouglas Anderson rx_bytes = mas->rx_rem_bytes; 4016d66507dSDouglas Anderson 4026d66507dSDouglas Anderson rx_buf = mas->cur_xfer->rx_buf + mas->cur_xfer->len - mas->rx_rem_bytes; 4036d66507dSDouglas Anderson while (i < rx_bytes) { 4046d66507dSDouglas Anderson u32 fifo_word = 0; 4056d66507dSDouglas Anderson u8 *fifo_byte = (u8 *)&fifo_word; 4066d66507dSDouglas Anderson unsigned int bytes_to_read; 4076d66507dSDouglas Anderson unsigned int j; 4086d66507dSDouglas Anderson 4096d66507dSDouglas Anderson bytes_to_read = min(bytes_per_fifo_word, rx_bytes - i); 4106d66507dSDouglas Anderson ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1); 4116d66507dSDouglas Anderson for (j = 0; j < bytes_to_read; j++) 4126d66507dSDouglas Anderson rx_buf[i++] = fifo_byte[j]; 4136d66507dSDouglas Anderson } 4146d66507dSDouglas Anderson mas->rx_rem_bytes -= rx_bytes; 4156d66507dSDouglas Anderson } 4166d66507dSDouglas Anderson 417561de45fSGirish Mahadevan static void setup_fifo_xfer(struct spi_transfer *xfer, 418561de45fSGirish Mahadevan struct spi_geni_master *mas, 419561de45fSGirish Mahadevan u16 mode, struct spi_master *spi) 420561de45fSGirish Mahadevan { 421561de45fSGirish Mahadevan u32 m_cmd = 0; 42214ac4e04SDouglas Anderson u32 len; 423561de45fSGirish Mahadevan struct geni_se *se = &mas->se; 424e68b6624SDouglas Anderson int ret; 425561de45fSGirish Mahadevan 4262ee471a1SDouglas Anderson /* 4272ee471a1SDouglas Anderson * Ensure that our interrupt handler isn't still running from some 4282ee471a1SDouglas Anderson * prior command before we start messing with the hardware behind 4292ee471a1SDouglas Anderson * its back. We don't need to _keep_ the lock here since we're only 4302ee471a1SDouglas Anderson * worried about racing with out interrupt handler. The SPI core 4312ee471a1SDouglas Anderson * already handles making sure that we're not trying to do two 4322ee471a1SDouglas Anderson * transfers at once or setting a chip select and doing a transfer 4332ee471a1SDouglas Anderson * concurrently. 4342ee471a1SDouglas Anderson * 4352ee471a1SDouglas Anderson * NOTE: we actually _can't_ hold the lock here because possibly we 4362ee471a1SDouglas Anderson * might call clk_set_rate() which needs to be able to sleep. 4372ee471a1SDouglas Anderson */ 4382ee471a1SDouglas Anderson spin_lock_irq(&mas->lock); 4392ee471a1SDouglas Anderson spin_unlock_irq(&mas->lock); 4402ee471a1SDouglas Anderson 441561de45fSGirish Mahadevan if (xfer->bits_per_word != mas->cur_bits_per_word) { 442561de45fSGirish Mahadevan spi_setup_word_len(mas, mode, xfer->bits_per_word); 443561de45fSGirish Mahadevan mas->cur_bits_per_word = xfer->bits_per_word; 444561de45fSGirish Mahadevan } 445561de45fSGirish Mahadevan 446561de45fSGirish Mahadevan /* Speed and bits per word can be overridden per transfer */ 4470e3b8a81SAkash Asthana ret = geni_spi_set_clock_and_bw(mas, xfer->speed_hz); 448e68b6624SDouglas Anderson if (ret) 449561de45fSGirish Mahadevan return; 450561de45fSGirish Mahadevan 451561de45fSGirish Mahadevan mas->tx_rem_bytes = 0; 452561de45fSGirish Mahadevan mas->rx_rem_bytes = 0; 453561de45fSGirish Mahadevan 454561de45fSGirish Mahadevan if (!(mas->cur_bits_per_word % MIN_WORD_LEN)) 455561de45fSGirish Mahadevan len = xfer->len * BITS_PER_BYTE / mas->cur_bits_per_word; 456561de45fSGirish Mahadevan else 457561de45fSGirish Mahadevan len = xfer->len / (mas->cur_bits_per_word / BITS_PER_BYTE + 1); 458561de45fSGirish Mahadevan len &= TRANS_LEN_MSK; 459561de45fSGirish Mahadevan 460561de45fSGirish Mahadevan mas->cur_xfer = xfer; 46119ea3275SStephen Boyd if (xfer->tx_buf) { 46219ea3275SStephen Boyd m_cmd |= SPI_TX_ONLY; 463561de45fSGirish Mahadevan mas->tx_rem_bytes = xfer->len; 464561de45fSGirish Mahadevan writel(len, se->base + SE_SPI_TX_TRANS_LEN); 465561de45fSGirish Mahadevan } 466561de45fSGirish Mahadevan 46719ea3275SStephen Boyd if (xfer->rx_buf) { 46819ea3275SStephen Boyd m_cmd |= SPI_RX_ONLY; 469561de45fSGirish Mahadevan writel(len, se->base + SE_SPI_RX_TRANS_LEN); 470561de45fSGirish Mahadevan mas->rx_rem_bytes = xfer->len; 471561de45fSGirish Mahadevan } 4722ee471a1SDouglas Anderson 4732ee471a1SDouglas Anderson /* 4742ee471a1SDouglas Anderson * Lock around right before we start the transfer since our 4752ee471a1SDouglas Anderson * interrupt could come in at any time now. 4762ee471a1SDouglas Anderson */ 4772ee471a1SDouglas Anderson spin_lock_irq(&mas->lock); 478561de45fSGirish Mahadevan geni_se_setup_m_cmd(se, m_cmd, FRAGMENTATION); 479561de45fSGirish Mahadevan 480561de45fSGirish Mahadevan /* 481561de45fSGirish Mahadevan * TX_WATERMARK_REG should be set after SPI configuration and 482561de45fSGirish Mahadevan * setting up GENI SE engine, as driver starts data transfer 483561de45fSGirish Mahadevan * for the watermark interrupt. 484561de45fSGirish Mahadevan */ 4856d66507dSDouglas Anderson if (m_cmd & SPI_TX_ONLY) { 4866d66507dSDouglas Anderson if (geni_spi_handle_tx(mas)) 487561de45fSGirish Mahadevan writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG); 4886d66507dSDouglas Anderson } 4892ee471a1SDouglas Anderson spin_unlock_irq(&mas->lock); 490561de45fSGirish Mahadevan } 491561de45fSGirish Mahadevan 492561de45fSGirish Mahadevan static int spi_geni_transfer_one(struct spi_master *spi, 493561de45fSGirish Mahadevan struct spi_device *slv, 494561de45fSGirish Mahadevan struct spi_transfer *xfer) 495561de45fSGirish Mahadevan { 496561de45fSGirish Mahadevan struct spi_geni_master *mas = spi_master_get_devdata(spi); 497561de45fSGirish Mahadevan 498561de45fSGirish Mahadevan /* Terminate and return success for 0 byte length transfer */ 499561de45fSGirish Mahadevan if (!xfer->len) 500561de45fSGirish Mahadevan return 0; 501561de45fSGirish Mahadevan 502561de45fSGirish Mahadevan setup_fifo_xfer(xfer, mas, slv->mode, spi); 503561de45fSGirish Mahadevan return 1; 504561de45fSGirish Mahadevan } 505561de45fSGirish Mahadevan 506561de45fSGirish Mahadevan static irqreturn_t geni_spi_isr(int irq, void *data) 507561de45fSGirish Mahadevan { 508561de45fSGirish Mahadevan struct spi_master *spi = data; 509561de45fSGirish Mahadevan struct spi_geni_master *mas = spi_master_get_devdata(spi); 510561de45fSGirish Mahadevan struct geni_se *se = &mas->se; 511561de45fSGirish Mahadevan u32 m_irq; 512561de45fSGirish Mahadevan 5132ee471a1SDouglas Anderson m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); 5142ee471a1SDouglas Anderson if (!m_irq) 515561de45fSGirish Mahadevan return IRQ_NONE; 516561de45fSGirish Mahadevan 517e191a082SDouglas Anderson if (m_irq & (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN | 518e191a082SDouglas Anderson M_RX_FIFO_RD_ERR_EN | M_RX_FIFO_WR_ERR_EN | 519e191a082SDouglas Anderson M_TX_FIFO_RD_ERR_EN | M_TX_FIFO_WR_ERR_EN)) 520e191a082SDouglas Anderson dev_warn(mas->dev, "Unexpected IRQ err status %#010x\n", m_irq); 521e191a082SDouglas Anderson 522539afdf9SDouglas Anderson spin_lock(&mas->lock); 523561de45fSGirish Mahadevan 524561de45fSGirish Mahadevan if ((m_irq & M_RX_FIFO_WATERMARK_EN) || (m_irq & M_RX_FIFO_LAST_EN)) 525561de45fSGirish Mahadevan geni_spi_handle_rx(mas); 526561de45fSGirish Mahadevan 527561de45fSGirish Mahadevan if (m_irq & M_TX_FIFO_WATERMARK_EN) 528561de45fSGirish Mahadevan geni_spi_handle_tx(mas); 529561de45fSGirish Mahadevan 530561de45fSGirish Mahadevan if (m_irq & M_CMD_DONE_EN) { 5317ba9bdcbSDouglas Anderson if (mas->cur_xfer) { 532561de45fSGirish Mahadevan spi_finalize_current_transfer(spi); 5337ba9bdcbSDouglas Anderson mas->cur_xfer = NULL; 534561de45fSGirish Mahadevan /* 53559ab0fa0SStephen Boyd * If this happens, then a CMD_DONE came before all the 53659ab0fa0SStephen Boyd * Tx buffer bytes were sent out. This is unusual, log 53759ab0fa0SStephen Boyd * this condition and disable the WM interrupt to 53859ab0fa0SStephen Boyd * prevent the system from stalling due an interrupt 53959ab0fa0SStephen Boyd * storm. 54059ab0fa0SStephen Boyd * 54159ab0fa0SStephen Boyd * If this happens when all Rx bytes haven't been 54259ab0fa0SStephen Boyd * received, log the condition. The only known time 54359ab0fa0SStephen Boyd * this can happen is if bits_per_word != 8 and some 54459ab0fa0SStephen Boyd * registers that expect xfer lengths in num spi_words 545561de45fSGirish Mahadevan * weren't written correctly. 546561de45fSGirish Mahadevan */ 547561de45fSGirish Mahadevan if (mas->tx_rem_bytes) { 548561de45fSGirish Mahadevan writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 549561de45fSGirish Mahadevan dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n", 550561de45fSGirish Mahadevan mas->tx_rem_bytes, mas->cur_bits_per_word); 551561de45fSGirish Mahadevan } 552561de45fSGirish Mahadevan if (mas->rx_rem_bytes) 553561de45fSGirish Mahadevan dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n", 554561de45fSGirish Mahadevan mas->rx_rem_bytes, mas->cur_bits_per_word); 55559ab0fa0SStephen Boyd } else { 55659ab0fa0SStephen Boyd complete(&mas->cs_done); 55759ab0fa0SStephen Boyd } 558561de45fSGirish Mahadevan } 559561de45fSGirish Mahadevan 5607ba9bdcbSDouglas Anderson if (m_irq & M_CMD_CANCEL_EN) 5617ba9bdcbSDouglas Anderson complete(&mas->cancel_done); 5627ba9bdcbSDouglas Anderson if (m_irq & M_CMD_ABORT_EN) 5637ba9bdcbSDouglas Anderson complete(&mas->abort_done); 564561de45fSGirish Mahadevan 5652ee471a1SDouglas Anderson /* 5662ee471a1SDouglas Anderson * It's safe or a good idea to Ack all of our our interrupts at the 5672ee471a1SDouglas Anderson * end of the function. Specifically: 5682ee471a1SDouglas Anderson * - M_CMD_DONE_EN / M_RX_FIFO_LAST_EN: Edge triggered interrupts and 5692ee471a1SDouglas Anderson * clearing Acks. Clearing at the end relies on nobody else having 5702ee471a1SDouglas Anderson * started a new transfer yet or else we could be clearing _their_ 5712ee471a1SDouglas Anderson * done bit, but everyone grabs the spinlock before starting a new 5722ee471a1SDouglas Anderson * transfer. 5732ee471a1SDouglas Anderson * - M_RX_FIFO_WATERMARK_EN / M_TX_FIFO_WATERMARK_EN: These appear 5742ee471a1SDouglas Anderson * to be "latched level" interrupts so it's important to clear them 5752ee471a1SDouglas Anderson * _after_ you've handled the condition and always safe to do so 5762ee471a1SDouglas Anderson * since they'll re-assert if they're still happening. 5772ee471a1SDouglas Anderson */ 578561de45fSGirish Mahadevan writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR); 5792ee471a1SDouglas Anderson 580539afdf9SDouglas Anderson spin_unlock(&mas->lock); 5812ee471a1SDouglas Anderson 5820dccff3cSAlok Chauhan return IRQ_HANDLED; 583561de45fSGirish Mahadevan } 584561de45fSGirish Mahadevan 585561de45fSGirish Mahadevan static int spi_geni_probe(struct platform_device *pdev) 586561de45fSGirish Mahadevan { 5876a34e285SAlok Chauhan int ret, irq; 588561de45fSGirish Mahadevan struct spi_master *spi; 589561de45fSGirish Mahadevan struct spi_geni_master *mas; 5906a34e285SAlok Chauhan void __iomem *base; 5916a34e285SAlok Chauhan struct clk *clk; 592ea1e5b33SStephen Boyd struct device *dev = &pdev->dev; 5936a34e285SAlok Chauhan 5946a34e285SAlok Chauhan irq = platform_get_irq(pdev, 0); 5956b8ac10eSStephen Boyd if (irq < 0) 5966a34e285SAlok Chauhan return irq; 5976a34e285SAlok Chauhan 598d8e477abSYueHaibing base = devm_platform_ioremap_resource(pdev, 0); 5996a34e285SAlok Chauhan if (IS_ERR(base)) 6006a34e285SAlok Chauhan return PTR_ERR(base); 6016a34e285SAlok Chauhan 602ea1e5b33SStephen Boyd clk = devm_clk_get(dev, "se"); 603ea1e5b33SStephen Boyd if (IS_ERR(clk)) 6046a34e285SAlok Chauhan return PTR_ERR(clk); 605561de45fSGirish Mahadevan 606ea1e5b33SStephen Boyd spi = spi_alloc_master(dev, sizeof(*mas)); 607561de45fSGirish Mahadevan if (!spi) 608561de45fSGirish Mahadevan return -ENOMEM; 609561de45fSGirish Mahadevan 610561de45fSGirish Mahadevan platform_set_drvdata(pdev, spi); 611561de45fSGirish Mahadevan mas = spi_master_get_devdata(spi); 6126a34e285SAlok Chauhan mas->irq = irq; 613ea1e5b33SStephen Boyd mas->dev = dev; 614ea1e5b33SStephen Boyd mas->se.dev = dev; 615ea1e5b33SStephen Boyd mas->se.wrapper = dev_get_drvdata(dev->parent); 6166a34e285SAlok Chauhan mas->se.base = base; 6176a34e285SAlok Chauhan mas->se.clk = clk; 6181a9e489eSRajendra Nayak mas->se.opp_table = dev_pm_opp_set_clkname(&pdev->dev, "se"); 6191a9e489eSRajendra Nayak if (IS_ERR(mas->se.opp_table)) 6201a9e489eSRajendra Nayak return PTR_ERR(mas->se.opp_table); 6211a9e489eSRajendra Nayak /* OPP table is optional */ 6221a9e489eSRajendra Nayak ret = dev_pm_opp_of_add_table(&pdev->dev); 6237d568edfSViresh Kumar if (ret && ret != -ENODEV) { 6241a9e489eSRajendra Nayak dev_err(&pdev->dev, "invalid OPP table in device tree\n"); 6257d568edfSViresh Kumar goto put_clkname; 6261a9e489eSRajendra Nayak } 627561de45fSGirish Mahadevan 628561de45fSGirish Mahadevan spi->bus_num = -1; 629ea1e5b33SStephen Boyd spi->dev.of_node = dev->of_node; 630561de45fSGirish Mahadevan spi->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH; 631561de45fSGirish Mahadevan spi->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 632561de45fSGirish Mahadevan spi->num_chipselect = 4; 633561de45fSGirish Mahadevan spi->max_speed_hz = 50000000; 634561de45fSGirish Mahadevan spi->prepare_message = spi_geni_prepare_message; 635561de45fSGirish Mahadevan spi->transfer_one = spi_geni_transfer_one; 636561de45fSGirish Mahadevan spi->auto_runtime_pm = true; 637561de45fSGirish Mahadevan spi->handle_err = handle_fifo_timeout; 638561de45fSGirish Mahadevan spi->set_cs = spi_geni_set_cs; 639561de45fSGirish Mahadevan 6407ba9bdcbSDouglas Anderson init_completion(&mas->cs_done); 6417ba9bdcbSDouglas Anderson init_completion(&mas->cancel_done); 6427ba9bdcbSDouglas Anderson init_completion(&mas->abort_done); 643561de45fSGirish Mahadevan spin_lock_init(&mas->lock); 644cfdab2cdSDouglas Anderson pm_runtime_use_autosuspend(&pdev->dev); 645cfdab2cdSDouglas Anderson pm_runtime_set_autosuspend_delay(&pdev->dev, 250); 646ea1e5b33SStephen Boyd pm_runtime_enable(dev); 647561de45fSGirish Mahadevan 6480e3b8a81SAkash Asthana ret = geni_icc_get(&mas->se, NULL); 6490e3b8a81SAkash Asthana if (ret) 6500e3b8a81SAkash Asthana goto spi_geni_probe_runtime_disable; 6510e3b8a81SAkash Asthana /* Set the bus quota to a reasonable value for register access */ 6520e3b8a81SAkash Asthana mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ); 6530e3b8a81SAkash Asthana mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; 6540e3b8a81SAkash Asthana 6550e3b8a81SAkash Asthana ret = geni_icc_set_bw(&mas->se); 6560e3b8a81SAkash Asthana if (ret) 6570e3b8a81SAkash Asthana goto spi_geni_probe_runtime_disable; 6580e3b8a81SAkash Asthana 659561de45fSGirish Mahadevan ret = spi_geni_init(mas); 660561de45fSGirish Mahadevan if (ret) 661561de45fSGirish Mahadevan goto spi_geni_probe_runtime_disable; 662561de45fSGirish Mahadevan 663ea1e5b33SStephen Boyd ret = request_irq(mas->irq, geni_spi_isr, 0, dev_name(dev), spi); 664561de45fSGirish Mahadevan if (ret) 665561de45fSGirish Mahadevan goto spi_geni_probe_runtime_disable; 666561de45fSGirish Mahadevan 667561de45fSGirish Mahadevan ret = spi_register_master(spi); 668561de45fSGirish Mahadevan if (ret) 669561de45fSGirish Mahadevan goto spi_geni_probe_free_irq; 670561de45fSGirish Mahadevan 671561de45fSGirish Mahadevan return 0; 672561de45fSGirish Mahadevan spi_geni_probe_free_irq: 673561de45fSGirish Mahadevan free_irq(mas->irq, spi); 674561de45fSGirish Mahadevan spi_geni_probe_runtime_disable: 675ea1e5b33SStephen Boyd pm_runtime_disable(dev); 676561de45fSGirish Mahadevan spi_master_put(spi); 6771a9e489eSRajendra Nayak dev_pm_opp_of_remove_table(&pdev->dev); 6787d568edfSViresh Kumar put_clkname: 6791a9e489eSRajendra Nayak dev_pm_opp_put_clkname(mas->se.opp_table); 680561de45fSGirish Mahadevan return ret; 681561de45fSGirish Mahadevan } 682561de45fSGirish Mahadevan 683561de45fSGirish Mahadevan static int spi_geni_remove(struct platform_device *pdev) 684561de45fSGirish Mahadevan { 685561de45fSGirish Mahadevan struct spi_master *spi = platform_get_drvdata(pdev); 686561de45fSGirish Mahadevan struct spi_geni_master *mas = spi_master_get_devdata(spi); 687561de45fSGirish Mahadevan 688561de45fSGirish Mahadevan /* Unregister _before_ disabling pm_runtime() so we stop transfers */ 689561de45fSGirish Mahadevan spi_unregister_master(spi); 690561de45fSGirish Mahadevan 691561de45fSGirish Mahadevan free_irq(mas->irq, spi); 692561de45fSGirish Mahadevan pm_runtime_disable(&pdev->dev); 6931a9e489eSRajendra Nayak dev_pm_opp_of_remove_table(&pdev->dev); 6941a9e489eSRajendra Nayak dev_pm_opp_put_clkname(mas->se.opp_table); 695561de45fSGirish Mahadevan return 0; 696561de45fSGirish Mahadevan } 697561de45fSGirish Mahadevan 698561de45fSGirish Mahadevan static int __maybe_unused spi_geni_runtime_suspend(struct device *dev) 699561de45fSGirish Mahadevan { 700561de45fSGirish Mahadevan struct spi_master *spi = dev_get_drvdata(dev); 701561de45fSGirish Mahadevan struct spi_geni_master *mas = spi_master_get_devdata(spi); 7020e3b8a81SAkash Asthana int ret; 703561de45fSGirish Mahadevan 7041a9e489eSRajendra Nayak /* Drop the performance state vote */ 7051a9e489eSRajendra Nayak dev_pm_opp_set_rate(dev, 0); 7061a9e489eSRajendra Nayak 7070e3b8a81SAkash Asthana ret = geni_se_resources_off(&mas->se); 7080e3b8a81SAkash Asthana if (ret) 7090e3b8a81SAkash Asthana return ret; 7100e3b8a81SAkash Asthana 7110e3b8a81SAkash Asthana return geni_icc_disable(&mas->se); 712561de45fSGirish Mahadevan } 713561de45fSGirish Mahadevan 714561de45fSGirish Mahadevan static int __maybe_unused spi_geni_runtime_resume(struct device *dev) 715561de45fSGirish Mahadevan { 716561de45fSGirish Mahadevan struct spi_master *spi = dev_get_drvdata(dev); 717561de45fSGirish Mahadevan struct spi_geni_master *mas = spi_master_get_devdata(spi); 7180e3b8a81SAkash Asthana int ret; 7190e3b8a81SAkash Asthana 7200e3b8a81SAkash Asthana ret = geni_icc_enable(&mas->se); 7210e3b8a81SAkash Asthana if (ret) 7220e3b8a81SAkash Asthana return ret; 723561de45fSGirish Mahadevan 7245f219524SDouglas Anderson ret = geni_se_resources_on(&mas->se); 7255f219524SDouglas Anderson if (ret) 7265f219524SDouglas Anderson return ret; 7275f219524SDouglas Anderson 7285f219524SDouglas Anderson return dev_pm_opp_set_rate(mas->dev, mas->cur_sclk_hz); 729561de45fSGirish Mahadevan } 730561de45fSGirish Mahadevan 731561de45fSGirish Mahadevan static int __maybe_unused spi_geni_suspend(struct device *dev) 732561de45fSGirish Mahadevan { 733561de45fSGirish Mahadevan struct spi_master *spi = dev_get_drvdata(dev); 734561de45fSGirish Mahadevan int ret; 735561de45fSGirish Mahadevan 736561de45fSGirish Mahadevan ret = spi_master_suspend(spi); 737561de45fSGirish Mahadevan if (ret) 738561de45fSGirish Mahadevan return ret; 739561de45fSGirish Mahadevan 740561de45fSGirish Mahadevan ret = pm_runtime_force_suspend(dev); 741561de45fSGirish Mahadevan if (ret) 742561de45fSGirish Mahadevan spi_master_resume(spi); 743561de45fSGirish Mahadevan 744561de45fSGirish Mahadevan return ret; 745561de45fSGirish Mahadevan } 746561de45fSGirish Mahadevan 747561de45fSGirish Mahadevan static int __maybe_unused spi_geni_resume(struct device *dev) 748561de45fSGirish Mahadevan { 749561de45fSGirish Mahadevan struct spi_master *spi = dev_get_drvdata(dev); 750561de45fSGirish Mahadevan int ret; 751561de45fSGirish Mahadevan 752561de45fSGirish Mahadevan ret = pm_runtime_force_resume(dev); 753561de45fSGirish Mahadevan if (ret) 754561de45fSGirish Mahadevan return ret; 755561de45fSGirish Mahadevan 756561de45fSGirish Mahadevan ret = spi_master_resume(spi); 757561de45fSGirish Mahadevan if (ret) 758561de45fSGirish Mahadevan pm_runtime_force_suspend(dev); 759561de45fSGirish Mahadevan 760561de45fSGirish Mahadevan return ret; 761561de45fSGirish Mahadevan } 762561de45fSGirish Mahadevan 763561de45fSGirish Mahadevan static const struct dev_pm_ops spi_geni_pm_ops = { 764561de45fSGirish Mahadevan SET_RUNTIME_PM_OPS(spi_geni_runtime_suspend, 765561de45fSGirish Mahadevan spi_geni_runtime_resume, NULL) 766561de45fSGirish Mahadevan SET_SYSTEM_SLEEP_PM_OPS(spi_geni_suspend, spi_geni_resume) 767561de45fSGirish Mahadevan }; 768561de45fSGirish Mahadevan 769561de45fSGirish Mahadevan static const struct of_device_id spi_geni_dt_match[] = { 770561de45fSGirish Mahadevan { .compatible = "qcom,geni-spi" }, 771561de45fSGirish Mahadevan {} 772561de45fSGirish Mahadevan }; 773561de45fSGirish Mahadevan MODULE_DEVICE_TABLE(of, spi_geni_dt_match); 774561de45fSGirish Mahadevan 775561de45fSGirish Mahadevan static struct platform_driver spi_geni_driver = { 776561de45fSGirish Mahadevan .probe = spi_geni_probe, 777561de45fSGirish Mahadevan .remove = spi_geni_remove, 778561de45fSGirish Mahadevan .driver = { 779561de45fSGirish Mahadevan .name = "geni_spi", 780561de45fSGirish Mahadevan .pm = &spi_geni_pm_ops, 781561de45fSGirish Mahadevan .of_match_table = spi_geni_dt_match, 782561de45fSGirish Mahadevan }, 783561de45fSGirish Mahadevan }; 784561de45fSGirish Mahadevan module_platform_driver(spi_geni_driver); 785561de45fSGirish Mahadevan 786561de45fSGirish Mahadevan MODULE_DESCRIPTION("SPI driver for GENI based QUP cores"); 787561de45fSGirish Mahadevan MODULE_LICENSE("GPL v2"); 788