1561de45fSGirish Mahadevan // SPDX-License-Identifier: GPL-2.0 2561de45fSGirish Mahadevan // Copyright (c) 2017-2018, The Linux foundation. All rights reserved. 3561de45fSGirish Mahadevan 4561de45fSGirish Mahadevan #include <linux/clk.h> 5b59c1224SVinod Koul #include <linux/dmaengine.h> 6b59c1224SVinod Koul #include <linux/dma-mapping.h> 7b59c1224SVinod Koul #include <linux/dma/qcom-gpi-dma.h> 8561de45fSGirish Mahadevan #include <linux/interrupt.h> 9561de45fSGirish Mahadevan #include <linux/io.h> 10561de45fSGirish Mahadevan #include <linux/log2.h> 11561de45fSGirish Mahadevan #include <linux/module.h> 12561de45fSGirish Mahadevan #include <linux/platform_device.h> 131a9e489eSRajendra Nayak #include <linux/pm_opp.h> 14561de45fSGirish Mahadevan #include <linux/pm_runtime.h> 15*491581f4SElliot Berman #include <linux/soc/qcom/geni-se.h> 16561de45fSGirish Mahadevan #include <linux/spi/spi.h> 17561de45fSGirish Mahadevan #include <linux/spinlock.h> 18561de45fSGirish Mahadevan 19561de45fSGirish Mahadevan /* SPI SE specific registers and respective register fields */ 20561de45fSGirish Mahadevan #define SE_SPI_CPHA 0x224 21561de45fSGirish Mahadevan #define CPHA BIT(0) 22561de45fSGirish Mahadevan 23561de45fSGirish Mahadevan #define SE_SPI_LOOPBACK 0x22c 24561de45fSGirish Mahadevan #define LOOPBACK_ENABLE 0x1 25561de45fSGirish Mahadevan #define NORMAL_MODE 0x0 26561de45fSGirish Mahadevan #define LOOPBACK_MSK GENMASK(1, 0) 27561de45fSGirish Mahadevan 28561de45fSGirish Mahadevan #define SE_SPI_CPOL 0x230 29561de45fSGirish Mahadevan #define CPOL BIT(2) 30561de45fSGirish Mahadevan 31561de45fSGirish Mahadevan #define SE_SPI_DEMUX_OUTPUT_INV 0x24c 32561de45fSGirish Mahadevan #define CS_DEMUX_OUTPUT_INV_MSK GENMASK(3, 0) 33561de45fSGirish Mahadevan 34561de45fSGirish Mahadevan #define SE_SPI_DEMUX_SEL 0x250 35561de45fSGirish Mahadevan #define CS_DEMUX_OUTPUT_SEL GENMASK(3, 0) 36561de45fSGirish Mahadevan 37561de45fSGirish Mahadevan #define SE_SPI_TRANS_CFG 0x25c 38561de45fSGirish Mahadevan #define CS_TOGGLE BIT(0) 39561de45fSGirish Mahadevan 40561de45fSGirish Mahadevan #define SE_SPI_WORD_LEN 0x268 41561de45fSGirish Mahadevan #define WORD_LEN_MSK GENMASK(9, 0) 42561de45fSGirish Mahadevan #define MIN_WORD_LEN 4 43561de45fSGirish Mahadevan 44561de45fSGirish Mahadevan #define SE_SPI_TX_TRANS_LEN 0x26c 45561de45fSGirish Mahadevan #define SE_SPI_RX_TRANS_LEN 0x270 46561de45fSGirish Mahadevan #define TRANS_LEN_MSK GENMASK(23, 0) 47561de45fSGirish Mahadevan 48561de45fSGirish Mahadevan #define SE_SPI_PRE_POST_CMD_DLY 0x274 49561de45fSGirish Mahadevan 50561de45fSGirish Mahadevan #define SE_SPI_DELAY_COUNTERS 0x278 51561de45fSGirish Mahadevan #define SPI_INTER_WORDS_DELAY_MSK GENMASK(9, 0) 52561de45fSGirish Mahadevan #define SPI_CS_CLK_DELAY_MSK GENMASK(19, 10) 53561de45fSGirish Mahadevan #define SPI_CS_CLK_DELAY_SHFT 10 54561de45fSGirish Mahadevan 55561de45fSGirish Mahadevan /* M_CMD OP codes for SPI */ 56561de45fSGirish Mahadevan #define SPI_TX_ONLY 1 57561de45fSGirish Mahadevan #define SPI_RX_ONLY 2 58561de45fSGirish Mahadevan #define SPI_TX_RX 7 59561de45fSGirish Mahadevan #define SPI_CS_ASSERT 8 60561de45fSGirish Mahadevan #define SPI_CS_DEASSERT 9 61561de45fSGirish Mahadevan #define SPI_SCK_ONLY 10 62561de45fSGirish Mahadevan /* M_CMD params for SPI */ 63561de45fSGirish Mahadevan #define SPI_PRE_CMD_DELAY BIT(0) 64561de45fSGirish Mahadevan #define TIMESTAMP_BEFORE BIT(1) 65561de45fSGirish Mahadevan #define FRAGMENTATION BIT(2) 66561de45fSGirish Mahadevan #define TIMESTAMP_AFTER BIT(3) 67561de45fSGirish Mahadevan #define POST_CMD_DELAY BIT(4) 68561de45fSGirish Mahadevan 69b59c1224SVinod Koul #define GSI_LOOPBACK_EN BIT(0) 70b59c1224SVinod Koul #define GSI_CS_TOGGLE BIT(3) 71b59c1224SVinod Koul #define GSI_CPHA BIT(4) 72b59c1224SVinod Koul #define GSI_CPOL BIT(5) 73b59c1224SVinod Koul 74561de45fSGirish Mahadevan struct spi_geni_master { 75561de45fSGirish Mahadevan struct geni_se se; 76561de45fSGirish Mahadevan struct device *dev; 77561de45fSGirish Mahadevan u32 tx_fifo_depth; 78561de45fSGirish Mahadevan u32 fifo_width_bits; 79561de45fSGirish Mahadevan u32 tx_wm; 80da48dc8cSDouglas Anderson u32 last_mode; 81561de45fSGirish Mahadevan unsigned long cur_speed_hz; 825f219524SDouglas Anderson unsigned long cur_sclk_hz; 83561de45fSGirish Mahadevan unsigned int cur_bits_per_word; 84561de45fSGirish Mahadevan unsigned int tx_rem_bytes; 85561de45fSGirish Mahadevan unsigned int rx_rem_bytes; 86561de45fSGirish Mahadevan const struct spi_transfer *cur_xfer; 877ba9bdcbSDouglas Anderson struct completion cs_done; 887ba9bdcbSDouglas Anderson struct completion cancel_done; 897ba9bdcbSDouglas Anderson struct completion abort_done; 90561de45fSGirish Mahadevan unsigned int oversampling; 91561de45fSGirish Mahadevan spinlock_t lock; 92561de45fSGirish Mahadevan int irq; 93638d8488SDouglas Anderson bool cs_flag; 94690d8b91SDouglas Anderson bool abort_failed; 95b59c1224SVinod Koul struct dma_chan *tx; 96b59c1224SVinod Koul struct dma_chan *rx; 97b59c1224SVinod Koul int cur_xfer_mode; 98561de45fSGirish Mahadevan }; 99561de45fSGirish Mahadevan 100561de45fSGirish Mahadevan static int get_spi_clk_cfg(unsigned int speed_hz, 101561de45fSGirish Mahadevan struct spi_geni_master *mas, 102561de45fSGirish Mahadevan unsigned int *clk_idx, 103561de45fSGirish Mahadevan unsigned int *clk_div) 104561de45fSGirish Mahadevan { 105561de45fSGirish Mahadevan unsigned long sclk_freq; 106561de45fSGirish Mahadevan unsigned int actual_hz; 107561de45fSGirish Mahadevan int ret; 108561de45fSGirish Mahadevan 109561de45fSGirish Mahadevan ret = geni_se_clk_freq_match(&mas->se, 110561de45fSGirish Mahadevan speed_hz * mas->oversampling, 111561de45fSGirish Mahadevan clk_idx, &sclk_freq, false); 112561de45fSGirish Mahadevan if (ret) { 113561de45fSGirish Mahadevan dev_err(mas->dev, "Failed(%d) to find src clk for %dHz\n", 114561de45fSGirish Mahadevan ret, speed_hz); 115561de45fSGirish Mahadevan return ret; 116561de45fSGirish Mahadevan } 117561de45fSGirish Mahadevan 118561de45fSGirish Mahadevan *clk_div = DIV_ROUND_UP(sclk_freq, mas->oversampling * speed_hz); 119561de45fSGirish Mahadevan actual_hz = sclk_freq / (mas->oversampling * *clk_div); 120561de45fSGirish Mahadevan 121561de45fSGirish Mahadevan dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz, 122561de45fSGirish Mahadevan actual_hz, sclk_freq, *clk_idx, *clk_div); 1231a9e489eSRajendra Nayak ret = dev_pm_opp_set_rate(mas->dev, sclk_freq); 124561de45fSGirish Mahadevan if (ret) 1251a9e489eSRajendra Nayak dev_err(mas->dev, "dev_pm_opp_set_rate failed %d\n", ret); 1265f219524SDouglas Anderson else 1275f219524SDouglas Anderson mas->cur_sclk_hz = sclk_freq; 1285f219524SDouglas Anderson 129561de45fSGirish Mahadevan return ret; 130561de45fSGirish Mahadevan } 131561de45fSGirish Mahadevan 132de43affeSStephen Boyd static void handle_fifo_timeout(struct spi_master *spi, 133de43affeSStephen Boyd struct spi_message *msg) 134de43affeSStephen Boyd { 135de43affeSStephen Boyd struct spi_geni_master *mas = spi_master_get_devdata(spi); 136539afdf9SDouglas Anderson unsigned long time_left; 137de43affeSStephen Boyd struct geni_se *se = &mas->se; 138de43affeSStephen Boyd 139539afdf9SDouglas Anderson spin_lock_irq(&mas->lock); 1407ba9bdcbSDouglas Anderson reinit_completion(&mas->cancel_done); 141de43affeSStephen Boyd writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 1427ba9bdcbSDouglas Anderson mas->cur_xfer = NULL; 1437ba9bdcbSDouglas Anderson geni_se_cancel_m_cmd(se); 144539afdf9SDouglas Anderson spin_unlock_irq(&mas->lock); 1457ba9bdcbSDouglas Anderson 1467ba9bdcbSDouglas Anderson time_left = wait_for_completion_timeout(&mas->cancel_done, HZ); 147de43affeSStephen Boyd if (time_left) 148de43affeSStephen Boyd return; 149de43affeSStephen Boyd 150539afdf9SDouglas Anderson spin_lock_irq(&mas->lock); 1517ba9bdcbSDouglas Anderson reinit_completion(&mas->abort_done); 152de43affeSStephen Boyd geni_se_abort_m_cmd(se); 153539afdf9SDouglas Anderson spin_unlock_irq(&mas->lock); 1547ba9bdcbSDouglas Anderson 1557ba9bdcbSDouglas Anderson time_left = wait_for_completion_timeout(&mas->abort_done, HZ); 156690d8b91SDouglas Anderson if (!time_left) { 157de43affeSStephen Boyd dev_err(mas->dev, "Failed to cancel/abort m_cmd\n"); 158690d8b91SDouglas Anderson 159690d8b91SDouglas Anderson /* 160690d8b91SDouglas Anderson * No need for a lock since SPI core has a lock and we never 161690d8b91SDouglas Anderson * access this from an interrupt. 162690d8b91SDouglas Anderson */ 163690d8b91SDouglas Anderson mas->abort_failed = true; 164690d8b91SDouglas Anderson } 165690d8b91SDouglas Anderson } 166690d8b91SDouglas Anderson 167f8039ea5SVinod Koul static void handle_gpi_timeout(struct spi_master *spi, struct spi_message *msg) 168f8039ea5SVinod Koul { 169f8039ea5SVinod Koul struct spi_geni_master *mas = spi_master_get_devdata(spi); 170f8039ea5SVinod Koul 171f8039ea5SVinod Koul dmaengine_terminate_sync(mas->tx); 172f8039ea5SVinod Koul dmaengine_terminate_sync(mas->rx); 173f8039ea5SVinod Koul } 174f8039ea5SVinod Koul 175f8039ea5SVinod Koul static void spi_geni_handle_err(struct spi_master *spi, struct spi_message *msg) 176f8039ea5SVinod Koul { 177f8039ea5SVinod Koul struct spi_geni_master *mas = spi_master_get_devdata(spi); 178f8039ea5SVinod Koul 179f8039ea5SVinod Koul switch (mas->cur_xfer_mode) { 180f8039ea5SVinod Koul case GENI_SE_FIFO: 181f8039ea5SVinod Koul handle_fifo_timeout(spi, msg); 182f8039ea5SVinod Koul break; 183f8039ea5SVinod Koul case GENI_GPI_DMA: 184f8039ea5SVinod Koul handle_gpi_timeout(spi, msg); 185f8039ea5SVinod Koul break; 186f8039ea5SVinod Koul default: 187f8039ea5SVinod Koul dev_err(mas->dev, "Abort on Mode:%d not supported", mas->cur_xfer_mode); 188f8039ea5SVinod Koul } 189f8039ea5SVinod Koul } 190f8039ea5SVinod Koul 191690d8b91SDouglas Anderson static bool spi_geni_is_abort_still_pending(struct spi_geni_master *mas) 192690d8b91SDouglas Anderson { 193690d8b91SDouglas Anderson struct geni_se *se = &mas->se; 194690d8b91SDouglas Anderson u32 m_irq, m_irq_en; 195690d8b91SDouglas Anderson 196690d8b91SDouglas Anderson if (!mas->abort_failed) 197690d8b91SDouglas Anderson return false; 198690d8b91SDouglas Anderson 199690d8b91SDouglas Anderson /* 200690d8b91SDouglas Anderson * The only known case where a transfer times out and then a cancel 201690d8b91SDouglas Anderson * times out then an abort times out is if something is blocking our 202690d8b91SDouglas Anderson * interrupt handler from running. Avoid starting any new transfers 203690d8b91SDouglas Anderson * until that sorts itself out. 204690d8b91SDouglas Anderson */ 205690d8b91SDouglas Anderson spin_lock_irq(&mas->lock); 206690d8b91SDouglas Anderson m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); 207690d8b91SDouglas Anderson m_irq_en = readl(se->base + SE_GENI_M_IRQ_EN); 208690d8b91SDouglas Anderson spin_unlock_irq(&mas->lock); 209690d8b91SDouglas Anderson 210690d8b91SDouglas Anderson if (m_irq & m_irq_en) { 211690d8b91SDouglas Anderson dev_err(mas->dev, "Interrupts pending after abort: %#010x\n", 212690d8b91SDouglas Anderson m_irq & m_irq_en); 213690d8b91SDouglas Anderson return true; 214690d8b91SDouglas Anderson } 215690d8b91SDouglas Anderson 216690d8b91SDouglas Anderson /* 217690d8b91SDouglas Anderson * If we're here the problem resolved itself so no need to check more 218690d8b91SDouglas Anderson * on future transfers. 219690d8b91SDouglas Anderson */ 220690d8b91SDouglas Anderson mas->abort_failed = false; 221690d8b91SDouglas Anderson 222690d8b91SDouglas Anderson return false; 223de43affeSStephen Boyd } 224de43affeSStephen Boyd 225561de45fSGirish Mahadevan static void spi_geni_set_cs(struct spi_device *slv, bool set_flag) 226561de45fSGirish Mahadevan { 227561de45fSGirish Mahadevan struct spi_geni_master *mas = spi_master_get_devdata(slv->master); 228561de45fSGirish Mahadevan struct spi_master *spi = dev_get_drvdata(mas->dev); 229561de45fSGirish Mahadevan struct geni_se *se = &mas->se; 2300dccff3cSAlok Chauhan unsigned long time_left; 231561de45fSGirish Mahadevan 232561de45fSGirish Mahadevan if (!(slv->mode & SPI_CS_HIGH)) 233561de45fSGirish Mahadevan set_flag = !set_flag; 234561de45fSGirish Mahadevan 235638d8488SDouglas Anderson if (set_flag == mas->cs_flag) 236638d8488SDouglas Anderson return; 237638d8488SDouglas Anderson 238690d8b91SDouglas Anderson pm_runtime_get_sync(mas->dev); 239690d8b91SDouglas Anderson 240690d8b91SDouglas Anderson if (spi_geni_is_abort_still_pending(mas)) { 241690d8b91SDouglas Anderson dev_err(mas->dev, "Can't set chip select\n"); 242690d8b91SDouglas Anderson goto exit; 243690d8b91SDouglas Anderson } 244690d8b91SDouglas Anderson 2452ee471a1SDouglas Anderson spin_lock_irq(&mas->lock); 2463d7d916fSDouglas Anderson if (mas->cur_xfer) { 2473d7d916fSDouglas Anderson dev_err(mas->dev, "Can't set CS when prev xfer running\n"); 2483d7d916fSDouglas Anderson spin_unlock_irq(&mas->lock); 2493d7d916fSDouglas Anderson goto exit; 2503d7d916fSDouglas Anderson } 2513d7d916fSDouglas Anderson 2523d7d916fSDouglas Anderson mas->cs_flag = set_flag; 2537ba9bdcbSDouglas Anderson reinit_completion(&mas->cs_done); 254561de45fSGirish Mahadevan if (set_flag) 255561de45fSGirish Mahadevan geni_se_setup_m_cmd(se, SPI_CS_ASSERT, 0); 256561de45fSGirish Mahadevan else 257561de45fSGirish Mahadevan geni_se_setup_m_cmd(se, SPI_CS_DEASSERT, 0); 2582ee471a1SDouglas Anderson spin_unlock_irq(&mas->lock); 259561de45fSGirish Mahadevan 2607ba9bdcbSDouglas Anderson time_left = wait_for_completion_timeout(&mas->cs_done, HZ); 26117fa81aaSDouglas Anderson if (!time_left) { 26217fa81aaSDouglas Anderson dev_warn(mas->dev, "Timeout setting chip select\n"); 263561de45fSGirish Mahadevan handle_fifo_timeout(spi, NULL); 26417fa81aaSDouglas Anderson } 265561de45fSGirish Mahadevan 266690d8b91SDouglas Anderson exit: 267561de45fSGirish Mahadevan pm_runtime_put(mas->dev); 268561de45fSGirish Mahadevan } 269561de45fSGirish Mahadevan 270561de45fSGirish Mahadevan static void spi_setup_word_len(struct spi_geni_master *mas, u16 mode, 271561de45fSGirish Mahadevan unsigned int bits_per_word) 272561de45fSGirish Mahadevan { 273561de45fSGirish Mahadevan unsigned int pack_words; 274561de45fSGirish Mahadevan bool msb_first = (mode & SPI_LSB_FIRST) ? false : true; 275561de45fSGirish Mahadevan struct geni_se *se = &mas->se; 276561de45fSGirish Mahadevan u32 word_len; 277561de45fSGirish Mahadevan 278561de45fSGirish Mahadevan /* 279561de45fSGirish Mahadevan * If bits_per_word isn't a byte aligned value, set the packing to be 280561de45fSGirish Mahadevan * 1 SPI word per FIFO word. 281561de45fSGirish Mahadevan */ 282561de45fSGirish Mahadevan if (!(mas->fifo_width_bits % bits_per_word)) 283561de45fSGirish Mahadevan pack_words = mas->fifo_width_bits / bits_per_word; 284561de45fSGirish Mahadevan else 285561de45fSGirish Mahadevan pack_words = 1; 286561de45fSGirish Mahadevan geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first, 287561de45fSGirish Mahadevan true, true); 288da48dc8cSDouglas Anderson word_len = (bits_per_word - MIN_WORD_LEN) & WORD_LEN_MSK; 289561de45fSGirish Mahadevan writel(word_len, se->base + SE_SPI_WORD_LEN); 290561de45fSGirish Mahadevan } 291561de45fSGirish Mahadevan 2920e3b8a81SAkash Asthana static int geni_spi_set_clock_and_bw(struct spi_geni_master *mas, 2930e3b8a81SAkash Asthana unsigned long clk_hz) 294e68b6624SDouglas Anderson { 295e68b6624SDouglas Anderson u32 clk_sel, m_clk_cfg, idx, div; 296e68b6624SDouglas Anderson struct geni_se *se = &mas->se; 297e68b6624SDouglas Anderson int ret; 298e68b6624SDouglas Anderson 29968890e20SDouglas Anderson if (clk_hz == mas->cur_speed_hz) 30068890e20SDouglas Anderson return 0; 30168890e20SDouglas Anderson 302e68b6624SDouglas Anderson ret = get_spi_clk_cfg(clk_hz, mas, &idx, &div); 303e68b6624SDouglas Anderson if (ret) { 304e68b6624SDouglas Anderson dev_err(mas->dev, "Err setting clk to %lu: %d\n", clk_hz, ret); 305e68b6624SDouglas Anderson return ret; 306e68b6624SDouglas Anderson } 307e68b6624SDouglas Anderson 308e68b6624SDouglas Anderson /* 309e68b6624SDouglas Anderson * SPI core clock gets configured with the requested frequency 310e68b6624SDouglas Anderson * or the frequency closer to the requested frequency. 311e68b6624SDouglas Anderson * For that reason requested frequency is stored in the 312e68b6624SDouglas Anderson * cur_speed_hz and referred in the consecutive transfer instead 313e68b6624SDouglas Anderson * of calling clk_get_rate() API. 314e68b6624SDouglas Anderson */ 315e68b6624SDouglas Anderson mas->cur_speed_hz = clk_hz; 316e68b6624SDouglas Anderson 317e68b6624SDouglas Anderson clk_sel = idx & CLK_SEL_MSK; 318e68b6624SDouglas Anderson m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN; 319e68b6624SDouglas Anderson writel(clk_sel, se->base + SE_GENI_CLK_SEL); 320e68b6624SDouglas Anderson writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG); 321e68b6624SDouglas Anderson 3220e3b8a81SAkash Asthana /* Set BW quota for CPU as driver supports FIFO mode only. */ 3230e3b8a81SAkash Asthana se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz); 3240e3b8a81SAkash Asthana ret = geni_icc_set_bw(se); 3250e3b8a81SAkash Asthana if (ret) 3260e3b8a81SAkash Asthana return ret; 3270e3b8a81SAkash Asthana 328e68b6624SDouglas Anderson return 0; 329e68b6624SDouglas Anderson } 330e68b6624SDouglas Anderson 331561de45fSGirish Mahadevan static int setup_fifo_params(struct spi_device *spi_slv, 332561de45fSGirish Mahadevan struct spi_master *spi) 333561de45fSGirish Mahadevan { 334561de45fSGirish Mahadevan struct spi_geni_master *mas = spi_master_get_devdata(spi); 335561de45fSGirish Mahadevan struct geni_se *se = &mas->se; 336da48dc8cSDouglas Anderson u32 loopback_cfg = 0, cpol = 0, cpha = 0, demux_output_inv = 0; 337e68b6624SDouglas Anderson u32 demux_sel; 338561de45fSGirish Mahadevan 339da48dc8cSDouglas Anderson if (mas->last_mode != spi_slv->mode) { 340561de45fSGirish Mahadevan if (spi_slv->mode & SPI_LOOP) 341da48dc8cSDouglas Anderson loopback_cfg = LOOPBACK_ENABLE; 342561de45fSGirish Mahadevan 343561de45fSGirish Mahadevan if (spi_slv->mode & SPI_CPOL) 344da48dc8cSDouglas Anderson cpol = CPOL; 345561de45fSGirish Mahadevan 346561de45fSGirish Mahadevan if (spi_slv->mode & SPI_CPHA) 347da48dc8cSDouglas Anderson cpha = CPHA; 348561de45fSGirish Mahadevan 349561de45fSGirish Mahadevan if (spi_slv->mode & SPI_CS_HIGH) 350561de45fSGirish Mahadevan demux_output_inv = BIT(spi_slv->chip_select); 351561de45fSGirish Mahadevan 352561de45fSGirish Mahadevan demux_sel = spi_slv->chip_select; 353561de45fSGirish Mahadevan mas->cur_bits_per_word = spi_slv->bits_per_word; 354561de45fSGirish Mahadevan 355561de45fSGirish Mahadevan spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word); 356561de45fSGirish Mahadevan writel(loopback_cfg, se->base + SE_SPI_LOOPBACK); 357561de45fSGirish Mahadevan writel(demux_sel, se->base + SE_SPI_DEMUX_SEL); 358561de45fSGirish Mahadevan writel(cpha, se->base + SE_SPI_CPHA); 359561de45fSGirish Mahadevan writel(cpol, se->base + SE_SPI_CPOL); 360561de45fSGirish Mahadevan writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV); 361e68b6624SDouglas Anderson 362da48dc8cSDouglas Anderson mas->last_mode = spi_slv->mode; 363da48dc8cSDouglas Anderson } 364da48dc8cSDouglas Anderson 3650e3b8a81SAkash Asthana return geni_spi_set_clock_and_bw(mas, spi_slv->max_speed_hz); 366561de45fSGirish Mahadevan } 367561de45fSGirish Mahadevan 368b59c1224SVinod Koul static void 369b59c1224SVinod Koul spi_gsi_callback_result(void *cb, const struct dmaengine_result *result) 370b59c1224SVinod Koul { 371b59c1224SVinod Koul struct spi_master *spi = cb; 372b59c1224SVinod Koul 37374b86d6aSVinod Koul spi->cur_msg->status = -EIO; 374b59c1224SVinod Koul if (result->result != DMA_TRANS_NOERROR) { 375b59c1224SVinod Koul dev_err(&spi->dev, "DMA txn failed: %d\n", result->result); 37674b86d6aSVinod Koul spi_finalize_current_transfer(spi); 377b59c1224SVinod Koul return; 378b59c1224SVinod Koul } 379b59c1224SVinod Koul 380b59c1224SVinod Koul if (!result->residue) { 38174b86d6aSVinod Koul spi->cur_msg->status = 0; 382b59c1224SVinod Koul dev_dbg(&spi->dev, "DMA txn completed\n"); 383b59c1224SVinod Koul } else { 384b59c1224SVinod Koul dev_err(&spi->dev, "DMA xfer has pending: %d\n", result->residue); 385b59c1224SVinod Koul } 38674b86d6aSVinod Koul 38774b86d6aSVinod Koul spi_finalize_current_transfer(spi); 388b59c1224SVinod Koul } 389b59c1224SVinod Koul 390b59c1224SVinod Koul static int setup_gsi_xfer(struct spi_transfer *xfer, struct spi_geni_master *mas, 391b59c1224SVinod Koul struct spi_device *spi_slv, struct spi_master *spi) 392b59c1224SVinod Koul { 393b59c1224SVinod Koul unsigned long flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK; 394b59c1224SVinod Koul struct dma_slave_config config = {}; 395b59c1224SVinod Koul struct gpi_spi_config peripheral = {}; 396b59c1224SVinod Koul struct dma_async_tx_descriptor *tx_desc, *rx_desc; 397b59c1224SVinod Koul int ret; 398b59c1224SVinod Koul 399b59c1224SVinod Koul config.peripheral_config = &peripheral; 400b59c1224SVinod Koul config.peripheral_size = sizeof(peripheral); 401b59c1224SVinod Koul peripheral.set_config = true; 402b59c1224SVinod Koul 403b59c1224SVinod Koul if (xfer->bits_per_word != mas->cur_bits_per_word || 404b59c1224SVinod Koul xfer->speed_hz != mas->cur_speed_hz) { 405b59c1224SVinod Koul mas->cur_bits_per_word = xfer->bits_per_word; 406b59c1224SVinod Koul mas->cur_speed_hz = xfer->speed_hz; 407b59c1224SVinod Koul } 408b59c1224SVinod Koul 409b59c1224SVinod Koul if (xfer->tx_buf && xfer->rx_buf) { 410b59c1224SVinod Koul peripheral.cmd = SPI_DUPLEX; 411b59c1224SVinod Koul } else if (xfer->tx_buf) { 412b59c1224SVinod Koul peripheral.cmd = SPI_TX; 413b59c1224SVinod Koul peripheral.rx_len = 0; 414b59c1224SVinod Koul } else if (xfer->rx_buf) { 415b59c1224SVinod Koul peripheral.cmd = SPI_RX; 416b59c1224SVinod Koul if (!(mas->cur_bits_per_word % MIN_WORD_LEN)) { 417b59c1224SVinod Koul peripheral.rx_len = ((xfer->len << 3) / mas->cur_bits_per_word); 418b59c1224SVinod Koul } else { 419b59c1224SVinod Koul int bytes_per_word = (mas->cur_bits_per_word / BITS_PER_BYTE) + 1; 420b59c1224SVinod Koul 421b59c1224SVinod Koul peripheral.rx_len = (xfer->len / bytes_per_word); 422b59c1224SVinod Koul } 423b59c1224SVinod Koul } 424b59c1224SVinod Koul 425b59c1224SVinod Koul peripheral.loopback_en = !!(spi_slv->mode & SPI_LOOP); 426b59c1224SVinod Koul peripheral.clock_pol_high = !!(spi_slv->mode & SPI_CPOL); 427b59c1224SVinod Koul peripheral.data_pol_high = !!(spi_slv->mode & SPI_CPHA); 428b59c1224SVinod Koul peripheral.cs = spi_slv->chip_select; 429b59c1224SVinod Koul peripheral.pack_en = true; 430b59c1224SVinod Koul peripheral.word_len = xfer->bits_per_word - MIN_WORD_LEN; 431b59c1224SVinod Koul 432b59c1224SVinod Koul ret = get_spi_clk_cfg(mas->cur_speed_hz, mas, 433b59c1224SVinod Koul &peripheral.clk_src, &peripheral.clk_div); 434b59c1224SVinod Koul if (ret) { 435b59c1224SVinod Koul dev_err(mas->dev, "Err in get_spi_clk_cfg() :%d\n", ret); 436b59c1224SVinod Koul return ret; 437b59c1224SVinod Koul } 438b59c1224SVinod Koul 439b59c1224SVinod Koul if (!xfer->cs_change) { 440b59c1224SVinod Koul if (!list_is_last(&xfer->transfer_list, &spi->cur_msg->transfers)) 441b59c1224SVinod Koul peripheral.fragmentation = FRAGMENTATION; 442b59c1224SVinod Koul } 443b59c1224SVinod Koul 444b59c1224SVinod Koul if (peripheral.cmd & SPI_RX) { 445b59c1224SVinod Koul dmaengine_slave_config(mas->rx, &config); 446b59c1224SVinod Koul rx_desc = dmaengine_prep_slave_sg(mas->rx, xfer->rx_sg.sgl, xfer->rx_sg.nents, 447b59c1224SVinod Koul DMA_DEV_TO_MEM, flags); 448b59c1224SVinod Koul if (!rx_desc) { 449b59c1224SVinod Koul dev_err(mas->dev, "Err setting up rx desc\n"); 450b59c1224SVinod Koul return -EIO; 451b59c1224SVinod Koul } 452b59c1224SVinod Koul } 453b59c1224SVinod Koul 454b59c1224SVinod Koul /* 455b59c1224SVinod Koul * Prepare the TX always, even for RX or tx_buf being null, we would 456b59c1224SVinod Koul * need TX to be prepared per GSI spec 457b59c1224SVinod Koul */ 458b59c1224SVinod Koul dmaengine_slave_config(mas->tx, &config); 459b59c1224SVinod Koul tx_desc = dmaengine_prep_slave_sg(mas->tx, xfer->tx_sg.sgl, xfer->tx_sg.nents, 460b59c1224SVinod Koul DMA_MEM_TO_DEV, flags); 461b59c1224SVinod Koul if (!tx_desc) { 462b59c1224SVinod Koul dev_err(mas->dev, "Err setting up tx desc\n"); 463b59c1224SVinod Koul return -EIO; 464b59c1224SVinod Koul } 465b59c1224SVinod Koul 466b59c1224SVinod Koul tx_desc->callback_result = spi_gsi_callback_result; 467b59c1224SVinod Koul tx_desc->callback_param = spi; 468b59c1224SVinod Koul 469b59c1224SVinod Koul if (peripheral.cmd & SPI_RX) 470b59c1224SVinod Koul dmaengine_submit(rx_desc); 471b59c1224SVinod Koul dmaengine_submit(tx_desc); 472b59c1224SVinod Koul 473b59c1224SVinod Koul if (peripheral.cmd & SPI_RX) 474b59c1224SVinod Koul dma_async_issue_pending(mas->rx); 475b59c1224SVinod Koul 476b59c1224SVinod Koul dma_async_issue_pending(mas->tx); 477b59c1224SVinod Koul return 1; 478b59c1224SVinod Koul } 479b59c1224SVinod Koul 480b59c1224SVinod Koul static bool geni_can_dma(struct spi_controller *ctlr, 481b59c1224SVinod Koul struct spi_device *slv, struct spi_transfer *xfer) 482b59c1224SVinod Koul { 483b59c1224SVinod Koul struct spi_geni_master *mas = spi_master_get_devdata(slv->master); 484b59c1224SVinod Koul 485b59c1224SVinod Koul /* check if dma is supported */ 486b59c1224SVinod Koul return mas->cur_xfer_mode != GENI_SE_FIFO; 487b59c1224SVinod Koul } 488b59c1224SVinod Koul 489561de45fSGirish Mahadevan static int spi_geni_prepare_message(struct spi_master *spi, 490561de45fSGirish Mahadevan struct spi_message *spi_msg) 491561de45fSGirish Mahadevan { 492561de45fSGirish Mahadevan struct spi_geni_master *mas = spi_master_get_devdata(spi); 493b59c1224SVinod Koul int ret; 494561de45fSGirish Mahadevan 495b59c1224SVinod Koul switch (mas->cur_xfer_mode) { 496b59c1224SVinod Koul case GENI_SE_FIFO: 497690d8b91SDouglas Anderson if (spi_geni_is_abort_still_pending(mas)) 498690d8b91SDouglas Anderson return -EBUSY; 499561de45fSGirish Mahadevan ret = setup_fifo_params(spi_msg->spi, spi); 500561de45fSGirish Mahadevan if (ret) 501561de45fSGirish Mahadevan dev_err(mas->dev, "Couldn't select mode %d\n", ret); 502561de45fSGirish Mahadevan return ret; 503b59c1224SVinod Koul 504b59c1224SVinod Koul case GENI_GPI_DMA: 505b59c1224SVinod Koul /* nothing to do for GPI DMA */ 506b59c1224SVinod Koul return 0; 507b59c1224SVinod Koul } 508b59c1224SVinod Koul 509b59c1224SVinod Koul dev_err(mas->dev, "Mode not supported %d", mas->cur_xfer_mode); 510b59c1224SVinod Koul return -EINVAL; 511b59c1224SVinod Koul } 512b59c1224SVinod Koul 513b59c1224SVinod Koul static int spi_geni_grab_gpi_chan(struct spi_geni_master *mas) 514b59c1224SVinod Koul { 515b59c1224SVinod Koul int ret; 516b59c1224SVinod Koul 517b59c1224SVinod Koul mas->tx = dma_request_chan(mas->dev, "tx"); 5186532582cSDan Carpenter if (IS_ERR(mas->tx)) { 5196532582cSDan Carpenter ret = dev_err_probe(mas->dev, PTR_ERR(mas->tx), 5206532582cSDan Carpenter "Failed to get tx DMA ch\n"); 521b59c1224SVinod Koul goto err_tx; 5226532582cSDan Carpenter } 523b59c1224SVinod Koul 524b59c1224SVinod Koul mas->rx = dma_request_chan(mas->dev, "rx"); 5256532582cSDan Carpenter if (IS_ERR(mas->rx)) { 5266532582cSDan Carpenter ret = dev_err_probe(mas->dev, PTR_ERR(mas->rx), 5276532582cSDan Carpenter "Failed to get rx DMA ch\n"); 528b59c1224SVinod Koul goto err_rx; 5296532582cSDan Carpenter } 530b59c1224SVinod Koul 531b59c1224SVinod Koul return 0; 532b59c1224SVinod Koul 533b59c1224SVinod Koul err_rx: 534b59c1224SVinod Koul mas->rx = NULL; 5356532582cSDan Carpenter dma_release_channel(mas->tx); 5366532582cSDan Carpenter err_tx: 5376532582cSDan Carpenter mas->tx = NULL; 538b59c1224SVinod Koul return ret; 539b59c1224SVinod Koul } 540b59c1224SVinod Koul 541b59c1224SVinod Koul static void spi_geni_release_dma_chan(struct spi_geni_master *mas) 542b59c1224SVinod Koul { 543b59c1224SVinod Koul if (mas->rx) { 544b59c1224SVinod Koul dma_release_channel(mas->rx); 545b59c1224SVinod Koul mas->rx = NULL; 546b59c1224SVinod Koul } 547b59c1224SVinod Koul 548b59c1224SVinod Koul if (mas->tx) { 549b59c1224SVinod Koul dma_release_channel(mas->tx); 550b59c1224SVinod Koul mas->tx = NULL; 551b59c1224SVinod Koul } 552561de45fSGirish Mahadevan } 553561de45fSGirish Mahadevan 554561de45fSGirish Mahadevan static int spi_geni_init(struct spi_geni_master *mas) 555561de45fSGirish Mahadevan { 556561de45fSGirish Mahadevan struct geni_se *se = &mas->se; 557561de45fSGirish Mahadevan unsigned int proto, major, minor, ver; 558b59c1224SVinod Koul u32 spi_tx_cfg, fifo_disable; 559b59c1224SVinod Koul int ret = -ENXIO; 560561de45fSGirish Mahadevan 561561de45fSGirish Mahadevan pm_runtime_get_sync(mas->dev); 562561de45fSGirish Mahadevan 563561de45fSGirish Mahadevan proto = geni_se_read_proto(se); 564561de45fSGirish Mahadevan if (proto != GENI_SE_SPI) { 565561de45fSGirish Mahadevan dev_err(mas->dev, "Invalid proto %d\n", proto); 566b59c1224SVinod Koul goto out_pm; 567561de45fSGirish Mahadevan } 568561de45fSGirish Mahadevan mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se); 569561de45fSGirish Mahadevan 570561de45fSGirish Mahadevan /* Width of Tx and Rx FIFO is same */ 571561de45fSGirish Mahadevan mas->fifo_width_bits = geni_se_get_tx_fifo_width(se); 572561de45fSGirish Mahadevan 573561de45fSGirish Mahadevan /* 574561de45fSGirish Mahadevan * Hardware programming guide suggests to configure 575561de45fSGirish Mahadevan * RX FIFO RFR level to fifo_depth-2. 576561de45fSGirish Mahadevan */ 577fc129a43SDouglas Anderson geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2); 578561de45fSGirish Mahadevan /* Transmit an entire FIFO worth of data per IRQ */ 579561de45fSGirish Mahadevan mas->tx_wm = 1; 580561de45fSGirish Mahadevan ver = geni_se_get_qup_hw_version(se); 581561de45fSGirish Mahadevan major = GENI_SE_VERSION_MAJOR(ver); 582561de45fSGirish Mahadevan minor = GENI_SE_VERSION_MINOR(ver); 583561de45fSGirish Mahadevan 584561de45fSGirish Mahadevan if (major == 1 && minor == 0) 585561de45fSGirish Mahadevan mas->oversampling = 2; 586561de45fSGirish Mahadevan else 587561de45fSGirish Mahadevan mas->oversampling = 1; 588561de45fSGirish Mahadevan 589b59c1224SVinod Koul fifo_disable = readl(se->base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE; 590b59c1224SVinod Koul switch (fifo_disable) { 591b59c1224SVinod Koul case 1: 592b59c1224SVinod Koul ret = spi_geni_grab_gpi_chan(mas); 593b59c1224SVinod Koul if (!ret) { /* success case */ 594b59c1224SVinod Koul mas->cur_xfer_mode = GENI_GPI_DMA; 595b59c1224SVinod Koul geni_se_select_mode(se, GENI_GPI_DMA); 596b59c1224SVinod Koul dev_dbg(mas->dev, "Using GPI DMA mode for SPI\n"); 597b59c1224SVinod Koul break; 598b59c1224SVinod Koul } 599b59c1224SVinod Koul /* 600b59c1224SVinod Koul * in case of failure to get dma channel, we can still do the 601b59c1224SVinod Koul * FIFO mode, so fallthrough 602b59c1224SVinod Koul */ 603b59c1224SVinod Koul dev_warn(mas->dev, "FIFO mode disabled, but couldn't get DMA, fall back to FIFO mode\n"); 604b59c1224SVinod Koul fallthrough; 605b59c1224SVinod Koul 606b59c1224SVinod Koul case 0: 607b59c1224SVinod Koul mas->cur_xfer_mode = GENI_SE_FIFO; 608da48dc8cSDouglas Anderson geni_se_select_mode(se, GENI_SE_FIFO); 609b59c1224SVinod Koul ret = 0; 610b59c1224SVinod Koul break; 611b59c1224SVinod Koul } 612da48dc8cSDouglas Anderson 61314ac4e04SDouglas Anderson /* We always control CS manually */ 61414ac4e04SDouglas Anderson spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG); 61514ac4e04SDouglas Anderson spi_tx_cfg &= ~CS_TOGGLE; 61614ac4e04SDouglas Anderson writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG); 61714ac4e04SDouglas Anderson 618b59c1224SVinod Koul out_pm: 619561de45fSGirish Mahadevan pm_runtime_put(mas->dev); 620b59c1224SVinod Koul return ret; 621561de45fSGirish Mahadevan } 622561de45fSGirish Mahadevan 6236d66507dSDouglas Anderson static unsigned int geni_byte_per_fifo_word(struct spi_geni_master *mas) 6246d66507dSDouglas Anderson { 6256d66507dSDouglas Anderson /* 6266d66507dSDouglas Anderson * Calculate how many bytes we'll put in each FIFO word. If the 6276d66507dSDouglas Anderson * transfer words don't pack cleanly into a FIFO word we'll just put 6286d66507dSDouglas Anderson * one transfer word in each FIFO word. If they do pack we'll pack 'em. 6296d66507dSDouglas Anderson */ 6306d66507dSDouglas Anderson if (mas->fifo_width_bits % mas->cur_bits_per_word) 6316d66507dSDouglas Anderson return roundup_pow_of_two(DIV_ROUND_UP(mas->cur_bits_per_word, 6326d66507dSDouglas Anderson BITS_PER_BYTE)); 6336d66507dSDouglas Anderson 6346d66507dSDouglas Anderson return mas->fifo_width_bits / BITS_PER_BYTE; 6356d66507dSDouglas Anderson } 6366d66507dSDouglas Anderson 6376d66507dSDouglas Anderson static bool geni_spi_handle_tx(struct spi_geni_master *mas) 6386d66507dSDouglas Anderson { 6396d66507dSDouglas Anderson struct geni_se *se = &mas->se; 6406d66507dSDouglas Anderson unsigned int max_bytes; 6416d66507dSDouglas Anderson const u8 *tx_buf; 6426d66507dSDouglas Anderson unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas); 6436d66507dSDouglas Anderson unsigned int i = 0; 6446d66507dSDouglas Anderson 6454aa1464aSDouglas Anderson /* Stop the watermark IRQ if nothing to send */ 6464aa1464aSDouglas Anderson if (!mas->cur_xfer) { 6474aa1464aSDouglas Anderson writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 6484aa1464aSDouglas Anderson return false; 6494aa1464aSDouglas Anderson } 6504aa1464aSDouglas Anderson 6516d66507dSDouglas Anderson max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * bytes_per_fifo_word; 6526d66507dSDouglas Anderson if (mas->tx_rem_bytes < max_bytes) 6536d66507dSDouglas Anderson max_bytes = mas->tx_rem_bytes; 6546d66507dSDouglas Anderson 6556d66507dSDouglas Anderson tx_buf = mas->cur_xfer->tx_buf + mas->cur_xfer->len - mas->tx_rem_bytes; 6566d66507dSDouglas Anderson while (i < max_bytes) { 6576d66507dSDouglas Anderson unsigned int j; 6586d66507dSDouglas Anderson unsigned int bytes_to_write; 6596d66507dSDouglas Anderson u32 fifo_word = 0; 6606d66507dSDouglas Anderson u8 *fifo_byte = (u8 *)&fifo_word; 6616d66507dSDouglas Anderson 6626d66507dSDouglas Anderson bytes_to_write = min(bytes_per_fifo_word, max_bytes - i); 6636d66507dSDouglas Anderson for (j = 0; j < bytes_to_write; j++) 6646d66507dSDouglas Anderson fifo_byte[j] = tx_buf[i++]; 6656d66507dSDouglas Anderson iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1); 6666d66507dSDouglas Anderson } 6676d66507dSDouglas Anderson mas->tx_rem_bytes -= max_bytes; 6686d66507dSDouglas Anderson if (!mas->tx_rem_bytes) { 6696d66507dSDouglas Anderson writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 6706d66507dSDouglas Anderson return false; 6716d66507dSDouglas Anderson } 6726d66507dSDouglas Anderson return true; 6736d66507dSDouglas Anderson } 6746d66507dSDouglas Anderson 6756d66507dSDouglas Anderson static void geni_spi_handle_rx(struct spi_geni_master *mas) 6766d66507dSDouglas Anderson { 6776d66507dSDouglas Anderson struct geni_se *se = &mas->se; 6786d66507dSDouglas Anderson u32 rx_fifo_status; 6796d66507dSDouglas Anderson unsigned int rx_bytes; 6806d66507dSDouglas Anderson unsigned int rx_last_byte_valid; 6816d66507dSDouglas Anderson u8 *rx_buf; 6826d66507dSDouglas Anderson unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas); 6836d66507dSDouglas Anderson unsigned int i = 0; 6846d66507dSDouglas Anderson 6856d66507dSDouglas Anderson rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS); 6866d66507dSDouglas Anderson rx_bytes = (rx_fifo_status & RX_FIFO_WC_MSK) * bytes_per_fifo_word; 6876d66507dSDouglas Anderson if (rx_fifo_status & RX_LAST) { 6886d66507dSDouglas Anderson rx_last_byte_valid = rx_fifo_status & RX_LAST_BYTE_VALID_MSK; 6896d66507dSDouglas Anderson rx_last_byte_valid >>= RX_LAST_BYTE_VALID_SHFT; 6906d66507dSDouglas Anderson if (rx_last_byte_valid && rx_last_byte_valid < 4) 6916d66507dSDouglas Anderson rx_bytes -= bytes_per_fifo_word - rx_last_byte_valid; 6926d66507dSDouglas Anderson } 6934aa1464aSDouglas Anderson 6944aa1464aSDouglas Anderson /* Clear out the FIFO and bail if nowhere to put it */ 6954aa1464aSDouglas Anderson if (!mas->cur_xfer) { 6964aa1464aSDouglas Anderson for (i = 0; i < DIV_ROUND_UP(rx_bytes, bytes_per_fifo_word); i++) 6974aa1464aSDouglas Anderson readl(se->base + SE_GENI_RX_FIFOn); 6984aa1464aSDouglas Anderson return; 6994aa1464aSDouglas Anderson } 7004aa1464aSDouglas Anderson 7016d66507dSDouglas Anderson if (mas->rx_rem_bytes < rx_bytes) 7026d66507dSDouglas Anderson rx_bytes = mas->rx_rem_bytes; 7036d66507dSDouglas Anderson 7046d66507dSDouglas Anderson rx_buf = mas->cur_xfer->rx_buf + mas->cur_xfer->len - mas->rx_rem_bytes; 7056d66507dSDouglas Anderson while (i < rx_bytes) { 7066d66507dSDouglas Anderson u32 fifo_word = 0; 7076d66507dSDouglas Anderson u8 *fifo_byte = (u8 *)&fifo_word; 7086d66507dSDouglas Anderson unsigned int bytes_to_read; 7096d66507dSDouglas Anderson unsigned int j; 7106d66507dSDouglas Anderson 7116d66507dSDouglas Anderson bytes_to_read = min(bytes_per_fifo_word, rx_bytes - i); 7126d66507dSDouglas Anderson ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1); 7136d66507dSDouglas Anderson for (j = 0; j < bytes_to_read; j++) 7146d66507dSDouglas Anderson rx_buf[i++] = fifo_byte[j]; 7156d66507dSDouglas Anderson } 7166d66507dSDouglas Anderson mas->rx_rem_bytes -= rx_bytes; 7176d66507dSDouglas Anderson } 7186d66507dSDouglas Anderson 719561de45fSGirish Mahadevan static void setup_fifo_xfer(struct spi_transfer *xfer, 720561de45fSGirish Mahadevan struct spi_geni_master *mas, 721561de45fSGirish Mahadevan u16 mode, struct spi_master *spi) 722561de45fSGirish Mahadevan { 723561de45fSGirish Mahadevan u32 m_cmd = 0; 72414ac4e04SDouglas Anderson u32 len; 725561de45fSGirish Mahadevan struct geni_se *se = &mas->se; 726e68b6624SDouglas Anderson int ret; 727561de45fSGirish Mahadevan 7282ee471a1SDouglas Anderson /* 7292ee471a1SDouglas Anderson * Ensure that our interrupt handler isn't still running from some 7302ee471a1SDouglas Anderson * prior command before we start messing with the hardware behind 7312ee471a1SDouglas Anderson * its back. We don't need to _keep_ the lock here since we're only 7322ee471a1SDouglas Anderson * worried about racing with out interrupt handler. The SPI core 7332ee471a1SDouglas Anderson * already handles making sure that we're not trying to do two 7342ee471a1SDouglas Anderson * transfers at once or setting a chip select and doing a transfer 7352ee471a1SDouglas Anderson * concurrently. 7362ee471a1SDouglas Anderson * 7372ee471a1SDouglas Anderson * NOTE: we actually _can't_ hold the lock here because possibly we 7382ee471a1SDouglas Anderson * might call clk_set_rate() which needs to be able to sleep. 7392ee471a1SDouglas Anderson */ 7402ee471a1SDouglas Anderson spin_lock_irq(&mas->lock); 7412ee471a1SDouglas Anderson spin_unlock_irq(&mas->lock); 7422ee471a1SDouglas Anderson 743561de45fSGirish Mahadevan if (xfer->bits_per_word != mas->cur_bits_per_word) { 744561de45fSGirish Mahadevan spi_setup_word_len(mas, mode, xfer->bits_per_word); 745561de45fSGirish Mahadevan mas->cur_bits_per_word = xfer->bits_per_word; 746561de45fSGirish Mahadevan } 747561de45fSGirish Mahadevan 748561de45fSGirish Mahadevan /* Speed and bits per word can be overridden per transfer */ 7490e3b8a81SAkash Asthana ret = geni_spi_set_clock_and_bw(mas, xfer->speed_hz); 750e68b6624SDouglas Anderson if (ret) 751561de45fSGirish Mahadevan return; 752561de45fSGirish Mahadevan 753561de45fSGirish Mahadevan mas->tx_rem_bytes = 0; 754561de45fSGirish Mahadevan mas->rx_rem_bytes = 0; 755561de45fSGirish Mahadevan 756561de45fSGirish Mahadevan if (!(mas->cur_bits_per_word % MIN_WORD_LEN)) 757561de45fSGirish Mahadevan len = xfer->len * BITS_PER_BYTE / mas->cur_bits_per_word; 758561de45fSGirish Mahadevan else 759561de45fSGirish Mahadevan len = xfer->len / (mas->cur_bits_per_word / BITS_PER_BYTE + 1); 760561de45fSGirish Mahadevan len &= TRANS_LEN_MSK; 761561de45fSGirish Mahadevan 762561de45fSGirish Mahadevan mas->cur_xfer = xfer; 76319ea3275SStephen Boyd if (xfer->tx_buf) { 76419ea3275SStephen Boyd m_cmd |= SPI_TX_ONLY; 765561de45fSGirish Mahadevan mas->tx_rem_bytes = xfer->len; 766561de45fSGirish Mahadevan writel(len, se->base + SE_SPI_TX_TRANS_LEN); 767561de45fSGirish Mahadevan } 768561de45fSGirish Mahadevan 76919ea3275SStephen Boyd if (xfer->rx_buf) { 77019ea3275SStephen Boyd m_cmd |= SPI_RX_ONLY; 771561de45fSGirish Mahadevan writel(len, se->base + SE_SPI_RX_TRANS_LEN); 772561de45fSGirish Mahadevan mas->rx_rem_bytes = xfer->len; 773561de45fSGirish Mahadevan } 7742ee471a1SDouglas Anderson 7752ee471a1SDouglas Anderson /* 7762ee471a1SDouglas Anderson * Lock around right before we start the transfer since our 7772ee471a1SDouglas Anderson * interrupt could come in at any time now. 7782ee471a1SDouglas Anderson */ 7792ee471a1SDouglas Anderson spin_lock_irq(&mas->lock); 780561de45fSGirish Mahadevan geni_se_setup_m_cmd(se, m_cmd, FRAGMENTATION); 7816d66507dSDouglas Anderson if (m_cmd & SPI_TX_ONLY) { 7826d66507dSDouglas Anderson if (geni_spi_handle_tx(mas)) 783561de45fSGirish Mahadevan writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG); 7846d66507dSDouglas Anderson } 7852ee471a1SDouglas Anderson spin_unlock_irq(&mas->lock); 786561de45fSGirish Mahadevan } 787561de45fSGirish Mahadevan 788561de45fSGirish Mahadevan static int spi_geni_transfer_one(struct spi_master *spi, 789561de45fSGirish Mahadevan struct spi_device *slv, 790561de45fSGirish Mahadevan struct spi_transfer *xfer) 791561de45fSGirish Mahadevan { 792561de45fSGirish Mahadevan struct spi_geni_master *mas = spi_master_get_devdata(spi); 793561de45fSGirish Mahadevan 794690d8b91SDouglas Anderson if (spi_geni_is_abort_still_pending(mas)) 795690d8b91SDouglas Anderson return -EBUSY; 796690d8b91SDouglas Anderson 797561de45fSGirish Mahadevan /* Terminate and return success for 0 byte length transfer */ 798561de45fSGirish Mahadevan if (!xfer->len) 799561de45fSGirish Mahadevan return 0; 800561de45fSGirish Mahadevan 801b59c1224SVinod Koul if (mas->cur_xfer_mode == GENI_SE_FIFO) { 802561de45fSGirish Mahadevan setup_fifo_xfer(xfer, mas, slv->mode, spi); 803561de45fSGirish Mahadevan return 1; 804561de45fSGirish Mahadevan } 805b59c1224SVinod Koul return setup_gsi_xfer(xfer, mas, slv, spi); 806b59c1224SVinod Koul } 807561de45fSGirish Mahadevan 808561de45fSGirish Mahadevan static irqreturn_t geni_spi_isr(int irq, void *data) 809561de45fSGirish Mahadevan { 810561de45fSGirish Mahadevan struct spi_master *spi = data; 811561de45fSGirish Mahadevan struct spi_geni_master *mas = spi_master_get_devdata(spi); 812561de45fSGirish Mahadevan struct geni_se *se = &mas->se; 813561de45fSGirish Mahadevan u32 m_irq; 814561de45fSGirish Mahadevan 8152ee471a1SDouglas Anderson m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); 8162ee471a1SDouglas Anderson if (!m_irq) 817561de45fSGirish Mahadevan return IRQ_NONE; 818561de45fSGirish Mahadevan 819e191a082SDouglas Anderson if (m_irq & (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN | 820e191a082SDouglas Anderson M_RX_FIFO_RD_ERR_EN | M_RX_FIFO_WR_ERR_EN | 821e191a082SDouglas Anderson M_TX_FIFO_RD_ERR_EN | M_TX_FIFO_WR_ERR_EN)) 822e191a082SDouglas Anderson dev_warn(mas->dev, "Unexpected IRQ err status %#010x\n", m_irq); 823e191a082SDouglas Anderson 824539afdf9SDouglas Anderson spin_lock(&mas->lock); 825561de45fSGirish Mahadevan 826561de45fSGirish Mahadevan if ((m_irq & M_RX_FIFO_WATERMARK_EN) || (m_irq & M_RX_FIFO_LAST_EN)) 827561de45fSGirish Mahadevan geni_spi_handle_rx(mas); 828561de45fSGirish Mahadevan 829561de45fSGirish Mahadevan if (m_irq & M_TX_FIFO_WATERMARK_EN) 830561de45fSGirish Mahadevan geni_spi_handle_tx(mas); 831561de45fSGirish Mahadevan 832561de45fSGirish Mahadevan if (m_irq & M_CMD_DONE_EN) { 8337ba9bdcbSDouglas Anderson if (mas->cur_xfer) { 834561de45fSGirish Mahadevan spi_finalize_current_transfer(spi); 8357ba9bdcbSDouglas Anderson mas->cur_xfer = NULL; 836561de45fSGirish Mahadevan /* 83759ab0fa0SStephen Boyd * If this happens, then a CMD_DONE came before all the 83859ab0fa0SStephen Boyd * Tx buffer bytes were sent out. This is unusual, log 83959ab0fa0SStephen Boyd * this condition and disable the WM interrupt to 84059ab0fa0SStephen Boyd * prevent the system from stalling due an interrupt 84159ab0fa0SStephen Boyd * storm. 84259ab0fa0SStephen Boyd * 84359ab0fa0SStephen Boyd * If this happens when all Rx bytes haven't been 84459ab0fa0SStephen Boyd * received, log the condition. The only known time 84559ab0fa0SStephen Boyd * this can happen is if bits_per_word != 8 and some 84659ab0fa0SStephen Boyd * registers that expect xfer lengths in num spi_words 847561de45fSGirish Mahadevan * weren't written correctly. 848561de45fSGirish Mahadevan */ 849561de45fSGirish Mahadevan if (mas->tx_rem_bytes) { 850561de45fSGirish Mahadevan writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 851561de45fSGirish Mahadevan dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n", 852561de45fSGirish Mahadevan mas->tx_rem_bytes, mas->cur_bits_per_word); 853561de45fSGirish Mahadevan } 854561de45fSGirish Mahadevan if (mas->rx_rem_bytes) 855561de45fSGirish Mahadevan dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n", 856561de45fSGirish Mahadevan mas->rx_rem_bytes, mas->cur_bits_per_word); 85759ab0fa0SStephen Boyd } else { 85859ab0fa0SStephen Boyd complete(&mas->cs_done); 85959ab0fa0SStephen Boyd } 860561de45fSGirish Mahadevan } 861561de45fSGirish Mahadevan 8627ba9bdcbSDouglas Anderson if (m_irq & M_CMD_CANCEL_EN) 8637ba9bdcbSDouglas Anderson complete(&mas->cancel_done); 8647ba9bdcbSDouglas Anderson if (m_irq & M_CMD_ABORT_EN) 8657ba9bdcbSDouglas Anderson complete(&mas->abort_done); 866561de45fSGirish Mahadevan 8672ee471a1SDouglas Anderson /* 868db56d030SJay Fang * It's safe or a good idea to Ack all of our interrupts at the end 869db56d030SJay Fang * of the function. Specifically: 8702ee471a1SDouglas Anderson * - M_CMD_DONE_EN / M_RX_FIFO_LAST_EN: Edge triggered interrupts and 8712ee471a1SDouglas Anderson * clearing Acks. Clearing at the end relies on nobody else having 8722ee471a1SDouglas Anderson * started a new transfer yet or else we could be clearing _their_ 8732ee471a1SDouglas Anderson * done bit, but everyone grabs the spinlock before starting a new 8742ee471a1SDouglas Anderson * transfer. 8752ee471a1SDouglas Anderson * - M_RX_FIFO_WATERMARK_EN / M_TX_FIFO_WATERMARK_EN: These appear 8762ee471a1SDouglas Anderson * to be "latched level" interrupts so it's important to clear them 8772ee471a1SDouglas Anderson * _after_ you've handled the condition and always safe to do so 8782ee471a1SDouglas Anderson * since they'll re-assert if they're still happening. 8792ee471a1SDouglas Anderson */ 880561de45fSGirish Mahadevan writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR); 8812ee471a1SDouglas Anderson 882539afdf9SDouglas Anderson spin_unlock(&mas->lock); 8832ee471a1SDouglas Anderson 8840dccff3cSAlok Chauhan return IRQ_HANDLED; 885561de45fSGirish Mahadevan } 886561de45fSGirish Mahadevan 887561de45fSGirish Mahadevan static int spi_geni_probe(struct platform_device *pdev) 888561de45fSGirish Mahadevan { 8896a34e285SAlok Chauhan int ret, irq; 890561de45fSGirish Mahadevan struct spi_master *spi; 891561de45fSGirish Mahadevan struct spi_geni_master *mas; 8926a34e285SAlok Chauhan void __iomem *base; 8936a34e285SAlok Chauhan struct clk *clk; 894ea1e5b33SStephen Boyd struct device *dev = &pdev->dev; 8956a34e285SAlok Chauhan 8966a34e285SAlok Chauhan irq = platform_get_irq(pdev, 0); 8976b8ac10eSStephen Boyd if (irq < 0) 8986a34e285SAlok Chauhan return irq; 8996a34e285SAlok Chauhan 900b59c1224SVinod Koul ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); 901b59c1224SVinod Koul if (ret) 902b59c1224SVinod Koul return dev_err_probe(dev, ret, "could not set DMA mask\n"); 903b59c1224SVinod Koul 904d8e477abSYueHaibing base = devm_platform_ioremap_resource(pdev, 0); 9056a34e285SAlok Chauhan if (IS_ERR(base)) 9066a34e285SAlok Chauhan return PTR_ERR(base); 9076a34e285SAlok Chauhan 908ea1e5b33SStephen Boyd clk = devm_clk_get(dev, "se"); 909ea1e5b33SStephen Boyd if (IS_ERR(clk)) 9106a34e285SAlok Chauhan return PTR_ERR(clk); 911561de45fSGirish Mahadevan 9128f96c434SLukas Wunner spi = devm_spi_alloc_master(dev, sizeof(*mas)); 913561de45fSGirish Mahadevan if (!spi) 914561de45fSGirish Mahadevan return -ENOMEM; 915561de45fSGirish Mahadevan 916561de45fSGirish Mahadevan platform_set_drvdata(pdev, spi); 917561de45fSGirish Mahadevan mas = spi_master_get_devdata(spi); 9186a34e285SAlok Chauhan mas->irq = irq; 919ea1e5b33SStephen Boyd mas->dev = dev; 920ea1e5b33SStephen Boyd mas->se.dev = dev; 921ea1e5b33SStephen Boyd mas->se.wrapper = dev_get_drvdata(dev->parent); 9226a34e285SAlok Chauhan mas->se.base = base; 9236a34e285SAlok Chauhan mas->se.clk = clk; 924cfb12911SYangtao Li 925cfb12911SYangtao Li ret = devm_pm_opp_set_clkname(&pdev->dev, "se"); 926cfb12911SYangtao Li if (ret) 927cfb12911SYangtao Li return ret; 9281a9e489eSRajendra Nayak /* OPP table is optional */ 929cfb12911SYangtao Li ret = devm_pm_opp_of_add_table(&pdev->dev); 9307d568edfSViresh Kumar if (ret && ret != -ENODEV) { 9311a9e489eSRajendra Nayak dev_err(&pdev->dev, "invalid OPP table in device tree\n"); 932cfb12911SYangtao Li return ret; 9331a9e489eSRajendra Nayak } 934561de45fSGirish Mahadevan 935561de45fSGirish Mahadevan spi->bus_num = -1; 936ea1e5b33SStephen Boyd spi->dev.of_node = dev->of_node; 937561de45fSGirish Mahadevan spi->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH; 938561de45fSGirish Mahadevan spi->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 939561de45fSGirish Mahadevan spi->num_chipselect = 4; 940561de45fSGirish Mahadevan spi->max_speed_hz = 50000000; 941561de45fSGirish Mahadevan spi->prepare_message = spi_geni_prepare_message; 942561de45fSGirish Mahadevan spi->transfer_one = spi_geni_transfer_one; 943b59c1224SVinod Koul spi->can_dma = geni_can_dma; 944b59c1224SVinod Koul spi->dma_map_dev = dev->parent; 945561de45fSGirish Mahadevan spi->auto_runtime_pm = true; 946f8039ea5SVinod Koul spi->handle_err = spi_geni_handle_err; 9473b25f337SStephen Boyd spi->use_gpio_descriptors = true; 948561de45fSGirish Mahadevan 9497ba9bdcbSDouglas Anderson init_completion(&mas->cs_done); 9507ba9bdcbSDouglas Anderson init_completion(&mas->cancel_done); 9517ba9bdcbSDouglas Anderson init_completion(&mas->abort_done); 952561de45fSGirish Mahadevan spin_lock_init(&mas->lock); 953cfdab2cdSDouglas Anderson pm_runtime_use_autosuspend(&pdev->dev); 954cfdab2cdSDouglas Anderson pm_runtime_set_autosuspend_delay(&pdev->dev, 250); 955ea1e5b33SStephen Boyd pm_runtime_enable(dev); 956561de45fSGirish Mahadevan 9570e3b8a81SAkash Asthana ret = geni_icc_get(&mas->se, NULL); 9580e3b8a81SAkash Asthana if (ret) 9590e3b8a81SAkash Asthana goto spi_geni_probe_runtime_disable; 9600e3b8a81SAkash Asthana /* Set the bus quota to a reasonable value for register access */ 9610e3b8a81SAkash Asthana mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ); 9620e3b8a81SAkash Asthana mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; 9630e3b8a81SAkash Asthana 9640e3b8a81SAkash Asthana ret = geni_icc_set_bw(&mas->se); 9650e3b8a81SAkash Asthana if (ret) 9660e3b8a81SAkash Asthana goto spi_geni_probe_runtime_disable; 9670e3b8a81SAkash Asthana 968561de45fSGirish Mahadevan ret = spi_geni_init(mas); 969561de45fSGirish Mahadevan if (ret) 970561de45fSGirish Mahadevan goto spi_geni_probe_runtime_disable; 971561de45fSGirish Mahadevan 972b59c1224SVinod Koul /* 973b59c1224SVinod Koul * check the mode supported and set_cs for fifo mode only 974b59c1224SVinod Koul * for dma (gsi) mode, the gsi will set cs based on params passed in 975b59c1224SVinod Koul * TRE 976b59c1224SVinod Koul */ 977b59c1224SVinod Koul if (mas->cur_xfer_mode == GENI_SE_FIFO) 978b59c1224SVinod Koul spi->set_cs = spi_geni_set_cs; 979b59c1224SVinod Koul 980ea1e5b33SStephen Boyd ret = request_irq(mas->irq, geni_spi_isr, 0, dev_name(dev), spi); 981561de45fSGirish Mahadevan if (ret) 982b59c1224SVinod Koul goto spi_geni_release_dma; 983561de45fSGirish Mahadevan 984561de45fSGirish Mahadevan ret = spi_register_master(spi); 985561de45fSGirish Mahadevan if (ret) 986561de45fSGirish Mahadevan goto spi_geni_probe_free_irq; 987561de45fSGirish Mahadevan 988561de45fSGirish Mahadevan return 0; 989561de45fSGirish Mahadevan spi_geni_probe_free_irq: 990561de45fSGirish Mahadevan free_irq(mas->irq, spi); 991b59c1224SVinod Koul spi_geni_release_dma: 992b59c1224SVinod Koul spi_geni_release_dma_chan(mas); 993561de45fSGirish Mahadevan spi_geni_probe_runtime_disable: 994ea1e5b33SStephen Boyd pm_runtime_disable(dev); 995561de45fSGirish Mahadevan return ret; 996561de45fSGirish Mahadevan } 997561de45fSGirish Mahadevan 998561de45fSGirish Mahadevan static int spi_geni_remove(struct platform_device *pdev) 999561de45fSGirish Mahadevan { 1000561de45fSGirish Mahadevan struct spi_master *spi = platform_get_drvdata(pdev); 1001561de45fSGirish Mahadevan struct spi_geni_master *mas = spi_master_get_devdata(spi); 1002561de45fSGirish Mahadevan 1003561de45fSGirish Mahadevan /* Unregister _before_ disabling pm_runtime() so we stop transfers */ 1004561de45fSGirish Mahadevan spi_unregister_master(spi); 1005561de45fSGirish Mahadevan 1006b59c1224SVinod Koul spi_geni_release_dma_chan(mas); 1007b59c1224SVinod Koul 1008561de45fSGirish Mahadevan free_irq(mas->irq, spi); 1009561de45fSGirish Mahadevan pm_runtime_disable(&pdev->dev); 1010561de45fSGirish Mahadevan return 0; 1011561de45fSGirish Mahadevan } 1012561de45fSGirish Mahadevan 1013561de45fSGirish Mahadevan static int __maybe_unused spi_geni_runtime_suspend(struct device *dev) 1014561de45fSGirish Mahadevan { 1015561de45fSGirish Mahadevan struct spi_master *spi = dev_get_drvdata(dev); 1016561de45fSGirish Mahadevan struct spi_geni_master *mas = spi_master_get_devdata(spi); 10170e3b8a81SAkash Asthana int ret; 1018561de45fSGirish Mahadevan 10191a9e489eSRajendra Nayak /* Drop the performance state vote */ 10201a9e489eSRajendra Nayak dev_pm_opp_set_rate(dev, 0); 10211a9e489eSRajendra Nayak 10220e3b8a81SAkash Asthana ret = geni_se_resources_off(&mas->se); 10230e3b8a81SAkash Asthana if (ret) 10240e3b8a81SAkash Asthana return ret; 10250e3b8a81SAkash Asthana 10260e3b8a81SAkash Asthana return geni_icc_disable(&mas->se); 1027561de45fSGirish Mahadevan } 1028561de45fSGirish Mahadevan 1029561de45fSGirish Mahadevan static int __maybe_unused spi_geni_runtime_resume(struct device *dev) 1030561de45fSGirish Mahadevan { 1031561de45fSGirish Mahadevan struct spi_master *spi = dev_get_drvdata(dev); 1032561de45fSGirish Mahadevan struct spi_geni_master *mas = spi_master_get_devdata(spi); 10330e3b8a81SAkash Asthana int ret; 10340e3b8a81SAkash Asthana 10350e3b8a81SAkash Asthana ret = geni_icc_enable(&mas->se); 10360e3b8a81SAkash Asthana if (ret) 10370e3b8a81SAkash Asthana return ret; 1038561de45fSGirish Mahadevan 10395f219524SDouglas Anderson ret = geni_se_resources_on(&mas->se); 10405f219524SDouglas Anderson if (ret) 10415f219524SDouglas Anderson return ret; 10425f219524SDouglas Anderson 10435f219524SDouglas Anderson return dev_pm_opp_set_rate(mas->dev, mas->cur_sclk_hz); 1044561de45fSGirish Mahadevan } 1045561de45fSGirish Mahadevan 1046561de45fSGirish Mahadevan static int __maybe_unused spi_geni_suspend(struct device *dev) 1047561de45fSGirish Mahadevan { 1048561de45fSGirish Mahadevan struct spi_master *spi = dev_get_drvdata(dev); 1049561de45fSGirish Mahadevan int ret; 1050561de45fSGirish Mahadevan 1051561de45fSGirish Mahadevan ret = spi_master_suspend(spi); 1052561de45fSGirish Mahadevan if (ret) 1053561de45fSGirish Mahadevan return ret; 1054561de45fSGirish Mahadevan 1055561de45fSGirish Mahadevan ret = pm_runtime_force_suspend(dev); 1056561de45fSGirish Mahadevan if (ret) 1057561de45fSGirish Mahadevan spi_master_resume(spi); 1058561de45fSGirish Mahadevan 1059561de45fSGirish Mahadevan return ret; 1060561de45fSGirish Mahadevan } 1061561de45fSGirish Mahadevan 1062561de45fSGirish Mahadevan static int __maybe_unused spi_geni_resume(struct device *dev) 1063561de45fSGirish Mahadevan { 1064561de45fSGirish Mahadevan struct spi_master *spi = dev_get_drvdata(dev); 1065561de45fSGirish Mahadevan int ret; 1066561de45fSGirish Mahadevan 1067561de45fSGirish Mahadevan ret = pm_runtime_force_resume(dev); 1068561de45fSGirish Mahadevan if (ret) 1069561de45fSGirish Mahadevan return ret; 1070561de45fSGirish Mahadevan 1071561de45fSGirish Mahadevan ret = spi_master_resume(spi); 1072561de45fSGirish Mahadevan if (ret) 1073561de45fSGirish Mahadevan pm_runtime_force_suspend(dev); 1074561de45fSGirish Mahadevan 1075561de45fSGirish Mahadevan return ret; 1076561de45fSGirish Mahadevan } 1077561de45fSGirish Mahadevan 1078561de45fSGirish Mahadevan static const struct dev_pm_ops spi_geni_pm_ops = { 1079561de45fSGirish Mahadevan SET_RUNTIME_PM_OPS(spi_geni_runtime_suspend, 1080561de45fSGirish Mahadevan spi_geni_runtime_resume, NULL) 1081561de45fSGirish Mahadevan SET_SYSTEM_SLEEP_PM_OPS(spi_geni_suspend, spi_geni_resume) 1082561de45fSGirish Mahadevan }; 1083561de45fSGirish Mahadevan 1084561de45fSGirish Mahadevan static const struct of_device_id spi_geni_dt_match[] = { 1085561de45fSGirish Mahadevan { .compatible = "qcom,geni-spi" }, 1086561de45fSGirish Mahadevan {} 1087561de45fSGirish Mahadevan }; 1088561de45fSGirish Mahadevan MODULE_DEVICE_TABLE(of, spi_geni_dt_match); 1089561de45fSGirish Mahadevan 1090561de45fSGirish Mahadevan static struct platform_driver spi_geni_driver = { 1091561de45fSGirish Mahadevan .probe = spi_geni_probe, 1092561de45fSGirish Mahadevan .remove = spi_geni_remove, 1093561de45fSGirish Mahadevan .driver = { 1094561de45fSGirish Mahadevan .name = "geni_spi", 1095561de45fSGirish Mahadevan .pm = &spi_geni_pm_ops, 1096561de45fSGirish Mahadevan .of_match_table = spi_geni_dt_match, 1097561de45fSGirish Mahadevan }, 1098561de45fSGirish Mahadevan }; 1099561de45fSGirish Mahadevan module_platform_driver(spi_geni_driver); 1100561de45fSGirish Mahadevan 1101561de45fSGirish Mahadevan MODULE_DESCRIPTION("SPI driver for GENI based QUP cores"); 1102561de45fSGirish Mahadevan MODULE_LICENSE("GPL v2"); 1103