1 /* 2 * Freescale SPI controller driver. 3 * 4 * Maintainer: Kumar Gala 5 * 6 * Copyright (C) 2006 Polycom, Inc. 7 * Copyright 2010 Freescale Semiconductor, Inc. 8 * 9 * CPM SPI and QE buffer descriptors mode support: 10 * Copyright (c) 2009 MontaVista Software, Inc. 11 * Author: Anton Vorontsov <avorontsov@ru.mvista.com> 12 * 13 * GRLIB support: 14 * Copyright (c) 2012 Aeroflex Gaisler AB. 15 * Author: Andreas Larsson <andreas@gaisler.com> 16 * 17 * This program is free software; you can redistribute it and/or modify it 18 * under the terms of the GNU General Public License as published by the 19 * Free Software Foundation; either version 2 of the License, or (at your 20 * option) any later version. 21 */ 22 #include <linux/module.h> 23 #include <linux/types.h> 24 #include <linux/kernel.h> 25 #include <linux/interrupt.h> 26 #include <linux/delay.h> 27 #include <linux/irq.h> 28 #include <linux/spi/spi.h> 29 #include <linux/spi/spi_bitbang.h> 30 #include <linux/platform_device.h> 31 #include <linux/fsl_devices.h> 32 #include <linux/dma-mapping.h> 33 #include <linux/mm.h> 34 #include <linux/mutex.h> 35 #include <linux/of.h> 36 #include <linux/of_platform.h> 37 #include <linux/of_address.h> 38 #include <linux/of_irq.h> 39 #include <linux/gpio.h> 40 #include <linux/of_gpio.h> 41 42 #include "spi-fsl-lib.h" 43 #include "spi-fsl-cpm.h" 44 #include "spi-fsl-spi.h" 45 46 #define TYPE_FSL 0 47 #define TYPE_GRLIB 1 48 49 struct fsl_spi_match_data { 50 int type; 51 }; 52 53 static struct fsl_spi_match_data of_fsl_spi_fsl_config = { 54 .type = TYPE_FSL, 55 }; 56 57 static struct fsl_spi_match_data of_fsl_spi_grlib_config = { 58 .type = TYPE_GRLIB, 59 }; 60 61 static struct of_device_id of_fsl_spi_match[] = { 62 { 63 .compatible = "fsl,spi", 64 .data = &of_fsl_spi_fsl_config, 65 }, 66 { 67 .compatible = "aeroflexgaisler,spictrl", 68 .data = &of_fsl_spi_grlib_config, 69 }, 70 {} 71 }; 72 MODULE_DEVICE_TABLE(of, of_fsl_spi_match); 73 74 static int fsl_spi_get_type(struct device *dev) 75 { 76 const struct of_device_id *match; 77 78 if (dev->of_node) { 79 match = of_match_node(of_fsl_spi_match, dev->of_node); 80 if (match && match->data) 81 return ((struct fsl_spi_match_data *)match->data)->type; 82 } 83 return TYPE_FSL; 84 } 85 86 static void fsl_spi_change_mode(struct spi_device *spi) 87 { 88 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master); 89 struct spi_mpc8xxx_cs *cs = spi->controller_state; 90 struct fsl_spi_reg *reg_base = mspi->reg_base; 91 __be32 __iomem *mode = ®_base->mode; 92 unsigned long flags; 93 94 if (cs->hw_mode == mpc8xxx_spi_read_reg(mode)) 95 return; 96 97 /* Turn off IRQs locally to minimize time that SPI is disabled. */ 98 local_irq_save(flags); 99 100 /* Turn off SPI unit prior changing mode */ 101 mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE); 102 103 /* When in CPM mode, we need to reinit tx and rx. */ 104 if (mspi->flags & SPI_CPM_MODE) { 105 fsl_spi_cpm_reinit_txrx(mspi); 106 } 107 mpc8xxx_spi_write_reg(mode, cs->hw_mode); 108 local_irq_restore(flags); 109 } 110 111 static void fsl_spi_chipselect(struct spi_device *spi, int value) 112 { 113 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); 114 struct fsl_spi_platform_data *pdata; 115 bool pol = spi->mode & SPI_CS_HIGH; 116 struct spi_mpc8xxx_cs *cs = spi->controller_state; 117 118 pdata = spi->dev.parent->parent->platform_data; 119 120 if (value == BITBANG_CS_INACTIVE) { 121 if (pdata->cs_control) 122 pdata->cs_control(spi, !pol); 123 } 124 125 if (value == BITBANG_CS_ACTIVE) { 126 mpc8xxx_spi->rx_shift = cs->rx_shift; 127 mpc8xxx_spi->tx_shift = cs->tx_shift; 128 mpc8xxx_spi->get_rx = cs->get_rx; 129 mpc8xxx_spi->get_tx = cs->get_tx; 130 131 fsl_spi_change_mode(spi); 132 133 if (pdata->cs_control) 134 pdata->cs_control(spi, pol); 135 } 136 } 137 138 static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift, 139 int bits_per_word, int msb_first) 140 { 141 *rx_shift = 0; 142 *tx_shift = 0; 143 if (msb_first) { 144 if (bits_per_word <= 8) { 145 *rx_shift = 16; 146 *tx_shift = 24; 147 } else if (bits_per_word <= 16) { 148 *rx_shift = 16; 149 *tx_shift = 16; 150 } 151 } else { 152 if (bits_per_word <= 8) 153 *rx_shift = 8; 154 } 155 } 156 157 static void fsl_spi_grlib_set_shifts(u32 *rx_shift, u32 *tx_shift, 158 int bits_per_word, int msb_first) 159 { 160 *rx_shift = 0; 161 *tx_shift = 0; 162 if (bits_per_word <= 16) { 163 if (msb_first) { 164 *rx_shift = 16; /* LSB in bit 16 */ 165 *tx_shift = 32 - bits_per_word; /* MSB in bit 31 */ 166 } else { 167 *rx_shift = 16 - bits_per_word; /* MSB in bit 15 */ 168 } 169 } 170 } 171 172 static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs, 173 struct spi_device *spi, 174 struct mpc8xxx_spi *mpc8xxx_spi, 175 int bits_per_word) 176 { 177 cs->rx_shift = 0; 178 cs->tx_shift = 0; 179 if (bits_per_word <= 8) { 180 cs->get_rx = mpc8xxx_spi_rx_buf_u8; 181 cs->get_tx = mpc8xxx_spi_tx_buf_u8; 182 } else if (bits_per_word <= 16) { 183 cs->get_rx = mpc8xxx_spi_rx_buf_u16; 184 cs->get_tx = mpc8xxx_spi_tx_buf_u16; 185 } else if (bits_per_word <= 32) { 186 cs->get_rx = mpc8xxx_spi_rx_buf_u32; 187 cs->get_tx = mpc8xxx_spi_tx_buf_u32; 188 } else 189 return -EINVAL; 190 191 if (mpc8xxx_spi->set_shifts) 192 mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift, 193 bits_per_word, 194 !(spi->mode & SPI_LSB_FIRST)); 195 196 mpc8xxx_spi->rx_shift = cs->rx_shift; 197 mpc8xxx_spi->tx_shift = cs->tx_shift; 198 mpc8xxx_spi->get_rx = cs->get_rx; 199 mpc8xxx_spi->get_tx = cs->get_tx; 200 201 return bits_per_word; 202 } 203 204 static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs, 205 struct spi_device *spi, 206 int bits_per_word) 207 { 208 /* QE uses Little Endian for words > 8 209 * so transform all words > 8 into 8 bits 210 * Unfortnatly that doesn't work for LSB so 211 * reject these for now */ 212 /* Note: 32 bits word, LSB works iff 213 * tfcr/rfcr is set to CPMFCR_GBL */ 214 if (spi->mode & SPI_LSB_FIRST && 215 bits_per_word > 8) 216 return -EINVAL; 217 if (bits_per_word > 8) 218 return 8; /* pretend its 8 bits */ 219 return bits_per_word; 220 } 221 222 static int fsl_spi_setup_transfer(struct spi_device *spi, 223 struct spi_transfer *t) 224 { 225 struct mpc8xxx_spi *mpc8xxx_spi; 226 int bits_per_word = 0; 227 u8 pm; 228 u32 hz = 0; 229 struct spi_mpc8xxx_cs *cs = spi->controller_state; 230 231 mpc8xxx_spi = spi_master_get_devdata(spi->master); 232 233 if (t) { 234 bits_per_word = t->bits_per_word; 235 hz = t->speed_hz; 236 } 237 238 /* spi_transfer level calls that work per-word */ 239 if (!bits_per_word) 240 bits_per_word = spi->bits_per_word; 241 242 /* Make sure its a bit width we support [4..16, 32] */ 243 if ((bits_per_word < 4) 244 || ((bits_per_word > 16) && (bits_per_word != 32)) 245 || (bits_per_word > mpc8xxx_spi->max_bits_per_word)) 246 return -EINVAL; 247 248 if (!hz) 249 hz = spi->max_speed_hz; 250 251 if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) 252 bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi, 253 mpc8xxx_spi, 254 bits_per_word); 255 else if (mpc8xxx_spi->flags & SPI_QE) 256 bits_per_word = mspi_apply_qe_mode_quirks(cs, spi, 257 bits_per_word); 258 259 if (bits_per_word < 0) 260 return bits_per_word; 261 262 if (bits_per_word == 32) 263 bits_per_word = 0; 264 else 265 bits_per_word = bits_per_word - 1; 266 267 /* mask out bits we are going to set */ 268 cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16 269 | SPMODE_PM(0xF)); 270 271 cs->hw_mode |= SPMODE_LEN(bits_per_word); 272 273 if ((mpc8xxx_spi->spibrg / hz) > 64) { 274 cs->hw_mode |= SPMODE_DIV16; 275 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1; 276 277 WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. " 278 "Will use %d Hz instead.\n", dev_name(&spi->dev), 279 hz, mpc8xxx_spi->spibrg / 1024); 280 if (pm > 16) 281 pm = 16; 282 } else { 283 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1; 284 } 285 if (pm) 286 pm--; 287 288 cs->hw_mode |= SPMODE_PM(pm); 289 290 fsl_spi_change_mode(spi); 291 return 0; 292 } 293 294 static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi, 295 struct spi_transfer *t, unsigned int len) 296 { 297 u32 word; 298 struct fsl_spi_reg *reg_base = mspi->reg_base; 299 300 mspi->count = len; 301 302 /* enable rx ints */ 303 mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE); 304 305 /* transmit word */ 306 word = mspi->get_tx(mspi); 307 mpc8xxx_spi_write_reg(®_base->transmit, word); 308 309 return 0; 310 } 311 312 static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t, 313 bool is_dma_mapped) 314 { 315 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); 316 struct fsl_spi_reg *reg_base; 317 unsigned int len = t->len; 318 u8 bits_per_word; 319 int ret; 320 321 reg_base = mpc8xxx_spi->reg_base; 322 bits_per_word = spi->bits_per_word; 323 if (t->bits_per_word) 324 bits_per_word = t->bits_per_word; 325 326 if (bits_per_word > 8) { 327 /* invalid length? */ 328 if (len & 1) 329 return -EINVAL; 330 len /= 2; 331 } 332 if (bits_per_word > 16) { 333 /* invalid length? */ 334 if (len & 1) 335 return -EINVAL; 336 len /= 2; 337 } 338 339 mpc8xxx_spi->tx = t->tx_buf; 340 mpc8xxx_spi->rx = t->rx_buf; 341 342 INIT_COMPLETION(mpc8xxx_spi->done); 343 344 if (mpc8xxx_spi->flags & SPI_CPM_MODE) 345 ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped); 346 else 347 ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len); 348 if (ret) 349 return ret; 350 351 wait_for_completion(&mpc8xxx_spi->done); 352 353 /* disable rx ints */ 354 mpc8xxx_spi_write_reg(®_base->mask, 0); 355 356 if (mpc8xxx_spi->flags & SPI_CPM_MODE) 357 fsl_spi_cpm_bufs_complete(mpc8xxx_spi); 358 359 return mpc8xxx_spi->count; 360 } 361 362 static void fsl_spi_do_one_msg(struct spi_message *m) 363 { 364 struct spi_device *spi = m->spi; 365 struct spi_transfer *t; 366 unsigned int cs_change; 367 const int nsecs = 50; 368 int status; 369 370 cs_change = 1; 371 status = 0; 372 list_for_each_entry(t, &m->transfers, transfer_list) { 373 if (t->bits_per_word || t->speed_hz) { 374 /* Don't allow changes if CS is active */ 375 status = -EINVAL; 376 377 if (cs_change) 378 status = fsl_spi_setup_transfer(spi, t); 379 if (status < 0) 380 break; 381 } 382 383 if (cs_change) { 384 fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE); 385 ndelay(nsecs); 386 } 387 cs_change = t->cs_change; 388 if (t->len) 389 status = fsl_spi_bufs(spi, t, m->is_dma_mapped); 390 if (status) { 391 status = -EMSGSIZE; 392 break; 393 } 394 m->actual_length += t->len; 395 396 if (t->delay_usecs) 397 udelay(t->delay_usecs); 398 399 if (cs_change) { 400 ndelay(nsecs); 401 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); 402 ndelay(nsecs); 403 } 404 } 405 406 m->status = status; 407 m->complete(m->context); 408 409 if (status || !cs_change) { 410 ndelay(nsecs); 411 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); 412 } 413 414 fsl_spi_setup_transfer(spi, NULL); 415 } 416 417 static int fsl_spi_setup(struct spi_device *spi) 418 { 419 struct mpc8xxx_spi *mpc8xxx_spi; 420 struct fsl_spi_reg *reg_base; 421 int retval; 422 u32 hw_mode; 423 struct spi_mpc8xxx_cs *cs = spi->controller_state; 424 425 if (!spi->max_speed_hz) 426 return -EINVAL; 427 428 if (!cs) { 429 cs = kzalloc(sizeof *cs, GFP_KERNEL); 430 if (!cs) 431 return -ENOMEM; 432 spi->controller_state = cs; 433 } 434 mpc8xxx_spi = spi_master_get_devdata(spi->master); 435 436 reg_base = mpc8xxx_spi->reg_base; 437 438 hw_mode = cs->hw_mode; /* Save original settings */ 439 cs->hw_mode = mpc8xxx_spi_read_reg(®_base->mode); 440 /* mask out bits we are going to set */ 441 cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH 442 | SPMODE_REV | SPMODE_LOOP); 443 444 if (spi->mode & SPI_CPHA) 445 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK; 446 if (spi->mode & SPI_CPOL) 447 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH; 448 if (!(spi->mode & SPI_LSB_FIRST)) 449 cs->hw_mode |= SPMODE_REV; 450 if (spi->mode & SPI_LOOP) 451 cs->hw_mode |= SPMODE_LOOP; 452 453 retval = fsl_spi_setup_transfer(spi, NULL); 454 if (retval < 0) { 455 cs->hw_mode = hw_mode; /* Restore settings */ 456 return retval; 457 } 458 459 if (mpc8xxx_spi->type == TYPE_GRLIB) { 460 if (gpio_is_valid(spi->cs_gpio)) { 461 int desel; 462 463 retval = gpio_request(spi->cs_gpio, 464 dev_name(&spi->dev)); 465 if (retval) 466 return retval; 467 468 desel = !(spi->mode & SPI_CS_HIGH); 469 retval = gpio_direction_output(spi->cs_gpio, desel); 470 if (retval) { 471 gpio_free(spi->cs_gpio); 472 return retval; 473 } 474 } else if (spi->cs_gpio != -ENOENT) { 475 if (spi->cs_gpio < 0) 476 return spi->cs_gpio; 477 return -EINVAL; 478 } 479 /* When spi->cs_gpio == -ENOENT, a hole in the phandle list 480 * indicates to use native chipselect if present, or allow for 481 * an always selected chip 482 */ 483 } 484 485 /* Initialize chipselect - might be active for SPI_CS_HIGH mode */ 486 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); 487 488 return 0; 489 } 490 491 static void fsl_spi_cleanup(struct spi_device *spi) 492 { 493 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); 494 495 if (mpc8xxx_spi->type == TYPE_GRLIB && gpio_is_valid(spi->cs_gpio)) 496 gpio_free(spi->cs_gpio); 497 } 498 499 static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) 500 { 501 struct fsl_spi_reg *reg_base = mspi->reg_base; 502 503 /* We need handle RX first */ 504 if (events & SPIE_NE) { 505 u32 rx_data = mpc8xxx_spi_read_reg(®_base->receive); 506 507 if (mspi->rx) 508 mspi->get_rx(rx_data, mspi); 509 } 510 511 if ((events & SPIE_NF) == 0) 512 /* spin until TX is done */ 513 while (((events = 514 mpc8xxx_spi_read_reg(®_base->event)) & 515 SPIE_NF) == 0) 516 cpu_relax(); 517 518 /* Clear the events */ 519 mpc8xxx_spi_write_reg(®_base->event, events); 520 521 mspi->count -= 1; 522 if (mspi->count) { 523 u32 word = mspi->get_tx(mspi); 524 525 mpc8xxx_spi_write_reg(®_base->transmit, word); 526 } else { 527 complete(&mspi->done); 528 } 529 } 530 531 static irqreturn_t fsl_spi_irq(s32 irq, void *context_data) 532 { 533 struct mpc8xxx_spi *mspi = context_data; 534 irqreturn_t ret = IRQ_NONE; 535 u32 events; 536 struct fsl_spi_reg *reg_base = mspi->reg_base; 537 538 /* Get interrupt events(tx/rx) */ 539 events = mpc8xxx_spi_read_reg(®_base->event); 540 if (events) 541 ret = IRQ_HANDLED; 542 543 dev_dbg(mspi->dev, "%s: events %x\n", __func__, events); 544 545 if (mspi->flags & SPI_CPM_MODE) 546 fsl_spi_cpm_irq(mspi, events); 547 else 548 fsl_spi_cpu_irq(mspi, events); 549 550 return ret; 551 } 552 553 static void fsl_spi_remove(struct mpc8xxx_spi *mspi) 554 { 555 iounmap(mspi->reg_base); 556 fsl_spi_cpm_free(mspi); 557 } 558 559 static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on) 560 { 561 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); 562 struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base; 563 u32 slvsel; 564 u16 cs = spi->chip_select; 565 566 if (gpio_is_valid(spi->cs_gpio)) { 567 gpio_set_value(spi->cs_gpio, on); 568 } else if (cs < mpc8xxx_spi->native_chipselects) { 569 slvsel = mpc8xxx_spi_read_reg(®_base->slvsel); 570 slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs)); 571 mpc8xxx_spi_write_reg(®_base->slvsel, slvsel); 572 } 573 } 574 575 static void fsl_spi_grlib_probe(struct device *dev) 576 { 577 struct fsl_spi_platform_data *pdata = dev->platform_data; 578 struct spi_master *master = dev_get_drvdata(dev); 579 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); 580 struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base; 581 int mbits; 582 u32 capabilities; 583 584 capabilities = mpc8xxx_spi_read_reg(®_base->cap); 585 586 mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts; 587 mbits = SPCAP_MAXWLEN(capabilities); 588 if (mbits) 589 mpc8xxx_spi->max_bits_per_word = mbits + 1; 590 591 mpc8xxx_spi->native_chipselects = 0; 592 if (SPCAP_SSEN(capabilities)) { 593 mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities); 594 mpc8xxx_spi_write_reg(®_base->slvsel, 0xffffffff); 595 } 596 master->num_chipselect = mpc8xxx_spi->native_chipselects; 597 pdata->cs_control = fsl_spi_grlib_cs_control; 598 } 599 600 static struct spi_master * fsl_spi_probe(struct device *dev, 601 struct resource *mem, unsigned int irq) 602 { 603 struct fsl_spi_platform_data *pdata = dev->platform_data; 604 struct spi_master *master; 605 struct mpc8xxx_spi *mpc8xxx_spi; 606 struct fsl_spi_reg *reg_base; 607 u32 regval; 608 int ret = 0; 609 610 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi)); 611 if (master == NULL) { 612 ret = -ENOMEM; 613 goto err; 614 } 615 616 dev_set_drvdata(dev, master); 617 618 ret = mpc8xxx_spi_probe(dev, mem, irq); 619 if (ret) 620 goto err_probe; 621 622 master->setup = fsl_spi_setup; 623 master->cleanup = fsl_spi_cleanup; 624 625 mpc8xxx_spi = spi_master_get_devdata(master); 626 mpc8xxx_spi->spi_do_one_msg = fsl_spi_do_one_msg; 627 mpc8xxx_spi->spi_remove = fsl_spi_remove; 628 mpc8xxx_spi->max_bits_per_word = 32; 629 mpc8xxx_spi->type = fsl_spi_get_type(dev); 630 631 ret = fsl_spi_cpm_init(mpc8xxx_spi); 632 if (ret) 633 goto err_cpm_init; 634 635 mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem)); 636 if (mpc8xxx_spi->reg_base == NULL) { 637 ret = -ENOMEM; 638 goto err_ioremap; 639 } 640 641 if (mpc8xxx_spi->type == TYPE_GRLIB) 642 fsl_spi_grlib_probe(dev); 643 644 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) 645 mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts; 646 647 if (mpc8xxx_spi->set_shifts) 648 /* 8 bits per word and MSB first */ 649 mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift, 650 &mpc8xxx_spi->tx_shift, 8, 1); 651 652 /* Register for SPI Interrupt */ 653 ret = request_irq(mpc8xxx_spi->irq, fsl_spi_irq, 654 0, "fsl_spi", mpc8xxx_spi); 655 656 if (ret != 0) 657 goto free_irq; 658 659 reg_base = mpc8xxx_spi->reg_base; 660 661 /* SPI controller initializations */ 662 mpc8xxx_spi_write_reg(®_base->mode, 0); 663 mpc8xxx_spi_write_reg(®_base->mask, 0); 664 mpc8xxx_spi_write_reg(®_base->command, 0); 665 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff); 666 667 /* Enable SPI interface */ 668 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; 669 if (mpc8xxx_spi->max_bits_per_word < 8) { 670 regval &= ~SPMODE_LEN(0xF); 671 regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1); 672 } 673 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) 674 regval |= SPMODE_OP; 675 676 mpc8xxx_spi_write_reg(®_base->mode, regval); 677 678 ret = spi_register_master(master); 679 if (ret < 0) 680 goto unreg_master; 681 682 dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base, 683 mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags)); 684 685 return master; 686 687 unreg_master: 688 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi); 689 free_irq: 690 iounmap(mpc8xxx_spi->reg_base); 691 err_ioremap: 692 fsl_spi_cpm_free(mpc8xxx_spi); 693 err_cpm_init: 694 err_probe: 695 spi_master_put(master); 696 err: 697 return ERR_PTR(ret); 698 } 699 700 static void fsl_spi_cs_control(struct spi_device *spi, bool on) 701 { 702 struct device *dev = spi->dev.parent->parent; 703 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(dev->platform_data); 704 u16 cs = spi->chip_select; 705 int gpio = pinfo->gpios[cs]; 706 bool alow = pinfo->alow_flags[cs]; 707 708 gpio_set_value(gpio, on ^ alow); 709 } 710 711 static int of_fsl_spi_get_chipselects(struct device *dev) 712 { 713 struct device_node *np = dev->of_node; 714 struct fsl_spi_platform_data *pdata = dev->platform_data; 715 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); 716 int ngpios; 717 int i = 0; 718 int ret; 719 720 ngpios = of_gpio_count(np); 721 if (ngpios <= 0) { 722 /* 723 * SPI w/o chip-select line. One SPI device is still permitted 724 * though. 725 */ 726 pdata->max_chipselect = 1; 727 return 0; 728 } 729 730 pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL); 731 if (!pinfo->gpios) 732 return -ENOMEM; 733 memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios)); 734 735 pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags), 736 GFP_KERNEL); 737 if (!pinfo->alow_flags) { 738 ret = -ENOMEM; 739 goto err_alloc_flags; 740 } 741 742 for (; i < ngpios; i++) { 743 int gpio; 744 enum of_gpio_flags flags; 745 746 gpio = of_get_gpio_flags(np, i, &flags); 747 if (!gpio_is_valid(gpio)) { 748 dev_err(dev, "invalid gpio #%d: %d\n", i, gpio); 749 ret = gpio; 750 goto err_loop; 751 } 752 753 ret = gpio_request(gpio, dev_name(dev)); 754 if (ret) { 755 dev_err(dev, "can't request gpio #%d: %d\n", i, ret); 756 goto err_loop; 757 } 758 759 pinfo->gpios[i] = gpio; 760 pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW; 761 762 ret = gpio_direction_output(pinfo->gpios[i], 763 pinfo->alow_flags[i]); 764 if (ret) { 765 dev_err(dev, "can't set output direction for gpio " 766 "#%d: %d\n", i, ret); 767 goto err_loop; 768 } 769 } 770 771 pdata->max_chipselect = ngpios; 772 pdata->cs_control = fsl_spi_cs_control; 773 774 return 0; 775 776 err_loop: 777 while (i >= 0) { 778 if (gpio_is_valid(pinfo->gpios[i])) 779 gpio_free(pinfo->gpios[i]); 780 i--; 781 } 782 783 kfree(pinfo->alow_flags); 784 pinfo->alow_flags = NULL; 785 err_alloc_flags: 786 kfree(pinfo->gpios); 787 pinfo->gpios = NULL; 788 return ret; 789 } 790 791 static int of_fsl_spi_free_chipselects(struct device *dev) 792 { 793 struct fsl_spi_platform_data *pdata = dev->platform_data; 794 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); 795 int i; 796 797 if (!pinfo->gpios) 798 return 0; 799 800 for (i = 0; i < pdata->max_chipselect; i++) { 801 if (gpio_is_valid(pinfo->gpios[i])) 802 gpio_free(pinfo->gpios[i]); 803 } 804 805 kfree(pinfo->gpios); 806 kfree(pinfo->alow_flags); 807 return 0; 808 } 809 810 static int of_fsl_spi_probe(struct platform_device *ofdev) 811 { 812 struct device *dev = &ofdev->dev; 813 struct device_node *np = ofdev->dev.of_node; 814 struct spi_master *master; 815 struct resource mem; 816 int irq, type; 817 int ret = -ENOMEM; 818 819 ret = of_mpc8xxx_spi_probe(ofdev); 820 if (ret) 821 return ret; 822 823 type = fsl_spi_get_type(&ofdev->dev); 824 if (type == TYPE_FSL) { 825 ret = of_fsl_spi_get_chipselects(dev); 826 if (ret) 827 goto err; 828 } 829 830 ret = of_address_to_resource(np, 0, &mem); 831 if (ret) 832 goto err; 833 834 irq = irq_of_parse_and_map(np, 0); 835 if (!irq) { 836 ret = -EINVAL; 837 goto err; 838 } 839 840 master = fsl_spi_probe(dev, &mem, irq); 841 if (IS_ERR(master)) { 842 ret = PTR_ERR(master); 843 goto err; 844 } 845 846 return 0; 847 848 err: 849 if (type == TYPE_FSL) 850 of_fsl_spi_free_chipselects(dev); 851 return ret; 852 } 853 854 static int of_fsl_spi_remove(struct platform_device *ofdev) 855 { 856 struct spi_master *master = platform_get_drvdata(ofdev); 857 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); 858 int ret; 859 860 ret = mpc8xxx_spi_remove(&ofdev->dev); 861 if (ret) 862 return ret; 863 if (mpc8xxx_spi->type == TYPE_FSL) 864 of_fsl_spi_free_chipselects(&ofdev->dev); 865 return 0; 866 } 867 868 static struct platform_driver of_fsl_spi_driver = { 869 .driver = { 870 .name = "fsl_spi", 871 .owner = THIS_MODULE, 872 .of_match_table = of_fsl_spi_match, 873 }, 874 .probe = of_fsl_spi_probe, 875 .remove = of_fsl_spi_remove, 876 }; 877 878 #ifdef CONFIG_MPC832x_RDB 879 /* 880 * XXX XXX XXX 881 * This is "legacy" platform driver, was used by the MPC8323E-RDB boards 882 * only. The driver should go away soon, since newer MPC8323E-RDB's device 883 * tree can work with OpenFirmware driver. But for now we support old trees 884 * as well. 885 */ 886 static int plat_mpc8xxx_spi_probe(struct platform_device *pdev) 887 { 888 struct resource *mem; 889 int irq; 890 struct spi_master *master; 891 892 if (!pdev->dev.platform_data) 893 return -EINVAL; 894 895 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 896 if (!mem) 897 return -EINVAL; 898 899 irq = platform_get_irq(pdev, 0); 900 if (irq <= 0) 901 return -EINVAL; 902 903 master = fsl_spi_probe(&pdev->dev, mem, irq); 904 return PTR_RET(master); 905 } 906 907 static int plat_mpc8xxx_spi_remove(struct platform_device *pdev) 908 { 909 return mpc8xxx_spi_remove(&pdev->dev); 910 } 911 912 MODULE_ALIAS("platform:mpc8xxx_spi"); 913 static struct platform_driver mpc8xxx_spi_driver = { 914 .probe = plat_mpc8xxx_spi_probe, 915 .remove = plat_mpc8xxx_spi_remove, 916 .driver = { 917 .name = "mpc8xxx_spi", 918 .owner = THIS_MODULE, 919 }, 920 }; 921 922 static bool legacy_driver_failed; 923 924 static void __init legacy_driver_register(void) 925 { 926 legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver); 927 } 928 929 static void __exit legacy_driver_unregister(void) 930 { 931 if (legacy_driver_failed) 932 return; 933 platform_driver_unregister(&mpc8xxx_spi_driver); 934 } 935 #else 936 static void __init legacy_driver_register(void) {} 937 static void __exit legacy_driver_unregister(void) {} 938 #endif /* CONFIG_MPC832x_RDB */ 939 940 static int __init fsl_spi_init(void) 941 { 942 legacy_driver_register(); 943 return platform_driver_register(&of_fsl_spi_driver); 944 } 945 module_init(fsl_spi_init); 946 947 static void __exit fsl_spi_exit(void) 948 { 949 platform_driver_unregister(&of_fsl_spi_driver); 950 legacy_driver_unregister(); 951 } 952 module_exit(fsl_spi_exit); 953 954 MODULE_AUTHOR("Kumar Gala"); 955 MODULE_DESCRIPTION("Simple Freescale SPI Driver"); 956 MODULE_LICENSE("GPL"); 957