1 /* 2 * Freescale SPI controller driver. 3 * 4 * Maintainer: Kumar Gala 5 * 6 * Copyright (C) 2006 Polycom, Inc. 7 * Copyright 2010 Freescale Semiconductor, Inc. 8 * 9 * CPM SPI and QE buffer descriptors mode support: 10 * Copyright (c) 2009 MontaVista Software, Inc. 11 * Author: Anton Vorontsov <avorontsov@ru.mvista.com> 12 * 13 * GRLIB support: 14 * Copyright (c) 2012 Aeroflex Gaisler AB. 15 * Author: Andreas Larsson <andreas@gaisler.com> 16 * 17 * This program is free software; you can redistribute it and/or modify it 18 * under the terms of the GNU General Public License as published by the 19 * Free Software Foundation; either version 2 of the License, or (at your 20 * option) any later version. 21 */ 22 #include <linux/delay.h> 23 #include <linux/dma-mapping.h> 24 #include <linux/fsl_devices.h> 25 #include <linux/gpio.h> 26 #include <linux/interrupt.h> 27 #include <linux/irq.h> 28 #include <linux/kernel.h> 29 #include <linux/mm.h> 30 #include <linux/module.h> 31 #include <linux/mutex.h> 32 #include <linux/of.h> 33 #include <linux/of_address.h> 34 #include <linux/of_irq.h> 35 #include <linux/of_gpio.h> 36 #include <linux/of_platform.h> 37 #include <linux/platform_device.h> 38 #include <linux/spi/spi.h> 39 #include <linux/spi/spi_bitbang.h> 40 #include <linux/types.h> 41 42 #ifdef CONFIG_FSL_SOC 43 #include <sysdev/fsl_soc.h> 44 #endif 45 46 /* Specific to the MPC8306/MPC8309 */ 47 #define IMMR_SPI_CS_OFFSET 0x14c 48 #define SPI_BOOT_SEL_BIT 0x80000000 49 50 #include "spi-fsl-lib.h" 51 #include "spi-fsl-cpm.h" 52 #include "spi-fsl-spi.h" 53 54 #define TYPE_FSL 0 55 #define TYPE_GRLIB 1 56 57 struct fsl_spi_match_data { 58 int type; 59 }; 60 61 static struct fsl_spi_match_data of_fsl_spi_fsl_config = { 62 .type = TYPE_FSL, 63 }; 64 65 static struct fsl_spi_match_data of_fsl_spi_grlib_config = { 66 .type = TYPE_GRLIB, 67 }; 68 69 static const struct of_device_id of_fsl_spi_match[] = { 70 { 71 .compatible = "fsl,spi", 72 .data = &of_fsl_spi_fsl_config, 73 }, 74 { 75 .compatible = "aeroflexgaisler,spictrl", 76 .data = &of_fsl_spi_grlib_config, 77 }, 78 {} 79 }; 80 MODULE_DEVICE_TABLE(of, of_fsl_spi_match); 81 82 static int fsl_spi_get_type(struct device *dev) 83 { 84 const struct of_device_id *match; 85 86 if (dev->of_node) { 87 match = of_match_node(of_fsl_spi_match, dev->of_node); 88 if (match && match->data) 89 return ((struct fsl_spi_match_data *)match->data)->type; 90 } 91 return TYPE_FSL; 92 } 93 94 static void fsl_spi_change_mode(struct spi_device *spi) 95 { 96 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master); 97 struct spi_mpc8xxx_cs *cs = spi->controller_state; 98 struct fsl_spi_reg *reg_base = mspi->reg_base; 99 __be32 __iomem *mode = ®_base->mode; 100 unsigned long flags; 101 102 if (cs->hw_mode == mpc8xxx_spi_read_reg(mode)) 103 return; 104 105 /* Turn off IRQs locally to minimize time that SPI is disabled. */ 106 local_irq_save(flags); 107 108 /* Turn off SPI unit prior changing mode */ 109 mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE); 110 111 /* When in CPM mode, we need to reinit tx and rx. */ 112 if (mspi->flags & SPI_CPM_MODE) { 113 fsl_spi_cpm_reinit_txrx(mspi); 114 } 115 mpc8xxx_spi_write_reg(mode, cs->hw_mode); 116 local_irq_restore(flags); 117 } 118 119 static void fsl_spi_chipselect(struct spi_device *spi, int value) 120 { 121 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); 122 struct fsl_spi_platform_data *pdata; 123 bool pol = spi->mode & SPI_CS_HIGH; 124 struct spi_mpc8xxx_cs *cs = spi->controller_state; 125 126 pdata = spi->dev.parent->parent->platform_data; 127 128 if (value == BITBANG_CS_INACTIVE) { 129 if (pdata->cs_control) 130 pdata->cs_control(spi, !pol); 131 } 132 133 if (value == BITBANG_CS_ACTIVE) { 134 mpc8xxx_spi->rx_shift = cs->rx_shift; 135 mpc8xxx_spi->tx_shift = cs->tx_shift; 136 mpc8xxx_spi->get_rx = cs->get_rx; 137 mpc8xxx_spi->get_tx = cs->get_tx; 138 139 fsl_spi_change_mode(spi); 140 141 if (pdata->cs_control) 142 pdata->cs_control(spi, pol); 143 } 144 } 145 146 static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift, 147 int bits_per_word, int msb_first) 148 { 149 *rx_shift = 0; 150 *tx_shift = 0; 151 if (msb_first) { 152 if (bits_per_word <= 8) { 153 *rx_shift = 16; 154 *tx_shift = 24; 155 } else if (bits_per_word <= 16) { 156 *rx_shift = 16; 157 *tx_shift = 16; 158 } 159 } else { 160 if (bits_per_word <= 8) 161 *rx_shift = 8; 162 } 163 } 164 165 static void fsl_spi_grlib_set_shifts(u32 *rx_shift, u32 *tx_shift, 166 int bits_per_word, int msb_first) 167 { 168 *rx_shift = 0; 169 *tx_shift = 0; 170 if (bits_per_word <= 16) { 171 if (msb_first) { 172 *rx_shift = 16; /* LSB in bit 16 */ 173 *tx_shift = 32 - bits_per_word; /* MSB in bit 31 */ 174 } else { 175 *rx_shift = 16 - bits_per_word; /* MSB in bit 15 */ 176 } 177 } 178 } 179 180 static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs, 181 struct spi_device *spi, 182 struct mpc8xxx_spi *mpc8xxx_spi, 183 int bits_per_word) 184 { 185 cs->rx_shift = 0; 186 cs->tx_shift = 0; 187 if (bits_per_word <= 8) { 188 cs->get_rx = mpc8xxx_spi_rx_buf_u8; 189 cs->get_tx = mpc8xxx_spi_tx_buf_u8; 190 } else if (bits_per_word <= 16) { 191 cs->get_rx = mpc8xxx_spi_rx_buf_u16; 192 cs->get_tx = mpc8xxx_spi_tx_buf_u16; 193 } else if (bits_per_word <= 32) { 194 cs->get_rx = mpc8xxx_spi_rx_buf_u32; 195 cs->get_tx = mpc8xxx_spi_tx_buf_u32; 196 } else 197 return -EINVAL; 198 199 if (mpc8xxx_spi->set_shifts) 200 mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift, 201 bits_per_word, 202 !(spi->mode & SPI_LSB_FIRST)); 203 204 mpc8xxx_spi->rx_shift = cs->rx_shift; 205 mpc8xxx_spi->tx_shift = cs->tx_shift; 206 mpc8xxx_spi->get_rx = cs->get_rx; 207 mpc8xxx_spi->get_tx = cs->get_tx; 208 209 return bits_per_word; 210 } 211 212 static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs, 213 struct spi_device *spi, 214 int bits_per_word) 215 { 216 /* QE uses Little Endian for words > 8 217 * so transform all words > 8 into 8 bits 218 * Unfortnatly that doesn't work for LSB so 219 * reject these for now */ 220 /* Note: 32 bits word, LSB works iff 221 * tfcr/rfcr is set to CPMFCR_GBL */ 222 if (spi->mode & SPI_LSB_FIRST && 223 bits_per_word > 8) 224 return -EINVAL; 225 if (bits_per_word > 8) 226 return 8; /* pretend its 8 bits */ 227 return bits_per_word; 228 } 229 230 static int fsl_spi_setup_transfer(struct spi_device *spi, 231 struct spi_transfer *t) 232 { 233 struct mpc8xxx_spi *mpc8xxx_spi; 234 int bits_per_word = 0; 235 u8 pm; 236 u32 hz = 0; 237 struct spi_mpc8xxx_cs *cs = spi->controller_state; 238 239 mpc8xxx_spi = spi_master_get_devdata(spi->master); 240 241 if (t) { 242 bits_per_word = t->bits_per_word; 243 hz = t->speed_hz; 244 } 245 246 /* spi_transfer level calls that work per-word */ 247 if (!bits_per_word) 248 bits_per_word = spi->bits_per_word; 249 250 if (!hz) 251 hz = spi->max_speed_hz; 252 253 if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) 254 bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi, 255 mpc8xxx_spi, 256 bits_per_word); 257 else if (mpc8xxx_spi->flags & SPI_QE) 258 bits_per_word = mspi_apply_qe_mode_quirks(cs, spi, 259 bits_per_word); 260 261 if (bits_per_word < 0) 262 return bits_per_word; 263 264 if (bits_per_word == 32) 265 bits_per_word = 0; 266 else 267 bits_per_word = bits_per_word - 1; 268 269 /* mask out bits we are going to set */ 270 cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16 271 | SPMODE_PM(0xF)); 272 273 cs->hw_mode |= SPMODE_LEN(bits_per_word); 274 275 if ((mpc8xxx_spi->spibrg / hz) > 64) { 276 cs->hw_mode |= SPMODE_DIV16; 277 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1; 278 WARN_ONCE(pm > 16, 279 "%s: Requested speed is too low: %d Hz. Will use %d Hz instead.\n", 280 dev_name(&spi->dev), hz, mpc8xxx_spi->spibrg / 1024); 281 if (pm > 16) 282 pm = 16; 283 } else { 284 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1; 285 } 286 if (pm) 287 pm--; 288 289 cs->hw_mode |= SPMODE_PM(pm); 290 291 fsl_spi_change_mode(spi); 292 return 0; 293 } 294 295 static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi, 296 struct spi_transfer *t, unsigned int len) 297 { 298 u32 word; 299 struct fsl_spi_reg *reg_base = mspi->reg_base; 300 301 mspi->count = len; 302 303 /* enable rx ints */ 304 mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE); 305 306 /* transmit word */ 307 word = mspi->get_tx(mspi); 308 mpc8xxx_spi_write_reg(®_base->transmit, word); 309 310 return 0; 311 } 312 313 static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t, 314 bool is_dma_mapped) 315 { 316 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); 317 struct fsl_spi_reg *reg_base; 318 unsigned int len = t->len; 319 u8 bits_per_word; 320 int ret; 321 322 reg_base = mpc8xxx_spi->reg_base; 323 bits_per_word = spi->bits_per_word; 324 if (t->bits_per_word) 325 bits_per_word = t->bits_per_word; 326 327 if (bits_per_word > 8) { 328 /* invalid length? */ 329 if (len & 1) 330 return -EINVAL; 331 len /= 2; 332 } 333 if (bits_per_word > 16) { 334 /* invalid length? */ 335 if (len & 1) 336 return -EINVAL; 337 len /= 2; 338 } 339 340 mpc8xxx_spi->tx = t->tx_buf; 341 mpc8xxx_spi->rx = t->rx_buf; 342 343 reinit_completion(&mpc8xxx_spi->done); 344 345 if (mpc8xxx_spi->flags & SPI_CPM_MODE) 346 ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped); 347 else 348 ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len); 349 if (ret) 350 return ret; 351 352 wait_for_completion(&mpc8xxx_spi->done); 353 354 /* disable rx ints */ 355 mpc8xxx_spi_write_reg(®_base->mask, 0); 356 357 if (mpc8xxx_spi->flags & SPI_CPM_MODE) 358 fsl_spi_cpm_bufs_complete(mpc8xxx_spi); 359 360 return mpc8xxx_spi->count; 361 } 362 363 static int fsl_spi_do_one_msg(struct spi_master *master, 364 struct spi_message *m) 365 { 366 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); 367 struct spi_device *spi = m->spi; 368 struct spi_transfer *t, *first; 369 unsigned int cs_change; 370 const int nsecs = 50; 371 int status, last_bpw; 372 373 /* 374 * In CPU mode, optimize large byte transfers to use larger 375 * bits_per_word values to reduce number of interrupts taken. 376 */ 377 if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) { 378 list_for_each_entry(t, &m->transfers, transfer_list) { 379 if (t->len < 256 || t->bits_per_word != 8) 380 continue; 381 if ((t->len & 3) == 0) 382 t->bits_per_word = 32; 383 else if ((t->len & 1) == 0) 384 t->bits_per_word = 16; 385 } 386 } 387 388 /* Don't allow changes if CS is active */ 389 cs_change = 1; 390 list_for_each_entry(t, &m->transfers, transfer_list) { 391 if (cs_change) 392 first = t; 393 cs_change = t->cs_change; 394 if (first->speed_hz != t->speed_hz) { 395 dev_err(&spi->dev, 396 "speed_hz cannot change while CS is active\n"); 397 return -EINVAL; 398 } 399 } 400 401 last_bpw = -1; 402 cs_change = 1; 403 status = -EINVAL; 404 list_for_each_entry(t, &m->transfers, transfer_list) { 405 if (cs_change || last_bpw != t->bits_per_word) 406 status = fsl_spi_setup_transfer(spi, t); 407 if (status < 0) 408 break; 409 last_bpw = t->bits_per_word; 410 411 if (cs_change) { 412 fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE); 413 ndelay(nsecs); 414 } 415 cs_change = t->cs_change; 416 if (t->len) 417 status = fsl_spi_bufs(spi, t, m->is_dma_mapped); 418 if (status) { 419 status = -EMSGSIZE; 420 break; 421 } 422 m->actual_length += t->len; 423 424 if (t->delay_usecs) 425 udelay(t->delay_usecs); 426 427 if (cs_change) { 428 ndelay(nsecs); 429 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); 430 ndelay(nsecs); 431 } 432 } 433 434 m->status = status; 435 spi_finalize_current_message(master); 436 437 if (status || !cs_change) { 438 ndelay(nsecs); 439 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); 440 } 441 442 fsl_spi_setup_transfer(spi, NULL); 443 return 0; 444 } 445 446 static int fsl_spi_setup(struct spi_device *spi) 447 { 448 struct mpc8xxx_spi *mpc8xxx_spi; 449 struct fsl_spi_reg *reg_base; 450 int retval; 451 u32 hw_mode; 452 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); 453 454 if (!spi->max_speed_hz) 455 return -EINVAL; 456 457 if (!cs) { 458 cs = kzalloc(sizeof(*cs), GFP_KERNEL); 459 if (!cs) 460 return -ENOMEM; 461 spi_set_ctldata(spi, cs); 462 } 463 mpc8xxx_spi = spi_master_get_devdata(spi->master); 464 465 reg_base = mpc8xxx_spi->reg_base; 466 467 hw_mode = cs->hw_mode; /* Save original settings */ 468 cs->hw_mode = mpc8xxx_spi_read_reg(®_base->mode); 469 /* mask out bits we are going to set */ 470 cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH 471 | SPMODE_REV | SPMODE_LOOP); 472 473 if (spi->mode & SPI_CPHA) 474 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK; 475 if (spi->mode & SPI_CPOL) 476 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH; 477 if (!(spi->mode & SPI_LSB_FIRST)) 478 cs->hw_mode |= SPMODE_REV; 479 if (spi->mode & SPI_LOOP) 480 cs->hw_mode |= SPMODE_LOOP; 481 482 retval = fsl_spi_setup_transfer(spi, NULL); 483 if (retval < 0) { 484 cs->hw_mode = hw_mode; /* Restore settings */ 485 return retval; 486 } 487 488 if (mpc8xxx_spi->type == TYPE_GRLIB) { 489 if (gpio_is_valid(spi->cs_gpio)) { 490 int desel; 491 492 retval = gpio_request(spi->cs_gpio, 493 dev_name(&spi->dev)); 494 if (retval) 495 return retval; 496 497 desel = !(spi->mode & SPI_CS_HIGH); 498 retval = gpio_direction_output(spi->cs_gpio, desel); 499 if (retval) { 500 gpio_free(spi->cs_gpio); 501 return retval; 502 } 503 } else if (spi->cs_gpio != -ENOENT) { 504 if (spi->cs_gpio < 0) 505 return spi->cs_gpio; 506 return -EINVAL; 507 } 508 /* When spi->cs_gpio == -ENOENT, a hole in the phandle list 509 * indicates to use native chipselect if present, or allow for 510 * an always selected chip 511 */ 512 } 513 514 /* Initialize chipselect - might be active for SPI_CS_HIGH mode */ 515 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); 516 517 return 0; 518 } 519 520 static void fsl_spi_cleanup(struct spi_device *spi) 521 { 522 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); 523 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); 524 525 if (mpc8xxx_spi->type == TYPE_GRLIB && gpio_is_valid(spi->cs_gpio)) 526 gpio_free(spi->cs_gpio); 527 528 kfree(cs); 529 spi_set_ctldata(spi, NULL); 530 } 531 532 static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) 533 { 534 struct fsl_spi_reg *reg_base = mspi->reg_base; 535 536 /* We need handle RX first */ 537 if (events & SPIE_NE) { 538 u32 rx_data = mpc8xxx_spi_read_reg(®_base->receive); 539 540 if (mspi->rx) 541 mspi->get_rx(rx_data, mspi); 542 } 543 544 if ((events & SPIE_NF) == 0) 545 /* spin until TX is done */ 546 while (((events = 547 mpc8xxx_spi_read_reg(®_base->event)) & 548 SPIE_NF) == 0) 549 cpu_relax(); 550 551 /* Clear the events */ 552 mpc8xxx_spi_write_reg(®_base->event, events); 553 554 mspi->count -= 1; 555 if (mspi->count) { 556 u32 word = mspi->get_tx(mspi); 557 558 mpc8xxx_spi_write_reg(®_base->transmit, word); 559 } else { 560 complete(&mspi->done); 561 } 562 } 563 564 static irqreturn_t fsl_spi_irq(s32 irq, void *context_data) 565 { 566 struct mpc8xxx_spi *mspi = context_data; 567 irqreturn_t ret = IRQ_NONE; 568 u32 events; 569 struct fsl_spi_reg *reg_base = mspi->reg_base; 570 571 /* Get interrupt events(tx/rx) */ 572 events = mpc8xxx_spi_read_reg(®_base->event); 573 if (events) 574 ret = IRQ_HANDLED; 575 576 dev_dbg(mspi->dev, "%s: events %x\n", __func__, events); 577 578 if (mspi->flags & SPI_CPM_MODE) 579 fsl_spi_cpm_irq(mspi, events); 580 else 581 fsl_spi_cpu_irq(mspi, events); 582 583 return ret; 584 } 585 586 static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on) 587 { 588 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); 589 struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base; 590 u32 slvsel; 591 u16 cs = spi->chip_select; 592 593 if (gpio_is_valid(spi->cs_gpio)) { 594 gpio_set_value(spi->cs_gpio, on); 595 } else if (cs < mpc8xxx_spi->native_chipselects) { 596 slvsel = mpc8xxx_spi_read_reg(®_base->slvsel); 597 slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs)); 598 mpc8xxx_spi_write_reg(®_base->slvsel, slvsel); 599 } 600 } 601 602 static void fsl_spi_grlib_probe(struct device *dev) 603 { 604 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); 605 struct spi_master *master = dev_get_drvdata(dev); 606 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); 607 struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base; 608 int mbits; 609 u32 capabilities; 610 611 capabilities = mpc8xxx_spi_read_reg(®_base->cap); 612 613 mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts; 614 mbits = SPCAP_MAXWLEN(capabilities); 615 if (mbits) 616 mpc8xxx_spi->max_bits_per_word = mbits + 1; 617 618 mpc8xxx_spi->native_chipselects = 0; 619 if (SPCAP_SSEN(capabilities)) { 620 mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities); 621 mpc8xxx_spi_write_reg(®_base->slvsel, 0xffffffff); 622 } 623 master->num_chipselect = mpc8xxx_spi->native_chipselects; 624 pdata->cs_control = fsl_spi_grlib_cs_control; 625 } 626 627 static struct spi_master * fsl_spi_probe(struct device *dev, 628 struct resource *mem, unsigned int irq) 629 { 630 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); 631 struct spi_master *master; 632 struct mpc8xxx_spi *mpc8xxx_spi; 633 struct fsl_spi_reg *reg_base; 634 u32 regval; 635 int ret = 0; 636 637 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi)); 638 if (master == NULL) { 639 ret = -ENOMEM; 640 goto err; 641 } 642 643 dev_set_drvdata(dev, master); 644 645 mpc8xxx_spi_probe(dev, mem, irq); 646 647 master->setup = fsl_spi_setup; 648 master->cleanup = fsl_spi_cleanup; 649 master->transfer_one_message = fsl_spi_do_one_msg; 650 651 mpc8xxx_spi = spi_master_get_devdata(master); 652 mpc8xxx_spi->max_bits_per_word = 32; 653 mpc8xxx_spi->type = fsl_spi_get_type(dev); 654 655 ret = fsl_spi_cpm_init(mpc8xxx_spi); 656 if (ret) 657 goto err_cpm_init; 658 659 mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem); 660 if (IS_ERR(mpc8xxx_spi->reg_base)) { 661 ret = PTR_ERR(mpc8xxx_spi->reg_base); 662 goto err_probe; 663 } 664 665 if (mpc8xxx_spi->type == TYPE_GRLIB) 666 fsl_spi_grlib_probe(dev); 667 668 master->bits_per_word_mask = 669 (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)) & 670 SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word); 671 672 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) 673 mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts; 674 675 if (mpc8xxx_spi->set_shifts) 676 /* 8 bits per word and MSB first */ 677 mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift, 678 &mpc8xxx_spi->tx_shift, 8, 1); 679 680 /* Register for SPI Interrupt */ 681 ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_spi_irq, 682 0, "fsl_spi", mpc8xxx_spi); 683 684 if (ret != 0) 685 goto err_probe; 686 687 reg_base = mpc8xxx_spi->reg_base; 688 689 /* SPI controller initializations */ 690 mpc8xxx_spi_write_reg(®_base->mode, 0); 691 mpc8xxx_spi_write_reg(®_base->mask, 0); 692 mpc8xxx_spi_write_reg(®_base->command, 0); 693 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff); 694 695 /* Enable SPI interface */ 696 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; 697 if (mpc8xxx_spi->max_bits_per_word < 8) { 698 regval &= ~SPMODE_LEN(0xF); 699 regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1); 700 } 701 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) 702 regval |= SPMODE_OP; 703 704 mpc8xxx_spi_write_reg(®_base->mode, regval); 705 706 ret = devm_spi_register_master(dev, master); 707 if (ret < 0) 708 goto err_probe; 709 710 dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base, 711 mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags)); 712 713 return master; 714 715 err_probe: 716 fsl_spi_cpm_free(mpc8xxx_spi); 717 err_cpm_init: 718 spi_master_put(master); 719 err: 720 return ERR_PTR(ret); 721 } 722 723 static void fsl_spi_cs_control(struct spi_device *spi, bool on) 724 { 725 struct device *dev = spi->dev.parent->parent; 726 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); 727 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); 728 u16 cs = spi->chip_select; 729 730 if (cs < pinfo->ngpios) { 731 int gpio = pinfo->gpios[cs]; 732 bool alow = pinfo->alow_flags[cs]; 733 734 gpio_set_value(gpio, on ^ alow); 735 } else { 736 if (WARN_ON_ONCE(cs > pinfo->ngpios || !pinfo->immr_spi_cs)) 737 return; 738 iowrite32be(on ? SPI_BOOT_SEL_BIT : 0, pinfo->immr_spi_cs); 739 } 740 } 741 742 static int of_fsl_spi_get_chipselects(struct device *dev) 743 { 744 struct device_node *np = dev->of_node; 745 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); 746 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); 747 bool spisel_boot = IS_ENABLED(CONFIG_FSL_SOC) && 748 of_property_read_bool(np, "fsl,spisel_boot"); 749 int ngpios; 750 int i = 0; 751 int ret; 752 753 ngpios = of_gpio_count(np); 754 ngpios = max(ngpios, 0); 755 if (ngpios == 0 && !spisel_boot) { 756 /* 757 * SPI w/o chip-select line. One SPI device is still permitted 758 * though. 759 */ 760 pdata->max_chipselect = 1; 761 return 0; 762 } 763 764 pinfo->ngpios = ngpios; 765 pinfo->gpios = kmalloc_array(ngpios, sizeof(*pinfo->gpios), 766 GFP_KERNEL); 767 if (!pinfo->gpios) 768 return -ENOMEM; 769 memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios)); 770 771 pinfo->alow_flags = kcalloc(ngpios, sizeof(*pinfo->alow_flags), 772 GFP_KERNEL); 773 if (!pinfo->alow_flags) { 774 ret = -ENOMEM; 775 goto err_alloc_flags; 776 } 777 778 for (; i < ngpios; i++) { 779 int gpio; 780 enum of_gpio_flags flags; 781 782 gpio = of_get_gpio_flags(np, i, &flags); 783 if (!gpio_is_valid(gpio)) { 784 dev_err(dev, "invalid gpio #%d: %d\n", i, gpio); 785 ret = gpio; 786 goto err_loop; 787 } 788 789 ret = gpio_request(gpio, dev_name(dev)); 790 if (ret) { 791 dev_err(dev, "can't request gpio #%d: %d\n", i, ret); 792 goto err_loop; 793 } 794 795 pinfo->gpios[i] = gpio; 796 pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW; 797 798 ret = gpio_direction_output(pinfo->gpios[i], 799 pinfo->alow_flags[i]); 800 if (ret) { 801 dev_err(dev, 802 "can't set output direction for gpio #%d: %d\n", 803 i, ret); 804 goto err_loop; 805 } 806 } 807 808 #if IS_ENABLED(CONFIG_FSL_SOC) 809 if (spisel_boot) { 810 pinfo->immr_spi_cs = ioremap(get_immrbase() + IMMR_SPI_CS_OFFSET, 4); 811 if (!pinfo->immr_spi_cs) { 812 ret = -ENOMEM; 813 i = ngpios - 1; 814 goto err_loop; 815 } 816 } 817 #endif 818 819 pdata->max_chipselect = ngpios + spisel_boot; 820 pdata->cs_control = fsl_spi_cs_control; 821 822 return 0; 823 824 err_loop: 825 while (i >= 0) { 826 if (gpio_is_valid(pinfo->gpios[i])) 827 gpio_free(pinfo->gpios[i]); 828 i--; 829 } 830 831 kfree(pinfo->alow_flags); 832 pinfo->alow_flags = NULL; 833 err_alloc_flags: 834 kfree(pinfo->gpios); 835 pinfo->gpios = NULL; 836 return ret; 837 } 838 839 static int of_fsl_spi_free_chipselects(struct device *dev) 840 { 841 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); 842 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); 843 int i; 844 845 if (!pinfo->gpios) 846 return 0; 847 848 for (i = 0; i < pdata->max_chipselect; i++) { 849 if (gpio_is_valid(pinfo->gpios[i])) 850 gpio_free(pinfo->gpios[i]); 851 } 852 853 kfree(pinfo->gpios); 854 kfree(pinfo->alow_flags); 855 return 0; 856 } 857 858 static int of_fsl_spi_probe(struct platform_device *ofdev) 859 { 860 struct device *dev = &ofdev->dev; 861 struct device_node *np = ofdev->dev.of_node; 862 struct spi_master *master; 863 struct resource mem; 864 int irq = 0, type; 865 int ret = -ENOMEM; 866 867 ret = of_mpc8xxx_spi_probe(ofdev); 868 if (ret) 869 return ret; 870 871 type = fsl_spi_get_type(&ofdev->dev); 872 if (type == TYPE_FSL) { 873 ret = of_fsl_spi_get_chipselects(dev); 874 if (ret) 875 goto err; 876 } 877 878 ret = of_address_to_resource(np, 0, &mem); 879 if (ret) 880 goto err; 881 882 irq = irq_of_parse_and_map(np, 0); 883 if (!irq) { 884 ret = -EINVAL; 885 goto err; 886 } 887 888 master = fsl_spi_probe(dev, &mem, irq); 889 if (IS_ERR(master)) { 890 ret = PTR_ERR(master); 891 goto err; 892 } 893 894 return 0; 895 896 err: 897 irq_dispose_mapping(irq); 898 if (type == TYPE_FSL) 899 of_fsl_spi_free_chipselects(dev); 900 return ret; 901 } 902 903 static int of_fsl_spi_remove(struct platform_device *ofdev) 904 { 905 struct spi_master *master = platform_get_drvdata(ofdev); 906 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); 907 908 fsl_spi_cpm_free(mpc8xxx_spi); 909 if (mpc8xxx_spi->type == TYPE_FSL) 910 of_fsl_spi_free_chipselects(&ofdev->dev); 911 return 0; 912 } 913 914 static struct platform_driver of_fsl_spi_driver = { 915 .driver = { 916 .name = "fsl_spi", 917 .of_match_table = of_fsl_spi_match, 918 }, 919 .probe = of_fsl_spi_probe, 920 .remove = of_fsl_spi_remove, 921 }; 922 923 #ifdef CONFIG_MPC832x_RDB 924 /* 925 * XXX XXX XXX 926 * This is "legacy" platform driver, was used by the MPC8323E-RDB boards 927 * only. The driver should go away soon, since newer MPC8323E-RDB's device 928 * tree can work with OpenFirmware driver. But for now we support old trees 929 * as well. 930 */ 931 static int plat_mpc8xxx_spi_probe(struct platform_device *pdev) 932 { 933 struct resource *mem; 934 int irq; 935 struct spi_master *master; 936 937 if (!dev_get_platdata(&pdev->dev)) 938 return -EINVAL; 939 940 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 941 if (!mem) 942 return -EINVAL; 943 944 irq = platform_get_irq(pdev, 0); 945 if (irq <= 0) 946 return -EINVAL; 947 948 master = fsl_spi_probe(&pdev->dev, mem, irq); 949 return PTR_ERR_OR_ZERO(master); 950 } 951 952 static int plat_mpc8xxx_spi_remove(struct platform_device *pdev) 953 { 954 struct spi_master *master = platform_get_drvdata(pdev); 955 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); 956 957 fsl_spi_cpm_free(mpc8xxx_spi); 958 959 return 0; 960 } 961 962 MODULE_ALIAS("platform:mpc8xxx_spi"); 963 static struct platform_driver mpc8xxx_spi_driver = { 964 .probe = plat_mpc8xxx_spi_probe, 965 .remove = plat_mpc8xxx_spi_remove, 966 .driver = { 967 .name = "mpc8xxx_spi", 968 }, 969 }; 970 971 static bool legacy_driver_failed; 972 973 static void __init legacy_driver_register(void) 974 { 975 legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver); 976 } 977 978 static void __exit legacy_driver_unregister(void) 979 { 980 if (legacy_driver_failed) 981 return; 982 platform_driver_unregister(&mpc8xxx_spi_driver); 983 } 984 #else 985 static void __init legacy_driver_register(void) {} 986 static void __exit legacy_driver_unregister(void) {} 987 #endif /* CONFIG_MPC832x_RDB */ 988 989 static int __init fsl_spi_init(void) 990 { 991 legacy_driver_register(); 992 return platform_driver_register(&of_fsl_spi_driver); 993 } 994 module_init(fsl_spi_init); 995 996 static void __exit fsl_spi_exit(void) 997 { 998 platform_driver_unregister(&of_fsl_spi_driver); 999 legacy_driver_unregister(); 1000 } 1001 module_exit(fsl_spi_exit); 1002 1003 MODULE_AUTHOR("Kumar Gala"); 1004 MODULE_DESCRIPTION("Simple Freescale SPI Driver"); 1005 MODULE_LICENSE("GPL"); 1006