1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Freescale i.MX7ULP LPSPI driver 4 // 5 // Copyright 2016 Freescale Semiconductor, Inc. 6 // Copyright 2018 NXP Semiconductors 7 8 #include <linux/clk.h> 9 #include <linux/completion.h> 10 #include <linux/delay.h> 11 #include <linux/err.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/irq.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/of_device.h> 19 #include <linux/platform_device.h> 20 #include <linux/slab.h> 21 #include <linux/spi/spi.h> 22 #include <linux/spi/spi_bitbang.h> 23 #include <linux/types.h> 24 25 #define DRIVER_NAME "fsl_lpspi" 26 27 /* i.MX7ULP LPSPI registers */ 28 #define IMX7ULP_VERID 0x0 29 #define IMX7ULP_PARAM 0x4 30 #define IMX7ULP_CR 0x10 31 #define IMX7ULP_SR 0x14 32 #define IMX7ULP_IER 0x18 33 #define IMX7ULP_DER 0x1c 34 #define IMX7ULP_CFGR0 0x20 35 #define IMX7ULP_CFGR1 0x24 36 #define IMX7ULP_DMR0 0x30 37 #define IMX7ULP_DMR1 0x34 38 #define IMX7ULP_CCR 0x40 39 #define IMX7ULP_FCR 0x58 40 #define IMX7ULP_FSR 0x5c 41 #define IMX7ULP_TCR 0x60 42 #define IMX7ULP_TDR 0x64 43 #define IMX7ULP_RSR 0x70 44 #define IMX7ULP_RDR 0x74 45 46 /* General control register field define */ 47 #define CR_RRF BIT(9) 48 #define CR_RTF BIT(8) 49 #define CR_RST BIT(1) 50 #define CR_MEN BIT(0) 51 #define SR_TCF BIT(10) 52 #define SR_RDF BIT(1) 53 #define SR_TDF BIT(0) 54 #define IER_TCIE BIT(10) 55 #define IER_RDIE BIT(1) 56 #define IER_TDIE BIT(0) 57 #define CFGR1_PCSCFG BIT(27) 58 #define CFGR1_PINCFG (BIT(24)|BIT(25)) 59 #define CFGR1_PCSPOL BIT(8) 60 #define CFGR1_NOSTALL BIT(3) 61 #define CFGR1_MASTER BIT(0) 62 #define RSR_RXEMPTY BIT(1) 63 #define TCR_CPOL BIT(31) 64 #define TCR_CPHA BIT(30) 65 #define TCR_CONT BIT(21) 66 #define TCR_CONTC BIT(20) 67 #define TCR_RXMSK BIT(19) 68 #define TCR_TXMSK BIT(18) 69 70 static int clkdivs[] = {1, 2, 4, 8, 16, 32, 64, 128}; 71 72 struct lpspi_config { 73 u8 bpw; 74 u8 chip_select; 75 u8 prescale; 76 u16 mode; 77 u32 speed_hz; 78 }; 79 80 struct fsl_lpspi_data { 81 struct device *dev; 82 void __iomem *base; 83 struct clk *clk; 84 bool is_slave; 85 86 void *rx_buf; 87 const void *tx_buf; 88 void (*tx)(struct fsl_lpspi_data *); 89 void (*rx)(struct fsl_lpspi_data *); 90 91 u32 remain; 92 u8 watermark; 93 u8 txfifosize; 94 u8 rxfifosize; 95 96 struct lpspi_config config; 97 struct completion xfer_done; 98 99 bool slave_aborted; 100 }; 101 102 static const struct of_device_id fsl_lpspi_dt_ids[] = { 103 { .compatible = "fsl,imx7ulp-spi", }, 104 { /* sentinel */ } 105 }; 106 MODULE_DEVICE_TABLE(of, fsl_lpspi_dt_ids); 107 108 #define LPSPI_BUF_RX(type) \ 109 static void fsl_lpspi_buf_rx_##type(struct fsl_lpspi_data *fsl_lpspi) \ 110 { \ 111 unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR); \ 112 \ 113 if (fsl_lpspi->rx_buf) { \ 114 *(type *)fsl_lpspi->rx_buf = val; \ 115 fsl_lpspi->rx_buf += sizeof(type); \ 116 } \ 117 } 118 119 #define LPSPI_BUF_TX(type) \ 120 static void fsl_lpspi_buf_tx_##type(struct fsl_lpspi_data *fsl_lpspi) \ 121 { \ 122 type val = 0; \ 123 \ 124 if (fsl_lpspi->tx_buf) { \ 125 val = *(type *)fsl_lpspi->tx_buf; \ 126 fsl_lpspi->tx_buf += sizeof(type); \ 127 } \ 128 \ 129 fsl_lpspi->remain -= sizeof(type); \ 130 writel(val, fsl_lpspi->base + IMX7ULP_TDR); \ 131 } 132 133 LPSPI_BUF_RX(u8) 134 LPSPI_BUF_TX(u8) 135 LPSPI_BUF_RX(u16) 136 LPSPI_BUF_TX(u16) 137 LPSPI_BUF_RX(u32) 138 LPSPI_BUF_TX(u32) 139 140 static void fsl_lpspi_intctrl(struct fsl_lpspi_data *fsl_lpspi, 141 unsigned int enable) 142 { 143 writel(enable, fsl_lpspi->base + IMX7ULP_IER); 144 } 145 146 static int lpspi_prepare_xfer_hardware(struct spi_controller *controller) 147 { 148 struct fsl_lpspi_data *fsl_lpspi = 149 spi_controller_get_devdata(controller); 150 151 return clk_prepare_enable(fsl_lpspi->clk); 152 } 153 154 static int lpspi_unprepare_xfer_hardware(struct spi_controller *controller) 155 { 156 struct fsl_lpspi_data *fsl_lpspi = 157 spi_controller_get_devdata(controller); 158 159 clk_disable_unprepare(fsl_lpspi->clk); 160 161 return 0; 162 } 163 164 static int fsl_lpspi_txfifo_empty(struct fsl_lpspi_data *fsl_lpspi) 165 { 166 u32 txcnt; 167 unsigned long orig_jiffies = jiffies; 168 169 do { 170 txcnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff; 171 172 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { 173 dev_dbg(fsl_lpspi->dev, "txfifo empty timeout\n"); 174 return -ETIMEDOUT; 175 } 176 cond_resched(); 177 178 } while (txcnt); 179 180 return 0; 181 } 182 183 static void fsl_lpspi_write_tx_fifo(struct fsl_lpspi_data *fsl_lpspi) 184 { 185 u8 txfifo_cnt; 186 187 txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff; 188 189 while (txfifo_cnt < fsl_lpspi->txfifosize) { 190 if (!fsl_lpspi->remain) 191 break; 192 fsl_lpspi->tx(fsl_lpspi); 193 txfifo_cnt++; 194 } 195 196 if (!fsl_lpspi->remain && (txfifo_cnt < fsl_lpspi->txfifosize)) 197 writel(0, fsl_lpspi->base + IMX7ULP_TDR); 198 else 199 fsl_lpspi_intctrl(fsl_lpspi, IER_TDIE); 200 } 201 202 static void fsl_lpspi_read_rx_fifo(struct fsl_lpspi_data *fsl_lpspi) 203 { 204 while (!(readl(fsl_lpspi->base + IMX7ULP_RSR) & RSR_RXEMPTY)) 205 fsl_lpspi->rx(fsl_lpspi); 206 } 207 208 static void fsl_lpspi_set_cmd(struct fsl_lpspi_data *fsl_lpspi, 209 bool is_first_xfer) 210 { 211 u32 temp = 0; 212 213 temp |= fsl_lpspi->config.bpw - 1; 214 temp |= (fsl_lpspi->config.mode & 0x3) << 30; 215 if (!fsl_lpspi->is_slave) { 216 temp |= fsl_lpspi->config.prescale << 27; 217 temp |= (fsl_lpspi->config.chip_select & 0x3) << 24; 218 219 /* 220 * Set TCR_CONT will keep SS asserted after current transfer. 221 * For the first transfer, clear TCR_CONTC to assert SS. 222 * For subsequent transfer, set TCR_CONTC to keep SS asserted. 223 */ 224 temp |= TCR_CONT; 225 if (is_first_xfer) 226 temp &= ~TCR_CONTC; 227 else 228 temp |= TCR_CONTC; 229 } 230 writel(temp, fsl_lpspi->base + IMX7ULP_TCR); 231 232 dev_dbg(fsl_lpspi->dev, "TCR=0x%x\n", temp); 233 } 234 235 static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi) 236 { 237 u32 temp; 238 239 temp = fsl_lpspi->watermark >> 1 | (fsl_lpspi->watermark >> 1) << 16; 240 241 writel(temp, fsl_lpspi->base + IMX7ULP_FCR); 242 243 dev_dbg(fsl_lpspi->dev, "FCR=0x%x\n", temp); 244 } 245 246 static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi) 247 { 248 struct lpspi_config config = fsl_lpspi->config; 249 unsigned int perclk_rate, scldiv; 250 u8 prescale; 251 252 perclk_rate = clk_get_rate(fsl_lpspi->clk); 253 for (prescale = 0; prescale < 8; prescale++) { 254 scldiv = perclk_rate / 255 (clkdivs[prescale] * config.speed_hz) - 2; 256 if (scldiv < 256) { 257 fsl_lpspi->config.prescale = prescale; 258 break; 259 } 260 } 261 262 if (prescale == 8 && scldiv >= 256) 263 return -EINVAL; 264 265 writel(scldiv | (scldiv << 8) | ((scldiv >> 1) << 16), 266 fsl_lpspi->base + IMX7ULP_CCR); 267 268 dev_dbg(fsl_lpspi->dev, "perclk=%d, speed=%d, prescale =%d, scldiv=%d\n", 269 perclk_rate, config.speed_hz, prescale, scldiv); 270 271 return 0; 272 } 273 274 static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi) 275 { 276 u32 temp; 277 int ret; 278 279 temp = CR_RST; 280 writel(temp, fsl_lpspi->base + IMX7ULP_CR); 281 writel(0, fsl_lpspi->base + IMX7ULP_CR); 282 283 if (!fsl_lpspi->is_slave) { 284 ret = fsl_lpspi_set_bitrate(fsl_lpspi); 285 if (ret) 286 return ret; 287 } 288 289 fsl_lpspi_set_watermark(fsl_lpspi); 290 291 if (!fsl_lpspi->is_slave) 292 temp = CFGR1_MASTER; 293 else 294 temp = CFGR1_PINCFG; 295 if (fsl_lpspi->config.mode & SPI_CS_HIGH) 296 temp |= CFGR1_PCSPOL; 297 writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1); 298 299 temp = readl(fsl_lpspi->base + IMX7ULP_CR); 300 temp |= CR_RRF | CR_RTF | CR_MEN; 301 writel(temp, fsl_lpspi->base + IMX7ULP_CR); 302 303 return 0; 304 } 305 306 static void fsl_lpspi_setup_transfer(struct spi_device *spi, 307 struct spi_transfer *t) 308 { 309 struct fsl_lpspi_data *fsl_lpspi = 310 spi_controller_get_devdata(spi->controller); 311 312 fsl_lpspi->config.mode = spi->mode; 313 fsl_lpspi->config.bpw = t ? t->bits_per_word : spi->bits_per_word; 314 fsl_lpspi->config.speed_hz = t ? t->speed_hz : spi->max_speed_hz; 315 fsl_lpspi->config.chip_select = spi->chip_select; 316 317 if (!fsl_lpspi->config.speed_hz) 318 fsl_lpspi->config.speed_hz = spi->max_speed_hz; 319 if (!fsl_lpspi->config.bpw) 320 fsl_lpspi->config.bpw = spi->bits_per_word; 321 322 /* Initialize the functions for transfer */ 323 if (fsl_lpspi->config.bpw <= 8) { 324 fsl_lpspi->rx = fsl_lpspi_buf_rx_u8; 325 fsl_lpspi->tx = fsl_lpspi_buf_tx_u8; 326 } else if (fsl_lpspi->config.bpw <= 16) { 327 fsl_lpspi->rx = fsl_lpspi_buf_rx_u16; 328 fsl_lpspi->tx = fsl_lpspi_buf_tx_u16; 329 } else { 330 fsl_lpspi->rx = fsl_lpspi_buf_rx_u32; 331 fsl_lpspi->tx = fsl_lpspi_buf_tx_u32; 332 } 333 334 if (t->len <= fsl_lpspi->txfifosize) 335 fsl_lpspi->watermark = t->len; 336 else 337 fsl_lpspi->watermark = fsl_lpspi->txfifosize; 338 339 fsl_lpspi_config(fsl_lpspi); 340 } 341 342 static int fsl_lpspi_slave_abort(struct spi_controller *controller) 343 { 344 struct fsl_lpspi_data *fsl_lpspi = 345 spi_controller_get_devdata(controller); 346 347 fsl_lpspi->slave_aborted = true; 348 complete(&fsl_lpspi->xfer_done); 349 return 0; 350 } 351 352 static int fsl_lpspi_wait_for_completion(struct spi_controller *controller) 353 { 354 struct fsl_lpspi_data *fsl_lpspi = 355 spi_controller_get_devdata(controller); 356 357 if (fsl_lpspi->is_slave) { 358 if (wait_for_completion_interruptible(&fsl_lpspi->xfer_done) || 359 fsl_lpspi->slave_aborted) { 360 dev_dbg(fsl_lpspi->dev, "interrupted\n"); 361 return -EINTR; 362 } 363 } else { 364 if (!wait_for_completion_timeout(&fsl_lpspi->xfer_done, HZ)) { 365 dev_dbg(fsl_lpspi->dev, "wait for completion timeout\n"); 366 return -ETIMEDOUT; 367 } 368 } 369 370 return 0; 371 } 372 373 static int fsl_lpspi_transfer_one(struct spi_controller *controller, 374 struct spi_device *spi, 375 struct spi_transfer *t) 376 { 377 struct fsl_lpspi_data *fsl_lpspi = 378 spi_controller_get_devdata(controller); 379 int ret; 380 381 fsl_lpspi->tx_buf = t->tx_buf; 382 fsl_lpspi->rx_buf = t->rx_buf; 383 fsl_lpspi->remain = t->len; 384 385 reinit_completion(&fsl_lpspi->xfer_done); 386 fsl_lpspi->slave_aborted = false; 387 388 fsl_lpspi_write_tx_fifo(fsl_lpspi); 389 390 ret = fsl_lpspi_wait_for_completion(controller); 391 if (ret) 392 return ret; 393 394 ret = fsl_lpspi_txfifo_empty(fsl_lpspi); 395 if (ret) 396 return ret; 397 398 fsl_lpspi_read_rx_fifo(fsl_lpspi); 399 400 return 0; 401 } 402 403 static int fsl_lpspi_transfer_one_msg(struct spi_controller *controller, 404 struct spi_message *msg) 405 { 406 struct fsl_lpspi_data *fsl_lpspi = 407 spi_controller_get_devdata(controller); 408 struct spi_device *spi = msg->spi; 409 struct spi_transfer *xfer; 410 bool is_first_xfer = true; 411 u32 temp; 412 int ret = 0; 413 414 msg->status = 0; 415 msg->actual_length = 0; 416 417 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 418 fsl_lpspi_setup_transfer(spi, xfer); 419 fsl_lpspi_set_cmd(fsl_lpspi, is_first_xfer); 420 421 is_first_xfer = false; 422 423 ret = fsl_lpspi_transfer_one(controller, spi, xfer); 424 if (ret < 0) 425 goto complete; 426 427 msg->actual_length += xfer->len; 428 } 429 430 complete: 431 if (!fsl_lpspi->is_slave) { 432 /* de-assert SS, then finalize current message */ 433 temp = readl(fsl_lpspi->base + IMX7ULP_TCR); 434 temp &= ~TCR_CONTC; 435 writel(temp, fsl_lpspi->base + IMX7ULP_TCR); 436 } 437 438 msg->status = ret; 439 spi_finalize_current_message(controller); 440 441 return ret; 442 } 443 444 static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id) 445 { 446 struct fsl_lpspi_data *fsl_lpspi = dev_id; 447 u32 temp; 448 449 fsl_lpspi_intctrl(fsl_lpspi, 0); 450 temp = readl(fsl_lpspi->base + IMX7ULP_SR); 451 452 fsl_lpspi_read_rx_fifo(fsl_lpspi); 453 454 if (temp & SR_TDF) { 455 fsl_lpspi_write_tx_fifo(fsl_lpspi); 456 457 if (!fsl_lpspi->remain) 458 complete(&fsl_lpspi->xfer_done); 459 460 return IRQ_HANDLED; 461 } 462 463 return IRQ_NONE; 464 } 465 466 static int fsl_lpspi_probe(struct platform_device *pdev) 467 { 468 struct fsl_lpspi_data *fsl_lpspi; 469 struct spi_controller *controller; 470 struct resource *res; 471 int ret, irq; 472 u32 temp; 473 474 if (of_property_read_bool((&pdev->dev)->of_node, "spi-slave")) 475 controller = spi_alloc_slave(&pdev->dev, 476 sizeof(struct fsl_lpspi_data)); 477 else 478 controller = spi_alloc_master(&pdev->dev, 479 sizeof(struct fsl_lpspi_data)); 480 481 if (!controller) 482 return -ENOMEM; 483 484 platform_set_drvdata(pdev, controller); 485 486 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32); 487 controller->bus_num = pdev->id; 488 489 fsl_lpspi = spi_controller_get_devdata(controller); 490 fsl_lpspi->dev = &pdev->dev; 491 fsl_lpspi->is_slave = of_property_read_bool((&pdev->dev)->of_node, 492 "spi-slave"); 493 494 controller->transfer_one_message = fsl_lpspi_transfer_one_msg; 495 controller->prepare_transfer_hardware = lpspi_prepare_xfer_hardware; 496 controller->unprepare_transfer_hardware = lpspi_unprepare_xfer_hardware; 497 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 498 controller->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX; 499 controller->dev.of_node = pdev->dev.of_node; 500 controller->bus_num = pdev->id; 501 controller->slave_abort = fsl_lpspi_slave_abort; 502 503 init_completion(&fsl_lpspi->xfer_done); 504 505 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 506 fsl_lpspi->base = devm_ioremap_resource(&pdev->dev, res); 507 if (IS_ERR(fsl_lpspi->base)) { 508 ret = PTR_ERR(fsl_lpspi->base); 509 goto out_controller_put; 510 } 511 512 irq = platform_get_irq(pdev, 0); 513 if (irq < 0) { 514 ret = irq; 515 goto out_controller_put; 516 } 517 518 ret = devm_request_irq(&pdev->dev, irq, fsl_lpspi_isr, 0, 519 dev_name(&pdev->dev), fsl_lpspi); 520 if (ret) { 521 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret); 522 goto out_controller_put; 523 } 524 525 fsl_lpspi->clk = devm_clk_get(&pdev->dev, "ipg"); 526 if (IS_ERR(fsl_lpspi->clk)) { 527 ret = PTR_ERR(fsl_lpspi->clk); 528 goto out_controller_put; 529 } 530 531 ret = clk_prepare_enable(fsl_lpspi->clk); 532 if (ret) { 533 dev_err(&pdev->dev, "can't enable lpspi clock, ret=%d\n", ret); 534 goto out_controller_put; 535 } 536 537 temp = readl(fsl_lpspi->base + IMX7ULP_PARAM); 538 fsl_lpspi->txfifosize = 1 << (temp & 0x0f); 539 fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f); 540 541 clk_disable_unprepare(fsl_lpspi->clk); 542 543 ret = devm_spi_register_controller(&pdev->dev, controller); 544 if (ret < 0) { 545 dev_err(&pdev->dev, "spi_register_controller error.\n"); 546 goto out_controller_put; 547 } 548 549 return 0; 550 551 out_controller_put: 552 spi_controller_put(controller); 553 554 return ret; 555 } 556 557 static int fsl_lpspi_remove(struct platform_device *pdev) 558 { 559 struct spi_controller *controller = platform_get_drvdata(pdev); 560 struct fsl_lpspi_data *fsl_lpspi = 561 spi_controller_get_devdata(controller); 562 563 clk_disable_unprepare(fsl_lpspi->clk); 564 565 return 0; 566 } 567 568 static struct platform_driver fsl_lpspi_driver = { 569 .driver = { 570 .name = DRIVER_NAME, 571 .of_match_table = fsl_lpspi_dt_ids, 572 }, 573 .probe = fsl_lpspi_probe, 574 .remove = fsl_lpspi_remove, 575 }; 576 module_platform_driver(fsl_lpspi_driver); 577 578 MODULE_DESCRIPTION("LPSPI Controller driver"); 579 MODULE_AUTHOR("Gao Pan <pandy.gao@nxp.com>"); 580 MODULE_LICENSE("GPL"); 581