1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Freescale i.MX7ULP LPSPI driver 4 // 5 // Copyright 2016 Freescale Semiconductor, Inc. 6 // Copyright 2018 NXP Semiconductors 7 8 #include <linux/clk.h> 9 #include <linux/completion.h> 10 #include <linux/delay.h> 11 #include <linux/dmaengine.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/err.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/irq.h> 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/pinctrl/consumer.h> 21 #include <linux/platform_device.h> 22 #include <linux/dma/imx-dma.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/slab.h> 25 #include <linux/spi/spi.h> 26 #include <linux/spi/spi_bitbang.h> 27 #include <linux/types.h> 28 29 #define DRIVER_NAME "fsl_lpspi" 30 31 #define FSL_LPSPI_RPM_TIMEOUT 50 /* 50ms */ 32 33 /* The maximum bytes that edma can transfer once.*/ 34 #define FSL_LPSPI_MAX_EDMA_BYTES ((1 << 15) - 1) 35 36 /* i.MX7ULP LPSPI registers */ 37 #define IMX7ULP_VERID 0x0 38 #define IMX7ULP_PARAM 0x4 39 #define IMX7ULP_CR 0x10 40 #define IMX7ULP_SR 0x14 41 #define IMX7ULP_IER 0x18 42 #define IMX7ULP_DER 0x1c 43 #define IMX7ULP_CFGR0 0x20 44 #define IMX7ULP_CFGR1 0x24 45 #define IMX7ULP_DMR0 0x30 46 #define IMX7ULP_DMR1 0x34 47 #define IMX7ULP_CCR 0x40 48 #define IMX7ULP_FCR 0x58 49 #define IMX7ULP_FSR 0x5c 50 #define IMX7ULP_TCR 0x60 51 #define IMX7ULP_TDR 0x64 52 #define IMX7ULP_RSR 0x70 53 #define IMX7ULP_RDR 0x74 54 55 /* General control register field define */ 56 #define CR_RRF BIT(9) 57 #define CR_RTF BIT(8) 58 #define CR_RST BIT(1) 59 #define CR_MEN BIT(0) 60 #define SR_MBF BIT(24) 61 #define SR_TCF BIT(10) 62 #define SR_FCF BIT(9) 63 #define SR_RDF BIT(1) 64 #define SR_TDF BIT(0) 65 #define IER_TCIE BIT(10) 66 #define IER_FCIE BIT(9) 67 #define IER_RDIE BIT(1) 68 #define IER_TDIE BIT(0) 69 #define DER_RDDE BIT(1) 70 #define DER_TDDE BIT(0) 71 #define CFGR1_PCSCFG BIT(27) 72 #define CFGR1_PINCFG (BIT(24)|BIT(25)) 73 #define CFGR1_PCSPOL BIT(8) 74 #define CFGR1_NOSTALL BIT(3) 75 #define CFGR1_HOST BIT(0) 76 #define FSR_TXCOUNT (0xFF) 77 #define RSR_RXEMPTY BIT(1) 78 #define TCR_CPOL BIT(31) 79 #define TCR_CPHA BIT(30) 80 #define TCR_CONT BIT(21) 81 #define TCR_CONTC BIT(20) 82 #define TCR_RXMSK BIT(19) 83 #define TCR_TXMSK BIT(18) 84 85 struct fsl_lpspi_devtype_data { 86 u8 prescale_max; 87 }; 88 89 struct lpspi_config { 90 u8 bpw; 91 u8 chip_select; 92 u8 prescale; 93 u16 mode; 94 u32 speed_hz; 95 }; 96 97 struct fsl_lpspi_data { 98 struct device *dev; 99 void __iomem *base; 100 unsigned long base_phys; 101 struct clk *clk_ipg; 102 struct clk *clk_per; 103 bool is_target; 104 bool is_only_cs1; 105 bool is_first_byte; 106 107 void *rx_buf; 108 const void *tx_buf; 109 void (*tx)(struct fsl_lpspi_data *); 110 void (*rx)(struct fsl_lpspi_data *); 111 112 u32 remain; 113 u8 watermark; 114 u8 txfifosize; 115 u8 rxfifosize; 116 117 struct lpspi_config config; 118 struct completion xfer_done; 119 120 bool target_aborted; 121 122 /* DMA */ 123 bool usedma; 124 struct completion dma_rx_completion; 125 struct completion dma_tx_completion; 126 127 const struct fsl_lpspi_devtype_data *devtype_data; 128 }; 129 130 /* 131 * ERR051608 fixed or not: 132 * https://www.nxp.com/docs/en/errata/i.MX93_1P87f.pdf 133 */ 134 static struct fsl_lpspi_devtype_data imx93_lpspi_devtype_data = { 135 .prescale_max = 1, 136 }; 137 138 static struct fsl_lpspi_devtype_data imx7ulp_lpspi_devtype_data = { 139 .prescale_max = 7, 140 }; 141 142 static const struct of_device_id fsl_lpspi_dt_ids[] = { 143 { .compatible = "fsl,imx7ulp-spi", .data = &imx7ulp_lpspi_devtype_data,}, 144 { .compatible = "fsl,imx93-spi", .data = &imx93_lpspi_devtype_data,}, 145 { /* sentinel */ } 146 }; 147 MODULE_DEVICE_TABLE(of, fsl_lpspi_dt_ids); 148 149 #define LPSPI_BUF_RX(type) \ 150 static void fsl_lpspi_buf_rx_##type(struct fsl_lpspi_data *fsl_lpspi) \ 151 { \ 152 unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR); \ 153 \ 154 if (fsl_lpspi->rx_buf) { \ 155 *(type *)fsl_lpspi->rx_buf = val; \ 156 fsl_lpspi->rx_buf += sizeof(type); \ 157 } \ 158 } 159 160 #define LPSPI_BUF_TX(type) \ 161 static void fsl_lpspi_buf_tx_##type(struct fsl_lpspi_data *fsl_lpspi) \ 162 { \ 163 type val = 0; \ 164 \ 165 if (fsl_lpspi->tx_buf) { \ 166 val = *(type *)fsl_lpspi->tx_buf; \ 167 fsl_lpspi->tx_buf += sizeof(type); \ 168 } \ 169 \ 170 fsl_lpspi->remain -= sizeof(type); \ 171 writel(val, fsl_lpspi->base + IMX7ULP_TDR); \ 172 } 173 174 LPSPI_BUF_RX(u8) 175 LPSPI_BUF_TX(u8) 176 LPSPI_BUF_RX(u16) 177 LPSPI_BUF_TX(u16) 178 LPSPI_BUF_RX(u32) 179 LPSPI_BUF_TX(u32) 180 181 static void fsl_lpspi_intctrl(struct fsl_lpspi_data *fsl_lpspi, 182 unsigned int enable) 183 { 184 writel(enable, fsl_lpspi->base + IMX7ULP_IER); 185 } 186 187 static int fsl_lpspi_bytes_per_word(const int bpw) 188 { 189 return DIV_ROUND_UP(bpw, BITS_PER_BYTE); 190 } 191 192 static bool fsl_lpspi_can_dma(struct spi_controller *controller, 193 struct spi_device *spi, 194 struct spi_transfer *transfer) 195 { 196 unsigned int bytes_per_word; 197 198 if (!controller->dma_rx) 199 return false; 200 201 bytes_per_word = fsl_lpspi_bytes_per_word(transfer->bits_per_word); 202 203 switch (bytes_per_word) { 204 case 1: 205 case 2: 206 case 4: 207 break; 208 default: 209 return false; 210 } 211 212 return true; 213 } 214 215 static int lpspi_prepare_xfer_hardware(struct spi_controller *controller) 216 { 217 struct fsl_lpspi_data *fsl_lpspi = 218 spi_controller_get_devdata(controller); 219 int ret; 220 221 ret = pm_runtime_resume_and_get(fsl_lpspi->dev); 222 if (ret < 0) { 223 dev_err(fsl_lpspi->dev, "failed to enable clock\n"); 224 return ret; 225 } 226 227 return 0; 228 } 229 230 static int lpspi_unprepare_xfer_hardware(struct spi_controller *controller) 231 { 232 struct fsl_lpspi_data *fsl_lpspi = 233 spi_controller_get_devdata(controller); 234 235 pm_runtime_mark_last_busy(fsl_lpspi->dev); 236 pm_runtime_put_autosuspend(fsl_lpspi->dev); 237 238 return 0; 239 } 240 241 static void fsl_lpspi_write_tx_fifo(struct fsl_lpspi_data *fsl_lpspi) 242 { 243 u8 txfifo_cnt; 244 u32 temp; 245 246 txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff; 247 248 while (txfifo_cnt < fsl_lpspi->txfifosize) { 249 if (!fsl_lpspi->remain) 250 break; 251 fsl_lpspi->tx(fsl_lpspi); 252 txfifo_cnt++; 253 } 254 255 if (txfifo_cnt < fsl_lpspi->txfifosize) { 256 if (!fsl_lpspi->is_target) { 257 temp = readl(fsl_lpspi->base + IMX7ULP_TCR); 258 temp &= ~TCR_CONTC; 259 writel(temp, fsl_lpspi->base + IMX7ULP_TCR); 260 } 261 262 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE); 263 } else 264 fsl_lpspi_intctrl(fsl_lpspi, IER_TDIE); 265 } 266 267 static void fsl_lpspi_read_rx_fifo(struct fsl_lpspi_data *fsl_lpspi) 268 { 269 while (!(readl(fsl_lpspi->base + IMX7ULP_RSR) & RSR_RXEMPTY)) 270 fsl_lpspi->rx(fsl_lpspi); 271 } 272 273 static void fsl_lpspi_set_cmd(struct fsl_lpspi_data *fsl_lpspi) 274 { 275 u32 temp = 0; 276 277 temp |= fsl_lpspi->config.bpw - 1; 278 temp |= (fsl_lpspi->config.mode & 0x3) << 30; 279 temp |= (fsl_lpspi->config.chip_select & 0x3) << 24; 280 if (!fsl_lpspi->is_target) { 281 temp |= fsl_lpspi->config.prescale << 27; 282 /* 283 * Set TCR_CONT will keep SS asserted after current transfer. 284 * For the first transfer, clear TCR_CONTC to assert SS. 285 * For subsequent transfer, set TCR_CONTC to keep SS asserted. 286 */ 287 if (!fsl_lpspi->usedma) { 288 temp |= TCR_CONT; 289 if (fsl_lpspi->is_first_byte) 290 temp &= ~TCR_CONTC; 291 else 292 temp |= TCR_CONTC; 293 } 294 } 295 writel(temp, fsl_lpspi->base + IMX7ULP_TCR); 296 297 dev_dbg(fsl_lpspi->dev, "TCR=0x%x\n", temp); 298 } 299 300 static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi) 301 { 302 u32 temp; 303 304 if (!fsl_lpspi->usedma) 305 temp = fsl_lpspi->watermark >> 1 | 306 (fsl_lpspi->watermark >> 1) << 16; 307 else 308 temp = fsl_lpspi->watermark >> 1; 309 310 writel(temp, fsl_lpspi->base + IMX7ULP_FCR); 311 312 dev_dbg(fsl_lpspi->dev, "FCR=0x%x\n", temp); 313 } 314 315 static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi) 316 { 317 struct lpspi_config config = fsl_lpspi->config; 318 unsigned int perclk_rate, div; 319 u8 prescale_max; 320 u8 prescale; 321 int scldiv; 322 323 perclk_rate = clk_get_rate(fsl_lpspi->clk_per); 324 prescale_max = fsl_lpspi->devtype_data->prescale_max; 325 326 if (!config.speed_hz) { 327 dev_err(fsl_lpspi->dev, 328 "error: the transmission speed provided is 0!\n"); 329 return -EINVAL; 330 } 331 332 if (config.speed_hz > perclk_rate / 2) { 333 dev_err(fsl_lpspi->dev, 334 "per-clk should be at least two times of transfer speed"); 335 return -EINVAL; 336 } 337 338 div = DIV_ROUND_UP(perclk_rate, config.speed_hz); 339 340 for (prescale = 0; prescale <= prescale_max; prescale++) { 341 scldiv = div / (1 << prescale) - 2; 342 if (scldiv >= 0 && scldiv < 256) { 343 fsl_lpspi->config.prescale = prescale; 344 break; 345 } 346 } 347 348 if (scldiv < 0 || scldiv >= 256) 349 return -EINVAL; 350 351 writel(scldiv | (scldiv << 8) | ((scldiv >> 1) << 16), 352 fsl_lpspi->base + IMX7ULP_CCR); 353 354 dev_dbg(fsl_lpspi->dev, "perclk=%d, speed=%d, prescale=%d, scldiv=%d\n", 355 perclk_rate, config.speed_hz, prescale, scldiv); 356 357 return 0; 358 } 359 360 static int fsl_lpspi_dma_configure(struct spi_controller *controller) 361 { 362 int ret; 363 enum dma_slave_buswidth buswidth; 364 struct dma_slave_config rx = {}, tx = {}; 365 struct fsl_lpspi_data *fsl_lpspi = 366 spi_controller_get_devdata(controller); 367 368 switch (fsl_lpspi_bytes_per_word(fsl_lpspi->config.bpw)) { 369 case 4: 370 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES; 371 break; 372 case 2: 373 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES; 374 break; 375 case 1: 376 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE; 377 break; 378 default: 379 return -EINVAL; 380 } 381 382 tx.direction = DMA_MEM_TO_DEV; 383 tx.dst_addr = fsl_lpspi->base_phys + IMX7ULP_TDR; 384 tx.dst_addr_width = buswidth; 385 tx.dst_maxburst = 1; 386 ret = dmaengine_slave_config(controller->dma_tx, &tx); 387 if (ret) { 388 dev_err(fsl_lpspi->dev, "TX dma configuration failed with %d\n", 389 ret); 390 return ret; 391 } 392 393 rx.direction = DMA_DEV_TO_MEM; 394 rx.src_addr = fsl_lpspi->base_phys + IMX7ULP_RDR; 395 rx.src_addr_width = buswidth; 396 rx.src_maxburst = 1; 397 ret = dmaengine_slave_config(controller->dma_rx, &rx); 398 if (ret) { 399 dev_err(fsl_lpspi->dev, "RX dma configuration failed with %d\n", 400 ret); 401 return ret; 402 } 403 404 return 0; 405 } 406 407 static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi) 408 { 409 u32 temp; 410 int ret; 411 412 if (!fsl_lpspi->is_target) { 413 ret = fsl_lpspi_set_bitrate(fsl_lpspi); 414 if (ret) 415 return ret; 416 } 417 418 fsl_lpspi_set_watermark(fsl_lpspi); 419 420 if (!fsl_lpspi->is_target) 421 temp = CFGR1_HOST; 422 else 423 temp = CFGR1_PINCFG; 424 if (fsl_lpspi->config.mode & SPI_CS_HIGH) 425 temp |= CFGR1_PCSPOL; 426 writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1); 427 428 temp = readl(fsl_lpspi->base + IMX7ULP_CR); 429 temp |= CR_RRF | CR_RTF | CR_MEN; 430 writel(temp, fsl_lpspi->base + IMX7ULP_CR); 431 432 temp = 0; 433 if (fsl_lpspi->usedma) 434 temp = DER_TDDE | DER_RDDE; 435 writel(temp, fsl_lpspi->base + IMX7ULP_DER); 436 437 return 0; 438 } 439 440 static int fsl_lpspi_setup_transfer(struct spi_controller *controller, 441 struct spi_device *spi, 442 struct spi_transfer *t) 443 { 444 struct fsl_lpspi_data *fsl_lpspi = 445 spi_controller_get_devdata(spi->controller); 446 447 if (t == NULL) 448 return -EINVAL; 449 450 fsl_lpspi->config.mode = spi->mode; 451 fsl_lpspi->config.bpw = t->bits_per_word; 452 fsl_lpspi->config.speed_hz = t->speed_hz; 453 if (fsl_lpspi->is_only_cs1) 454 fsl_lpspi->config.chip_select = 1; 455 else 456 fsl_lpspi->config.chip_select = spi_get_chipselect(spi, 0); 457 458 if (!fsl_lpspi->config.speed_hz) 459 fsl_lpspi->config.speed_hz = spi->max_speed_hz; 460 if (!fsl_lpspi->config.bpw) 461 fsl_lpspi->config.bpw = spi->bits_per_word; 462 463 /* Initialize the functions for transfer */ 464 if (fsl_lpspi->config.bpw <= 8) { 465 fsl_lpspi->rx = fsl_lpspi_buf_rx_u8; 466 fsl_lpspi->tx = fsl_lpspi_buf_tx_u8; 467 } else if (fsl_lpspi->config.bpw <= 16) { 468 fsl_lpspi->rx = fsl_lpspi_buf_rx_u16; 469 fsl_lpspi->tx = fsl_lpspi_buf_tx_u16; 470 } else { 471 fsl_lpspi->rx = fsl_lpspi_buf_rx_u32; 472 fsl_lpspi->tx = fsl_lpspi_buf_tx_u32; 473 } 474 475 if (t->len <= fsl_lpspi->txfifosize) 476 fsl_lpspi->watermark = t->len; 477 else 478 fsl_lpspi->watermark = fsl_lpspi->txfifosize; 479 480 if (fsl_lpspi_can_dma(controller, spi, t)) 481 fsl_lpspi->usedma = true; 482 else 483 fsl_lpspi->usedma = false; 484 485 return fsl_lpspi_config(fsl_lpspi); 486 } 487 488 static int fsl_lpspi_target_abort(struct spi_controller *controller) 489 { 490 struct fsl_lpspi_data *fsl_lpspi = 491 spi_controller_get_devdata(controller); 492 493 fsl_lpspi->target_aborted = true; 494 if (!fsl_lpspi->usedma) 495 complete(&fsl_lpspi->xfer_done); 496 else { 497 complete(&fsl_lpspi->dma_tx_completion); 498 complete(&fsl_lpspi->dma_rx_completion); 499 } 500 501 return 0; 502 } 503 504 static int fsl_lpspi_wait_for_completion(struct spi_controller *controller) 505 { 506 struct fsl_lpspi_data *fsl_lpspi = 507 spi_controller_get_devdata(controller); 508 509 if (fsl_lpspi->is_target) { 510 if (wait_for_completion_interruptible(&fsl_lpspi->xfer_done) || 511 fsl_lpspi->target_aborted) { 512 dev_dbg(fsl_lpspi->dev, "interrupted\n"); 513 return -EINTR; 514 } 515 } else { 516 if (!wait_for_completion_timeout(&fsl_lpspi->xfer_done, HZ)) { 517 dev_dbg(fsl_lpspi->dev, "wait for completion timeout\n"); 518 return -ETIMEDOUT; 519 } 520 } 521 522 return 0; 523 } 524 525 static int fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi) 526 { 527 u32 temp; 528 529 if (!fsl_lpspi->usedma) { 530 /* Disable all interrupt */ 531 fsl_lpspi_intctrl(fsl_lpspi, 0); 532 } 533 534 /* W1C for all flags in SR */ 535 temp = 0x3F << 8; 536 writel(temp, fsl_lpspi->base + IMX7ULP_SR); 537 538 /* Clear FIFO and disable module */ 539 temp = CR_RRF | CR_RTF; 540 writel(temp, fsl_lpspi->base + IMX7ULP_CR); 541 542 return 0; 543 } 544 545 static void fsl_lpspi_dma_rx_callback(void *cookie) 546 { 547 struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie; 548 549 complete(&fsl_lpspi->dma_rx_completion); 550 } 551 552 static void fsl_lpspi_dma_tx_callback(void *cookie) 553 { 554 struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie; 555 556 complete(&fsl_lpspi->dma_tx_completion); 557 } 558 559 static int fsl_lpspi_calculate_timeout(struct fsl_lpspi_data *fsl_lpspi, 560 int size) 561 { 562 unsigned long timeout = 0; 563 564 /* Time with actual data transfer and CS change delay related to HW */ 565 timeout = (8 + 4) * size / fsl_lpspi->config.speed_hz; 566 567 /* Add extra second for scheduler related activities */ 568 timeout += 1; 569 570 /* Double calculated timeout */ 571 return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC); 572 } 573 574 static int fsl_lpspi_dma_transfer(struct spi_controller *controller, 575 struct fsl_lpspi_data *fsl_lpspi, 576 struct spi_transfer *transfer) 577 { 578 struct dma_async_tx_descriptor *desc_tx, *desc_rx; 579 unsigned long transfer_timeout; 580 unsigned long timeout; 581 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg; 582 int ret; 583 584 ret = fsl_lpspi_dma_configure(controller); 585 if (ret) 586 return ret; 587 588 desc_rx = dmaengine_prep_slave_sg(controller->dma_rx, 589 rx->sgl, rx->nents, DMA_DEV_TO_MEM, 590 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 591 if (!desc_rx) 592 return -EINVAL; 593 594 desc_rx->callback = fsl_lpspi_dma_rx_callback; 595 desc_rx->callback_param = (void *)fsl_lpspi; 596 dmaengine_submit(desc_rx); 597 reinit_completion(&fsl_lpspi->dma_rx_completion); 598 dma_async_issue_pending(controller->dma_rx); 599 600 desc_tx = dmaengine_prep_slave_sg(controller->dma_tx, 601 tx->sgl, tx->nents, DMA_MEM_TO_DEV, 602 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 603 if (!desc_tx) { 604 dmaengine_terminate_all(controller->dma_tx); 605 return -EINVAL; 606 } 607 608 desc_tx->callback = fsl_lpspi_dma_tx_callback; 609 desc_tx->callback_param = (void *)fsl_lpspi; 610 dmaengine_submit(desc_tx); 611 reinit_completion(&fsl_lpspi->dma_tx_completion); 612 dma_async_issue_pending(controller->dma_tx); 613 614 fsl_lpspi->target_aborted = false; 615 616 if (!fsl_lpspi->is_target) { 617 transfer_timeout = fsl_lpspi_calculate_timeout(fsl_lpspi, 618 transfer->len); 619 620 /* Wait eDMA to finish the data transfer.*/ 621 timeout = wait_for_completion_timeout(&fsl_lpspi->dma_tx_completion, 622 transfer_timeout); 623 if (!timeout) { 624 dev_err(fsl_lpspi->dev, "I/O Error in DMA TX\n"); 625 dmaengine_terminate_all(controller->dma_tx); 626 dmaengine_terminate_all(controller->dma_rx); 627 fsl_lpspi_reset(fsl_lpspi); 628 return -ETIMEDOUT; 629 } 630 631 timeout = wait_for_completion_timeout(&fsl_lpspi->dma_rx_completion, 632 transfer_timeout); 633 if (!timeout) { 634 dev_err(fsl_lpspi->dev, "I/O Error in DMA RX\n"); 635 dmaengine_terminate_all(controller->dma_tx); 636 dmaengine_terminate_all(controller->dma_rx); 637 fsl_lpspi_reset(fsl_lpspi); 638 return -ETIMEDOUT; 639 } 640 } else { 641 if (wait_for_completion_interruptible(&fsl_lpspi->dma_tx_completion) || 642 fsl_lpspi->target_aborted) { 643 dev_dbg(fsl_lpspi->dev, 644 "I/O Error in DMA TX interrupted\n"); 645 dmaengine_terminate_all(controller->dma_tx); 646 dmaengine_terminate_all(controller->dma_rx); 647 fsl_lpspi_reset(fsl_lpspi); 648 return -EINTR; 649 } 650 651 if (wait_for_completion_interruptible(&fsl_lpspi->dma_rx_completion) || 652 fsl_lpspi->target_aborted) { 653 dev_dbg(fsl_lpspi->dev, 654 "I/O Error in DMA RX interrupted\n"); 655 dmaengine_terminate_all(controller->dma_tx); 656 dmaengine_terminate_all(controller->dma_rx); 657 fsl_lpspi_reset(fsl_lpspi); 658 return -EINTR; 659 } 660 } 661 662 fsl_lpspi_reset(fsl_lpspi); 663 664 return 0; 665 } 666 667 static void fsl_lpspi_dma_exit(struct spi_controller *controller) 668 { 669 if (controller->dma_rx) { 670 dma_release_channel(controller->dma_rx); 671 controller->dma_rx = NULL; 672 } 673 674 if (controller->dma_tx) { 675 dma_release_channel(controller->dma_tx); 676 controller->dma_tx = NULL; 677 } 678 } 679 680 static int fsl_lpspi_dma_init(struct device *dev, 681 struct fsl_lpspi_data *fsl_lpspi, 682 struct spi_controller *controller) 683 { 684 int ret; 685 686 /* Prepare for TX DMA: */ 687 controller->dma_tx = dma_request_chan(dev, "tx"); 688 if (IS_ERR(controller->dma_tx)) { 689 ret = PTR_ERR(controller->dma_tx); 690 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret); 691 controller->dma_tx = NULL; 692 goto err; 693 } 694 695 /* Prepare for RX DMA: */ 696 controller->dma_rx = dma_request_chan(dev, "rx"); 697 if (IS_ERR(controller->dma_rx)) { 698 ret = PTR_ERR(controller->dma_rx); 699 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret); 700 controller->dma_rx = NULL; 701 goto err; 702 } 703 704 init_completion(&fsl_lpspi->dma_rx_completion); 705 init_completion(&fsl_lpspi->dma_tx_completion); 706 controller->can_dma = fsl_lpspi_can_dma; 707 controller->max_dma_len = FSL_LPSPI_MAX_EDMA_BYTES; 708 709 return 0; 710 err: 711 fsl_lpspi_dma_exit(controller); 712 return ret; 713 } 714 715 static int fsl_lpspi_pio_transfer(struct spi_controller *controller, 716 struct spi_transfer *t) 717 { 718 struct fsl_lpspi_data *fsl_lpspi = 719 spi_controller_get_devdata(controller); 720 int ret; 721 722 fsl_lpspi->tx_buf = t->tx_buf; 723 fsl_lpspi->rx_buf = t->rx_buf; 724 fsl_lpspi->remain = t->len; 725 726 reinit_completion(&fsl_lpspi->xfer_done); 727 fsl_lpspi->target_aborted = false; 728 729 fsl_lpspi_write_tx_fifo(fsl_lpspi); 730 731 ret = fsl_lpspi_wait_for_completion(controller); 732 if (ret) 733 return ret; 734 735 fsl_lpspi_reset(fsl_lpspi); 736 737 return 0; 738 } 739 740 static int fsl_lpspi_transfer_one(struct spi_controller *controller, 741 struct spi_device *spi, 742 struct spi_transfer *t) 743 { 744 struct fsl_lpspi_data *fsl_lpspi = 745 spi_controller_get_devdata(controller); 746 int ret; 747 748 fsl_lpspi->is_first_byte = true; 749 ret = fsl_lpspi_setup_transfer(controller, spi, t); 750 if (ret < 0) 751 return ret; 752 753 fsl_lpspi_set_cmd(fsl_lpspi); 754 fsl_lpspi->is_first_byte = false; 755 756 if (fsl_lpspi->usedma) 757 ret = fsl_lpspi_dma_transfer(controller, fsl_lpspi, t); 758 else 759 ret = fsl_lpspi_pio_transfer(controller, t); 760 if (ret < 0) 761 return ret; 762 763 return 0; 764 } 765 766 static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id) 767 { 768 u32 temp_SR, temp_IER; 769 struct fsl_lpspi_data *fsl_lpspi = dev_id; 770 771 temp_IER = readl(fsl_lpspi->base + IMX7ULP_IER); 772 fsl_lpspi_intctrl(fsl_lpspi, 0); 773 temp_SR = readl(fsl_lpspi->base + IMX7ULP_SR); 774 775 fsl_lpspi_read_rx_fifo(fsl_lpspi); 776 777 if ((temp_SR & SR_TDF) && (temp_IER & IER_TDIE)) { 778 fsl_lpspi_write_tx_fifo(fsl_lpspi); 779 return IRQ_HANDLED; 780 } 781 782 if (temp_SR & SR_MBF || 783 readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_TXCOUNT) { 784 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR); 785 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE); 786 return IRQ_HANDLED; 787 } 788 789 if (temp_SR & SR_FCF && (temp_IER & IER_FCIE)) { 790 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR); 791 complete(&fsl_lpspi->xfer_done); 792 return IRQ_HANDLED; 793 } 794 795 return IRQ_NONE; 796 } 797 798 #ifdef CONFIG_PM 799 static int fsl_lpspi_runtime_resume(struct device *dev) 800 { 801 struct spi_controller *controller = dev_get_drvdata(dev); 802 struct fsl_lpspi_data *fsl_lpspi; 803 int ret; 804 805 fsl_lpspi = spi_controller_get_devdata(controller); 806 807 ret = clk_prepare_enable(fsl_lpspi->clk_per); 808 if (ret) 809 return ret; 810 811 ret = clk_prepare_enable(fsl_lpspi->clk_ipg); 812 if (ret) { 813 clk_disable_unprepare(fsl_lpspi->clk_per); 814 return ret; 815 } 816 817 return 0; 818 } 819 820 static int fsl_lpspi_runtime_suspend(struct device *dev) 821 { 822 struct spi_controller *controller = dev_get_drvdata(dev); 823 struct fsl_lpspi_data *fsl_lpspi; 824 825 fsl_lpspi = spi_controller_get_devdata(controller); 826 827 clk_disable_unprepare(fsl_lpspi->clk_per); 828 clk_disable_unprepare(fsl_lpspi->clk_ipg); 829 830 return 0; 831 } 832 #endif 833 834 static int fsl_lpspi_init_rpm(struct fsl_lpspi_data *fsl_lpspi) 835 { 836 struct device *dev = fsl_lpspi->dev; 837 838 pm_runtime_enable(dev); 839 pm_runtime_set_autosuspend_delay(dev, FSL_LPSPI_RPM_TIMEOUT); 840 pm_runtime_use_autosuspend(dev); 841 842 return 0; 843 } 844 845 static int fsl_lpspi_probe(struct platform_device *pdev) 846 { 847 const struct fsl_lpspi_devtype_data *devtype_data; 848 struct fsl_lpspi_data *fsl_lpspi; 849 struct spi_controller *controller; 850 struct resource *res; 851 int ret, irq; 852 u32 num_cs; 853 u32 temp; 854 bool is_target; 855 856 devtype_data = of_device_get_match_data(&pdev->dev); 857 if (!devtype_data) 858 return -ENODEV; 859 860 is_target = of_property_read_bool((&pdev->dev)->of_node, "spi-slave"); 861 if (is_target) 862 controller = devm_spi_alloc_target(&pdev->dev, 863 sizeof(struct fsl_lpspi_data)); 864 else 865 controller = devm_spi_alloc_host(&pdev->dev, 866 sizeof(struct fsl_lpspi_data)); 867 868 if (!controller) 869 return -ENOMEM; 870 871 platform_set_drvdata(pdev, controller); 872 873 fsl_lpspi = spi_controller_get_devdata(controller); 874 fsl_lpspi->dev = &pdev->dev; 875 fsl_lpspi->is_target = is_target; 876 fsl_lpspi->is_only_cs1 = of_property_read_bool((&pdev->dev)->of_node, 877 "fsl,spi-only-use-cs1-sel"); 878 fsl_lpspi->devtype_data = devtype_data; 879 880 init_completion(&fsl_lpspi->xfer_done); 881 882 fsl_lpspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 883 if (IS_ERR(fsl_lpspi->base)) { 884 ret = PTR_ERR(fsl_lpspi->base); 885 return ret; 886 } 887 fsl_lpspi->base_phys = res->start; 888 889 irq = platform_get_irq(pdev, 0); 890 if (irq < 0) { 891 ret = irq; 892 return ret; 893 } 894 895 ret = devm_request_irq(&pdev->dev, irq, fsl_lpspi_isr, IRQF_NO_AUTOEN, 896 dev_name(&pdev->dev), fsl_lpspi); 897 if (ret) { 898 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret); 899 return ret; 900 } 901 902 fsl_lpspi->clk_per = devm_clk_get(&pdev->dev, "per"); 903 if (IS_ERR(fsl_lpspi->clk_per)) { 904 ret = PTR_ERR(fsl_lpspi->clk_per); 905 return ret; 906 } 907 908 fsl_lpspi->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 909 if (IS_ERR(fsl_lpspi->clk_ipg)) { 910 ret = PTR_ERR(fsl_lpspi->clk_ipg); 911 return ret; 912 } 913 914 /* enable the clock */ 915 ret = fsl_lpspi_init_rpm(fsl_lpspi); 916 if (ret) 917 return ret; 918 919 ret = pm_runtime_get_sync(fsl_lpspi->dev); 920 if (ret < 0) { 921 dev_err(fsl_lpspi->dev, "failed to enable clock\n"); 922 goto out_pm_get; 923 } 924 925 temp = readl(fsl_lpspi->base + IMX7ULP_PARAM); 926 fsl_lpspi->txfifosize = 1 << (temp & 0x0f); 927 fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f); 928 if (of_property_read_u32((&pdev->dev)->of_node, "num-cs", 929 &num_cs)) { 930 if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx93-spi")) 931 num_cs = ((temp >> 16) & 0xf); 932 else 933 num_cs = 1; 934 } 935 936 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32); 937 controller->transfer_one = fsl_lpspi_transfer_one; 938 controller->prepare_transfer_hardware = lpspi_prepare_xfer_hardware; 939 controller->unprepare_transfer_hardware = lpspi_unprepare_xfer_hardware; 940 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 941 controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX; 942 controller->dev.of_node = pdev->dev.of_node; 943 controller->bus_num = pdev->id; 944 controller->num_chipselect = num_cs; 945 controller->target_abort = fsl_lpspi_target_abort; 946 if (!fsl_lpspi->is_target) 947 controller->use_gpio_descriptors = true; 948 949 ret = fsl_lpspi_dma_init(&pdev->dev, fsl_lpspi, controller); 950 if (ret == -EPROBE_DEFER) 951 goto out_pm_get; 952 if (ret < 0) { 953 dev_warn(&pdev->dev, "dma setup error %d, use pio\n", ret); 954 enable_irq(irq); 955 } 956 957 ret = devm_spi_register_controller(&pdev->dev, controller); 958 if (ret < 0) { 959 dev_err_probe(&pdev->dev, ret, "spi_register_controller error\n"); 960 goto free_dma; 961 } 962 963 pm_runtime_mark_last_busy(fsl_lpspi->dev); 964 pm_runtime_put_autosuspend(fsl_lpspi->dev); 965 966 return 0; 967 968 free_dma: 969 fsl_lpspi_dma_exit(controller); 970 out_pm_get: 971 pm_runtime_dont_use_autosuspend(fsl_lpspi->dev); 972 pm_runtime_put_sync(fsl_lpspi->dev); 973 pm_runtime_disable(fsl_lpspi->dev); 974 975 return ret; 976 } 977 978 static void fsl_lpspi_remove(struct platform_device *pdev) 979 { 980 struct spi_controller *controller = platform_get_drvdata(pdev); 981 struct fsl_lpspi_data *fsl_lpspi = 982 spi_controller_get_devdata(controller); 983 984 fsl_lpspi_dma_exit(controller); 985 986 pm_runtime_dont_use_autosuspend(fsl_lpspi->dev); 987 pm_runtime_disable(fsl_lpspi->dev); 988 } 989 990 static int __maybe_unused fsl_lpspi_suspend(struct device *dev) 991 { 992 pinctrl_pm_select_sleep_state(dev); 993 return pm_runtime_force_suspend(dev); 994 } 995 996 static int __maybe_unused fsl_lpspi_resume(struct device *dev) 997 { 998 int ret; 999 1000 ret = pm_runtime_force_resume(dev); 1001 if (ret) { 1002 dev_err(dev, "Error in resume: %d\n", ret); 1003 return ret; 1004 } 1005 1006 pinctrl_pm_select_default_state(dev); 1007 1008 return 0; 1009 } 1010 1011 static const struct dev_pm_ops fsl_lpspi_pm_ops = { 1012 SET_RUNTIME_PM_OPS(fsl_lpspi_runtime_suspend, 1013 fsl_lpspi_runtime_resume, NULL) 1014 SET_SYSTEM_SLEEP_PM_OPS(fsl_lpspi_suspend, fsl_lpspi_resume) 1015 }; 1016 1017 static struct platform_driver fsl_lpspi_driver = { 1018 .driver = { 1019 .name = DRIVER_NAME, 1020 .of_match_table = fsl_lpspi_dt_ids, 1021 .pm = &fsl_lpspi_pm_ops, 1022 }, 1023 .probe = fsl_lpspi_probe, 1024 .remove_new = fsl_lpspi_remove, 1025 }; 1026 module_platform_driver(fsl_lpspi_driver); 1027 1028 MODULE_DESCRIPTION("LPSPI Controller driver"); 1029 MODULE_AUTHOR("Gao Pan <pandy.gao@nxp.com>"); 1030 MODULE_LICENSE("GPL"); 1031