1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Freescale i.MX7ULP LPSPI driver 4 // 5 // Copyright 2016 Freescale Semiconductor, Inc. 6 // Copyright 2018 NXP Semiconductors 7 8 #include <linux/clk.h> 9 #include <linux/completion.h> 10 #include <linux/delay.h> 11 #include <linux/dmaengine.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/err.h> 14 #include <linux/gpio.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/irq.h> 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/of_device.h> 22 #include <linux/of_gpio.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/platform_device.h> 25 #include <linux/platform_data/dma-imx.h> 26 #include <linux/platform_data/spi-imx.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/slab.h> 29 #include <linux/spi/spi.h> 30 #include <linux/spi/spi_bitbang.h> 31 #include <linux/types.h> 32 33 #define DRIVER_NAME "fsl_lpspi" 34 35 #define FSL_LPSPI_RPM_TIMEOUT 50 /* 50ms */ 36 37 /* The maximum bytes that edma can transfer once.*/ 38 #define FSL_LPSPI_MAX_EDMA_BYTES ((1 << 15) - 1) 39 40 /* i.MX7ULP LPSPI registers */ 41 #define IMX7ULP_VERID 0x0 42 #define IMX7ULP_PARAM 0x4 43 #define IMX7ULP_CR 0x10 44 #define IMX7ULP_SR 0x14 45 #define IMX7ULP_IER 0x18 46 #define IMX7ULP_DER 0x1c 47 #define IMX7ULP_CFGR0 0x20 48 #define IMX7ULP_CFGR1 0x24 49 #define IMX7ULP_DMR0 0x30 50 #define IMX7ULP_DMR1 0x34 51 #define IMX7ULP_CCR 0x40 52 #define IMX7ULP_FCR 0x58 53 #define IMX7ULP_FSR 0x5c 54 #define IMX7ULP_TCR 0x60 55 #define IMX7ULP_TDR 0x64 56 #define IMX7ULP_RSR 0x70 57 #define IMX7ULP_RDR 0x74 58 59 /* General control register field define */ 60 #define CR_RRF BIT(9) 61 #define CR_RTF BIT(8) 62 #define CR_RST BIT(1) 63 #define CR_MEN BIT(0) 64 #define SR_MBF BIT(24) 65 #define SR_TCF BIT(10) 66 #define SR_FCF BIT(9) 67 #define SR_RDF BIT(1) 68 #define SR_TDF BIT(0) 69 #define IER_TCIE BIT(10) 70 #define IER_FCIE BIT(9) 71 #define IER_RDIE BIT(1) 72 #define IER_TDIE BIT(0) 73 #define DER_RDDE BIT(1) 74 #define DER_TDDE BIT(0) 75 #define CFGR1_PCSCFG BIT(27) 76 #define CFGR1_PINCFG (BIT(24)|BIT(25)) 77 #define CFGR1_PCSPOL BIT(8) 78 #define CFGR1_NOSTALL BIT(3) 79 #define CFGR1_MASTER BIT(0) 80 #define FSR_TXCOUNT (0xFF) 81 #define RSR_RXEMPTY BIT(1) 82 #define TCR_CPOL BIT(31) 83 #define TCR_CPHA BIT(30) 84 #define TCR_CONT BIT(21) 85 #define TCR_CONTC BIT(20) 86 #define TCR_RXMSK BIT(19) 87 #define TCR_TXMSK BIT(18) 88 89 struct lpspi_config { 90 u8 bpw; 91 u8 chip_select; 92 u8 prescale; 93 u16 mode; 94 u32 speed_hz; 95 }; 96 97 struct fsl_lpspi_data { 98 struct device *dev; 99 void __iomem *base; 100 unsigned long base_phys; 101 struct clk *clk_ipg; 102 struct clk *clk_per; 103 bool is_slave; 104 bool is_first_byte; 105 106 void *rx_buf; 107 const void *tx_buf; 108 void (*tx)(struct fsl_lpspi_data *); 109 void (*rx)(struct fsl_lpspi_data *); 110 111 u32 remain; 112 u8 watermark; 113 u8 txfifosize; 114 u8 rxfifosize; 115 116 struct lpspi_config config; 117 struct completion xfer_done; 118 119 bool slave_aborted; 120 121 /* DMA */ 122 bool usedma; 123 struct completion dma_rx_completion; 124 struct completion dma_tx_completion; 125 126 int chipselect[]; 127 }; 128 129 static const struct of_device_id fsl_lpspi_dt_ids[] = { 130 { .compatible = "fsl,imx7ulp-spi", }, 131 { /* sentinel */ } 132 }; 133 MODULE_DEVICE_TABLE(of, fsl_lpspi_dt_ids); 134 135 #define LPSPI_BUF_RX(type) \ 136 static void fsl_lpspi_buf_rx_##type(struct fsl_lpspi_data *fsl_lpspi) \ 137 { \ 138 unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR); \ 139 \ 140 if (fsl_lpspi->rx_buf) { \ 141 *(type *)fsl_lpspi->rx_buf = val; \ 142 fsl_lpspi->rx_buf += sizeof(type); \ 143 } \ 144 } 145 146 #define LPSPI_BUF_TX(type) \ 147 static void fsl_lpspi_buf_tx_##type(struct fsl_lpspi_data *fsl_lpspi) \ 148 { \ 149 type val = 0; \ 150 \ 151 if (fsl_lpspi->tx_buf) { \ 152 val = *(type *)fsl_lpspi->tx_buf; \ 153 fsl_lpspi->tx_buf += sizeof(type); \ 154 } \ 155 \ 156 fsl_lpspi->remain -= sizeof(type); \ 157 writel(val, fsl_lpspi->base + IMX7ULP_TDR); \ 158 } 159 160 LPSPI_BUF_RX(u8) 161 LPSPI_BUF_TX(u8) 162 LPSPI_BUF_RX(u16) 163 LPSPI_BUF_TX(u16) 164 LPSPI_BUF_RX(u32) 165 LPSPI_BUF_TX(u32) 166 167 static void fsl_lpspi_intctrl(struct fsl_lpspi_data *fsl_lpspi, 168 unsigned int enable) 169 { 170 writel(enable, fsl_lpspi->base + IMX7ULP_IER); 171 } 172 173 static int fsl_lpspi_bytes_per_word(const int bpw) 174 { 175 return DIV_ROUND_UP(bpw, BITS_PER_BYTE); 176 } 177 178 static bool fsl_lpspi_can_dma(struct spi_controller *controller, 179 struct spi_device *spi, 180 struct spi_transfer *transfer) 181 { 182 unsigned int bytes_per_word; 183 184 if (!controller->dma_rx) 185 return false; 186 187 bytes_per_word = fsl_lpspi_bytes_per_word(transfer->bits_per_word); 188 189 switch (bytes_per_word) { 190 case 1: 191 case 2: 192 case 4: 193 break; 194 default: 195 return false; 196 } 197 198 return true; 199 } 200 201 static int lpspi_prepare_xfer_hardware(struct spi_controller *controller) 202 { 203 struct fsl_lpspi_data *fsl_lpspi = 204 spi_controller_get_devdata(controller); 205 int ret; 206 207 ret = pm_runtime_get_sync(fsl_lpspi->dev); 208 if (ret < 0) { 209 dev_err(fsl_lpspi->dev, "failed to enable clock\n"); 210 return ret; 211 } 212 213 return 0; 214 } 215 216 static int lpspi_unprepare_xfer_hardware(struct spi_controller *controller) 217 { 218 struct fsl_lpspi_data *fsl_lpspi = 219 spi_controller_get_devdata(controller); 220 221 pm_runtime_mark_last_busy(fsl_lpspi->dev); 222 pm_runtime_put_autosuspend(fsl_lpspi->dev); 223 224 return 0; 225 } 226 227 static int fsl_lpspi_prepare_message(struct spi_controller *controller, 228 struct spi_message *msg) 229 { 230 struct fsl_lpspi_data *fsl_lpspi = 231 spi_controller_get_devdata(controller); 232 struct spi_device *spi = msg->spi; 233 int gpio = fsl_lpspi->chipselect[spi->chip_select]; 234 235 if (gpio_is_valid(gpio)) 236 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1); 237 238 return 0; 239 } 240 241 static void fsl_lpspi_write_tx_fifo(struct fsl_lpspi_data *fsl_lpspi) 242 { 243 u8 txfifo_cnt; 244 u32 temp; 245 246 txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff; 247 248 while (txfifo_cnt < fsl_lpspi->txfifosize) { 249 if (!fsl_lpspi->remain) 250 break; 251 fsl_lpspi->tx(fsl_lpspi); 252 txfifo_cnt++; 253 } 254 255 if (txfifo_cnt < fsl_lpspi->txfifosize) { 256 if (!fsl_lpspi->is_slave) { 257 temp = readl(fsl_lpspi->base + IMX7ULP_TCR); 258 temp &= ~TCR_CONTC; 259 writel(temp, fsl_lpspi->base + IMX7ULP_TCR); 260 } 261 262 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE); 263 } else 264 fsl_lpspi_intctrl(fsl_lpspi, IER_TDIE); 265 } 266 267 static void fsl_lpspi_read_rx_fifo(struct fsl_lpspi_data *fsl_lpspi) 268 { 269 while (!(readl(fsl_lpspi->base + IMX7ULP_RSR) & RSR_RXEMPTY)) 270 fsl_lpspi->rx(fsl_lpspi); 271 } 272 273 static void fsl_lpspi_set_cmd(struct fsl_lpspi_data *fsl_lpspi) 274 { 275 u32 temp = 0; 276 277 temp |= fsl_lpspi->config.bpw - 1; 278 temp |= (fsl_lpspi->config.mode & 0x3) << 30; 279 if (!fsl_lpspi->is_slave) { 280 temp |= fsl_lpspi->config.prescale << 27; 281 temp |= (fsl_lpspi->config.chip_select & 0x3) << 24; 282 283 /* 284 * Set TCR_CONT will keep SS asserted after current transfer. 285 * For the first transfer, clear TCR_CONTC to assert SS. 286 * For subsequent transfer, set TCR_CONTC to keep SS asserted. 287 */ 288 if (!fsl_lpspi->usedma) { 289 temp |= TCR_CONT; 290 if (fsl_lpspi->is_first_byte) 291 temp &= ~TCR_CONTC; 292 else 293 temp |= TCR_CONTC; 294 } 295 } 296 writel(temp, fsl_lpspi->base + IMX7ULP_TCR); 297 298 dev_dbg(fsl_lpspi->dev, "TCR=0x%x\n", temp); 299 } 300 301 static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi) 302 { 303 u32 temp; 304 305 if (!fsl_lpspi->usedma) 306 temp = fsl_lpspi->watermark >> 1 | 307 (fsl_lpspi->watermark >> 1) << 16; 308 else 309 temp = fsl_lpspi->watermark >> 1; 310 311 writel(temp, fsl_lpspi->base + IMX7ULP_FCR); 312 313 dev_dbg(fsl_lpspi->dev, "FCR=0x%x\n", temp); 314 } 315 316 static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi) 317 { 318 struct lpspi_config config = fsl_lpspi->config; 319 unsigned int perclk_rate, scldiv; 320 u8 prescale; 321 322 perclk_rate = clk_get_rate(fsl_lpspi->clk_per); 323 324 if (config.speed_hz > perclk_rate / 2) { 325 dev_err(fsl_lpspi->dev, 326 "per-clk should be at least two times of transfer speed"); 327 return -EINVAL; 328 } 329 330 for (prescale = 0; prescale < 8; prescale++) { 331 scldiv = perclk_rate / config.speed_hz / (1 << prescale) - 2; 332 if (scldiv < 256) { 333 fsl_lpspi->config.prescale = prescale; 334 break; 335 } 336 } 337 338 if (scldiv >= 256) 339 return -EINVAL; 340 341 writel(scldiv | (scldiv << 8) | ((scldiv >> 1) << 16), 342 fsl_lpspi->base + IMX7ULP_CCR); 343 344 dev_dbg(fsl_lpspi->dev, "perclk=%d, speed=%d, prescale=%d, scldiv=%d\n", 345 perclk_rate, config.speed_hz, prescale, scldiv); 346 347 return 0; 348 } 349 350 static int fsl_lpspi_dma_configure(struct spi_controller *controller) 351 { 352 int ret; 353 enum dma_slave_buswidth buswidth; 354 struct dma_slave_config rx = {}, tx = {}; 355 struct fsl_lpspi_data *fsl_lpspi = 356 spi_controller_get_devdata(controller); 357 358 switch (fsl_lpspi_bytes_per_word(fsl_lpspi->config.bpw)) { 359 case 4: 360 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES; 361 break; 362 case 2: 363 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES; 364 break; 365 case 1: 366 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE; 367 break; 368 default: 369 return -EINVAL; 370 } 371 372 tx.direction = DMA_MEM_TO_DEV; 373 tx.dst_addr = fsl_lpspi->base_phys + IMX7ULP_TDR; 374 tx.dst_addr_width = buswidth; 375 tx.dst_maxburst = 1; 376 ret = dmaengine_slave_config(controller->dma_tx, &tx); 377 if (ret) { 378 dev_err(fsl_lpspi->dev, "TX dma configuration failed with %d\n", 379 ret); 380 return ret; 381 } 382 383 rx.direction = DMA_DEV_TO_MEM; 384 rx.src_addr = fsl_lpspi->base_phys + IMX7ULP_RDR; 385 rx.src_addr_width = buswidth; 386 rx.src_maxburst = 1; 387 ret = dmaengine_slave_config(controller->dma_rx, &rx); 388 if (ret) { 389 dev_err(fsl_lpspi->dev, "RX dma configuration failed with %d\n", 390 ret); 391 return ret; 392 } 393 394 return 0; 395 } 396 397 static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi) 398 { 399 u32 temp; 400 int ret; 401 402 if (!fsl_lpspi->is_slave) { 403 ret = fsl_lpspi_set_bitrate(fsl_lpspi); 404 if (ret) 405 return ret; 406 } 407 408 fsl_lpspi_set_watermark(fsl_lpspi); 409 410 if (!fsl_lpspi->is_slave) 411 temp = CFGR1_MASTER; 412 else 413 temp = CFGR1_PINCFG; 414 if (fsl_lpspi->config.mode & SPI_CS_HIGH) 415 temp |= CFGR1_PCSPOL; 416 writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1); 417 418 temp = readl(fsl_lpspi->base + IMX7ULP_CR); 419 temp |= CR_RRF | CR_RTF | CR_MEN; 420 writel(temp, fsl_lpspi->base + IMX7ULP_CR); 421 422 temp = 0; 423 if (fsl_lpspi->usedma) 424 temp = DER_TDDE | DER_RDDE; 425 writel(temp, fsl_lpspi->base + IMX7ULP_DER); 426 427 return 0; 428 } 429 430 static int fsl_lpspi_setup_transfer(struct spi_controller *controller, 431 struct spi_device *spi, 432 struct spi_transfer *t) 433 { 434 struct fsl_lpspi_data *fsl_lpspi = 435 spi_controller_get_devdata(spi->controller); 436 437 if (t == NULL) 438 return -EINVAL; 439 440 fsl_lpspi->config.mode = spi->mode; 441 fsl_lpspi->config.bpw = t->bits_per_word; 442 fsl_lpspi->config.speed_hz = t->speed_hz; 443 fsl_lpspi->config.chip_select = spi->chip_select; 444 445 if (!fsl_lpspi->config.speed_hz) 446 fsl_lpspi->config.speed_hz = spi->max_speed_hz; 447 if (!fsl_lpspi->config.bpw) 448 fsl_lpspi->config.bpw = spi->bits_per_word; 449 450 /* Initialize the functions for transfer */ 451 if (fsl_lpspi->config.bpw <= 8) { 452 fsl_lpspi->rx = fsl_lpspi_buf_rx_u8; 453 fsl_lpspi->tx = fsl_lpspi_buf_tx_u8; 454 } else if (fsl_lpspi->config.bpw <= 16) { 455 fsl_lpspi->rx = fsl_lpspi_buf_rx_u16; 456 fsl_lpspi->tx = fsl_lpspi_buf_tx_u16; 457 } else { 458 fsl_lpspi->rx = fsl_lpspi_buf_rx_u32; 459 fsl_lpspi->tx = fsl_lpspi_buf_tx_u32; 460 } 461 462 if (t->len <= fsl_lpspi->txfifosize) 463 fsl_lpspi->watermark = t->len; 464 else 465 fsl_lpspi->watermark = fsl_lpspi->txfifosize; 466 467 if (fsl_lpspi_can_dma(controller, spi, t)) 468 fsl_lpspi->usedma = true; 469 else 470 fsl_lpspi->usedma = false; 471 472 return fsl_lpspi_config(fsl_lpspi); 473 } 474 475 static int fsl_lpspi_slave_abort(struct spi_controller *controller) 476 { 477 struct fsl_lpspi_data *fsl_lpspi = 478 spi_controller_get_devdata(controller); 479 480 fsl_lpspi->slave_aborted = true; 481 if (!fsl_lpspi->usedma) 482 complete(&fsl_lpspi->xfer_done); 483 else { 484 complete(&fsl_lpspi->dma_tx_completion); 485 complete(&fsl_lpspi->dma_rx_completion); 486 } 487 488 return 0; 489 } 490 491 static int fsl_lpspi_wait_for_completion(struct spi_controller *controller) 492 { 493 struct fsl_lpspi_data *fsl_lpspi = 494 spi_controller_get_devdata(controller); 495 496 if (fsl_lpspi->is_slave) { 497 if (wait_for_completion_interruptible(&fsl_lpspi->xfer_done) || 498 fsl_lpspi->slave_aborted) { 499 dev_dbg(fsl_lpspi->dev, "interrupted\n"); 500 return -EINTR; 501 } 502 } else { 503 if (!wait_for_completion_timeout(&fsl_lpspi->xfer_done, HZ)) { 504 dev_dbg(fsl_lpspi->dev, "wait for completion timeout\n"); 505 return -ETIMEDOUT; 506 } 507 } 508 509 return 0; 510 } 511 512 static int fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi) 513 { 514 u32 temp; 515 516 if (!fsl_lpspi->usedma) { 517 /* Disable all interrupt */ 518 fsl_lpspi_intctrl(fsl_lpspi, 0); 519 } 520 521 /* W1C for all flags in SR */ 522 temp = 0x3F << 8; 523 writel(temp, fsl_lpspi->base + IMX7ULP_SR); 524 525 /* Clear FIFO and disable module */ 526 temp = CR_RRF | CR_RTF; 527 writel(temp, fsl_lpspi->base + IMX7ULP_CR); 528 529 return 0; 530 } 531 532 static void fsl_lpspi_dma_rx_callback(void *cookie) 533 { 534 struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie; 535 536 complete(&fsl_lpspi->dma_rx_completion); 537 } 538 539 static void fsl_lpspi_dma_tx_callback(void *cookie) 540 { 541 struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie; 542 543 complete(&fsl_lpspi->dma_tx_completion); 544 } 545 546 static int fsl_lpspi_calculate_timeout(struct fsl_lpspi_data *fsl_lpspi, 547 int size) 548 { 549 unsigned long timeout = 0; 550 551 /* Time with actual data transfer and CS change delay related to HW */ 552 timeout = (8 + 4) * size / fsl_lpspi->config.speed_hz; 553 554 /* Add extra second for scheduler related activities */ 555 timeout += 1; 556 557 /* Double calculated timeout */ 558 return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC); 559 } 560 561 static int fsl_lpspi_dma_transfer(struct spi_controller *controller, 562 struct fsl_lpspi_data *fsl_lpspi, 563 struct spi_transfer *transfer) 564 { 565 struct dma_async_tx_descriptor *desc_tx, *desc_rx; 566 unsigned long transfer_timeout; 567 unsigned long timeout; 568 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg; 569 int ret; 570 571 ret = fsl_lpspi_dma_configure(controller); 572 if (ret) 573 return ret; 574 575 desc_rx = dmaengine_prep_slave_sg(controller->dma_rx, 576 rx->sgl, rx->nents, DMA_DEV_TO_MEM, 577 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 578 if (!desc_rx) 579 return -EINVAL; 580 581 desc_rx->callback = fsl_lpspi_dma_rx_callback; 582 desc_rx->callback_param = (void *)fsl_lpspi; 583 dmaengine_submit(desc_rx); 584 reinit_completion(&fsl_lpspi->dma_rx_completion); 585 dma_async_issue_pending(controller->dma_rx); 586 587 desc_tx = dmaengine_prep_slave_sg(controller->dma_tx, 588 tx->sgl, tx->nents, DMA_MEM_TO_DEV, 589 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 590 if (!desc_tx) { 591 dmaengine_terminate_all(controller->dma_tx); 592 return -EINVAL; 593 } 594 595 desc_tx->callback = fsl_lpspi_dma_tx_callback; 596 desc_tx->callback_param = (void *)fsl_lpspi; 597 dmaengine_submit(desc_tx); 598 reinit_completion(&fsl_lpspi->dma_tx_completion); 599 dma_async_issue_pending(controller->dma_tx); 600 601 fsl_lpspi->slave_aborted = false; 602 603 if (!fsl_lpspi->is_slave) { 604 transfer_timeout = fsl_lpspi_calculate_timeout(fsl_lpspi, 605 transfer->len); 606 607 /* Wait eDMA to finish the data transfer.*/ 608 timeout = wait_for_completion_timeout(&fsl_lpspi->dma_tx_completion, 609 transfer_timeout); 610 if (!timeout) { 611 dev_err(fsl_lpspi->dev, "I/O Error in DMA TX\n"); 612 dmaengine_terminate_all(controller->dma_tx); 613 dmaengine_terminate_all(controller->dma_rx); 614 fsl_lpspi_reset(fsl_lpspi); 615 return -ETIMEDOUT; 616 } 617 618 timeout = wait_for_completion_timeout(&fsl_lpspi->dma_rx_completion, 619 transfer_timeout); 620 if (!timeout) { 621 dev_err(fsl_lpspi->dev, "I/O Error in DMA RX\n"); 622 dmaengine_terminate_all(controller->dma_tx); 623 dmaengine_terminate_all(controller->dma_rx); 624 fsl_lpspi_reset(fsl_lpspi); 625 return -ETIMEDOUT; 626 } 627 } else { 628 if (wait_for_completion_interruptible(&fsl_lpspi->dma_tx_completion) || 629 fsl_lpspi->slave_aborted) { 630 dev_dbg(fsl_lpspi->dev, 631 "I/O Error in DMA TX interrupted\n"); 632 dmaengine_terminate_all(controller->dma_tx); 633 dmaengine_terminate_all(controller->dma_rx); 634 fsl_lpspi_reset(fsl_lpspi); 635 return -EINTR; 636 } 637 638 if (wait_for_completion_interruptible(&fsl_lpspi->dma_rx_completion) || 639 fsl_lpspi->slave_aborted) { 640 dev_dbg(fsl_lpspi->dev, 641 "I/O Error in DMA RX interrupted\n"); 642 dmaengine_terminate_all(controller->dma_tx); 643 dmaengine_terminate_all(controller->dma_rx); 644 fsl_lpspi_reset(fsl_lpspi); 645 return -EINTR; 646 } 647 } 648 649 fsl_lpspi_reset(fsl_lpspi); 650 651 return 0; 652 } 653 654 static void fsl_lpspi_dma_exit(struct spi_controller *controller) 655 { 656 if (controller->dma_rx) { 657 dma_release_channel(controller->dma_rx); 658 controller->dma_rx = NULL; 659 } 660 661 if (controller->dma_tx) { 662 dma_release_channel(controller->dma_tx); 663 controller->dma_tx = NULL; 664 } 665 } 666 667 static int fsl_lpspi_dma_init(struct device *dev, 668 struct fsl_lpspi_data *fsl_lpspi, 669 struct spi_controller *controller) 670 { 671 int ret; 672 673 /* Prepare for TX DMA: */ 674 controller->dma_tx = dma_request_chan(dev, "tx"); 675 if (IS_ERR(controller->dma_tx)) { 676 ret = PTR_ERR(controller->dma_tx); 677 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret); 678 controller->dma_tx = NULL; 679 goto err; 680 } 681 682 /* Prepare for RX DMA: */ 683 controller->dma_rx = dma_request_chan(dev, "rx"); 684 if (IS_ERR(controller->dma_rx)) { 685 ret = PTR_ERR(controller->dma_rx); 686 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret); 687 controller->dma_rx = NULL; 688 goto err; 689 } 690 691 init_completion(&fsl_lpspi->dma_rx_completion); 692 init_completion(&fsl_lpspi->dma_tx_completion); 693 controller->can_dma = fsl_lpspi_can_dma; 694 controller->max_dma_len = FSL_LPSPI_MAX_EDMA_BYTES; 695 696 return 0; 697 err: 698 fsl_lpspi_dma_exit(controller); 699 return ret; 700 } 701 702 static int fsl_lpspi_pio_transfer(struct spi_controller *controller, 703 struct spi_transfer *t) 704 { 705 struct fsl_lpspi_data *fsl_lpspi = 706 spi_controller_get_devdata(controller); 707 int ret; 708 709 fsl_lpspi->tx_buf = t->tx_buf; 710 fsl_lpspi->rx_buf = t->rx_buf; 711 fsl_lpspi->remain = t->len; 712 713 reinit_completion(&fsl_lpspi->xfer_done); 714 fsl_lpspi->slave_aborted = false; 715 716 fsl_lpspi_write_tx_fifo(fsl_lpspi); 717 718 ret = fsl_lpspi_wait_for_completion(controller); 719 if (ret) 720 return ret; 721 722 fsl_lpspi_reset(fsl_lpspi); 723 724 return 0; 725 } 726 727 static int fsl_lpspi_transfer_one(struct spi_controller *controller, 728 struct spi_device *spi, 729 struct spi_transfer *t) 730 { 731 struct fsl_lpspi_data *fsl_lpspi = 732 spi_controller_get_devdata(controller); 733 int ret; 734 735 fsl_lpspi->is_first_byte = true; 736 ret = fsl_lpspi_setup_transfer(controller, spi, t); 737 if (ret < 0) 738 return ret; 739 740 fsl_lpspi_set_cmd(fsl_lpspi); 741 fsl_lpspi->is_first_byte = false; 742 743 if (fsl_lpspi->usedma) 744 ret = fsl_lpspi_dma_transfer(controller, fsl_lpspi, t); 745 else 746 ret = fsl_lpspi_pio_transfer(controller, t); 747 if (ret < 0) 748 return ret; 749 750 return 0; 751 } 752 753 static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id) 754 { 755 u32 temp_SR, temp_IER; 756 struct fsl_lpspi_data *fsl_lpspi = dev_id; 757 758 temp_IER = readl(fsl_lpspi->base + IMX7ULP_IER); 759 fsl_lpspi_intctrl(fsl_lpspi, 0); 760 temp_SR = readl(fsl_lpspi->base + IMX7ULP_SR); 761 762 fsl_lpspi_read_rx_fifo(fsl_lpspi); 763 764 if ((temp_SR & SR_TDF) && (temp_IER & IER_TDIE)) { 765 fsl_lpspi_write_tx_fifo(fsl_lpspi); 766 return IRQ_HANDLED; 767 } 768 769 if (temp_SR & SR_MBF || 770 readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_TXCOUNT) { 771 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR); 772 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE); 773 return IRQ_HANDLED; 774 } 775 776 if (temp_SR & SR_FCF && (temp_IER & IER_FCIE)) { 777 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR); 778 complete(&fsl_lpspi->xfer_done); 779 return IRQ_HANDLED; 780 } 781 782 return IRQ_NONE; 783 } 784 785 #ifdef CONFIG_PM 786 static int fsl_lpspi_runtime_resume(struct device *dev) 787 { 788 struct spi_controller *controller = dev_get_drvdata(dev); 789 struct fsl_lpspi_data *fsl_lpspi; 790 int ret; 791 792 fsl_lpspi = spi_controller_get_devdata(controller); 793 794 ret = clk_prepare_enable(fsl_lpspi->clk_per); 795 if (ret) 796 return ret; 797 798 ret = clk_prepare_enable(fsl_lpspi->clk_ipg); 799 if (ret) { 800 clk_disable_unprepare(fsl_lpspi->clk_per); 801 return ret; 802 } 803 804 return 0; 805 } 806 807 static int fsl_lpspi_runtime_suspend(struct device *dev) 808 { 809 struct spi_controller *controller = dev_get_drvdata(dev); 810 struct fsl_lpspi_data *fsl_lpspi; 811 812 fsl_lpspi = spi_controller_get_devdata(controller); 813 814 clk_disable_unprepare(fsl_lpspi->clk_per); 815 clk_disable_unprepare(fsl_lpspi->clk_ipg); 816 817 return 0; 818 } 819 #endif 820 821 static int fsl_lpspi_init_rpm(struct fsl_lpspi_data *fsl_lpspi) 822 { 823 struct device *dev = fsl_lpspi->dev; 824 825 pm_runtime_enable(dev); 826 pm_runtime_set_autosuspend_delay(dev, FSL_LPSPI_RPM_TIMEOUT); 827 pm_runtime_use_autosuspend(dev); 828 829 return 0; 830 } 831 832 static int fsl_lpspi_probe(struct platform_device *pdev) 833 { 834 struct device_node *np = pdev->dev.of_node; 835 struct fsl_lpspi_data *fsl_lpspi; 836 struct spi_controller *controller; 837 struct spi_imx_master *lpspi_platform_info = 838 dev_get_platdata(&pdev->dev); 839 struct resource *res; 840 int i, ret, irq; 841 u32 temp; 842 bool is_slave; 843 844 is_slave = of_property_read_bool((&pdev->dev)->of_node, "spi-slave"); 845 if (is_slave) 846 controller = spi_alloc_slave(&pdev->dev, 847 sizeof(struct fsl_lpspi_data)); 848 else 849 controller = spi_alloc_master(&pdev->dev, 850 sizeof(struct fsl_lpspi_data)); 851 852 if (!controller) 853 return -ENOMEM; 854 855 platform_set_drvdata(pdev, controller); 856 857 fsl_lpspi = spi_controller_get_devdata(controller); 858 fsl_lpspi->dev = &pdev->dev; 859 fsl_lpspi->is_slave = is_slave; 860 861 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32); 862 controller->transfer_one = fsl_lpspi_transfer_one; 863 controller->prepare_transfer_hardware = lpspi_prepare_xfer_hardware; 864 controller->unprepare_transfer_hardware = lpspi_unprepare_xfer_hardware; 865 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 866 controller->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX; 867 controller->dev.of_node = pdev->dev.of_node; 868 controller->bus_num = pdev->id; 869 controller->slave_abort = fsl_lpspi_slave_abort; 870 871 ret = devm_spi_register_controller(&pdev->dev, controller); 872 if (ret < 0) { 873 dev_err(&pdev->dev, "spi_register_controller error.\n"); 874 goto out_controller_put; 875 } 876 877 if (!fsl_lpspi->is_slave) { 878 for (i = 0; i < controller->num_chipselect; i++) { 879 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i); 880 881 if (!gpio_is_valid(cs_gpio) && lpspi_platform_info) 882 cs_gpio = lpspi_platform_info->chipselect[i]; 883 884 fsl_lpspi->chipselect[i] = cs_gpio; 885 if (!gpio_is_valid(cs_gpio)) 886 continue; 887 888 ret = devm_gpio_request(&pdev->dev, 889 fsl_lpspi->chipselect[i], 890 DRIVER_NAME); 891 if (ret) { 892 dev_err(&pdev->dev, "can't get cs gpios\n"); 893 goto out_controller_put; 894 } 895 } 896 controller->cs_gpios = fsl_lpspi->chipselect; 897 controller->prepare_message = fsl_lpspi_prepare_message; 898 } 899 900 init_completion(&fsl_lpspi->xfer_done); 901 902 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 903 fsl_lpspi->base = devm_ioremap_resource(&pdev->dev, res); 904 if (IS_ERR(fsl_lpspi->base)) { 905 ret = PTR_ERR(fsl_lpspi->base); 906 goto out_controller_put; 907 } 908 fsl_lpspi->base_phys = res->start; 909 910 irq = platform_get_irq(pdev, 0); 911 if (irq < 0) { 912 ret = irq; 913 goto out_controller_put; 914 } 915 916 ret = devm_request_irq(&pdev->dev, irq, fsl_lpspi_isr, 0, 917 dev_name(&pdev->dev), fsl_lpspi); 918 if (ret) { 919 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret); 920 goto out_controller_put; 921 } 922 923 fsl_lpspi->clk_per = devm_clk_get(&pdev->dev, "per"); 924 if (IS_ERR(fsl_lpspi->clk_per)) { 925 ret = PTR_ERR(fsl_lpspi->clk_per); 926 goto out_controller_put; 927 } 928 929 fsl_lpspi->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 930 if (IS_ERR(fsl_lpspi->clk_ipg)) { 931 ret = PTR_ERR(fsl_lpspi->clk_ipg); 932 goto out_controller_put; 933 } 934 935 /* enable the clock */ 936 ret = fsl_lpspi_init_rpm(fsl_lpspi); 937 if (ret) 938 goto out_controller_put; 939 940 ret = pm_runtime_get_sync(fsl_lpspi->dev); 941 if (ret < 0) { 942 dev_err(fsl_lpspi->dev, "failed to enable clock\n"); 943 goto out_pm_get; 944 } 945 946 temp = readl(fsl_lpspi->base + IMX7ULP_PARAM); 947 fsl_lpspi->txfifosize = 1 << (temp & 0x0f); 948 fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f); 949 950 ret = fsl_lpspi_dma_init(&pdev->dev, fsl_lpspi, controller); 951 if (ret == -EPROBE_DEFER) 952 goto out_pm_get; 953 954 if (ret < 0) 955 dev_err(&pdev->dev, "dma setup error %d, use pio\n", ret); 956 957 return 0; 958 959 out_pm_get: 960 pm_runtime_put_noidle(fsl_lpspi->dev); 961 out_controller_put: 962 spi_controller_put(controller); 963 964 return ret; 965 } 966 967 static int fsl_lpspi_remove(struct platform_device *pdev) 968 { 969 struct spi_controller *controller = platform_get_drvdata(pdev); 970 struct fsl_lpspi_data *fsl_lpspi = 971 spi_controller_get_devdata(controller); 972 973 pm_runtime_disable(fsl_lpspi->dev); 974 975 spi_master_put(controller); 976 977 return 0; 978 } 979 980 #ifdef CONFIG_PM_SLEEP 981 static int fsl_lpspi_suspend(struct device *dev) 982 { 983 int ret; 984 985 pinctrl_pm_select_sleep_state(dev); 986 ret = pm_runtime_force_suspend(dev); 987 return ret; 988 } 989 990 static int fsl_lpspi_resume(struct device *dev) 991 { 992 int ret; 993 994 ret = pm_runtime_force_resume(dev); 995 if (ret) { 996 dev_err(dev, "Error in resume: %d\n", ret); 997 return ret; 998 } 999 1000 pinctrl_pm_select_default_state(dev); 1001 1002 return 0; 1003 } 1004 #endif /* CONFIG_PM_SLEEP */ 1005 1006 static const struct dev_pm_ops fsl_lpspi_pm_ops = { 1007 SET_RUNTIME_PM_OPS(fsl_lpspi_runtime_suspend, 1008 fsl_lpspi_runtime_resume, NULL) 1009 SET_SYSTEM_SLEEP_PM_OPS(fsl_lpspi_suspend, fsl_lpspi_resume) 1010 }; 1011 1012 static struct platform_driver fsl_lpspi_driver = { 1013 .driver = { 1014 .name = DRIVER_NAME, 1015 .of_match_table = fsl_lpspi_dt_ids, 1016 .pm = &fsl_lpspi_pm_ops, 1017 }, 1018 .probe = fsl_lpspi_probe, 1019 .remove = fsl_lpspi_remove, 1020 }; 1021 module_platform_driver(fsl_lpspi_driver); 1022 1023 MODULE_DESCRIPTION("LPSPI Controller driver"); 1024 MODULE_AUTHOR("Gao Pan <pandy.gao@nxp.com>"); 1025 MODULE_LICENSE("GPL"); 1026